VPA2000

VPA2000 RENESAS | Alldatasheet

Document overview

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Technical content

Features

/square4 2A high efficiency boost regulator with integrated switch for AVDD /square4 1.2V low-power regulator for DisplayPort TCON /square4 2.5V, 300mA LDO for DisplayPort TCON /square4 Built-in high speed VCOM buffer /square4 External 2x charge pump for VGH /square4 Negative regulator for VGL /square4 Over-current, over-voltage, and over-temperature protection /square4 Built-in soft start /square4 Reset output for DisplayPort TCON /square4 QFN-24, 4x4mm, Pb-free (RoHS compliant) package

Applications

/square4 DisplayPort devices /square4 TFT-LCD display panels for notebooks /square4 TFT-LCD display panels for monitors

Description

The VPA2000 is a 6-output power management IC for TFT-LCD panels. It is integrated into a 24 lead 4x4mm QFN package to provide a small-footprint, low- temperature, and low-cost solution. The current mode control dc-dc step-up switching regulator (boost) is designed to deliver the AVDD source driver voltage with high efficiency. The 1.2MHz switching frequency allows for a small external inductor to meet PCB area and height requirements. The negative gate drive voltage (VGL) is regulated by the on-board linear regulator. A built-in high speed VCOM buffer provides the voltage to drive the capacitive backplane of the TFT-LCD panel. Both VGL and VCOM output voltages can be adjusted by an external resistor divider. A simple, low-cost, external 2x charge pump supplies the positive gate drive voltage (VGH). The internal 2.5V fixed output LDO and 1.2V fixed output charge pump supply the core voltages for the timing controller (TCON). The 1.2V charge pump dissipates approximately 80% less power than a traditional LDO solution. Block Diagram VON Boost VC OM LDO Vcore VOFF 3.3V 16V / 50mA 8V / 600mA 4V / 100mA 2.5V / 300mA 1.2V / 300mA -5V / 30mA VGH VGL 50mA VON Boost VC OM LDO Vcore VOFF 3.3V 16V / 50mA 8V / 600mA 4V / 100mA 2.5V / 300mA 1.2V / 300mA -5V / 30mA VGH VGL 50mA F igure 1. VPA2000 Block Diagram

March 2010 – Rev 1.0: Initial Version

Table 1. Absolute Maximum Ratings Summary Table 2. Package Thermal Resistivity altitude, and other unlisted variables. conditions for extended periods may affect reliability.

March 11, 2010 4 SPECIFICATION TABLE V IN = 2.7V to 4.0V. Unless otherwise specified, all specifications are tested under T A = 25°C. The ◙ denotes specifications that apply for T A = -40°C to +85°C. [Note 4] Tabl e 3. General Electrical Specifications SYMBOL PARAMETER CO NDI TIONS ◙ MIN TYP MAX UNITS V IN Operating input voltage range ◙ 2 .7 4.0 V IQ_VIN V IN quiescent current V IN = 2.7V to 4.0V 3 m A [Note 4] Specifications over the -40°C to +85°C operation ambient temperature are guaranteed by design, characterization and statistical correlation. V IN = 2.7V to 4.0V; CIN = 10µF, CAVDD = 22µF. Unless otherwise specified, all specifications are tested under T A = 25°C. The ◙ denotes specifications that apply for T A = -40°C to +85°C. [Note 4] Tabl e 4. Step-up Switching Regulator (Boost) Specification SYMBOL PARAMETER CONDI TIONS ◙ MIN TYP MAX UNITS AVDD Output voltage range 16 V V FBB FBB reference voltage Me asure V COMP , VFBB = VCOMP 1.188 1.2 1.212 V Line regulation IAVDD = 100mA, VIN = 3V to 4V 0. 2 % Load regulation IAVDD = 50mA to 200mA, AVDD = 8V 2 % Overall accuracy (Line, Load, Tem perature) ◙ -3 3 % IFBB_LEAK FBB pin input leakage current V FBB = 0.5V to 1.5V ◙ - 100 100 nA RDS(ON) N-channel switch ON-resistance V IN = 3.3V 0. 2 0.35 Ω ICL N-channel switch current limit V FBB = 1.1V, VRLIM = VIN ◙ 1.8 2.35 2.8 A ISW_LEAK SWN pin leakage current V FBB = 1.4V, VSWN = 20V ◙ 0. 1 1 µA fOSC Switching frequency 1. 2 MHz D MAX Maximum duty cycle ◙ 8 6 93 % tMIN Minimum on-time 50 ns g m Error amplifier transconductance 16 00 µS ISS COMP soft start source current During soft start 2 µ A OVP AVDD over-voltage trip point Measure at AVDD pin Vin = 3.3V ◙ 18 19.5 21 V AVDD trip point hysteresis 1.7 V V FBB_FAULT FBB fault trip point Me asure at FBB pin ◙ 0.95 1 1.05 V [Note 4] Specifications over the -40°C to +85°C operation ambient temperature are guaranteed by design, characterization and statistical correlation.

March 11, 2010 5 VIN = 2.7V to 4.0V; CLDO = 1µF. Unless otherwise specified, all specifications are tested under T A = 25°C. Th e ◙ denotes specifications that apply for T A = -40°C to +85°C. [Note 4] Ta ble 5. Low Voltage Linear Regulator SYMBOL PARAMETER CO NDITIONS ◙ MIN TYP MAX UNITS 3.0V < VIN < 4.0V 3 00 mA IOUT_MAX Maximum LDO output current .7V < VIN ≤ 3.0V 1 50 mA Output voltage setpoint accuracy ◙ -4 4 % Output voltage line regulation V IN = 2.7V to 4.0V 0 .3 % Output voltage load regulation I LDO = 0 to 300mA 0 .3 % V DO Output dropout voltage ILDO = 300mA [Note 5] ◙ 5 00 mV ISC Short circuit current V LDO = 0V, VIN = 3.3V 3 00 600 mA PSRR Power supply rejection ratio Freq = 120Hz 70 dB [Note 4] Specifications over the -40°C to +85°C operation ambient temperature are guaranteed by design, characterization and statistical correlation. [Note 5] LDO dropout voltage is the minimum input to output differential voltage to keep the output voltage as a 2% reduction from a nominal level measured at V IN = VLDO +1V. Th e ◙ denotes specifications that apply for T A = -40°C to +85°C. [Note 4] Ta ble 6. Negative High Voltage Linear Regulator / Controller SYMBOL PARAMETER CO NDITIONS ◙ MIN TYP MAX UNITS V FBVGL _ OS FBVGL offset voltage ◙ -15 15 mV Output voltage line regulation V IN = 3.0V to 3.6V 0 .2 % Output voltage load regulation I GL = 0 to 20mA 0 .3 % V DO Output dropout voltage I GL = 10mA [Note 6][Note 7] 5 00 mV IOUT_MAX Maximum output current V VGLREG = 4V, VFBVGL = 0.1V 3 0 mA RDS(ON) N-channel switch ON-resistance I VGLREG = 10mA 2 0 Ω [Note 4] Specifications over the -40°C to +85°C operation ambient temperature are guaranteed by design, characterization and statistical correlation. [Note 6] Guaranteed by design, not 100% production tested. [Note 7] Negative linear regulator dropout voltage is the minimum A VDD to |V GL | differential voltage to keep |V GL | as a 2% reduction from a nominal level measured at V ADDD =|V GL |+2V. Th e ◙ denotes specifications that apply for T A = -40°C to +85°C. [Note 4] Ta ble 7. Reference Output SYMBOL PARAMETER CO NDITIONS ◙ MIN TYP MAX UNITS V REF Output voltage 1 .2 V Output voltage accuracy V IN = 3.0V to 3.6V ◙ -3 3 % Output voltage line regulation V IN = 3.0V to 4.0V ◙ 0 .2 % Output voltage load regulation I REF = 50 to 100µA ◙ 0 .3 % IREF_SINK V REF pin sink current V IN = 1.8V 1 0 µA IREF_SOURCE V REF pin source current ◙ 200 µA [Note 4] Specifications over the -40°C to +85°C operation ambient temperature are guaranteed by design, characterization and statistical correlation.

Table 8. VCOM Buffer [Note 4] Specifications over the -40°C to +85°C operation ambient temperature are guaranteed by design, characterization and statistical correlation. [Note 4] Specifications over the -40°C to +85°C operation ambient temperature are guaranteed by design, characterization and statistical correlation. [Note 6] Guaranteed by design, not 100% production tested.

Table 10. UVLO and Thermal Protection Circuits [Note 4] Specifications over the -40°C to +85°C operation ambient temperature are guaranteed by design, characterization and statistical correlation. [Note 6] Guaranteed by design, not 100% production tested. V IN = 2.7V to 4.0V. Unless otherwise specified, all specifications are tested under T A = 25°C. [Note 4] Specifications over the -40°C to +85°C operation ambient temperature are guaranteed by design, characterization and statistical correlation. [Note 4] Specifications over the -40°C to +85°C operation ambient temperature are guaranteed by design, characterization and statistical correlation.

March 11, 2010 8 TYPICAL PERFORMANCE CHARACTERISTICS 8.02 8.04 8.06 8.08 8.1 0 100 200 300 400 IOUT (mA) VOUT (V) VIN=3.3V TA=25° C Fi gure 2. Boost 8V Output Voltage vs. Output Current 100 0 100 200 300 400 IOUT (mA) Efficiency (%) VIN=3.3V TA=25° C Fi gure 3. Boost 8V Output Efficiency vs. Output Current 1.0 1.1 1.2 1.3 1.4 2.5 3 3.5 4 VIN (V) Switching Frequency (MHz) TA=25° C TA=-40° C TA=85° C Fi gure 4. Boost Switching Frequency vs. Input Voltage -5.10 -5.05 -5.00 -4.95 -4.90 0 10 20 30 40 50 IGL (mA) VGL (V) VIN=3.3V AVDD=8V TA=25° C Fi gure 5. VGL Output Voltage vs. Output Current 2.5 3 3.5 4 VIN (V) Offset Voltage (mV) TA=25° C Fi gure 6. VGL Input Offset Voltage vs. Input Voltage 1.18 1.19 1.20 1.21 1.22 0 1 2 3 IREF (mA) VREF (V) VIN=3.3V TA=25° C Fi gure 7. VREF Output Voltage vs. Output Current

March 11, 2010 9 100 150 200 250 0 20 40 60 80 100 ICOM (mA) Differential Voltage (mV) VINP1-VINN1 TA=25° C Fi gure 8. VCOM Input Differential Voltage vs. Output Current (Sourcing Current) -100 -80 -60 -40 -20 0 20 40 60 80 100 ICOM (mA) Differential Voltage (mV) VINP1-VINN1 TA=25° C Fi gure 9. VCOM Input Differential Voltage vs. Output Current (Sinking Current) 0.2 0.3 0.4 0.5 0.6 0.7 6 8 10 12 14 16 18 AVDD (V) Supply Current (mA) TA=85° C TA=25° C TA=-40° C Fi gure 10. V COM Supply Current vs. AVDD Supply Voltage 1.18 1.19 1.20 1.21 1.22 0 50 100 150 200 250 300 IOUT (mA) VCORE (V) VIN=2.7V VIN=4.0V VIN=3.3V TA=25° C Fi gure 11. V CORE Output Voltage vs. Output Current 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 0 50 100 150 200 250 300 IOUT (mA) Minimum Input Voltage (V) VOUT=1.2V TA=25° C TA=-40° C TA=85° C Fi gure 12. V CORE Minimum Input Voltage vs. Output Current 2.0 2.2 2.4 2.6 2.8 2.5 3 3.5 4 VIN (V) Switching Frequency (MHz) TA=25° C TA=-40° C TA=85° C Fi gure 13. VCORE Switching Frequency vs. Input Voltage

March 11, 2010 10 100 200 300 400 0 50 100 150 200 250 300 ILDOOUT (mA) VDO (mV) TA=85° C TA=25° C TA=-40° C Fi gure 14. LDO Dropout Voltage vs. Output Current 2.46 2.48 2.50 2.52 2.54 0 50 100 150 200 250 300 IOUT (mA) VLDO (V) VIN=3.3V VIN=2.7V VIN=4.0V TA=25° C Fi gure 15. LDO Output Voltage vs. Output Current F igure 16. Power Up Sequence (Typical Application Circuit with VGH set to 3x A VDD ) F igure 17. Boost Switching Waveform at I OUT = 100mA Fi gure 18. Boost Load Transient Response for IAVDD = 0 to 200mA Fi gure 19. Boost Load Transient Response for IAVDD = 100mA to 200mA IAVDD 100mA/div AVDD 200mV/div AC IAVDD 100mA/div AVDD 200mV/div AC IL 500mA/div SWN 5V/div AVDD 20mV/div AC AVDD 10V/div V GH 20V/div V LDO 5V/div V CORE 2V/div V COM 5V/div V GL 5V/div

March 11, 2010 11 Fi gure 20. V CORE Load Transient Response for ICORE = 50mA to 150mA Fi gure 21. V COM Load Transient Response for ICOM = 100mA Capacitive Load Fi gure 22. VCOM Large Signal Response Fi gure 23. VCOM Small Signal Response Fi gure 24. LDO Load Transient Response f or ILDO = 150mA to 300mA Fi gure 25. RSTOUT Function Waveforms INP1 500mV/div V COM 500mV/div V COM 50mV/div INP1 50mV/div ICORE 50mA/div V CORE 20mV/div AC V COM 200mA/div AC ICOM 100mA/div 3.5V 4.0V 4.5V 3.5V 4.0V 4.5V 3.95V 4.00V 4.05V 3.95V 4.00V 4.05V ILDO 100mA/div V LDO 50mV/div AC V IN 2V/div AVDD 5V/div RSTOUT 2V/div

Table 13. Pin Descriptions 1 GND2 Ground connections for VCORE. Connect this pin to ground. 2 VGLREG Output Output of the linear regulator for negative gate driver voltage. resistor between this pin and VREF pin. Values of these resistors define output voltage V GL . 4 VREF Output Output of the internal reference block. 5 VIN2 Input Power supply input voltage. Place a decoupling 1µF capacitor next to this pin. 6 LDO Output Output of the internal 2.5V LDO supplies the I/O voltage of DP TCON. any voltage source lower than VIN. r V GH to allow negative output V GL to rise first. 11 INN1 Input Negative input for the internal VCOM buffer. Connect to OUT1 for unity gain configuration. 12 INP1 Input Positive input for the internal VCOM buffer. Connect through a resistor divider to A VDD . 13 AVDD Input Connect to the output of the boost regulator. This voltage is used to power VCOM buffer. 14 OUT1 Output Output of the VCOM driver. 15 GND3 Ground connections for the IC. 16 FBB Input Feedback pin for the A VDD . Connect this pin to the output through a resistor divider. 18 RLIM Connect this pin to V IN to set the maximum peak current level for the boost switch.

March 11, 2010 13 NUMBER LABEL I/O DESCRIPTION 19 SWN Connection for the drain terminal of the boost power switch. 20 GND1 Ground connections for the boost switch. Route the boost output capacitors ground returns to this pin with the smallest loop area possible. Connect this pin to ground. 21 VIN1 Input Power supply input voltage. Place a decoupling 4.7µF capacitor next to this pin. 22 C1P Positive terminal of flying capacitor required by the charge pump. 23 VCORE Output Output of the built-in charge pump. This pin supplies 1.2V for the core voltage of DP TCON. 24 C1N Negative terminal of flying capacitor required by the charge pump. - PAD Thermal pad. Connect this pad to ground. Use thermal vias and large copper area for improved thermal performance.

March 11, 2010 14 FUNCTIONAL DIAGRAM Fi gure 27. VPA2000 Functional Diagram

March 11, 2010 15 THEORY OF OPERATION The VPA2000 is a complete power solution for TFT-LCD p anels and display port timing controllers. It contains a boost regulator, a negative voltage regulator, a VCOM buffer, a 2.5V fixed output LDO, a 1.2V fixed output charge pump, and an external 2x charge pump. Boost Regulator The VPA2000 boost regulator is designed to generate the AVDD voltage for the source drivers in the TFT-LCD panel. I ts current mode control architecture with fixed 1.2MHz switching frequency provides fast transient response and reduces the number of external components for compensation. When the internal power N-channel MOSFET (connected to SWN pin) is turned on, current starts to flow from V IN to g round, and the inductor current starts to ramp up and stores the energy. The ramping current is sensed and is added with the slope compensation ramp. When the ramp current reaches its control level, the MOSFET is turned off, and the energy stored in the inductor will feed to the output (A VDD ). The M OSFET on-off ratio (duty cycle) is varied by the input to output ratio and can be calculated with the following equation during continuous conduction mode (CCM): VDD IN A V1 D − = [1] Th e output voltage A VDD is set by an external resistor d ivider R7 and R8. A VDD can be calculated with equation:  + × =R8 R71 1.2V AVDD [2] Th e boost regulator has a built-in over-voltage protection (OVP) to prevent the output voltage from exceeding 20V. Always connect the boost output (A VDD ) to AVDD pin to a ctivate the OVP function and enable the VCOM buffer. Fi gure 28. VPA2000 Boost Regulator Block Diagram

March 11, 2010 16 If over-voltage is detected during normal operation, the power N-channel MOSFET will turn off, and it will turn on again when output voltage drops below the comparator hysteretic level. On the other hand, if over-voltage is detected during power up, the boost regulator will shut down. Fi gure 29. Over-voltage Protection Besides over-voltage protection, the boost regulator has a n over-current protection to prevent excess current from flowing into the power N-channel MOSFET. When the inductor peak current is beyond the current limit level, the N-channel MOSFET will shut down. Thus, during over- current, the output voltage will be lower than the programmed output voltage. Connecting the RLIM pin to V IN will set the current limit level to its default value 2.35A. Th e current limit level can be adjusted lower by placing a resistor divider from V REF pin to ground, see Figure 28 for d etails. Therefore, I LIM is calculated as: (A)R4 R3 R4V 35 . 2 IREFLIM +× × = [3] where V REF = 1.2V. For example, to set the current limit l evel to 1A, choose R4 = 4.99kΩ, so R3 will be 9.09kΩ. Inductor Current F i gure 30. Inductor Current Waveforms For stability, connect a 4.99kΩ resistor, R C , in series with a 6.8nF capacitor, C C , from COMP pin to ground. Th e average inductor current is proportional to the boost regulator output current. As the output current decreases, the inductor current will eventually reach zero, and if the output current is further decreased, the boost regulator will operate in discontinuous conduction mode (DCM). The output current level that results in DCM is approximately: L f D) (1 D V SW INOUT [4] w here f SW is the switching frequency of the boost regulator. W hen the output current level is reduced even further, the boost converter will skip pulses randomly in order to maintain the output regulation. The pulse skipping feature is inherent to the boost regulator, and it improves the light- load efficiency due to the reduction of switching losses. Negative Linear Regulator The negative linear regulator provides the negative output v oltage (VGL) with a 2-phase operation. During the first phase, when V SWN is equal to A VDD , the flying capacitors C GLFLY and C VGLREG are charged up. During the second p hase, when V SWN is equal to 0V, it level shifts C GLFLY , and C GLFLY and C GL are now connected in parallel. Thus, C GL c harges up to a negative voltage. The voltage across C GLFLY and C VGLREG is controlled by the N -channel MOSFET, and V GL is set by the external r esistor divider R9 and R10 with the following equation: R10 R9-1.2V VGL × = [5] Fi gure 31. Negative Linear Regulator Block Diagram

March 11, 2010 17 VCOM Buffer The VPA2000 VCOM buffer is an operational t ransconductance amplifier. Since the stability of the amplifier is improved with larger capacitive loads, it becomes an ideal power supply for the backplane of TFT-LCD panels. Connect INN1 pin to OUT1 pin to configure the VCOM buffer as a unity gain amplifier. To adjust the output voltage of the VCOM buffer, connect a resistor divider on pin INP1 from A VDD to GND, as shown i n Figure 39. Therefore, R6 R5 R6A VVDDCOM + = [6] Low Dropout Linear Regulator (LDO) The VPA2000 LDO provides a 2.5V fixed output with m aximum 300mA current. It is designed to supply the I/O voltage for display port timing controllers. To ensure stability, a minimum 1.0µF output capacitor with ESR < 0.5Ω is required for the LDO. Ceramic capacitors are the best choice for their low ESR range on the order of mΩ. Higher output capacitance will help to reduce the output ripple. The LDO has a short-circuit current protection which limits the current to be 600mA during a short-circuit condition. VCORE Charge Pump The VCORE output is a 0.5x regulated charge pump with f ixed 1.2V output voltage, designed as a low cost replacement for buck regulators. The charge pump operates at constant frequency with 50% duty cycle. During the first phase, flying capacitor C FLY is placed in s eries with output capacitor C OUT. The input current c harges both the flying capacitor and the output capacitor, and supplies the output load. During the second phase, the output capacitor and the flying capacitor are placed in parallel, and both capacitors are discharged to supply the output load. Since V IN conducts to V OUT with 50% duty c ycle, the average input current is equal to 50% of the output current. As a result, it dissipates approximately 80% less power than a standard LDO. To regulate the output voltage, the error amplifier controls the input P-channel MOSFET gate driver voltage, which controls the amount of current flowing into the flying capacitor during the charging phase. Thus, the flying capacitor’s differential voltage is charged up to be equal to the output voltage. The value of C FLY should be 0.22µF. To ensure stability o ver its operating current range, a 4.7µF or larger output capacitor is required. Higher output capacitance will help to reduce the output ripple and will have better transient response performance. The charge pump has over-current protection which ensures the maximum output current is limited to 600mA during over current and 80mA during a short-circuit condition. VI N VCORE 0.22µ F 7µ F VI N VCORE Phase 1 P hase 2 CFLY CCORE 0.22µ F CF LY 4.7µ F CCORE Fi gure 32. 0.5x Charge Pump 2 Phase Operation Fi gure 33. Input Current flowing Diagram

March 11, 2010 19 Power Up Sequence All of the output voltages will be enabled after the input voltage exceeds the UVLO level. A VDD and V GL will start to rise 300µs after they are enabled. The ON pin is an open- drain output, and it will pull low after 3.4ms, and can be used to delay the V GH output. Refer to Figure 37 for an illustration. Fi gure 37. Power Up Sequence Over-temperature Protection When the junction temperature of the VPA2000 reaches 50°C, the over-temperature protection will activate and shut down the device. It will resume to its previous operating condition when the junction temperature falls below 135°C.

calculate R7. Thus, R7=28kΩ. works for most applications. he current limit level to 2.35A (default value). A 10µF or greater value input capacitor should be used. VIN2 pin, respectively, to bypass the input voltage. which greatly reduces the input voltage ripple. Table 14. VPA2000 Components Selection

1. Place the inductor and diode as close as possible to
2. Pin20 (GND1) is the power ground of the boost

output capacitors, and back to pin 20.

1. Separate all grounds on the top layer and connect all

ground connections through vias to the ground plane.

1. Locate all feedback resistor dividers close to the

the resistor dividers as short as possible.

1. Keep the traces from SWN to C GHFLY to D2 and D3
2. Keep the traces from SWN to C GLFLY to D4 and D5
3. Place output capacitors C OUT1, C LDO , and C VCORE close

o their respective output pins.

1. Keep all input decoupling capacitors close to the input

Figure 38. Optimized Layout for Boost Converter

March 11, 2010 22 APPLICATION Fi gure 39. VPA2000 Typical Application Circuit

March 11, 2010 23 PACKAGE OUTLINE DRAWING Fi gure 40. Package Outline Drawing

Table 15. Ordering Summary

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