VP7610

VP7610 ZARLINK | Alldatasheet

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COLOUR DIGITAL VIDEO CAMERA DECODER IC The VP7610 iCamHost™ Processor chip can decode the signals from a variety of iVision™ compatible digital video cameras (such as Silicon Vision’s iCam™) and process them for use in a host computer system. Digital cameras can offer real cost and performance gains in applications which require a digital video input, and iVision technology realises both these benefits. In a typical analog camera the digitised output from the CCD imager is normally encoded into an analog composite video signal which then has to be re- digitised at the input to the host system. By employing the iVision approach the output from the camera is maintained as a digital signal, but in a format which allows for a low cost 9- wire connection to the host. Eliminating the unnecessary conversion to an analog signal and back again not only saves cost, but also avoids any possible degradation of image quality. Other benefits include direct control of the camera from the host and the ability to power the camera from the host system so saving the cost of a separate power supply. The VP7610 supports two software selectable CamPort™ interface ports, either of which can receive the digital video from an iVision™ compatible digital video camera. The output is a standard colour digital video signal, similar to standard composite analog-digital decoder chips such as the Philips SAA7110 and SAA7111. All iCamHost™ operating modes are controlled by the host PC via an I 2C interface. Hardware I/O controls include output enable and I2C address offset. NOTE: iCamTM , CamPort™ and iCamHost™ are trademarks of Silicon Vision, Inc., Fremont, CA. DS4585 - 1.6 AUGUST 1996

FEATURES

n Accommodates different camera configurations based on a variety of CCD imager resolutions n Requires only a small, low-cost 9 pin mini-DIN to connect to camera n Receives the image signal from the camera in digital form at a frame rate determined by the host n Decodes all necessary synchronization and clock signals from the digital data stream n Programmable gamma correction curve in RGB colourspace n Programmable colour-separation matrix n Collects image status data within user-defined rectangular gated zone of CCD sensor n Programmable horizontal and vertical aperture correction n Pin-strap selectable output format in 16 bit YUV 4:2:2 or 8 bit CCIR 656 YUV 4:2:2 n Test pattern generator for SMPTE colourbars n Bypass mode to output unprocessed 8 bit CCD pixel samples in the luminance channel n Dual iCamPort™ camera input ports, software selectable n Completely iVision™ Compatible Fig.1 Functional Block Diagram PORT A I2 C UV RGB C M Y G CC IR6 01 or CC IR6 56

768 X 8 X 2

& FILTERING CHROMINANCE & LUMINANCE METRICS OUTPUT FORMATTER SERIAL BUS CONTROLLER COLOUR MATRIX CONVERTER PIXEL SEPARATOR RAM CONTROL 2H LINE DELAY FIFO RAM DEMUX & SYNC RECOVERY GAMMA CORRECTION COLOUR SPACE CONVERSION APERTURE CORRECTION OUTPUT ENABLE FIELD & COLOUR FLAGS ADDRESS OFFSET SYNC & CLK

The VP7610 iCamHost™ is a fully synchronous real-time pipeline pixel processor for converting digitized CCD photosite samples into co-sited, colour calibrated, gamma corrected and aperture corrected digital video in an industry- conventional format similar to analog video decoders. The VP7610 supports the full iVision™ Command Set for control of camera head functions such as frame rate, resolution, exposure and colour depth via the CamPort™ Interface. Access to all registers and functions is provided by an I C state machine. Demux and sync recovery The incoming CCD photosite bytes come in a single nibble at a time in a “bi-endian” fashion from one of two CamPort™s. These nibbles are clocked in via a separate pixel clock signal. The formatting signals such as start of active video, end of active video, and start of new frame are all encoded into the nibble stream. The output is an 8 bit byte of CCD sample for each pixel clock, as well as separate horizontal and vertical sync signals. RAM control & 2H line delay FIFO RAM Since the iCamHost™ assumes an interlaced scanning CCD with a CMYG colour mosaic format, the colour content is derived from different locations around where the output video pixel is desired. Specifically, the first line from the CCD contains “red-like” colour content, alternating with the following line containing “blue-like” colour content. The third line is real-time, and the first opportunity to output properly co- sited luminance and chrominance as though the colour pixels were superimposed upon themselves, all on the second line. Pixel separator Since the colourspace converter requires the 3 most recent lines of CCD data, this block handles the shuffling of either the 2 red and 1 blue line, or 2 blue and 1 red line of data. Colour matrix converter The input to this converter is derived from the relative sums and differences of the above 3 lines of sample data, and processes them through a programmable 3x3 matrix multiplier. The output is colour-separated and calibrated RGB samples. Gamma corrector Since CRT monitors have a non-linear RGB intensity response to input signal, gamma correction must be performed in RGB space as well to prevent cross-coupling errors between luminance and chrominance. This block is a programmable 16 line-segment curve generator to provide not only gamma correction, but any arbitrary contiguous curve of positive slope, with end points at any level to adjust contrast and range. Colourspace converter Since the output of the processor is to be YUV and not RGB, a fixed-coefficient 3x3 matrix converter is used. Chrominance sub-sampling & filtering Spatial sub-sampling and filtering is performed since the output sampling format must be reduced from 4:4:4 to 4:2:2 because most video systems do not require more chrominance data for video camera input. Output formatter Devices taking digital video input such as capture, graphics and compression chips usually require the YUV to be formatted either in 16 bit (YU then YV) mode or 8 bit (U then Y then V then Y) mode. The output mode is pin-strap selectable. An output enable input signal may be used when sharing a data bus with other video decoders. Other useful signals such as field and colour flags are also provided. Aperture corrector Since both the luminance and chrominance are derived from spatially spread pixels and the ideal output would be as though all the pixels were superimposed upon one another, a programmable vertical and horizontal aperture correction can be applied to either “soften” or “sharpen” the image. Scene-sensing luminance and chrominance metrics There are no hard-wired closed-loop control circuits in the processor. To achieve great flexibility in control over the behavior of the camera head and processor system, a user- defined region of interest is programmed which provides statistical information about the field of video only within that region. Peak luminance, total luminance, total red chrominance and total blue chrominance are provided and updated after each field. Serial bus control To provide read-write control over the registers within the processor, a standard I 2C state-machine is provided. Its address may be offset by 3 bits to preclude address conflicts.

Colour Calibration Matrix 78 bit 9x9 bit signed coefficients converting CMYG to RGB Gating Zone Start Pixel 16 bits 8 bits for column # and for row #, in 4 pixel increments Gating Zone End Pixel 16 bits 8 bits for column # and for row #, in 4 pixel increments Gamma Correction 128 bit Locus of 16 points of 8 bits each forms many curves Horiz. Aperture Correction 4 bits 00H = 0%, 40H = +100%, 70H = +175%, F0H= -175% Vert. Aperture Correction 4 bits 00H = 0%, 40H = + 50%, 70H = + 87%, F0H= - 87% Processor bypass 2 bits 0=normal, 1=pass raw 8 bit samples to Y output pins CamPort TM select 1 bit 0=port A, 1=port B Test pattern generator 1 bits 0=live video, 1=colourbars PARAMETER MAXIMUM VALUE OR SPECIFICATION CCD Resolution Up to 768 pixels per line Field Rate Up to 60 fields per second Video Sample Rate 30 MHz. max. input clock rate, 15MHz. max. output clock rate Video Sample Quantization 8 bit samples in 2 nibbles of 4 bits each Control Signals Standard I 2C protocol Configuration Inputs I 2C address offset, output enable Gamma Correction Programmable via 16 arbitrary connected line segments Output Format CCIR601 compliant 4:2:2 digital video, pixels per line=CCD pixels Output Colourspace YCrCb luminance & chrominance Output Signals 16 bit digital video, H & V sync, 1X & 2X clock, field ID, chroma ID Power Consumption 950mW PERFORMANCE STATUS REGISTERS FUNCTION SIZE DESCRIPTION Gated Luminance Sum 32 bits Sum of luminance values within gated zone Gated Luminance Peak 8 bits Value of peak luminance pixel(s) within gated zone Gate Red Chrominance Sum 32 bits Sum of red chrominance values within gated zone Gated Blue Chrominance Sum 32 bits Sum of blue chrominance values within gated zone CONTROL REGISTERS

Pin # I/O Name Description 60 In* CPCLK Clock - This input receives the clock from the CamPort™ camera on port A.

54 In* CPD3 CamPort™ Data Bit 3 - This bus receives the data from the CamPort™ camera on port

55 In* CPD2 CamPort™ Data Bit 2 - Port A

56 In* CPD1 CamPort™ Data Bit 1 - Port A

59 In* CPD0 CamPort™ Data Bit 0 - Port A

88 In* CPCKB CamPort™ B Clock - This input receives the clock from the CamPort™ camera on port

84 In* CPDB3 CamPort™ B Data Bit 3 - This bus receives the data from the CamPort™ camera on

port B.

85 In* CPDB2 CamPort™ B Data Bit 2

86 In* CPDB1 CamPort™ B Data Bit 1

87 In* CPDB0 CamPort™ B Data Bit 0

91 Out CPSEL CamPort™ Select Status - When this output is low, the data from CamPort™ A is being

used, when this output is high, the data from CamPort™ B is being used. This pin is controlled by Bit 3 of the Configuration Register (sub-address = 0x00)

44 In RSTN Reset Not - When this Schmidtt trigger input is low, the chip is placed into a known

state. When this input is high, the chip can operate. 11 Out YY7 Luminance Out bit 7 - When CCSEL is low this bus carries the luminance data. When CCSEL is high this bus carries multiplexed luminance and chrominance data

10 Out YY6 Luminance Out bit 6

9 Out YY5 Luminance Out bit 5

6 Out YY4 Luminance Out bit 4

5 Out YY3 Luminance Out bit 3

4 Out YY2 Luminance Out bit 2

3 Out YY1 Luminance Out bit 1

2 Out YY0 Luminance Out bit 0

23 Out UV7 Chrominance Out bit 7 - When CCSEL is low this bus carries the chrominance data. When CCSEL is high this bus carries a constant value of 0x80 (128).

22 Out UV6 Chrominance Out bit 6

21 Out UV5 Chrominance Out bit 5

20 Out UV4 Chrominance Out bit 4

17 Out UV3 Chrominance Out bit 3

16 Out UV2 Chrominance Out bit 2

15 Out UV1 Chrominance Out bit 1

14 Out UV0 Chrominance Out bit 0

24 Out CLK2 Clock Out 2X - This clock runs at twice the pixel rate

27 Out CLK1 Clock Out 1X - This clock runs at the pixel rate. 34 In OUTEN Output Enable - When this input is high, the signals YY[7..0], UV[7..0], HSYNC, VSYNC, CLK2, CLK1, HACT, VACT, FIELD and BFLAG are driven. When this input is low, these signals are high-impedance. SIGNALS & PINOUT * CamPort inputs are TTL levels. All other inputs are CMOS. See Static Electrical Characteristics table.

12 Out VSYNC Vertical Sync - This signal goes low for 3 horizontal lines to mark the beginning of each

field. In Odd fields, it starts and ends when HSYNC and HACT are low. In Even fields, it starts and ends when HSYNC and HACT are high.

13 Out HSYNC Horizontal Sync - This signal goes low and returns high in the horizontal blanking

interval, to mark the beginning of each line.

28 Out HACT Horizontal Active - This signal is high when there is valid video data on the luminance

and chrominance busses. Data is valid only when this signal and VACT are high.

29 Out VACT Vertical Active - This signal is high when there is valid video data on the luminance and

chrominance busses. Data is valid only when this signal and HACT are high. 30 Out FIELD Field Flag - This signal indicates the field. When it is low, the field is odd. When it is high, the field is even.

31 Out BFLAG Blue Flag - This signal indicates when Blue chrominance data is on the chrominance

bus. 35 In CCSEL CCIR 656 Select - When this input is high, the YY[7..0] bus carries multiplexed lumi- nance and chrominance data in conformance with CCIR 656. When this signal is low, the YY[7..0] bus carries only luminance data.

36 In RCLK Register Clock - This input clocks the control circuitry in the chip and must be running in

order to access the registers via the I2C bus. The frequency on this input should be between 10 and 20 MHz. 38 In INVI Inverter In - This CMOS Schmidt trigger input controls the INVO output. This inverter can be used to form an RC oscillator to drive the input RCLK. It is typically connected through a resistor to INVO and through a capacitor to GND. This oscillator has a period roughly equal to the time constant R*C. 37 Out INVO Inverter Out - This signal outputs the opposite level from that applied to INVI. If this inverter is used to form an RC oscillator, this pin would be connected to RCLK.

42 In OSXI Oscillator Crystal Input - The crystal oscillator is another way to produce a clock for the

input RCLK. A crystal is connected between this input and OSXO. 41 Out OSXO Oscillator Crystal Output - A crystal is connected between this output and OSXI.

39 Out OSCO Oscillator Output - If the crystal oscillator is used to produce the register clock, this

CMOS output drives the RCLK input.

45 In IAD3 I

2C Address Select Bit 3 - The IAD[3..1] inputs select the I2C address that the chip will respond to. The address is 0x60 + 8 * IAD3 + 4 * IAD2 + 2 * IAD1.

43 In IAD2 I 2C Address Select Bit 2

40 In IAD1 I 2C Address Select Bit 1

48 In SDAI Serial Data In - This input is connected to the I 2C Data line. It may be connected through a filter to reduce noise susceptibility. 47 Out SDAO Serial Data Out - This open-drain output connects directly to the I2C Data line. 48 Out SDMN Serial Data Monitor - This output is low when the SDAO output is driving low. This output is high when the SDAO output is high impedance. 49 In SCLI Serial Clock In - This input is connected to the I 2C Clock line. It may be connected through a filter to reduce noise susceptibility.

89 Out SCLOA Serial Clock Out Port A - This output drives the level on the SCLI input when the

CamPort™ A is selected. When the CamPort™ B is selected this output is driven high. This is not an open-drain output.

90 Out SCLOB Serial Clock Out Port B - This output drives the level on the SCLI input when the

CamPort™ B is selected. When the CamPort™ A is selected this output is driven high. This is not an open-drain output. 52 In TST0 Test Pin - This pin should be tied low.

53 In TST1 Test Pin - This pin should be tied low. 61 In TST2 Test Pin - This pin should be tied low. 62 In TST3 Test Pin - This pin should be tied low. 63 In TST4 Test Pin - This pin should be tied low. 71 In TSTOE Test Output Enable - This pin should be tied high. Out TOUT Test Outputs - These pins should be unconnected. In GND Power In VDD Power 64, 65, 66, 67, 70, 72, 73, 74, 77, 78, 79, 80, 81, 92, 93, 94, 95, 96, 97, 98, 99 1, 7, 19, 25, 32, 51, 57, 69, 75, 82, 8, 18, 26, 33, 50, 58, 68, 76, 83, 100 REGISTER DESCRIPTIONS The VP7610 iCamHost™ processor station address is strap-configurable to any even location between 0x60 and 0x6E inclusive. Since most iCam cameras currently built use the Station Address 0x68, it is recommended that the iCamHost™ be strapped to a different address. The register addresses shown below are the sub-addresses written to the iCamHost™ immediately after the Station Address. The 7 LSBs of the sub-address must match the specified address. The MSB of the sub-address controls the auto-increment feature of the iCamHost™. If the MSB of the sub-address is a ‘1’, (sub-addresses 0x80 through 0xFF), the sub-address register in the iCamHost™ is incremented to the next address immediately after the data register is read or written. If the MSB of the sub-address is a ‘0’, (sub-addresses 0x00 through 0x7F), the sub-address register in the iCamHost™ remains constant regardless of any reads or writes to the data register. Address 0x00 Configuration Control Register Read/Write Bits 7 - 4 Always read as ‘0’ Bit 3 Cfg3 - Camera Input Port Enable ‘1’ CamPort™ ‘B’ is source ‘0’ CamPort™ ‘A’ is source Bit 2 Cfg2 - Colour Bar Enable ‘1’ Colour Bar Test Pattern Output ‘0’ Normal Video Output Bit 1 Cfg1 - RGB to YUV Converter Bypass ‘1’ Green + BnR Pattern Output ‘0’ Normal YUV Output Bit 0 Cfg0 - Separator Bypass ‘1’ Sum = CCD Data, Diff = 0 ‘0’ Normal Separator Output Cfg3 Cfg2 Cfg1 Cfg0

Address 0x02 Peak Luma Filter Control Register Read/Write Bits 7 - 3 Always read as ‘0’ Bits 2 - 0 Peak Luma Filter Control ‘000’ - PLF K = 1, No Luma Filter ‘001’ - PLF K = 1/2, Fast Luma Filter ‘010’ - PLF K = 1/4, Med Fast Luma Filter ‘011’ - PLF K = 1/8, Med Slow Luma Filter ‘1XX’ - PLF K = 1/16, Slow Luma Filter Address 0x01 RESERVED Address 0x04 Horizontal Start Register Read/Write Bits 7 - 0 Horizontal Start Register Four times the value of this register is the Horizontal starting pixel for the Metrics window. Address 0x05 Horizontal Stop Register Read/Write Bits 7 - 0 Horizontal Stop Register Four times the value of this register is the Horizontal ending pixel for the Metrics window. Address 0x06 Vertical Start Register Read/Write Bits 7 - 0 Vertical Start Register Four times the value of this register is the Vertical starting line (in the frame) for the Metrics window (two times in the field). Address 0x07 Vertical Stop Register Read/Write Bits 7 - 0 Vertical Stop Register Four times the value of this register is the Vertical ending line (in the frame) for the Metrics window (two times in the field). HStop7 HStop6 HStop5 HStop4 HStop3 HStop2 HStop1 HStop0 VStrt7 VStrt6 VStrt5 VStrt4 VStrt3 VStrt2 VStrt1 VStrt0 VStop7 VStop6 VStop5 VStop4 VStop3 VStop2 VStop1 VStop0 PLF2 PLF1 PLF07 HStrt7 HStrt6 HStrt5 HStrt4 HStrt3 HStrt2 HStrt1 HStrt0

Address 0x08 Horizontal Aperture Control Register Read/Write Bits 7 Horizontal Aperture Sign Bit ‘1’ Correction is negative (blurring) ‘0’ Correction is positive (sharpening) Bits 6 - 4 Horizontal Aperture Control Value ‘000’ - No Aperture Correction ‘111’ - Maximum Aperture Correction Bits 3 - 0 Always read as ‘0’ Address 0x09 Vertical Aperture Control Register Read/Write Bits 7 Vertical Aperture Sign Bit ‘1’ Correction is negative (blurring) ‘0’ Correction is positive (sharpening) Bits 6 - 4 Vertical Aperture Control Value ‘000’ - No Aperture Correction ‘111’ - Maximum Aperture Correction Bits 3 - 0 Always read as ‘0’ Address 0x0E Hardware Version Register Read Only Bits 7 - 0 Hardware Version Register 0x01 - Zeus II Board Rev 0.1 0x10 - CHP-7600 Rev 1.0 0x11 - CHP-7610 Rev 1.1 Address 0x0F Timing Status Register Read Only Bits 7 - 2 Field Count A number between 0 and 63 which increments at the beginning of every Vertical Blanking Interval Bit 1 Field Bit ‘1’ Even Field - Digital Field 2 ‘0’ Odd Field - Digital Field 1 Bit 0 Vertical Blanking ‘1’ Vertical Blanking Interval ‘0’ Vertical Active Interval VApt7 VApt6 VApt5 VApt4 HVer7 HVer6 HVer5 HVer4 HVer3 HVer2 HVer1 HVer0 FCnt5 FCnt4 FCnt3 FCnt2 FCnt1 FCnt0 Fld VBlk HApt7 HApt6 HApt5 HApt4

Address 0x10 Lower Byte Red Chroma Register Read Only This register contains Bits 07 - 00 of the Sum of the Red Chrominance of the pixels within the Metrics window. Address 0x11 Lower Middle Byte Red Chroma Register Read Only This register contains Bits 15 - 08 of the Sum of the Red Chrominance of the pixels within the Metrics window. Address 0x12 Upper Middle Byte Red Chroma Register Read Only This register contains Bits 23 - 16 of the Sum of the Red Chrominance of the pixels within the Metrics window. Address 0x13 Upper Byte Red Chroma Register Read Only This register contains Bits 31 - 24 of the Sum of the Red Chrominance of the pixels within the Metrics window. Address 0x14 Lower Byte Blue Chroma Register Read Only This register contains Bits 07 - 00 of the Sum of the Blue Chrominance of the pixels within the Metrics window. Address 0x15 Lower Middle Byte Blue Chroma Register Read Only This register contains Bits 15 - 08 of the Sum of the Blue Chrominance of the pixels within the Metrics window. Address 0x16 Upper Middle Byte Blue Chroma Register Read Only This register contains Bits 23 - 16 of the Sum of the Blue Chrominance of the pixels within the Metrics window. Address 0x17 Upper Byte Blue Chroma Register Read Only This register contains Bits 31 - 24 of the Sum of the Blue Chrominance of the pixels within the Metrics window. Address 0x18 Lower Byte Luminance Register Read Only This register contains Bits 07 - 00 of the Sum of the Luminance of the pixels within the Metrics window. Address 0x19 Lower Middle Byte Luminance Register Read Only This register contains Bits 15 - 08 of the Sum of the Luminance of the pixels within the Metrics window. Address 0x1A Upper Middle Byte Luminance Register Read Only This register contains Bits 23 - 16 of the Sum of the Luminance of the pixels within the Metrics window. Address 0x1B Upper Byte Luminance Register Read Only This register contains Bits 31 - 24 of the Sum of the Luminance of the pixels within the Metrics window. Address 0x1C Peak Luminance Register Read Only This register contains the peak value of the filtered Luminance of the pixels within the Metrics window. Address 0x20 Sum to Red Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Red signal from the Sum signal. Address 0x21 AmB to Red Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Red signal from the AmB signal. Address 0x22 CmD to Red Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Red signal from the CmD signal.

Address 0x23 Red Coefficients Sign Register Read/Write Bit 1 Sign for CmD to Red Coefficient Bit 0 Sign for AmB to Red Coefficient ‘1’ Coefficient is negative ‘0’ Coefficient is positive Address 0x24 Sum to Green Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Green signal from the Sum signal. Address 0x25 AmB to Green Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Green signal from the AmB signal. Address 0x26 CmD to Green Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Green signal from the CmD signal. Address 0x27 Green Coefficients Sign Register Read/Write Bit 1 Sign for CmD to Green Coefficient Bit 0 Sign for AmB to Green Coefficient ‘1’ Coefficient is negative ‘0’ Coefficient is positive Address 0x28 Sum to Blue Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Blue signal from the Sum signal. Address 0x29 AmB to Blue Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Blue signal from the AmB signal. Address 0x2A CmD to Blue Coefficient Register Read/Write This register contains the magnitude of the Coefficient which determines the contribution to the Blue signal from the CmD signal. Address 0x2B Blue Coefficients Sign Register Read/Write Bit 1 Sign for CmD to Blue Coefficient Bit 0 Sign for AmB to Blue Coefficient ‘1’ Coefficient is negative ‘0’ Coefficient is positive Addresses 0x30 - 0x3F Gamma Values Write Register Write The 16 values that are written to these 16 registers determine the breakpoints in the Gamma correction circuit. The breakpoint values should be written in ascending order starting at address 0x30. Addresses 0x30 - 0x3F Gamma Values Read Register Read The breakpoints in the Gamma correction circuit are read from these registers. GCmD GAmB BCmD BAmB RCmD RAmB

RCLK to output (CPSEL, SDAO, SDMN) rising edge of CPCKA or CPCKB to output (YY[7..0], UV[7..0], CLK1, VSYNC, HSYNC,VACT, HACT, BFLAG) falling edge of CLK2 to output (YY[7..0], UV[7..0], CLK1, VSYNC, HSYNC, VACT, HACT, BFLAG) rising edge of CLK2 to output (YY[7..0], UV[7..0], CLK1,VSYNC, HSYNC, VACT, HACT, BFLAG) falling edge of CLK1 to output (YY[7..0], UV[7..0],VSYNC, HSYNC, VACT, HACT, BFLAG) rising edge of CLK1 to output (YY[7..0], UV[7..0], VSYNC, HSYNC, VACT, HACT, BFLAG) propagation delay from CPCKA or CPCKB to CK2 propagation delay from INVI to INVO propagation delay from SCLI to SCLOA or SCLOB (0.4*tCPX)-2 tCPX-3 (0.6*tCPX)+5 tCPX+3 ns ns ns ns ns ns ns ns ns fCPX tCPX dcCPX tsuCPDX thCPDX fRCK twRSTN DescriptionName frequency CPCKA or CPCKB period CPCKA or CPCKB duty cycle CPCKA or CPCKB setup time, CPDA [3..0] to CPCKA or CPDB [3..0] to CPCKB hold time, CPDA [3..0] to CPCKA or CPDB [3..0] to CPCKB frequency RCLK pulse width of RSTN Unit Min. Max. MHz ns ns ns MHz ns 100 TIMING REQUIREMENTS Value tcqRCLK tcpCPX tcqCK2f tcqCK2r tcpCK1f tcqCK1r tpdCK2 tpdINV tpdSCL DescriptionName Unit Min. TIMING CHARACTERISTICS Value Max.

Min. 0.8VDD 0.7VDD 2.0 0.8 Typ. Max. 0.4 0.2VDD 300 Output high voltage Output low voltage Input high voltage (CMOS input) Input low voltage (CMOS input) Input high voltage (TTL input) Input low voltage (TTL input) Input leakage current Input capacitance Output leakage current Output S/C current NOTES ON MAXIMUM RATINGS 1. Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied. 2. Maximum dissipation for 1 second should not be exceeded, only one output to be tested at any one time. 3. Exposure to absolute maximum ratings for extended periods may affect device reliablity. 4. Current is defined as negative into the device. ABSOLUTE MAXIMUM RATINGS [See Notes] Supply voltage VDD -0.5V to 7.0V Input voltage VIN -0.5V to VDD + 0.5V Output voltage VOUT -0.5V to VDD + 0.5V Clamp diode current per pin IK (see note 2) 18mA Static discharge voltage (HBM) 500V Storage temperature TS -55°C to 150°C Ambient temperature with power applied TAMB 0°C to 70°C Junction temperature 125 °C Package power dissipation 1000mW STATIC ELECTRICAL CHARACTERISTICS Operating Conditions (unless otherwise stated) Tamb = 0°C to +70°C VDD = 5.0v ± 5% V V V V V V µA pF µA mA VOH VOL VIHC VILC VIHT VILT IIN C IN IOZ ISC IOH = 4mA IOL = -4mA GND < VIN < VDD GND < VOUT < VDD VDD = Max Characteristic Symbol Value Units Conditions

ORDERING INFORMATION

VP7610 CG FPIR (Note: Prior to full release to production device may be designated as VP7610 PR FPIR)

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