VP510

VP510 ZARLINK | Alldatasheet

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Bi Directional Colour Space Converter Advance Information DS3507 - 1.6 September 1996

DESCRIPTION

The VP510 converts three channels of RGB data into two channels of decimated chrominance and luminance data. Alternatively it converts two channels of luminance and chromi- nance data into three channels of interpolated RGB data. Each channel has its own RAM based look up table, which can be loaded from a host system and then used for gamma correction and/or ranging. The direction of the data flow is controlled by a bit in a Control Register, and causes previous outputs to become inputs and vice versa. The filters change from the decimating to the interpolating mode, and correspondingly follow or precede the colour space conversion. The 3 x 3 conversion matrix is provided with user definable 12 bit coefficients which have a range from -4.0 to +4.0. The luminance channel is provided with a 23 tap low pass filter which can decimate or interpolate by two. The chrominance channels each have two 11 tap filters in series which can decimate or interpolate by four. This arrangement allows the device to accept or produce RGB data which has been 2x oversampled, thus avoiding the need for external analog anti- aliasing filters. If necessary the device will still accept or produce video data which has not been oversampled.

FEATURES

I User definable colour space conversion I Sampling rates up to 27 MHz I On chip decimating or interpolating FIR filters I Conversion from 24 bit inputs to 16 bit outputs or vice versa I RAM based look up tables for gamma correction I 100 pin Quad Flat Pack ASSOCIATED PRODUCTS I VP2611 Integrated H.261 Video Encoder I VP2615 H.261 Video Decoder I VP520S Two dimensional Video Filter Figure 1. Simplified Block Diagram

23 TAP

256 X 8 BITS

3 X 3

11 TAP

ORDERING INFORMATION

(Commercial Temperature - PLCC Package).

R7:0 I/O Unsigned Red data. Range may be changed by the RAM look up table G7:0 I/O Unsigned Green data. Range may be changed by the RAM look up table B7:0 I/O Unsigned Blue data. Range may be changed by the RAM look up table Y7:0 I/O Unsigned Luminance data in or out. Range is user definable C7:0 I/O Two's complement or offset binary multiplexed chrominance data. Range is user definable D7:0 I/O Host data bus used for reading or writing A4:0 I Host Address Bus. Matrix coefficients and the control register are directly addressable CLK I External line locked clock. All inputs and outputs are referenced to the rising edge HREF I Horizontal or Composite reference used as a start of line indicator and to clear the FIR filters HDLY O HREF input delayed by the 39 clock delay to a correctly filtered output FI I Input Flag as defined by the user. No internal operation. FO O FI delayed by the 39 clock delay to a correctly filtered output CRI I An input which indicates that valid luminance and chrominance data is present CRO O An output which indicates that valid luminance and chrominance data is on the output pins OEN I Active low output enable for the tristate bus. Used in conjunction with a Control Register bit CS I Active low Chip Select from the host system RD I Active low request from the host to read the matrix coefficients and RAM contents WR I Active low request from the host to write to the device RES I Asynchronous low reset used to initialise the device. Must be present for at least 1024 clock periods LOOK UP TABLES When the device is configured to produce chrominance and luminance outputs from RGB inputs, each of the three look up tables is addressed by its appropriate colour bus. Any changes to the data thus occur before the colour space conversion. Typically the look up tables are used to provide gamma correction to linear RGB inputs, and / or to limit the range of the inputs. The coefficients in the conversion matrix are usually defined to expect either a range of 1 - 254 or 16 - 235, when converting to Cr and Cb chrominance values. When the device is configured to produce RGB outputs, the look up tables are positioned just before the output buses. If linear outputs are required the tables can then be used to remove the gamma correction which is produced by the coefficients in the conversion matrix. They can also be used to expand the range produced by the conversion matrix. The RAM's are not dual ported and use by the host system takes priority over pixel accessing. The RAM's are not directly addressable from the host since the device only uses a 5 bit address bus. Instead each RAM has an internal address counter which must be cleared by writing to address decimal 27. Data is then sequentially written to the Red RAM by supplying 256 bytes of data and address 28. Similarly using address 29 will cause write operations to the green RAM, and address 30 will cause write operations to the blue RAM. The counters do not wrap around and must be reset by using address 27 before further write or read operations are re- quired. Read operations are mechanized in a similar manner to write operations, except that a read strobe must be supplied instead of a write strobe. Since each RAM has its own address counter the red, green, and blue operations can be intermin- gled on a byte by byte basis, rather than completing one colour before starting the next. Although host operations are asynchronous to the device clock, this clock must be present to internally effect a read or write operation. The read and write strobes are internally synchronized to the clock, and the read strobe must be active for at least five clock periods, and the write strobe for two clock periods. CONVERSION MATRIX The 3 x 3 matrix multiplier performs the following basic operation on three channels with identical sampling rates; O/PA c1 c2 c3 I/PA O/PB = c4 c5 c6 X I/PB O/PC c7 c8 c9 I/PC When converting from RGB to colour difference informa- tion, any decimation of the chrominance channels must be done after the above operation. Conversely when producing RGB data the chrominance channels must be interpolated before the matrix operation. The configuration bit in the Control Register takes care of this reorganization. The coefficients C9:1 are loaded from the host system, and are directly addressable using the 5 bits provided ( see Table 1 ). Each coefficient must be loaded as two bytes since it uses a total of 12 bits. The upper 4 bits in the most significant byte are don't care values. If the loaded values are read back by the host, these four bits will always be zero's, and are not sign bits. The 12 coefficient bits are comprised of 3 signed integer and 9 fractional bits. This gives a decimal range of -4.00 to approximately +3.998, with the fractional bits actually giving a decimal resolution of 0.001953. Pixel data going into the matrix multiplier uses a total of 13 bits; 10 signed integer bits plus 3 fractional bits. This additional pixel accuracy is only obtained from the output of the interpo- lating filters, where 10 integer bits are necessary to accommo- date signed data with undershoot and overshoot beyond the nominal gain.

overshoot beyond the nominal 8 bit unsigned value. will have been chosen to produce an output in the range ± 127. illustrates the bit significance at various points in the data path. converter without further rounding. Figure 3. Response of the Luminance FilterFig 2. Bit significance in the Y Filter

filter with 13.5 MHz output sampling. various points in the calculation. chrominance, the range can be represented by 8 integer bits. section on Chrominance Outputs. HREF goes active low the outputs will go low after 39 clocks. need for analog anti aliasing filters before the A/D converters. Figure 4. Bit significance Figure 5. Response of the Chrominance Filters

9.3 Un - normalized

27 MHz

before colour space conversion. forced low after the 39 clock pipeline delay. inputs will then be applied to the ranging and offset circuitry. Figure 6. RGB I/O Timing (Advanced Data) Figure 7. Chrominance I/O Timing (Advanced Data)

first converted samples are available from each line. sample without causing aliasing effects. matrix converter, which is internally represented by 13 bits. on the output pins, as shown in Figure 2. Figure 7. The CRO signal can be used as a clock enable or a half rate clock for the next component in the system. Figure 8. Chrominance and Luminance Output Options Figure 9. Host Interface Timing (Advanced Data)

8 BIT CLIPPED

greater than 255 will saturate at 255. are clipped to the maximum values allowed. since higher order bits were selected at the output of the filter. bit in the Control Register. This is illustrated in Figure 8. greater than 235 will be forced to 235. BYPASS pin is reset then the NORM bit must be set. active for the whole of the strobe times. write strobe must be active for at least 2 clock periods. not go low impedance before this pipeline delay. rectly addressable, and use the locations given in Table 1. scheme used is descibed in the section on the look up tables. that neither output bus is low impedance, even if OEN is low. description of individual bits see the releant sections.

0 OEI This bit must be set and the OEN pin must be

be controlled by software or by driving a pin.

1 SEL This bit controls the range of the luminance and

0 C1 L Byte 1 C1 H Byte

2 C2 L Byte 3 C2 H Byte

4 C3 L Byte 5 C3 H Byte

6 C4 L Byte 7 C4 H Byte

8 C5 L Byte 9 C5 H Byte

10 C6 L Byte 11 C6 H Byte

12 C7 L Byte 13 C7 H Byte

14 C8 L Byte 15 C8 H Byte

16 C9 L Byte 17 C9 H Byte

27 RAM Address Reset

28 R/W Red RAM

29 R/W Green RAM

30 R/W Blue RAM

31 Control Register

Table 1. Internal Address Map

3 BYPASS This bit should be reset when Cr Cb data is to

being processed. NORM must then be set.It should be set when the ranging and offset circuit is to be bypassed.

4 NORM When this bit is reset the chrominance outputs

are not normalized, and the 8 bit outputs rep resent a range of ±1. When NORM is set the outputs will represents a range of ±0.5, still using 8 bits. 7:5 Reserved. Must all be reset. CONVERSION BETWEEN RGB AND YUV If incoming, gamma corrected, analog RGB is normalized to a range of 0 to 1, then the following coefficients will produce YUV outputs. Y will have a range of 0 to 1, U will have a range of ±0.436, and V will have a range of ±0.615. The NORM bit must be reset, and the BYPASS bit set. The 8 bit chrominance outputs then represent a possible range of ±1. Y 0.299 0.587 0.114 R U = -0.147 -0.289 0.436 G V 0.615 -0.51 -0.100 B The coefficients given below will produce gamma cor- rected RGB normalized to a range of ±1, when YUV have the ranges given above. R 1 0 1.140 Y G = 1 -0.395 -0.581 U B 1 2.032 0 V These coefficients translate to the following HEX values, which define the 12 bit number to be loaded. Note that these are given as simple three digit HEX values, without a separate 3 bit integer and 9 bit fractional part. Y 099 12C 03A R U = F64 F6C 0DF G V 13A EF8 FCC B R 200 000 247 Y G = 200 F35 ED6 U B 200 410 000 V If normalized digital UV components are required, the coefficients must be modified as given below. The NORM and BYPASS bits should then be set. The U I/O range is expanded to ±0.5, and the V I/O range is compressed to the same values. Y has an I/O range of 0 to 255. The 8 bit chrominance outputs now represent a range of ±0.5. Y 0.299 0.587 0.114 R U = -0.169 -0.331 0.500 G V 0.5 -0.419 -0.081 B R 1 0 1.42 Y G = 1 -0.344 -0.714 U B 1 1.772 0 V The equivalent HEX values which be loaded into the device are given below; Y 099 12C 03A R U = FA9 F56 100 G V 100 F29 FD6 B R 200 000 2CD Y G = 200 F4F E92 U B 200 38B 000 V CONVERSION BETWEEN RGB AND YIQ The coefficients for converting analog RGB to YIQ are given below. The gamma corrected RGB inputs have a range of 0 to 1. Analog I and Q have ranges of ±0.596 and ±0.525 respectively, and the NORM bit must be reset to produce 8 bit outputs representing a range of ±1. The BYPASS bit must be set. Y 0.299 0.587 0.114 R I = 0.596 -0.275 -0.321 G Q 0.212 -0.523 0.311 B In the opposite direction the following coefficients produce gamma corrected RGB, when the YIQ inputs have the ranges given above. R 1 0.956 0.620 Y G = 1 -0.272 -0.647 I B 1 -1.108 1.705 Q In HEX these values become; Y 099 12C 03A R I = 131 F73 F5B G Q 06C EF4 09F B R 200 1E9 139 Y G = 200 F74 EB4 I B 200 SDC8 368 Q The conversion between digital RGB and normalized digital YIQ requires the following coefficients. I and Q are then compressed to fall in the range of ±0.5, and the NORM bit must be set since the 8 bit chrominance outputs now represent ±0.5. The BYPASS bit must also be set. Y 0.299 0.587 0.114 R I = 0.500 -0.231 -0.269 G Q 0.203 -0.500 0.297 B R 1 1.139 0.648 Y G = 1 -0.324 -0.677 I B 1 -1.321 1.783 Q These correspond to the HEX coefficients gven below; Y 099 12C 03A R I = 100 F89 F76 G Q 068 F00 098 B

G = 200 F5A EA5 I B 200 D5B 391 Q CONVERSION FROM Y Cr Cb TO RGB The analog conversion matrix is given below; R = Y + 1.402( Cr - 128 ) G = Y - 0.714( Cr - 128 ) - 0.344( Cb - 128 ) B = Y +1.772( Cb - 128 ) If the Y Cr Cb ranges are all 1 to 254, then the RGB range produced will be 1 to 254. If the Y range is 16 to 235 and the Cr Cb ranges are 16 to 240, then the expected RGB range is 16 to 235. Incoming Y CR Cb data can be adjusted to either of these ranges by using the SEL bit in the Control Register. The input circuit also does the necessary subtraction of 128 from the Cr and Cb values ( the BYPASS bit must be reset ). The resulting HEX values which must be loaded into the coefficient store are given below; C1 C2 C3 200 2CE 0 C4 C5 C6 = 200 E92 F50 C7 C8 C9 200 0 38B The digital conversion matrix is given below; R = Y + 1.37( Cr - 128 ) G = Y - 0.698( Cr - 128 ) - 0.336( Cb - 128 ) B Y + 1.73( Cb - 128 ) The corresponding HEX values are given below; C1 C2 C3 200 2BD 0 C4 C5 C6 = 200 E9B F54 C7 C8 C9 200 0 376 The digitalmatrix only functions correctly when the Y range is 16 to 235 and the Cr Cb ranges are 16 to 240. The RGB range produced should then be 16 to 235. Both the SEL and BYPASS bits should thus be reset. CONVERSION FROM RGB TO Y Cr Cb The analog matrix is given below; Y = 0.299R + 0.587G + 0.114B Cr = 0.5R - 0.419G - 0.081B + 128 Cb = -0.169R - 0.331G + 0.5B + 128 This can handle RGB ranges of either 1 to 254 or 16 to 235. If necessary the RAM based look up tables can be used to limit the range of the incoming RGB. The BYPASS bit must always be reset, and the NORM bit set, when producing Cr and Cb data. The SEL bit is used to limit the range of the YCr Cb values which are outputed. When SEL is set all three output ranges are 1 to 254. When it is reset the Y range is 16 to 235, and the Cr Cb ranges are 16 to 240. Values ouside the range limits will be forced to the correct maximum or minimum value. The offset of 128 is added to the Cr Cb values before the ranging is done. The HEX values which correspond to the analog matrix are given below; C1 C2 C3 99 12D 3A C4 C5 C6 = 100 F29 FD7 C7 C8 C9 FA9 F57 100 In the CCIR601 specification the digital matrix is ex- pressed as fractions of 256, and is given below; Y = 77/256R + 150/256G + 29/256B Cr = 131/256R - 110/256G - 21/256B + 128 Cb = -44/256R - 87/256G + 131/256B + 128 The HEX values which correspond to this digital matrix are given below; C1 C2 C3 9A 12C 3A C4 C5 C6 = 106 F24 FD6 C7 C8 C9 FA8 F52 106 This matrix expects the RGB inputs to be in the range of 16 to 235, and also the SEL bit to detemine the output range. CONVERSION BETWEEN RGB AND Y,R- Y,AND B-Y The analog matrices used to convert between RGB and Y Cr Cb can also be used with normalized colour difference information. The BYPASS bit must, however, be reset to avoid the 128 offset circuitry. RGB and Y inputs and outputs will have a range of 0 to 255. Colour difference inputs and outputs will have a range of -128 to +127 ( ±0.5 ). The NORM bit should always be set. When working with analog colour difference values the following coefficients should be used, with the NORM bit reset. R - Y will have a range of ±0.701, and B - Y a range of ±0.886. Y 0.299 0.587 0.114 R B-Y -0.299 -0.587 0.886 B R = 1 1 0 Y G 1 -0.509 -0.194 R-Y B 1 0 1 B-Y The corresponding HEX values are given below; Y 099 12C 03A R R-Y = 167 ED3 FC6 G B-Y F67 ED3 1C6 B R 200 200 0 Y G = 200 EFB F9D R-Y B 200 0 200 B-Y

Figure 11. Y Cr Cb response to step changes in RGB filters will always be identical since they use identical circuits. The Red channel uses a different interpolating filter. Figure 10. RGB Response to step changes in Y Cr Cb

27 MHZ CLOCK PERIODS

13.5 MHZ CLOCK PERIODS

ABSOLUTE MAXIMUM RATINGS [See Notes] Supply voltage Vcc -0.5V to 7.0V Input voltage VIN -0.5V to Vcc + 0.5V Output voltage VOUT -0.5V to Vcc + 0.5V Clamp diode current per pin IK (see note 2) 18mA Static discharge voltage (HMB) 500V Storage temperature T S -65°C to 150°C Ambient temperature with power applied TAMB 0°C to 70°C Junction temperature 100 °C Package power dissipation 1000mW Delay from output high to output high impedance Test Waveform - measurement le vel Delay from output low to output high impedance HV 0.5V V 0.5V L 1.5V 0.5V 1.5V 0.5V Delay from output high impedance to output low Delay from output high impedance to output high V - Voltage reached when output driven hig V - Voltage reached when output driven low H L NOTES ON MAXIMUM RATINGS 1. Exceeding these ratings may cause permanent damage. Functional operation under these conditions is not implied. 2. Maximum dissipation or 1 second should not be exceeded, only one output to be tested at any one time. 3. Exposure to absolute maximum ratings for extended periods may affect device reliablity. 4. Current is defined as negative into the device. Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input leakage current Input capacitance Output leakage current Output S/C current Conditions I OH = 4mA IOL = -4mA 3V for CLK GND < VIN < VCC GND < VOUT < VCC VCC = Max Units V V V V µA pF µA mA Symbol VOH VOL VIH VIL IIN CIN IOZ ISC Min. 3.4 2.0 -10 -50 Max. 0.4 0.8 +10 +50 300 Value Typ. STATIC ELECTRICAL CHARACTERISTICS Operating Conditions (unless otherwise stated) Tamb = 0 C to +70°C Vcc = 5.0v ± 10% FUNCTION PIN NC 1 NC 2 NC 3 VDD 4 CLK 5 RES 6 GND 7 OEN 8 GND 9 FI 10 NC 11 HREF 12 FO 13 HDLY 14 CRI 15 CRO 16 GND 17 VDD 18 R7 19 R6 20 R5 21 R4 22 R3 23 R2 24 R1 25 FUNCTION PIN C0 76 NC 77 GND 78 NC 79 NC 80 VDD 81 D7 82 D6 83 D5 84 D4 85 D3 86 D2 87 D1 88 D0 89 GND 90 VDD 91 A4 92 A3 93 A2 94 A1 95 A0 96 CS 97 RD 98 WR 99 GND 100 Pin Out Diagram

Internet: http://www.gpsemi.com CUSTOMER SERVICE CENTRES G FRANCE & BENELUX Les Ulis Cedex Tel: (1) 69 18 90 00 Fax : (1) 64 46 06 07 G GERMANY Munich Tel: (089) 419508-20 Fax : (089) 419508-55 G ITALY Milan Tel: (02) 6607151 Fax: (02) 66040993 G JAPAN Tokyo Tel: (03) 5276-5501 Fax: (03) 5276-5510 G KOREA Seoul Tel: (2) 5668141 Fax: (2) 5697933 G NORTH AMERICA Scotts Valley, USA Tel: (408) 438 2900 Fax: (408) 438 5576/6231 G SOUTH EAST ASIA Singapore Tel:(65) 3827708 Fax: (65) 3828872 G SWEDEN Stockholm Tel: 46 8 702 97 70 Fax: 46 8 640 47 36 G TAIWAN, ROC Taipei Tel: 886 2 25461260 Fax: 886 2 27190260 G UK, EIRE, DENMARK, FINLAND & NORWAY Swindon Tel: (01793) 726666 Fax : (01793) 518582 These are supported by Agents and Distributors in major countries world-wide. © Mitel Corporation 1998 Publication No. DS3507 Issue No. 1.6 September 1996 TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM HEADQUARTERS OPERATIONS MITEL SEMICONDUCTOR Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (01793) 518000 Fax: (01793) 518411 MITEL SEMICONDUCTOR

1500 Green Hills Road,

Scotts Valley, California 95066-4922 United States of America. Tel (408) 438 2900 Fax: (408) 438 5576/6231 This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request. All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners. VP510 CG GPFR (Commercial Temperature - PLCC Package).

www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I 2C Patent rights to use these components in and I 2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE For more information about all Zarlink products visit our Web Site at