VP310

VP310 MITEL | Alldatasheet

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SHORTFORM TECHNICAL MANUAL DS 5155 -1.00 21/04/99

Ordering Information

VP310 - Key Features VP310 CG GQ1R

• Conforms to EBU specification for DVB-S and DirecTV specification for DSS.
• On-chip digital filtering supports 1 to 45MBaud Symbol rates.
• On-chip 6-bit 60 or 90MHz dual-ADC.
• High speed scanning mode for blind symbol rate and code rate acquisition.
• Up to ± 15MHz LNB frequency tracking.
• Fully digital timing and phase recovery loops.
• High level software interface for minimum development time.
• DiSEqC™ v1.1: control outputs for full control of LNB and dish.

Applications

• DVB 1 to 45MBaud compliant satellite receivers.
• DSS 20MBaud compliant satellite receivers.
• SCPC receivers. (Single Channel Per Carrier)
• SMATV trans-modulators. (Single Master Antenna TV)
• LMDS. (Local Multipoint Distribution Service)
• Satellite PC applications. The VP310 is a QPSK/BPSK 1 to 45MBaud demodulator and channel decoder for digital satellite television transmissions to the European Broadcast Union ETS 300 421 specification. It receives analog I and Q signals from the tuner, digitises and digitally demodulates this signal, and implements the complete DVB/DSS FEC (Forward Error Correction), and de-scrambling function. The output is in the form of MPEG2 or DSS transport stream data packets. The VP310 also provides automatic gain control to the RF front-end devices. The VP310 has a serial I²C port interface to the control microprocessor. Minimal software is required to control the VP310 because of the built in automatic search and decode control functions.

standards and other systems, such as LMDS, that use the same architecture. initialisation and basic channel change are included in section 2. also after the Viterbi module. For receiver installation, a high speed scan or ‘blind search’ mode is available. symbol rate and convolutional coding scheme. Figure 1. VP310 Functional Block Diagram.

• I²C bus microprocessor interface.
• All digital clock and carrier recovery.
• On-chip PLL clock generation using low cost 10 to 15MHz crystal.
• 3.3V operation.
• 80 pin MQFP package.
• Low external component count.
• Commercial temperature range 0 to 70°C. Demodulator
• BPSK or QPSK programmable.
• Optional fast acquisition mode for low symbol rates. Viterbi
• Programmable decoder rates 1/2, 2/3, 3/4, 5/6, 6/7, 7/8.
• Constraint length k=7.
• Trace back depth 128.
• Extensive SNR and BER monitors. De-Interleaver
• Compliant with DVB and DSS standards. Reed Solomon
• (204, 188) for DVB and (146,130) for DSS.
• Reed Solomon Bit-error-rate monitor to indicate Viterbi performance. De-Scrambler
• EBU specification De-scrambler for DVB mode. Outputs
• MPEG transport parallel & serial output.
• Integrated MPEG2 TEI bit processing for DVB only. Application Support
• Channel decoder system evaluation board.
• I²C interface board to PC.
• Windows based evaluation software.
• ANSI C generic software.
• Application support help desk via email/telephone.

PLEASE NOTE: This manual has the following convention: All numerical values are shown as decimal numbers, unless otherwise defined. 1. FUNCTIONAL DESCRIPTION

1.1 Introduction

VP310 is a single-chip variable rate digital QPSK/BPSK satellite demodulator and channel decoder. The VP310 accepts base-band in-phase and quadrature analog signals and delivers an MPEG or DSS packet data stream. Digital filtering in VP310 removes the need for any external anti-alias filtering for all symbol rates from 1 to 45Mbaud. Frequency, timing and carrier phase recovery are all digital and the only feed-back to the analog front-end is for automatic gain control. The digital phase recovery loop enables very fine bandwidth control that is needed to overcome performance degradation due to phase and thermal noise. All acquisition algorithms are built into the VP310 controller. The VP310 can be operated in a Command Driven Control (CDC) mode by specifying the Symbol rate and Viterbi code rate. There is also a provision for a search for unknown Symbol rates and Viterbi code rates.

1.2 Analog-to-Digital Converter

The VP310 contains dual 6-bit A/D converters which each sample a 1.0Vpp single-ended analog input at up to 90MHz. The fixed rate sampling clock is provided on-chip using a programmable PLL needing only a low cost 10 to 15MHz crystal. Different crystal frequencies can be combined with different PLL ratios, depending on the maximum symbol rate, allowing a flexible approach to clock generation.

1.3 QPSK Demodulator

The demodulator in the VP310 consists of signal amplitude offset compensation, frequency offset compensation, decimation filtering, carrier recovery, symbol recovery and matched filtering. The decimation filters give continuous operation from 2Mbits/s to 90Mbits/s allowing one receiver to cover the needs of the consumer market as well as the single carrier per channel (SCPC) market with the same components without compromising performance, that is, the channel reception is within 0.5dB from theory. For a given Symbol rate, control algorithms on the chip detect the number of decimation stages needed and switch them in automatically. The frequency offset compensation circuitry is capable of tracking out up to ± 15MHz frequency offset. This allows the system to cope with relatively large frequency uncertainties introduced by the Low Noise Block (LNB). Full control of the LNB is provided by the DiSEqC outputs from the VP310. Horizontal / Vertical polarisation and an instruction modulated 22kHz signal are available under register control. All DiSEqC v1.1 functions are implemented on the VP310.

An internal state machine that handles all the demodulator functions controls the signal tracking and acquisition. Various pre-set modes are available as well as blind acquisition where the receiver has no prior knowledge of the received signal. Fast acquisition algorithms have been provided for low Symbol rate applications. Full interactive control of the acquisition function is possible for debug purposes. In the event of a signal fade or a cycle slip, QPSK demodulator allows sufficient time for the FEC to re-acquire lock, for example, via a phase rotation in the Viterbi decoder. This is to minimise the loss of signal due to the signal fade. Only if the FEC fails to re-acquire lock for a long period (which is programmable) would QPSK try to re-acquire the signal. The matched filter is a root-raised-cosine filter with either 0.20 or 0.35 roll-off, compliant with DSS and DVB standards. Although not a part of the DVB standard, VP310 allows a roll-off of 0.20 to be used with other DVB parameters. An AGC signal is provided to control the signal levels in the tuner section of the receiver and ensure the signal level fed to the VP310 is set at an optimal value under all reception conditions. The VP310 provides comprehensive information on the input signal and the state of the various parts of the device. This information includes Signal to Noise Ratio (SNR), signal level, AGC lock, timing and carrier lock signals. A maskable interrupt output is available to inform the host controller when events occur.

1.4 Forward Error Correction

The VP310 contains FEC blocks to enable error correction for DVB-S and DSS transmissions. The Viterbi decoder block can decode the convolutional code with rates 1/2, 2/3, 3/4, 5/6, 6/7 or 7/8. The block features automatic synchronisation and automatic code rate detection. The trace back depth of 128 provides better performance at high code rates and the built-in synchronisation algorithm allows the Viterbi decoder to lock onto signals with very poor signal-to-noise ratios. Viterbi bit error rate monitor provides an indication of the error rate at QPSK output. The 24-bit error count register in the Viterbi decoder allows the bit error rate at the output of the QPSK demodulator to be monitored. The 24-bit bit error count register in the Reed-Solomon decoder allows the Viterbi output bit error rate to be monitored. The 16-bit uncorrectable packet counter yields information about the output packet error rate. These three monitors and the QPSK SNR register allows the performance of the device and its individual components, such as the QPSK demodulator and the Viterbi decoder, to be monitored extensively by the external microprocessor. The frame/byte align block features a sophisticated synchronisation algorithm to ensure reliable recovery of DVB and DSS framed data streams under worst case signal conditions. The de- interleaver uses on-chip RAM and is compatible with the DVB and DSS algorithms. The Reed-Solomon decoder is a truncated version of the (255, 239) code. The code block size is 204 for DVB and 146 for DSS. The decoder provides a count of the number of uncorrectable blocks as well as the number of bit errors corrected. The latter gives an indication of the bit error rate at the output of the Viterbi decoder.

signal. The data clock may be inverted under software control.

1.4.1.1 Viterbi error count measurement

and punctured version of the decoded bit stream to obtain a count of errors see Figure 2 below. Figure 2. Viterbi block diagram. loaded with the error count.

Figure 3. Viterbi error count measurement.

1.4.1.2 Viterbi error count coarse indication

satellite. This VIT_MAXERR mode is enabled by setting the FEC_STAT_EN register bit B0. a change of state on the STATUS line. The output signal will be in the audio frequency range.

Figure 4. Viterbi error count coarse indication.

1.4.2 The Frame Alignment block

frame alignment block also removes the 180° phase ambiguity not removed by Viterbi decoder.

1.4.3 The De-interleaver block

1.4.3.1 DVB

Before transmission, the data bytes are interleaved with each other in a cyclic pattern of twelve. realised using on-chip Random Access Memory (RAM).

Figure 5. DVB Conceptual diagram of the convolutional de-interleaver block.

1.4.3.2 DSS

Before transmission, the data bytes are interleaved with each other in a cyclic pattern of thirteen. Memory (RAM) as used for DVB, but utilising different addressing algorithm. Figure 6. DSS Conceptual diagram of the convolutional de-interleaver block.

1.4.4 The Reed Solomon Decoder block

DSS is 146. Hence DVB code is (204, 188) and DSS code is (146, 130), with both having T = 8. Figure 7. DVB block structure. Figure 8. DSS block structure.

1.4.5 The Energy Dispersal (de-scrambler) block, DVB only

packets have the same synch byte 47hex. Figure 9. DVB Energy dispersal conceptual diagram.

1.4.6 Output stage

by VP310 to be very close to the minimum required to output packet data without packet overlap.

1.5 Control

Figure 10. VP310 Control Structure. VP310 to re-acquire the signal. band selection, polarisation and dish position. either I²C bus or 3-wire bus, recreated on the General Purpose Port (GPP).

1.5.1 Known Symbol Rate and Code Rate mode

1.5.2 Symbol Rate and Code Rate Search mode

installation of a set top box.

1.6 Applications Information

1.6.1 IF conversion

Figure 11. Single Conversion System Diagram.

1.6.2 Direct conversion

directly down to I and Q baseband channels at zero intermediate frequency. SAW filter in conventional single conversion tuners. Figure 12. Direct Conversion System Diagram.

1. VP310 software control This section describes the sequences of register operations needed to acquire DVB and DSS channels with known or unknown parameters. Communication with the VP310 is via a standard I²C bus and the first byte following the chip address, in write mode, is the register address (RADD). The register map is organised to group important Read registers at the lowest addresses, then the main control Write registers in the next block of addresses. The first register to be written must be the Configuration register, which has been placed at the highest register address, because it is only written once during the initialisation sequence. The CONFIG register can only be reset by the hardware reset. The VP310 is held in a power saving mode following the hardware reset. After a hardware reset, the VP310 must be taken out of the power save mode by writing a one to the MSB of the CONFIG register. When VP310 is not being used it can be put back into the power save mode by writing a zero to the MSB of CONFIG.

2.1 Initialisation sequence

VP310 w ill be in the power save mode after a hardware reset. The first command to be written must be to the CONFIGURATION register at address 127. After loading this register, wait 150µs before writing to the RESET register. During this wait, the tuner can programmed to the required channel frequency via the General Purpose Port (register 20). Next write 128 to the RESET register (21) to reset the VP310 state machine and all parameter registers to the default settings. The default settings of the VP310 assumes a Gain Control Amplifier with a negative gain Vs voltage slope, i.e. the gain increases with decreasing voltage. However, if this slope is positive, the polarity of the AGC control signal can be inverted by programming 1 to bit B0 of the AGC_CTRL register, i.e. by changing the default AGC_CTRL setting from 38 to 39. It is best to do this immediately after writing 128 to the RESET register. Then the AGC loop can settle whilst the other registers of VP310 are programmed. Note that the initial value, minimum value and the maximum value of the AGC control voltage can also be programmed using the corresponding VP310 registers. After this, the LNB controls are defined, in register (22) DISEQC_MODE. The signal parameters should then be written to the VP310. The symbol rate (registers 23 & 25 SYM_RATE) may be specified within ±2% of the required value, absolute precision is not required to achieve successful lock and tracking. If the symbol rate is unknown, a search mode is available.

Selecting the correct bit of register (25) VIT_MODE, if known, programs the convolutional code rate. If the code rate is unknown, some or all of the bits of VIT_MODE may be set to force the VP310 to search for the code rate. Finally, the VP310 is given a GO command, register (27) GO = 1, to release the state machine and to start the signal acquisition sequence. This is summarised as an example in the following flow diagram.

send TUNER DATA via I2C bus (5 bytes). Figure 13. Initialisation sequence in DVB mode.

2.2 Spectral Inversion

Spectral inversion of the QPSK signal can be caused by the transmitter or the receiver front-end. before QPSK demodulation, by setting Q_IQ_SP bit B6 of QPSK_CTRL register (26) to 1. with the bit B6 of VIT_MODE register first at zero and then at one.

2.3 Simple channel change sequence

necessary to change the tuner data and possibly the DiSEqC data. NO reset is necessary. send TUNER DATA via I2C bus (5 bytes). Figure 14. Simple channel change sequence.

2.4 Channel change sequence with a new symbol rate

the tuner data and possibly the DiSEqC data and Symbol rate. NO reset is necessary. send TUNER DATA via I2C bus (5 bytes). Figure 15. Channel change sequence with new Symbol rate, DVB mode.

2.5 Channel change sequence with Search mode

programming more than one bit in VIT_MODE (26) register. Note: code rate 6/7 is not searched for DVB mode. searched, a QPSK Baud End interrupt (Bit B6, QPSK_INT_L (2)) is issued. send TUNER DATA via I2C bus (5 bytes). Figure 16. Channel change sequence with search mode, DVB mode.

MONITOR, provided the register (103) MON_CTRL = 3. The tolerance of the result is ±0.25%. code rate found can be read from FEC_STATUS[B6-4], see register 6 for details. Read Symbol rate from MONITOR registers 123 & 124. Read code rate from FEC_STATUS[B6-4] register 6. Figure 17. Results of Symbol rate and code rate search, DVB or DSS mode.

2.6 DSS mode of acquisition

This mode is very similar to the DVB mode, except that the Symbol rate is fixed at 20 MBaud. contents of registers (23-24) SYM_RATE and register (25) VIT_MODE are ignored in DSS mode. send TUNER DATA via I2C bus (5 bytes). Figure 18. Initialisation sequence in DSS mode.

2.7 Signal and Performance Monitors

The LNB error frequency can be obtained from LNB_FREQ registers (7 – 8). Any LNB error may be removed by offsetting the LNB frequency and re-tuning the tuner by the indicated amount. However, note that VP310 compensates for this frequency error before QPSK demodulation. Hence it is not necessary to re-tune the front-end unless this LNB error causes a significant amount of signal energy to be lost due to anti-alias filtering. The tuner RF signal level indication can be obtained from AGC H and AGC M registers (108 – 109). VP310 input signal level indication can be obtained from SIG_LEV register (19). An indication of Signal to Noise Ratio (SNR) can be obtained from M_SNR registers (9 – 10) where a formula is given. This measurement is only intended as a guide to the SNR of the channel being received. It should not be taken as the absolute value of SNR. QPSK output Bit Error Rate is available by dividing the reading from VIT_ERRCNT registers (11 – 13) by the reading from VIT_ERRPER registers (83 – 85). Viterbi output Bit Error Rate is available by reading RS_BERCNT registers (14 – 16). Two readings are taken with a known time interval separating them. The first reading resets the counter at the start of the time period, so it is ignored. The Reed Solomon uncorrected block error count can be found from RS_UBC registers (17 – 18). This reading is related to the cycle slip performance of the tuner. The measurement technique is similar to that for the Viterbi Bit Error Rate above, two readings being taken over a defined time period. In this case the period will usually be very long, say 24 hours, to accumulate a reasonable count.

1. VP310 register map RADD is a virtual register with no address containing the address of the register to be accessed. It is written immediately after the I²C write address. NAME ADR B7 B6 B5 B4 B3 B2 B1 B0 DEF hex RADD N/A IAI AD6 AD5 AD4 AD3 AD2 AD1 AD0 -

3.1 Write / Read register map

NAME ADR B7 B6 B5 B4 B3 B2 B1 B0 DEF hex GPP_CTRL 20 Reserved I2C_PAS GPP_DIR[2:0] GPP_PIN[2:0] 20 RESET 21 FR _310 PR_310 FR_QP PR_QP FR_VIT PR_VIT PR_BA PR_DS 00 DISEQC_MODE 22 Reserved HV DISEQC instruction length 22kHz mode 00 SYM_RATE H 23 SEARCH Reserved SYM_RATE[13:8] in MBaud (high byte) 1B SYM_RATE L 24 SYM_RATE[7:0] in MBaud (low byte) 80 VIT_MODE 25 Reserved V_IQ_SP CR 7/8 CR 6/7 CR 5/6 CR 3/4 CR 2/3 CR 1/2 44 QPSK_CTRL 26 Reserved Q_IQ_SP Reserved Reserved Reserved AFC_M Reserved RO LL_20 00 GO 27 Reserved GO 00 IE_QPSK H 28 IE_QPSK[23:16] Interrupt enable QPSK (high byte) 00 IE_QPSK M 29 IE_QPSK[15:8] Interrupt enable QPSK (middle byte) 00 IE_QPSK L 30 IE_QPSK [7:0] Interrupt enable QPSK (low byte) 00 IE_FEC 31 IE_FEC[7:0] Interrupt enable FEC 00 QPSK_STAT_EN 32 QPSK_STAT_EN[7:0] Enable various QPSK outputs on STATUS pin 00 FEC_STAT_EN 33 FEC_STAT_EN[3:0] Enable various FEC outputs on STATUS pin 04 SYS_CLK 34 SYS_CLK[7:0] - System clock frequency x2 in MHz 00 DISEQC_RATIO 35 DISEQC_RATIO[7:0] 00 DISEQC_INSTR 36 DISEQC Instruction [7:0] 00 FR_LIM 37 Reserved FR_LIM[6:0] - Freq. Limit in MHz 30 FR_OFF 38 FR_OFF[7:0] - Freq. Offset in MHz 00 AGC_CTRL 39 Reserved Reserved AGC_SD[1:0] AGC_BW[2:0] AGC_SL 26 AGC_REF 41 AGC_REF[7:0] AGC reference level 67 OP_CTRL 96 Reserved BKERIV MCLKIV EN_TEI BSO BA_LK[2:0] 33 MON_CTRL 103 MON_CTRL[7:0] Monitor control 00 CONFIG 127 310_EN DSS_B DSS_A BPSK P LL_FACTOR[1:0] CRYS15 ADCEXT 08

3.2 Read only register map

Writing to these registers will have no effect. NAME ADR B7 B6 B5 B4 B3 B2 B1 B0 DEF hex QPSK_INT H 00 QPSK_INT[23:16] Interrupt QPSK (high byte) 00 QPSK_INT M 01 QPSK_INT [15:8] Interrupt QPSK (middle byte) 00 QPSK_INT L 02 QPSK_INT [7:0] Interrupt QPSK (low byte) 00 FEC_INT 03 FEC_INT[7:0] Interrupt FEC 00 QPSK_STAT H 04 QPSK STATUS[15:8] (high byte) 00 QPSK_STAT L 05 QPSK STATUS[7:0] (low byte) 00 FEC_STATUS 06 FEC STATUS[7:0] 00 LNB_FREQ H 07 LNB_FREQ[15:8] Measured LNB frequency error (high byte) 00 LNB_FREQ L 08 LNB_FREQ [7:0] Measured LNB frequency error (low byte) 00 M_SNR H 09 Reserved M_SNR[14:8] Measured SNR (high byte) 00 M_SNR L 10 M_SNR [7:0] Measured SNR (low byte) 00 VIT_ERRCNT H 11 VIT_ERRCNT[23:16] - Viterbi error count (high byte) 00 VIT_ERRCNT M 12 VIT_ERRCNT [15:8] - Viterbi error count (middle byte) 00 VIT_ERRCNT L 13 VIT_ERRCNT [7:0] - Viterbi error count (low byte) 00 RS_BERCNT H 14 RS_BERCNT [23:16] - Reed Solomon bit errors corrected (high byte) 00 RS_BERCNT M 15 RS_BERCNT[15:8] - Reed Solomon bit errors corrected (middle byte) 00 RS_BERCNT L 16 RS_BERCNT[7:0] - Reed Solomon bit errors corrected (low byte) 00 RS_UBC H 17 RS_UBC [15:8] - Reed Solomon uncorrected block errors (high byte) 00 RS_UBC L 18 RS_UBC[7:0] - Reed Solomon uncorrected block errors (low byte) 00 SIG_LEVEL 19 SIG_LEVEL[11:4] - Signal level at VP 310 input 00 AGC H 108 AGC[23:16] - Front end AGC (high byte) 00 AGC M 109 AGC[15:8] - Front end AGC (middle byte) 00 AGC L 110 AGC[7:0] - Front end AGC (low byte) 00 FREQ_ERR1 H 111 FREQ_ERR1[23:16] Input frequency error course (high byte) 00 FREQ_ERR1 M 112 FREQ_ERR1[15:8] Input frequency error course (middle byte) 00 FREQ_ERR1 L 113 FREQ_ERR1[7:0] Input frequency error course (low byte) 00 FREQ_ERR2 H 114 FREQ_ERR2[15:8] Input frequency error fine (high byte) 00 FREQ_ERR2 L 115 FREQ_ERR2[7:0] Input frequency error fine (low byte) 00 SYM_RAT_OP H 116 SYM_RAT_OP[15:8] Symbol Rate Output (high byte) 00 SYM_RAT_OP L 117 SYM_RAT_OP [7:0] Symbol Rate Output (low byte) 00 MONITOR H 123 MONITOR[15:8] Monitor (high byte) 00 MONITOR L 124 MONITOR[7:0] Monitor (low byte) 00

1. ELECTRICAL CHARACTERISTICS

4.1 Recommended operating conditions

Table 1. Recommended operating conditions.

4.2 Absolute maximum ratings

Table 2. Maximum operating conditions. Note: Stresses exceeding these listed under absolute maximum ratings may induce failure. at or above these conditions is not implied.

4.3 Crystal specification

Parallel resonant fundamental frequency (preferred) 9.99 to 16.00MHz. Tolerance over operating temperature range ± 25ppm. Nominal load capacitance 30pF. Figure 19. Crystal oscillator circuit. marginally exceed the maximum symbol rate required.

4.4 DC electrical characteristics

Output level open drain 4 mA drive current. Table 3. DC electrical characteristics.

4.5 Numerical listing of pin-out

1 VSS 21 PLLVDD 41 VSS 61 MDO[1]

2 VDD 22 PLLGND 42 VDD 62 VDD

3 IIN[1] 23 PLL1 43 AGC 63 MDO[2]

4 IIN[0] 24 ADCFGND 44 GPP[0] (SCL2) 64 MDO[3]

5 QIN[5] 25 ADCFVDD 45 GPP[1] (SDA2) 65 MDO[4]

6 QIN[4] 26 VRT 46 GPP[2] 66 MDO[5]

7 QIN[3] 27 IREF 47 DISEQC[1] 67 VDD

8 QIN[2] 28 ISINGP 48 DISEQC[0] 68 MDO[6]

9 VDD 29 COMP 49 RESET 69 MDO[7]

10 VSS 30 ADCDVDD 50 VDD 70 VSS

11 QIN[1] 31 ADCDGND 51 VSS 71 MDOEN

12 QIN[0] 32 VRM 52 STATUS 72 MOVAL

13 VDD 33 QSINGP 53 SCL 73 VDD

14 CLKIN 34 QREF 54 SDA 74 VSS

15 VSS 35 VRB 55 VDD 75 BKERR

16 CLKOUT 36 ADCAGND 56 VSS 76 MOSTRT

17 VDD 37 ADCAVDD 57 IRQ 77 IIN[5]

18 XTI 38 RREF 58 MCLK 78 IIN[4]

19 XTO 39 TEST1 59 MDO[0] 79 IIN[3]

20 VSS 40 TEST2 60 VSS 80 IIN[2]

Table 4. Numerical listing of pin-out.

1. APPENDIX 1: Application Schematic

Figure 20. Application Schematic.

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