VP3082

SN65HVD3082E_17 TI1 | Alldatasheet

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Technical content

R A B R RE DE D D R A B R RE DE D D R D R RE DE D A B R D R RE DE D A B Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community Reference Design An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN65HVD3082E,SN75HVD3082E,SN65HVD3085E,SN65HVD3088E SLLS562I –AUGUST 2009–REVISED SEPTEMBER 2016 SNx5HVD308xELow-PowerRS-485Transceivers,AvailableinaSmallMSOP-8Package

1 Features

1• Available in a Small MSOP-8 Package

• Meets or Exceeds the Requirements of the TIA/EIA-485A Standard
• Low Quiescent Power – 0.3-mA Active Mode – 1-nA Shutdown Mode
• 1/8 Unit Load up to 256 Nodes on a Bus
• Bus-Pin ESD Protection up to 15 kV
• Industry-Standard SN75176 Footprint
• Failsafe Receiver (Bus Open, Bus Shorted, Bus Idle)
• Glitch-Free Power-Up and Power-Down Bus Inputs and Outputs

2 Applications

• Energy Meter Networks
• Motor Control
• Power Inverters
• Industrial Automation
• Building Automation Networks
• Battery-Powered Applications
• Telecommunications Equipment

3 Description

The SNx5HVD308xE devices are half-duplex transceivers designed for RS-485 data bus networks. Powered by a 5-V supply, they are fully compliant with TIA/EIA-485A standard. With controlled transition times, these devices are suitable for transmitting data over long twisted-pair cables. SN65HVD3082E and SN75HVD3082E devices are optimized for signaling rates up to 200 kbps. The SN65HVD3085E device is suitable for data transmission up to 1 Mbps, whereas the SN65HVD3088E device is suitable for applications that require signaling rates up to 20 Mbps. These devices are designed to operate with very low supply current, typically 0.3 mA, exclusive of the load. When in the inactive-shutdown mode, the supply current drops to a few nanoamps, which makes these devices ideal for power-sensitive applications. The wide common-mode range and high ESD- protection levels of these devices makes them suitable for demanding applications such as energy meter networks, electrical inverters, status and command signals across telecom racks, cabled chassis interconnects, and industrial automation networks where noise tolerance is essential. These devices match the industry-standard footprint of the SN75176 device. Power-on-reset circuits keep the outputs in a high-impedance state until the supply voltage has stabilized. A thermal-shutdown function protects the device from damage due to system fault conditions. The SN75HVD3082E is characterized for operation from 0°C to 70°C and SN65HVD308xE are characterized for operation from –40°C to 85°C air temperature. The D package version of the SN65HVD3082E has been characterized for operation from -40°C to 105°C. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) SN65HVD3082E SN65HVD3088E SOIC (8) 4.90 mm × 3.91 mm VSSOP (8) 3.00 mm × 3.00 mm PDIP (8) 9.81 mm × 6.35 mm SN75HVD3082E SN65HVD3085E SOIC (8) 4.90 mm × 3.91 mm VSSOP (8) 3.00 mm × 3.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Schematic

SN65HVD3082E,SN75HVD3082E,SN65HVD3085E,SN65HVD3088E SLLS562I –AUGUST 2009–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: SN65HVD3082E SN75HVD3082E SN65HVD3085E SN65HVD3088E Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Table of Contents

12.3 Receiving Notification of Documentation Updates 23

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision H (August 2015) to Revision I Page

• Added text to the Description, "The D package version of the SN65HVD3082E has been characterized for operation
• Changed the Operating free-air temperature for SN65HVD3082E (D package) From: MAX = 85°C To: 105°C in Changes from Revision G (May 2009) to Revision H Page
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device Changes from Revision F (March 2009) to Revision G Page

A B SN65HVD3082E,SN75HVD3082E,SN65HVD3085E,SN65HVD3088E www.ti.com SLLS562I –AUGUST 2009–REVISED SEPTEMBER 2016 Product Folder Links: SN65HVD3082E SN75HVD3082E SN65HVD3085E SN65HVD3088E Submit Documentation FeedbackCopyright © 2009–2016, Texas Instruments Incorporated

5 Pin Configuration and Functions

D, P, and DGK Packages 8-Pin SOIC, VSSOP, and PDIP Top View Pin Functions PIN TYPE DESCRIPTION NAME NO. A 6 Bus input/output Driver output or receiver input (complementary to B) B 7 Bus input/output Driver output or receiver input (complementary to A) D 4 Digital input Driver data input DE 3 Digital input Driver enable, active high GND 5 Reference potential Local device ground R 1 Digital output Receive data output RE 2 Digital input Receiver enable, active low VCC 8 Supply 4.5-V to 5.5-V supply (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range unless otherwise noted(1) (2) MIN MAX UNIT Supply voltage, VCC –0.5 7 V Voltage at A or B –9 14 V Voltage at any logic pin –0.3 VCC + 0.3 V Receiver output current –24 24 mA Voltage input, transient pulse, A and B, through 100 Ω (see Figure 20) –50 50 V Junction Temperature, TJ 170 °C Storage temperature, Tstg 150 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. (3) Tested in accordance with IEC 61000-4-4.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS- 001(1) Bus pins and GND ±15000 V All pins ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 Electrical Fast Transient/Burst, A, B, and GND(3) ±4000

SN65HVD3082E,SN75HVD3082E,SN65HVD3085E,SN65HVD3088E SLLS562I –AUGUST 2009–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: SN65HVD3082E SN75HVD3082E SN65HVD3085E SN65HVD3088E Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.

6.3 Recommended Operating Conditions

over operating free-air temperature range unless otherwise noted(1) MIN NOM MAX UNIT Supply voltage, VCC 4.5 5.5 V Voltage at any bus terminal (separately or common mode) , VI –7 12 High-level input voltage (D, DE, or RE inputs), VIH 2 VCC V Low-level input voltage (D, DE, or RE inputs), VIL 0 0.8 V Differential input voltage, VID –12 12 V Output current, IO Driver –60 60 mA Receiver –8 8 Differential load resistance, RL 54 60 Ω Signaling rate, 1/tUI SN65HVD3082E, SN75HVD3082E 0.2 MbpsSN65HVD3085E 1 SN65HVD3088E 20 Operating free-air temperature, TA SN65HVD3082E (D package) –40 105 °CSN65HVD3082E (DGK and P packages), SN65HVD3085E, SN65HVD3088E –40 85 SN75HVD3082E 0 70 Junction temperature, TJ –40 130 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.4 Thermal Information

THERMAL METRIC(1) SN65HVD3082E, SN75HVD3082E, SN65HVD3085E, SN65HVD3088E SN65HVD3082E, SN65HVD3088E UNITD (SOIC) DGK (VSSOP) P (PDIP)

8 PINS 8 PINS 8 PINS

RθJA Junction-to-ambient thermal resistance 130 180 70 °C/W RθJC(top) Junction-to-case (top) thermal resistance 80 66 80 °C/W RθJB Junction-to-board thermal resistance 55 110 40 °C/W ψJT Junction-to-top characterization parameter 7.9 4.6 17.6 °C/W ψJB Junction-to-board characterization parameter 47 73.1 28.3 °C/W

SN65HVD3082E,SN75HVD3082E,SN65HVD3085E,SN65HVD3088E www.ti.com SLLS562I –AUGUST 2009–REVISED SEPTEMBER 2016 Product Folder Links: SN65HVD3082E SN75HVD3082E SN65HVD3085E SN65HVD3088E Submit Documentation FeedbackCopyright © 2009–2016, Texas Instruments Incorporated (1) All typical values are at 25°C and with a 5-V supply.

6.5 Electrical Characteristics: Driver

over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT |VOD| Differential output voltage IO = 0, No Load 3 4.3 V RL = 54 Ω (see Figure 8) 1.5 2.3 RL = 100 Ω 2 VTEST = –7 V to 12 V (see Figure 9) 1.5 Δ|VOD| Change in magnitude of differential output voltage See Figure 8 and Figure 9 –0.2 0 0.2 V VOC(SS) Steady-state common-mode output voltage See Figure 10 1 2.6 3 V ΔVOC(SS) Change in steady-state common-mode output voltage –0.1 0 0.1 VOC(PP) Peak-to-peak common-mode output voltage See Figure 10 500 mV IOZ High-impedance output current See receiver input currents in Electrical Characteristics: Receiver II Input current D, DE –100 100 µA IOS Short-circuit output current −7 V ≤ VO ≤ 12 V (see Figure 14) –250 250 mA (1) All typical values are at 25°C and with a 5-V supply.

6.6 Electrical Characteristics: Receiver

over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIT+ Positive-going differential input threshold voltage IO = –8 mA –85 –10 mV VIT– Negative-going differential input threshold voltage IO = 8 mA –200 –115 mV Vhys Hysteresis voltage (VIT+ – VIT–) 30 mV VOH High-level output voltage VID = 200 mV, IOH = –8 mA (see Figure 15) 4 4.6 V VOL Low-level output voltage VID = –200 mV, IO = 8 mA (see Figure 15) 0.15 0.4 V IOZ High-impedance-state output current VO = 0 or VCC, RE = VCC –1 1 μA II Bus input current VIH = 12 V, VCC = 5 V 0.04 0.1 mA VIH = 12 V, VCC = 0 V 0.06 0.125 VIH = –7 V, VCC = 5 V –0.1 –0.04 VIH = –7 V, VCC = 0 V –0.05 –0.03 IIH High-level input current, (RE) VIH = 2 V –60 –30 μA IIL Low-level input current, (RE) VIL = 0.8 V –60 –30 μA Cdiff Differential input capacitance VI = 0.4 sin (4E6πt) + 0.5 V, DE at 0 V 7 pF

SN65HVD3082E,SN75HVD3082E,SN65HVD3085E,SN65HVD3088E SLLS562I –AUGUST 2009–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: SN65HVD3082E SN75HVD3082E SN65HVD3085E SN65HVD3088E Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated (1) All typical values are at 25°C and with a 5-V supply.

6.7 Power Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT ICC Driver and receiver enabled D at VCC or open, DE at VCC, RE at 0 V, No load 425 900 µA Driver enabled, receiver disabled D at VCC or open, DE at VCC, RE at VCC, No load 330 600 µA Receiver enabled, driver disabled D at VCC or open, DE at 0 V, RE at 0 V, No load 300 600 µA Driver and receiver disabled D at VCC or open, DE at 0 V, RE at VCC 0.001 2 µA P(AVG) Average power dissipation Input to D is a 50% duty cycle square wave at max specified signal rate RL = 54 Ω VCC = 5.5 V, TJ = 130°C ALL HVD3082E 203 mWALL HVD3085E 205 ALL HVD3088E 276

6.8 Switching Characteristics: Driver

over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH tPHL Propagation delay time, low-to-high-level output Propagation delay time, high-to-low-level output RL = 54 Ω, CL = 50 pF (see Figure 11) HVD3082E 700 1300 nsHVD3085E 150 500 HVD3088E 12 20 tr tf Differential output signal rise time Differential output signal fall time RL = 54 Ω, CL = 50 pF (see Figure 11) HVD3082E 500 900 1500 nsHVD3085E 200 300 HVD3088E 7 15 tsk(p) Pulse skew (|tPHL – tPLH|) RL = 54 Ω, CL = 50 pF (see Figure 11) HVD3082E 20 200 nsHVD3085E 5 50 HVD3088E 1.4 2 tPZH tPZL Propagation delay time, high-impedance-to- high-level output Propagation delay time, high-impedance-to-low- level output RL = 110 Ω, RE at 0 V (see Figure 12 and Figure 13) HVD3082E 2500 7000 nsHVD3085E 1000 2500 HVD3088E 13 30 tPHZ tPLZ Propagation delay time, high-level-to-high- impedance output Propagation delay time, low-level-to-high- impedance output RL = 110 Ω, RE at 0 V (see Figure 12 and Figure 13) HVD3082E 80 200 nsHVD3085E 60 100 HVD3088E 12 30 tPZH(SHDN) tPZL(SHDN) Propagation delay time, shutdown-to-high-level output Propagation delay time, shutdown-to-low-level output RL = 110 Ω, RE at VCC (see Figure 12) HVD3082E 3500 7000 nsHVD3085E 2500 4500 HVD3088E 1600 2600

SN65HVD3082E,SN75HVD3082E,SN65HVD3085E,SN65HVD3088E www.ti.com SLLS562I –AUGUST 2009–REVISED SEPTEMBER 2016 Product Folder Links: SN65HVD3082E SN75HVD3082E SN65HVD3085E SN65HVD3088E Submit Documentation FeedbackCopyright © 2009–2016, Texas Instruments Incorporated

6.9 Switching Characteristics: Receiver

over recommended operating conditions unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high- level output CL = 15 pF (see Figure 16) HVD3082E HVD3085E 75 200 ns HVD3086E 100 tPHL Propagation delay time, high-to-low- level output HVD3082E HVD3085E 79 200 ns HVD3088E 100 tsk(p) Pulse skew (|tPHL – tPLH|) HVD3082E HVD3085E 4 30 ns HVD3088E 10 tr Output signal rise time VID = –1.5 V to 1.5 V, CL = 15 pF (see Figure 16) 1.5 3 ns tf Output signal fall time 1.8 3 ns tPZH Output enable time to high level CL = 15 pF, DE at 3 V (see Figure 17 and Figure 18) HVD3082E HVD3085E 5 50 ns HVD3088E 30 tPZL Output enable time to low level HVD3082E HVD3085E 10 50 ns HVD3088E 30 tPHZ Output enable time from high level HVD3082E HVD3085E 5 50 ns HVD3088E 30 tPLZ Output disable time from low level HVD3082E HVD3085E 8 50 ns HVD3088E 30 tPZH(SHDN) Propagation delay time, shutdown-to-high-level output CL = 15 pF, DE at 0 V, (see Figure 19) 1600 3500 ns tPZL(SHDN) Propagation delay time, shutdown-to-low-level output 1700 3500 ns

6.10 Typical Characteristics

Figure 1. Bus Input Current Figure 2. SN65HVD3082E RMS Supply Current Figure 3. SN65HVD3085E RMS Supply Current Figure 4. SN65HVD3088E RMS Supply Current Figure 5. Driver Differential Output Voltage Figure 6. Receiver Output Voltage

Figure 7. SN65HVD3088E Driver Rise and Fall Time

7 Parameter Measurement Information

and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle. ZO = 50 Ω (unless otherwise specified). Figure 8. Driver Test Circuit, VOD and VOC Without Common-Mode Loading Figure 9. Driver Test Circuit, VOD With Common-Mode Loading Figure 10. Driver VOC Test Circuit and Waveforms Figure 11. Driver Switching Test Circuit and Waveforms

3 V□if□Testing□B□Output

0 V□if□Testing□B□Output

and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle. ZO = 50 Ω (unless otherwise specified). Figure 12. Driver Enable and Disable Test Circuit and Waveforms, High Output Figure 13. Driver Enable and Disable Test Circuit and Waveforms, Low Output Figure 14. Driver Short-Circuit Figure 15. Receiver Switching Test Circuit and

and fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle. ZO = 50 Ω (unless otherwise specified). Figure 21. Equivalent Input and Output Schematic Diagrams

8 Detailed Description

8.1 Overview

also feature a high degree of ESD protection and typical standby current consumption of 1 nA.

8.2 Functional Block Diagram

8.3 Feature Description

state with high-impedance outputs.

8.4 Device Functional Modes

A turns high and B turns low. Table 1. Driver Function Table

low. If VID is between VIT+ and VIT– the output is indeterminate. Table 2. Receiver Function Table

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

transmissions. The driver and receiver enable pins allow for the configuration of different operating modes. Figure 22. Half-Duplex Transceiver Configurations into the bus traffic whether the driver is transmitting data or not. Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal. when the direction-control line is low. sends and can verify that the correct data have been transmitted.

9.2 Typical Application

Figure 23. Typical Application Circuit

9.2.1 Design Requirements

applications with varying requirements, such as distance, data rate, and number of nodes.

9.2.1.1 Data Rate and Bus Length

small signal jitter of up to 5 or 10%. Figure 24. Cable Length vs Data Rate Characteristic

9.2.1.2 Stub Length

• tr is the 10/90 rise time of the driver
• c is the speed of light (3 × 108 m/s)
• v is the signal velocity of the cable or trace as a factor of c (1)

9.2.1.3 Bus Loading

it is possible to connect up to 256 receivers to the bus.

9.2.1.4 Receiver Failsafe

• open bus conditions such as a disconnected connector,
• shorted bus conditions such as cable damage shorting the twisted-pair together, or
• idle bus conditions that occur when no driver on the bus is actively driving In any of these cases, the differential receiver outputs a failsafe logic High state, so that the output of the receiver is not indeterminate. Receiver failsafe is accomplished by offsetting the receiver thresholds so that the input indeterminate range does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than +200 mV, and must output a Low when the VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are VIT+ and VIT– and VHYS. As seen in the table, differential signals more negative than –200 mV will always cause a Low receiver output. Similarly, differential signals more positive than +200 mV will always cause a High receiver output. When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output is High. Only when the differential input is more negative than VIT– will the receiver output transition to a Low state. So, the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value VHYS (the separation between VIT+ and VIT– ) as well as the value of VIT+.

9.2.2 Detailed Design Procedure

Figure 25. Transient Protection Against ESD, EFT, and Surge Transients surge (IEC 61000-4-5) transients. Table 3 shows the associated Bill of Materials. Table 3. Bill of Materials

SN65HVD3082E,SN75HVD3082E,SN65HVD3085E,SN65HVD3088E SLLS562I –AUGUST 2009–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: SN65HVD3082E SN75HVD3082E SN65HVD3085E SN65HVD3088E Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated

9.2.2.1 Power Usage in an RS-485 Transceiver

Power consumption is a concern in many applications. Power supply current is delivered to the bus load as well as to the transceiver circuitry. For a typical RS-485 bus configuration, the load that an active driver must drive consists of all of the receiving nodes, plus the termination resistors at each end of the bus. The load presented by the receiving nodes depends on the input impedance of the receiver. The TIA/EIA-485-A standard defines a unit load as allowing up to 1 mA. With up to 32 unit loads allowed on the bus, the total current supplied to all receivers can be as high as 32 mA. The HVD308xE is rated as a 1/8 unit load device. As shown in , the bus input current is less than 1/8 mA, allowing up to 256 nodes on a single bus. The current in the termination resistors depends on the differential bus voltage. The standard requires active drivers to produce at least 1.5 V of differential signal. For a bus terminated with one standard 120-Ω resistor at each end, this sums to 25 mA differential output current whenever the bus is active. Typically the HVD308xE can drive more than 25-mA to a 60-Ω load, resulting in a differential output voltage higher than the minimum required by the standard (see Figure 3). Overall, the total load current can be 60 mA to a loaded RS-485 bus. This is in addition to the current required by the transceiver itself; the HVD308xE circuitry requires only about 0.4 mA with both driver and receiver enabled, and only 0.3 mA with either the driver enabled or with the receiver enabled. In low-power shutdown mode, neither the driver nor receiver is active, and the supply current is low. Supply current increases with signaling rate primarily due to the totem pole outputs of the driver (see Figure 2). When these outputs change state, there is a moment when both the high-side and low-side output transistors are conducting and this creates a short spike in the supply current. As the frequency of state changes increases, more power is used.

9.2.2.2 Low-Power Shutdown Mode

When both the driver and receiver are disabled (DE low and RE high) the device is in shutdown mode. If the enable inputs are in this state for less than 60 ns, the device does not enter shutdown mode. This guards against inadvertently entering shutdown mode during driver or receiver enabling. Only when the enable inputs are held in this state for 300 ns or more, the device is assured to be in shutdown mode. In this low-power shutdown mode, most internal circuitry is powered down, and the supply current is typically 1 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active. If only the driver is re-enabled (DE transitions to high) the driver outputs are driven according to the D input after the enable times given by tPZH(SHDN) and tPZL(SHDN) in the driver switching characteristics. If the D input is open when the driver is enabled, the driver outputs defaults to A high and B low, in accordance with the driver failsafe feature. If only the receiver is re-enabled (RE transitions to low) the receiver output is driven according to the state of the bus inputs (A and B) after the enable times given by tPZH(SHDN) and tPZL(SHDN) in the receiver switching characteristics. If there is no valid state on the bus the receiver responds as described in the failsafe operation section. If both the receiver and driver are re-enabled simultaneously, the receiver output is driven according to the state of the bus inputs (A and B) and the driver output is driven according to the D input. NOTE The state of the active driver affects the inputs to the receiver. Therefore, the receiver outputs are valid as soon as the driver outputs are valid.

10 Power Supply Recommendations

inductance of the PCB power planes.

11 Layout

11.1 Layout Guidelines

be applied during PCB design.

• Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
• Use VCC and ground planes to provide low-inductance. NOTE High-frequency currents follow the path of least inductance and not the path of least impedance.
• Design the protection components into the direction of the signal path. Do not force the transients currents to divert from the signal path to reach the protection device.
• Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, and controller ICs on the board.
• Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to minimize effective via-inductance.
• Use 1-kΩ to 10-kΩ pullup or pulldown resistors for enable lines to limit noise currents in these lines during transient events.
• Insert series pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the transceiver and prevent it from latching up.
• While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient blocking units (TBUs) that limit transient current to 200 mA.

11.2 Layout Example

Figure 26. SNx5HVD308xE Layout Example

11.3 Thermal Considerations for IC Packages

temperature divided by the operating power.

• the PCB design (50% variation)
• altitude (20% variation)
• device power (5% variation) θJA can be used to compare the thermal performance of packages if the specific test conditions are defined and used. Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal characteristics of holding fixtures. θJA is often misused when it is used to calculate junction temperatures for other installations. TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal performance and consists of a single trace layer 25-mm long and 2-oz thick copper. The high-k board gives best case in-use condition and consists of two 1-oz buried power planes with a single trace layer 25-mm long with 2-oz thick copper. A 4% to 50% difference in θJA can be measured between these two test cards. θJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow from die, through the mold compound into the copper block. θJC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict junction temperature as it provides pessimistic numbers if the case temperature is measured in a non- standard system and junction temperatures are backed out. It can be used with θJB in 1-dimensional thermal simulation of a package system. θJB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate structure. θJB is only defined for the high-k test card. θJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance (especially for BGAs with thermal balls) and can be used for simple 1-dimensional network analysis of package system (see Figure 27).

Figure 27. Thermal Resistance

12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Related Links

resources, tools and software, and quick access to sample or buy. Table 4. Related Links

12.3 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

12.4 Community Resources

solve problems with fellow engineers. contact information for technical support.

12.5 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.6 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

12.7 Glossary

This glossary lists and explains terms, acronyms, and definitions.

SN65HVD3082E,SN75HVD3082E,SN65HVD3085E,SN65HVD3088E SLLS562I –AUGUST 2009–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: SN65HVD3082E SN75HVD3082E SN65HVD3085E SN65HVD3088E Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 15-Apr-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples HPA00516EDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VP3082 HPA00580EDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VP3082 HPA01082DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VP3082 SN65HVD3082ED ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VP3082 SN65HVD3082EDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VP3082 SN65HVD3082EDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 NWN SN65HVD3082EDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 NWN SN65HVD3082EDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VP3082 SN65HVD3082EDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VP3082 SN65HVD3082EP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 65HVD3082 SN65HVD3082EPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type -40 to 85 65HVD3082 SN65HVD3085ED ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VP3085 SN65HVD3085EDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VP3085 SN65HVD3085EDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 NWK SN65HVD3085EDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NWK SN65HVD3085EDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 NWK SN65HVD3085EDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NWK

www.ti.com 15-Apr-2017 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN65HVD3085EDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VP3085 SN65HVD3088ED ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VP3088 SN65HVD3088EDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VP3088 SN65HVD3088EDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 NWH SN65HVD3088EDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NWH SN65HVD3088EDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-1-260C-UNLIM -40 to 85 NWH SN65HVD3088EDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NWH SN65HVD3088EDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VP3088 SN65HVD3088EDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 VP3088 SN75HVD3082ED ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 VN3082 SN75HVD3082EDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 VN3082 SN75HVD3082EDGK ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NWM SN75HVD3082EDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NWM SN75HVD3082EDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | Call TI Level-1-260C-UNLIM 0 to 70 NWM SN75HVD3082EDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 NWM SN75HVD3082EDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 VN3082 SN75HVD3082EDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 VN3082 SN75HVD3082EP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 75HVD3082

www.ti.com 15-Apr-2017 Addendum-Page 3 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples SN75HVD3082EPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type 0 to 70 75HVD3082 SNHVD3082EDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 NWN (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 15-Apr-2017 Addendum-Page 4

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 26-Sep-2016 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65HVD3082EDGKR VSSOP DGK 8 2500 367.0 367.0 38.0 SN65HVD3082EDR SOIC D 8 2500 340.5 338.1 20.6 SN65HVD3082EDR SOIC D 8 2500 367.0 367.0 35.0 SN65HVD3085EDGKR VSSOP DGK 8 2500 367.0 367.0 38.0 SN65HVD3085EDR SOIC D 8 2500 340.5 338.1 20.6 SN65HVD3088EDGKR VSSOP DGK 8 2500 367.0 367.0 38.0 SN65HVD3088EDR SOIC D 8 2500 340.5 338.1 20.6 SN75HVD3082EDGKR VSSOP DGK 8 2500 367.0 367.0 38.0 SN75HVD3082EDR SOIC D 8 2500 340.5 338.1 20.6 PACKAGE MATERIALS INFORMATION www.ti.com 26-Sep-2016 Pack Materials-Page 2

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