VP215

VP215 ZARLINK | Alldatasheet

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1 CLKIN

N.C. N.C. DA5 DA4 DA3 DA2 DA1 DA0 OGND VCCO DB5 DB4 DB3 DB2 DB1 DB0 VP215 Fig.1 Pin connections - top view (wide body) Fig.2 System block diagram The VP215 is a dual 90MHz 6-bit Analog to Digital Converter designed for use in consumer satellite receivers and decoders, video systems, multimedia and communications applications. Operating from a single +5V supply, the VP215 includes an on-chip high bandwidth ADC driver amplifier, a 6-bit ADC and digital I/O that can be interfaced to either +5V or +3V. The VP215 also has the necessary bias voltages for the reference resistor chain in the 'flash' architecture of the ADC.

FEATURES

n TTL Clock/Data Interface n 0.5 Volt Analog Input Range n Internal ADC Reference n Digital I/O’s compatible with +5V or +3V logic n Single 5 Volt Supply n Dual ADC System for good channel matching

APPLICATIONS

ORDERING INFORMATION

VP215A CG MP1S (Commercial - 28 pin plastic SO) VP215 Dual 90MHz 6-Bit Analog to Digital Converter Preliminary Information DS4068 - 1.4 May 1996

ELECTRICAL CHARACTERISTICS

Test conditions (unless otherwise stated) Tamb = 25°C, VCCA/D/O = +5V, full temperature range = 0°C to +70°C DC CHARACTERISTICS All specifications apply to either of the two ADCs Characteristic Symbol Temp. Test Level Min. Value Typ. Max. Units Conditions Resolution - - - 6 - - Bits Static performance Differential non-linearity Integral non-linearity DNL INL +25°C Full +25°C Full ±0.5 ±0.5 ±0.5 ±0.5 LSB LSB LSB LSB No missing codes Full 4 Guaranteed Power supply Analog supply voltage Digital supply voltage Output supply voltage Analog supply current Digital supply current Output supply current Power dissipation V CCA VCCD VCCO AICC DICC OICC PD Full Full Full +25°C Full +25°C Full +25°C Full +25°C 4.75 4.75 4.75 260 5.0 5.0 5.0 360 5.25 5.25 5.25 460 V V V mA mA mA mA mA mA mW Analog input Input range Input resistance Input capacitance Gain variation Gain matching Input -3dB bandwidth Ain input voltage Comp output V in R in C in G V G m F3dB Aindc Vcomp Full +25°C +25°C +25°C +25°C +25°C +25°C +25°C 20k 3.35 1.8 0.5 25k 4.0 200 3.6 2.0 30k 0.25 0.25 3.85 2.2 V Ω pF dB dB MHz V V Pk to Pk Fin=300Hz to 20MHz Fin=15.36MHz CLKIN Input voltage high Input voltage low Input current high Input current low V ih Vil Iih Iil +25°C Full +25°C Full +25°C Full +25°C Full 2.0 –0.2 –0.35 0.8 –0.5 V V V V µA mA V CCD = 5.25V Vin = 2.7V VCCD = 5.25V Vin = 0.4V TTL digital outputs Output voltage high Output voltage low Output current high Output current low V oh Vol Ioh Iol +25°C Full +25°C Full +25°C Full +25°C Full 2.4 3.0 0.4 -400 V V V V µA mA V CCO = 4.75V Ioh = 400µA VCCO = 4.75V Iol = 1mA VCCO = 4.75V VCCO = 4.75V THERMAL CHARACTERISTICS THERMAL RESISTANCES Junction to case(Θ jc) 32°C/W Junction to ambient(Θ ja) 84°C/W ABSOLUTE MAXIMUM RATINGS DC supply voltage (VCCA , VCCD , VCCO ) -0.3 to+7V Analog input voltage (VIN) -0.3 to VCC +0.3V Digital inputs (CLKIN) VCC Digital output current (Ioh, Iol, Isc)-20 to +20mA Ambient operating temperature (Tamb)0°C to +70°C Storage temperature (Tstorage) -55°C to +125°C

DC CHARACTERISTICS (cont.) Reference voltage Vref ladder bottom Vref ladder middle Vref ladder top VRB VRM VRT +25°C +25°C +25°C 2.367 2.848 3.337 2.525 3.04 3.55 2.671 3.212 3.763 V V V Characteristic Symbol Temp. Test Level Min. Value Typ. Max. Units Conditions AC CHARACTERISTICS Characteristic Symbol Temp. Test Level Min. Value Typ. Max. Units Conditions Switching performance Clock high pulse width Clock low pulse width Max. conversion rate Data output setup time Data output hold time Aperture delay Aperture delay matching Aperture jitter T pw 1 Tpw 0 Fmax Tsetup Thold Tad Tadδ Taj +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C 5.7 5.7 0.25 0.5 ns ns MHz ns ns ns ns ps rms Cload=10pF Cload=10pF Dynamic performance Differential non-linearity Integral non-linearity Signal to noise ratio Total harmonic distortion Effective No. of bits Crosstalk rejection Input offset Error rate DNL INL SNR THD ENOB CTR V os BER +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C –0.95 31.8 5.0 5.6 ±0.5 10e +1.2 LSB LSB dB dBc bits dBc LSB F CLK = 90.11MHz FIN = 11.26MHz NOTES 1. An input voltage of 0.0 volts ±0.5 LSB should nominally correspond to the ‘011111’ to ‘100000’B transition edge. TEST LEVELS Level 1 - 100% production tested. Level 2 - 100% production tested at 25°C and sample tested at specified temperatures. Level 3 - Sample tested only. Level 4 - Parameter is guaranteed by design and characterisation testing. Level 5 - Parameter is typical value only. Table 1: Output coding Code Input Voltage Digital Output

0.5 Volt Full Scale Binary

00 Least positive valid input000000

63 Most positive valid input111111

PIN DESCRIPTIONS - 28 Pin Plastic SO Package Pin Name Description CLKIN V CCD DGND VRT COMPA VINA AGND VCCA VRM COMPB VINB VRB N.C. N.C. DB0 DB1 DB2 DB3 DB4 DB5 V CCO OGND DA0 DA1 DA2 DA3 DA4 DA5 TTL clock input Digital voltage supply for ADC’s and input clock Digital ground Reference voltage- ladder top Capacitor compensation - A channel Analog signal input - A channel Analog ground Analog voltage supply for drivers and references Reference voltage- ladder middle Capacitor compensation - B channel Analog signal input - B channel Reference voltage- ladder bottom Not connected Not connected TTL digital output - channel B - LSB TTL digital output - channel B - MSB Output voltage supply for TTL data outputs Output ground TTL digital output - channel A - LSB TTL digital output - channel A - MSB Table 2: Pin descriptions Effective Number of Bits (ENOB) This is a measure of a device's dynamic performance and may be obtained from the SNR or from a sine wave curve test fit according to the following expressions: ENOB = SNR-1.76/6.02 or ENOB = N-log2[rms error (actual)/rms error (ideal)] where N is the conversion resolution and the actual rms error is the deviation from an ideal sine wave, calculated from the converter outputs with a sine wave input. Integral Non-linearity (INL) The deviation of the centre of each code from a reference line which has been determined by a least squares curve fit. Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude to the rms value of ‘noise’ which is defined as the sum of all other spectral components, including the harmonics, but excluding D.C. with a full-scale analog input signal. ELECTRICAL CHARACTERISTICS DEFINITIONS Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency, as determined by FFT analysis is reduced by 3dB. Aperture Delay The delay between the rising edge of the 90MHz clock signal and the instant the analog input signal is sampled. Aperture Jitter The sample to sample variation in aperture delay. Bit Error Rate (BER) The number of spurious code errors produced for any given input sinewave frequency at a given clock frequency. In this case it is the number of codes occurring outside the histogram cusp for a 1/2 FS sinewave. Data Outputs, Set-up and Hold Time Data output timings are measured from the 50% threshold to the 50% threshold on the rising edge of the output clock. Differential Non-linearity The deviation in any code width from an ideal 1 LSB step.

The VP215 is a dual 90MHz 6-bit ADC system, (see Fig.2). Included on chip is a high bandwidth ADC driver amplifier, a 6-bit analog to digital converter, latches and TTL compatible data outputs. The VP215 also has the necessary bias voltages for the reference resistor chain in the ‘flash’ architecture of the ADC. Analog Input The analog inputs, (VIN A,B) are A.C. coupled into the non-inverting input of the ADC driver amplifiers, which provide the necessary bandwidth, gain, offset and low impedance required to drive the ADC. The amplifier has been designed so that an input of 0 volts will produce an output level equal to the voltage present at the middle of the ADC resistor chain, VRM (3.00V typ.). This is achieved by an internal feedback loop within each amplifier which compares the amplifier output with VRM, (see Fig.3). This voltage will produce a transition binary code of 011111 to 100000 at the output of the ADC. Reference Voltage An on chip band gap voltage reference circuit combined with two op-amps provides all the necessary bias voltages for the ADC reference resistor chain, bottom (VRB), middle (VRM) and top(VRT). VRB, VRM and VRT have been brought out to pins 12, 9 and 4 respectively and should be decoupled with 100nF capacitors close to the package pins. ADC Circuit The VP215 employs a ‘flash’ architecture consisting of a reference resistor chain, an array of 64 comparators, encoding logic and a 6-bit latch. The 63 reference levels generated by the resistor chain are compared with the analog output signal from the ADC driver amplifier using the comparator array. This produces a thermometer code which the encoding logic converts into a 6-bit word. Digital Interface The TTL data output pins, (DA0-DA5) and (DB0-DB5), have been optimized to interface with devices in close proximity to the VP215 and are designed to provide satisfactory logic levels at speeds up to 90MHz into a fanout of one and a total load capacitance of 10pF. All data outputs should have approximately equivalent loading to ensure proper setup and hold times. For capacitive loads in excess of 10pF, output buffers are recommended. Clock Interface The clock signal to the ADC synchronizes the sampling, conversion and output stages of the device as shown in the timing diagram (see Fig.4). The output of the ADC driver amp is sampled when the comparator array is latched on the rising edge of the input clock. Data is then presented to the TTL data outputs and latched on the falling edge of the input clock. INPUT SIGNAL VRM TO ADC ADC DRIVER AMP C C C COMP COMP_(Q,I) DC SHIFT Fig.3 DC offset internal feedback loop τ1C LatchComparator L V ref. VIN(A,B) Clock to ADC Data Out CLKIN Data Outputs TTL Threshold Tpw 1 Tpw 0 VIN(A,B) THold N N+1N-1 N+1NN-1 Tsu Fig.4 System timing diagram

As with all high speed A to D converters, careful consideration must be given to the PCB layout. High performance can be obtained from the VP215 by tying all grounds to a solid low impedance ground plane. Separate analog and digital ground planes with a single common link under the device can also be used to help reduce the amount of digital noise fed back into the analog section of the converter. The VP215 should be decoupled with low impedance 100nF ceramic capacitors close to the package pins to avoid lead inductance effects and the decoupling on supply lines should further be improved by using a 47µF tantalum capacitor in parallel with a 100nF ceramic capacitor. If VCCA is derived from VCCD, a small inductor should be used to reduce digital noise on the analog power supply. Jitter and noise on clock input pins must be minimised. Long clock lines should therefore be avoided and all clock lines correctly terminated. Cross talk of digital signals to the analog inputs must also be prevented as sampling cross talk produces DC offsets on the sampled data, for this reason analog inputs should not be run next to clock or data lines. Device connections to the ground plane should be as short as possible. Application Circuit Fig.5 shows a typical applications circuit for the VP215. The supply connections are made using separate low noise digital and analog power supplies and VCCD is further isolated from VCCO using a 1.2µH inductor. The COMPA and COMPB pins must be decoupled to reduce any ripple at low frequencies which may distort the ADC driver amplifier output, (see Fig.2.) The decoupling capacitor value is determined by the required low frequency performance of the system and can be obtained from the following equation. C Comp = 75x10- 6 Fin x VRipple A ripple voltage ≤ 10mV is recommended for good system performance, e.g. If the analog input frequency Fin= 10KHz a value of 0.75µF is required for CComp . To ensure effective A.C. coupling at low input frequencies, the coupling capacitors on pins 6 and 11 can be calculated from the high pass filter corner frequency equation, where F c = Lower -3dB corner frequency (R = Input Resistance, 25K typ. - 20K min) Fc = 1 2 x π x RC Fig.5 Applications diagram VP215 14 15 Analog Ground Digital Ground A Channel Data B Channel Data CLKIN VINA VCCA VINB 1.2µH 47µ47µ 100n100n100n 100n C c C c C comp C comp 50R 50R 50R 100n VCCD 100n 100n 100n

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