VP1058 ZARLINK | Alldatasheet

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This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/

8-BIT, 25MHz, VIDEO FLASH ADC (SINGLE + 5V SUPPLY) DS3003 - 3.0 The VP1058 is a low power analog-to-digital flash converter which requires no preceding sample and hold stage. Operating from a single +5V supply, it is capable of digitising analog signals with frequencies up to the Nyquist limit. Output data is available in four possible 8-bit formats, selectable via two digital control inputs, giving either true or inverted code in binary or offset twos' complement.

FEATURES

n 60MHz 3dB Analog Input Bandwidth n Single +5V Supply Operation n Low Power Consumption (Typically 670mW) n +3V to +5V Analog Input Range n Selectable Data Format n TTL Compatible n Direct Replacement for TDC 1058 or CXA 1096P n Low Cost n No Missing Codes - Guaranteed

APPLICATIONS

n Low-Cost, High-Speed Data Conversion OPERATING TEMPERATURE RANGE Commercial 0°C to 70°C (Still - Air ambient)

ORDERING INFORMATION

VP1058 F CG DPAS (Commercial - Plastic DIL Package, DP28) VP1058 F CG HPAS (Commercial - Quad Plastic J Lead Package, HP28) VP1058 F CG DGAS (Commercial - Ceramic DIL Package, DG28) ABSOLUTE MAXIMUM RATINGS Supply voltage +7V Analog input, AIN VCC +0.5 Reference voltage VRT , VRB VCC +0.5 Reference voltage VRT , VRB 2.5V Digital inputs V CC Mid-ref input current -50mA to +50mA Digital output current -20mA to +20mA Voltage between AGND and DGND -0.5V to +0.5V Voltage between AV CC and DVCC -0.5V to +0.5V D 7 MSB NMINV D 6 VRM D 5 VRB D 4 AV CC DGND NC DV CC A IN AGND NC AGND A IN AGND NC DV CC AV CC DGND V RT NLINV CONV D 3 D 0 LSB D 2 D 1 12 8 VP1058 Pin Function D

7 MSB

D D 2 Function D 1 D 0 LSB CONV VRT AV CC NC A IN Pin Function NC A IN NC AV CC VRB VRM NMINV Pin Fig.1 Pin Connections (Top View) HP28 DP28 DG28 ADVANCE INFORMATION

Fig.2 Internal block diagram 19.25 6, 10 5, 11 21, 23 7, 8, 9 R R R R AV CC DV CC D 0 D 7 VRB VRM VRT CONV NLINV NMINV A IN R x 256 AGND DGND TTL/CMOS OUTPUTS MSB ENCODER D LATCH8 Pin No. 2 - 4 5, 11 6, 10 7 - 9 13 - 15 19, 25 20, 22, 24 21, 23

Description

Most significant bit (output data bit 7) Output data bits 6 to 4 Digital ground Digital supply pin (+5V) Analog ground Not Least significant bits INvert - inverts data D 0 to D6 when taken low Output data bits 3 to 1 Least significant bit (output data bit 0) Clock input - the rate of input (CONVert) clock signal determines the ADC sampling rate Top of reference resistor chain Analog supply pin Not connected Analog input pin Bottom of reference resistor chain Midpoint of reference resistor - can be used for linearity adjustment Not Most significant bit INvert - inverts data bit D 7 when taken low Function D 7 D 6 - D4 DGND DV CC AGND NLINV D 3 - D1 D 0 CONV VRT AV CC NC AIN VRB VRM NMINV PIN DESCRIPTIONS THERMAL CHARACTERISTICS Storage Temperature Range -65 °C to +150°C Maximum Junction Operating Temperature +175 °C Lead Temperature (soldering 60 seconds) 300 °C DP HP DG Junction to Ambient θjA 55 57 44 °C/W Junction to Case θjc 14 15 9 °C/W RECOMMENDED OPERATING CONDITIONS Supply Voltage 5V ± 0.25V Reference VRT 5V ± 0.1V Reference VRB 3V ± 0.1V AV CC to DVCC 0V ± 50mV Analog Input 4V ± 1V

VRT > VRB AIN at FS & 1.019MHz Clock min.high Clock min.low Max. conversion rate Aperture delay Output data delay Output hold time Aperture Jitter Dynamic Performance Differential non-linearity Integral non-linearity S/N ratio Effective No. of bits Characteristic Symbol Temp Test level Min. Typ. Max. Value. tPW1 tPW0 fMAX tAD tD tHO DNL INL SNR ENOB Full Full Full Full Full Full Full Full -0.85 ±0.5 44.5 44.0 43.5 43.5 43.0 7.2 7.1 7.0 ns ns MHz ns ns ns ns ns ps LSB LSB dB dB dB dB dB dB bits bits bits A IN at FS & 12.5MHz With standard LSTLL load fCLK = 25MHz AIN = 1.019MHz AIN = 1.019MHz AIN = 2.438MHz AIN = 2.438MHz AIN = 4.388MHz AIN = 4.388MHz AIN = 1.019MHz AIN = 2.438MHz AIN = 4.388MHz AC CHARACTERISTICS ConditionsUnits AV CC /DVCC ICC P AIN IIN f3dB C IN R D VRT VRB VRTO VRBO R TC VIH VIL IIH IIH IIL VOH VOL DNL INL Power Supply Supply voltage Supply current Power dissipation Analog Input Input range Input bias current 3dB bandwidth Input capacitance Reference Ladder Ladder resistance Ladder voltage (top) Ladder voltage (bottom) Ladder offset (top) Ladder offset (bottom) Ladder temp. coeff. Digital Inputs Logic '1' voltage Logic '0' voltage Logic '1' current Logic '1' current Logic '0' current Digital Outputs Logic '1' voltage Logic '0' voltage Static performance Differential non-linearity Integral non-linearity Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 4.75 105 500 540 V RB 2.5 2.0 2.4 2.4 125 125 670 670 150 100 5.0 3.0 0.33 ±0.5 ±0.5 ±0.5 ±0.5 5.25 165 150 900 830 V RT 500 145 125 AV CC + 0.1 0.8 350 -150 0.4 0.4 V mA mA mW mW V µA MHz pF Ω Ω V V mV mV Ω /°C V V µA µA µA V V V V LSB LSB LSB LSB AGND/DGND = 0V V I = VCC = MAX VI = 2.4V, VCC = MAX VI = 0.4V, VCC = MAX Into a standard LSTTL load Characteristic Symbol Temp Test level Min. Typ. Max. Value. ConditionsUnits

ELECTRICAL CHARACTERISTICS

These characteristics are guaranteed over the following conditions conditions (unless otherwise stated): VCC = +5V ± 0.25V, Tamb = 25°C DC CHARACTERISTICS

ELECTRICAL CHARACTERISTICS DEFINITIONS Analog Bandwidth The analog input frequency, at which the spectral power of the fundamental frequency as determined by Fast Fourier Transform analysis, is 3dB down on the DC level. Aperture Delay The delay between the falling edge of the CONV signal and the instant at which the analog input is sampled. Aperture Jitter The variation between successive samples of the aperture delay. Conversion Rate The maximum rate at which the converter will run. Differential Non-Linearity (DNL) The deviation of any code width from an ideal LSB step. Effective Number of Bits (ENOB) This is a measure of the dynamic performance which is calculated from the following expression.: ENOB = SNR-1.76 6.02 SNR is the signal-to-noise ratio, in decibels, at the test frequency. Integral Non-Linearity (INL) The deviation of the centre of each code from a reference line which has been determined by a least squares curve fit. Output Data Delay The delay between the 50% point of the rising edge of the CONV signal and the 50% point of any data output change. Reference Ladder Offset The voltage error at the ends of the resistor chain caused by the lead frame and bond wire. Signal-to-Noise Ratio (SNR) The ratio of the RMS signal amplitude to the RMS value of 'noise' which is defined as the sum of all other spectral components including harmonics but excluding DC with a full scale analog input signal. Test Levels Level 1 -100% production tested Level 2 -100% production tested at 25°C and sample tested at specified temperatures Level 3 -Sample tested only Level 4 -Parameter is guaranteed by design and characteristics testing Level 5 -Parameter is a typical value only CONVERSION TIMING Operation of the VP1058 requires that an external clock be applied to the CONV (convert) pin. This CONV signal synchronises the sampling, conversion, and output stages of the devices as shown in the timing diagram (Fig.3). The analog input is sampled when the comparator array is latched after a rising edge on the CONV pin. This rising edge also causes the result of the previous sample to be transferred to the outputs. Data at the outputs is latched at the same time as the 255 to 8 encoding of the current sample. Both these operations are performed on the falling edge of the CONV signal. This results in a 'pipeline' delay which means that the digital result of sample 'N' is available for acquisition by external circuitry whilst sample 'N+2' is being taken. The time interval between a rising edge on the CONV pin and the comparators latching is the aperture delay time (t AD ). This time may be subject to small variations mainly due to temperature and component matching. The short term uncertainty in the aperture delay time is specified by the aperture jitter (or aperture error). Output data becomes valid after t D (output data delay). Data remains valid for at least tHO (output hold time) after the rising edge of the CONV pin. Fig.3 Timing diagram DATA VALID N DATA VALID N+1DATA VALID N-1DATA VALID N-2 SAMPLE N SAMPLE N+1 SAMPLE N+2 SAMPLE N+3 PIPELINE DELAY DATA OUTPUT CONV VIN tAD tD tHOtpw1 tpw0 tCYC

GENERAL CIRCUIT DESCRIPTION The VP1058 employs a 'flash' architecture consisting of a reference resistor chain, an array of 256 comparators, encoding logic, and a full 8-bit D-type output latch. The 255 reference levels generated by the resistor chain are compared with the analog input signal by the comparator array. This produces a thermometer code which the encoding logic coverts into an 8-bit word. The D-type latch accepts this data and holds the outputs until the next conversion. The format of the output data is determined by the NLINV and NMINV control lines. Analog Input The maximum amplitude and offset of the input is defined by the setting of the two reference voltages V RB and VRT . A signal outside this range will cause the output to be either full- scale positive or full-scale negative, depending on whether the signal is off scale in the positive or negative direction. For optimum performance, the input signal should be biased at +4.0V with a 2V peak-to-peak amplitude. The necessary gain, offset and low impedance drive required for the input signal can be provided by use of a high slew rate ADC driver. Reference Voltage The reference chain between pins V RB and VRT is formed of 256 series resistors and has a total resistance of approximately 90Ω . A mid-reference pin, V RM , is provided for precise setting of the integral linearity, although adjustment is not necessary to meet the data sheet specification. The VP1058 will convert analog signals in the range V RB < AIN < VRT , where VRB and VRT are in the range +3V to +5V. (The design of the VP1058 has been optimised for VRB = 3V and VRT = 5V). All reference pins should be adequately decoupled close to the device. Output Format The output data format is controlled by the logic levels at the NLINV and NMINV pins as shown on the output coding table. These inputs are active low and may be tied to DV CC for logic '1' or DGND for logic '0'. Both inputs are considered DC controls and as such should only be altered while the converter is in the steady state. True NMINV = 1 NLINV = 1 0000 0000 0000 0001 l 0111 1111 1000 0000 1000 0001 l 1111 1110 1111 1111 Inverted 1111 1111 1111 1110 l 1000 0000 0111 1111 0111 1110 l 0000 0001 0000 0000 True 1000 0000 1000 0001 l 1111 1111 0000 0000 0000 0001 l 0111 1110 0111 1111 Inverted 0111 1111 0111 1110 l 0000 0000 1111 1111 1111 1110 l 1000 0001 1000 0000 20.V Full Scale 7.8431mV Step 5.0V 4.9922V l 4.0039V 3.9961V 3.9882V l 3.0079V 3.0V 2.048V Full Scale 8.0mV Step 5.0V 4.9922V l 3.9840V 3.9760V 3.9680V l 2.9680V 2.960V 000 001 l 127 128 129 l 254 255 Offset 2s' complementBinaryInput voltage Code Table 1 Output coding 40µA40µA AGND AV CC A IN VRB VRT Fig.4 Analog input Fig.5 TTL output stage DV CC DGND OUTPUT

As with all high speed analog-to-digital converters, careful consideration must be given to circuit layout. The best performance from the VP1058 can be achieved by use of separate analog and digital ground planes. Ideally these should be connected at a point close to the device. This will reduce the amount of digital switching noise fed back into the analog section of the converter, so aiding device performance. Supply line decoupling is important when dealing with mixed analog and digital signals, as they can provide a feedback path from the digital output currents. Therefore, the VP1058 should be decoupled close to the device supply pins with good quality high frequency, low inductance capacitors. Due to the high clock rates, long clock lines to the device should be avoided to reduce noise pick up. A typical applications circuit is shown below. The analog input amplifier should be a wideband, high slew rate op-amp used to drive the input directly. A stable reference is needed for both input offset and gain control (e.g. REF12Z micropower voltage reference as shown in Fig.6). Both analog input pins should be connected close to the device with the input amplifiers feedback loop closed at the point. The reference inputs should be adequately decoupled to ground so as to limit the effects of system noise on conversion accuracy. A capacitor at the mid-reference point (as shown) may be useful in correcting any inherent reference ladder skew. The circuit will accept a 1V p-p video signal and level shift and multiply it to provide the recommended 2V p-p signal to drive the VP1058. 1DB7 28NMINV 12LNINV 2DB6 3DB5 4DB4 13DB3 14DB2 15DB1 16DB0 +5V DV CC +5V AV CC +5V AV CC AV CCDV CC VRT VRB VRM A IN A IN CONV17 DGND 5, 11 AGND 7, 8, 9 +5V 0.1µ 0.1µ 1N4148 0.1µ 0.1µ 6, 10 19, 25 +12V 2N2222TAB1043 0.1µ 6K2 2.9k 3.3k +12V 0.1µ TAB1043 2N2907 REFGAIN AD842 OR SIMILAR1k REF12Z (1.22V REFERENCE) 1k 1k ANALOG INPUT (VANIN ) 0.1µ 1.3k 0.1µ OFFSET CLOCK VO VOUTVREF 390 VP1058 Fig.6 Typical applications circuit

GEC PLESSEY SEMICONDUCTORS Cheney Manor, Swindon, Wiltshire SN2 2QW, United Kingdom. Tel: (0793) 518000 Fax: (0793) 518411 GEC PLESSEY SEMICONDUCTORS P.O. Box 660017

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www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request. Purchase of Zarlink’s I2C components conveys a licence under the Philips I 2C Patent rights to use these components in and I 2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE For more information about all Zarlink products visit our Web Site at