VP1040

SN65HVD1040 TI | Alldatasheet

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6 CANL

WAKE□UP FILTER BUS□MONITOR MUX OVER TEMPERATURE SENSOR DRIVER TIME -OUT DOMINANT 1TXD

30 A/c109

10 A/c109

5 SPLIT/ 2

Wake-up: µ A Typical Telecom Base Station Status and Control Bus-Fault Protection of V to V SAE J1939 Standard Data Bus Interface Rugged Split-Pin Bus Stability NMEA 2000 Standard Data Bus Interface Dominant Time-Out Function ISO 11783 Standard Data Bus Interface Power-Up/Down Glitch-Free Bus Inputs and Industrial Automation Outputs DeviceNet Data Buses High Input Impedance with Low V CC Monotonic Outputs During Power Cycling DeviceNet Vendor ID 806 The SN65HVD1040 meets or exceeds the specifications of the ISO 11898 standard for use in a Controller Area Network (CAN). As CAN transceivers, these devices provide differential transmit and receive capability for a CAN controller at signaling rates of up to megabit per second (Mbps) (1) Designed for operation in especially harsh environments, the device pins, cross-wire, overvoltage and loss of ground protection from to overtemperature shutdown, a V to V common-mode range, and will withstand voltage transients from 200 V to 200 V according to ISO 7637. (1) The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. DeviceNet is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com (Continued) TXD GND VCC RXD STB CANH CANL SPLIT SN65HVD1040 SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. The STB input (pin selects between two different modes of operation; high-speed or low-power mode. The high-speed mode of operation is selected by connecting STB to ground. If a high logic level is applied to the STB pin of the SN65HVD1040, the device enters a low-power bus-monitor standby mode. While the SN65HVD1040 is in the low-power bus-monitor standby mode, a dominant bit greater than µ s on the bus is passed by the bus-monitor circuit to the receiver output. The local protocol controller may then reactivate the device when it needs to transmit to the bus. A dominant-time-out circuit in the SN65HVD1040 prevents the driver from blocking network communication during a hardware or software failure. The time-out circuit is triggered by a falling edge on TXD (pin 1). If no rising edge is seen before the time-out constant of the circuit expires, the driver is disabled. The circuit is then reset by the next rising edge on TXD. The SPLIT output (pin is available on the SN65HVD1040 as a V CC common-mode bus voltage bias for a split-termination network. The SN65HVD1040 is characterized for operation from C to 125 ORDERING INFORMATION DOMINANT LOW-POWER MARKED PART NUMBER PACKAGE (1) ORDERING NUMBER TIME-OUT BUS MONITOR AS SN65HVD1040D (rail) SN65HVD1040 YES YES SOIC-8 VP1040 SN65HVD1040DR (reel) (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com Submit Documentation Feedback

www.ti.com ABSOLUTE MAXIMUM RATINGS (1) RECOMMENDED OPERATING CONDITIONS SUPPLY CURRRENT DEVICE SWITCHING CHARACTERISTICS SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 VALUE V CC Supply voltage (2) 0.3 V to V V I(bus) Voltage range at any bus terminal (CANH, CANL, SPLIT) V to V I O(OUT) Receiver output current -20 mA to mA Voltage input, transient pulse (3) (CANH, CANL, SPLIT) 200 V to 200 V Human Body Model Bus terminals and GND kV Human body model (4) All pins kV ESD Charged-device-model (5) All pins kV Machine model 200 V V I Voltage input range (TXD, STB) 0.5 V to V T J Junction temperature C to 170 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. (3) Tested in accordance with ISO 7637, test pulses 3a, 3b, (4) Tested in accordance JEDEC Standard 22, Test Method A114-A. (5) Tested in accordance JEDEC Standard 22, Test Method C101. MIN NOM MAX UNIT V CC Supply voltage 4.75 5.25 V V I or V IC Voltage at any bus terminal (separately or common mode) (1) V V IH High-level input voltage 5.25 V TXD, STB V IL Low-level input voltage 0.8 V V ID Differential input voltage V Driver I OH High-level output current mA Receiver Driver I OL Low-level output current mA Receiver t SS Maximum pulse width to remain in standby 0.7 µ s T J Junction temperature 150 C (1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet. over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Dominant V I Ω Load, STB at V mA I CC Supply current, V CC Recessive V I V CC STB at V Standby STB at VCC, VI VCC µ A over recommended operating conditiions (unless otherwise noted) TEST MIN TYP MAX UNIT PARAMETER CONDITIONS t loop1 Total loop delay, driver input to receiver output, Recessive to Dominant 230 STB at ns See Figure t loop2 Total loop delay, driver input to receiver output, Dominant to Recessive 230 Submit Documentation Feedback

www.ti.com DRIVER ELECTRICAL CHARACTERISTICS DRIVER SWITCHING CHARACTERISTICS SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 over recommended operating conditiions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT CANH 2.9 3.4 4.5 Bus output voltage V I STB at R L Ω See Figure and V O(D) V (Dominant) Figure CANL 0.8 1.75 V O(R) Bus output voltage (Recessive) V I STB at See Figure and Figure 2.5 V V O Bus output voltage (Standby) R L Ω STB at V CC See Figure and Figure 0.1 0.1 V V I R L Ω STB at See Figure and 1.5 Figure and Figure V OD(D) Differential output voltage (Dominant) V V I R L Ω STB at See Figure and 1.4 Figure Output symmetry (Dominant or V SYM STB at See Figure and Figure 0.9 V CC V CC 1.1 V CC V Recessive) V O(CANH) V O(CANL) V I R L Ω STB at See Figure and 0.012 0.012 Figure V OD(R) Differential output voltage (Recessive) V V I STB at No Load 0.5 0.05 Common-mode output voltage V OC(D) 2.3 (Dominant) STB at See Figure V Peak-to-peak common-mode output V OC(pp) 0.3 voltage I IH High-level input current, TXD input V I at V CC µ A I IL Low-level input current, TXD input V I at V µ A I O(off) Power-off TXD Leakage current V CC at TXD at V µ A V CANH CANL Open, See Figure 120 V CANH CANL Open, See Figure 0.36 Short-circuit steady-state output I OS(ss) mA current V CANL CANH Open, See Figure 0.5 V CANL CANH Open, See Figure 120 See Input capacitance to ground in RECEIVER C O Output capacitance ELECTRICAL CHARACTERISTICS (1) All typical values are at C with a 5-V supply. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t PLH Propagation delay time, low-to-high-level output 120 t PHL Propagation delay time, high-to-low-level output 120 t sk(p) Pulse skew (|t PHL t PLH STB at See Figure ns t r Differential output signal rise time t f Differential output signal fall time t en Enable time from silent mode to dominant See Figure µ s t dom Dominant time-out See Figure 300 450 700 µ s Submit Documentation Feedback

www.ti.com RECEIVER ELECTRICAL CHARACTERISTICS RECEIVER SWITCHING CHARACTERISTICS SPLIT-PIN CHARACTERISTICS STB-PIN CHARACTERISTICS SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT Positive-going input threshold V IT+ 800 900 voltage STB at See Table High-speed Negative-going input threshold V IT mode 500 650 mV voltage V hys Hysteresis voltage IT+ V IT STB at V CC 100 125 V IT Input threshold voltage Standby mode STB at V CC 500 1150 V OH High-level output voltage I O mA, See Figure 4.6 V V OL Low-level output voltage I O mA, See Figure 0.2 0.4 V CANH or CANL V CC at I I(off) Power-off bus input current µ A TXD at V I O(off) Power-off RXD leakage current V CC at RXD at V µ A C I Input capacitance to ground, (CANH or CANL) TXD at V I 0.4 sin (4E6 π 2.5 V pF C ID Differential input capacitance TXD at V I 0.4 sin (4E6 π pF R ID Differential input resistance TXD at STD at V k Ω R IN Input resistance, (CANH or CANL) TXD at STD at V Input resistance matching R I(m) V CANH V CANL IN (CANH) R IN (CANL) x 100% (1) All typical values are at C with a 5-V supply. over recommended operating conditiions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t pLH Propagation delay time, low-to-high-level output 100 130 t pHL Propagation delay time, high-to-low-level output 130 STB at TXD at See ns Figure t r Output signal rise time t f Output signal fall time t BUS Dominant time required on bus for wake-up from STB at V CC Figure 0.7 µ s standby (1) (1) The device under test shall not signal a wake-up condition with dominant pulses shorter than t BUS (min) and shall signal a wake-up condition with dominant pulses longer than t BUS (max). Dominant pulses with a length between t BUS (min) and t BUS (max) may lead to a wake-up. over recommended operating conditiions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT V O Output voltage 500 µ A I O 500 µ A 0.3 V CC 0.5 V CC 0.7 V CC V I O(stb) Standby mode leakage current STB at V V O V µ A over recommended operating conditiions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I IH High level input current STB at V µ A I IL Low level input current STB at V µ A Submit Documentation Feedback

www.ti.com PARAMETER MEASUREMENT INFORMATION 2.5 V 3.5 V 1.5 V Recessive Dominant O(CANH)V O(CANL)V TXD STB II VI VOD RL IO(CANH) VO(CANH) VOCIO(CANL) VO(CANL) VO(CANH) + VO(CANL)

0 V VOD

60 /C0087 /C00431% 330 /C0087 /C00431% 330 /C0087 /C00431% −2 V /C0051 VTEST /C0051 7 V R L = 60 /C0087 /C00431\`% VO STB CANH CANH V I TXD (see Note A) tftr 10% 90%0.9 V 0 V V O(D) V I VO VO(R) C L = 100 pF /C004320% (see Note B) VCC VCC tPLH tPHL 0.5 V VCC V O CANH CANL RXD V I(CANH) V I (CANL) IOV IDVI(CANH) + VI(CANL) 2VIC = SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 Figure Driver Voltage, Current, and Test Definition Figure Bus Logic State Voltage Definitions Figure Driver V OD Test Circuit Figure Driver Test Circuit and Voltage Waveforms Figure Receiver Voltage and Current Definitions Submit Documentation Feedback

www.ti.com CANH CANL RXD V I STB VO IO 2□V 2.4□V 3.5□V VOH t ft r 1.5□V VOL 90% 10% VI VO 1.5□V (see□Note A) CL =□15□pF 20% (see□Note□B) tPLH tPLH 0.7□VCC 0.3□VCC 50% 50% CANH CANL C L TXD STB RXD V O − 15 pF /C004320% DUT 60 /C0087 /C00431% VI VO ten VCC 0 V V OH VOL NOTE: C L = 100 pF Includes Instrumentation and Fixture Capacitance Within ±20% CANH CANL V I TXD STB 27 /C0087 /C00431% 27 /C0087 /C00431% 47 nF /C004320% VOC = VO (CANH) + VO (CANL) VOC VOC(PP) SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 PARAMETER MEASUREMENT INFORMATION (continued) The input pulse is supplied by a generator having the following characteristics: PRR 125 kHz, 50% duty cycle, t r ns, t f 6ns, Z O Ω C L includes instrumentation and fixture capacitance within 20%. Figure Receiver Test Circuit and Voltage Waveforms Table Differential Input Voltage Threshold Test INPUT OUTPUT V CANH V CANL ID R 11.1 V V 900 mV L V OL V 11.1 V 900 mV L V V V L V V V L 11.5 V V 500 mV H V OH V 11.5 V 500 mV H V V V H V V V H Open Open X H Figure t en Test Circuit and Voltage Waveforms All V I input pulses are from V to V CC and supplied by a generator having the following characteristics: t r or t f ns. Pulse Repetition Rate (PRR) 125 kHz, 50% duty cycle. Figure Peak-to-Peak Common Mode Output Voltage Test and Waveform Submit Documentation Feedback

www.ti.com 50% 50%50% NOTE: C L = 100 pF Includes Instrumentation and Fixture Capacitance Within ±20% CANH CANL C L TXD STB RXD V O − 15 pF /C004320% DUT 60 /C0087 /C00431% TXD Input RXD Output tloop2 tloop1 VCC 0 V V OH VOL STB CANH CANL V O 500 mV900 mV C L (see Note B) R L = 60 /C0087 /C00431% TXD (see Note A) VI VO tdom VCC 0 V V OD(D) 0 V VI 1.5 V CANH CANL RXD VO V I IO C L STB 3.5 V V I V O 400 mV 2.65 V 1.5 V VOH V OL (see Note A) VCC (see Note B) 0.7 /C0109s tBUS SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 All V I input pulses are from V to V CC and supplied by a generator with the following characteristics: t r or t f ns. Pulse Repetition Rate (PRR) 125 kHz, 50% duty cycle. Figure t loop Test Circuit and Voltage Waveforms All V I input pulses are from V to V CC and supplied by a generator with the following characteristics: t r or t f ns. Pulse Repetition Rate (PRR) 500 Hz, 50% duty cycle. C L 100 pF includes instrumentation and fixture capacitance within 20%. Figure 10. Dominant Time-Out Test Circuit and Waveform For V I bit width 0.7 µ V O V OH For V I I bit width µ V O V OL V I input pulses are supplied from a generator with the following characteristics; t r or t f ns. Pulse Repetition Rate (PRR) Hz, 30% duty cycle. C L pF includes instrumentation and fixture capacitance within 20%. Figure 11. t BUS Test Circuit and Waveform Submit Documentation Feedback

www.ti.com CANH CANLSTB Vin Vin 0 V 0 V 12 V −12 V or 0 V

0 V or V

VIN −12 V or 12 V IOS(P) 200 /C0109s IOS(SS) 10 /C0109s CANH CANL 4.7 nF VI TXD STB 60 1% 60 1% O(CANL)V O(CANH)V SYMV = + O (CANL)VO( CANH)V 20% ±/c87 /c87 ± SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 Figure 12. Driver Short-Circuit Current Test and Waveform Figure 13. Driver Output Symmetry Test Circuit Submit Documentation Feedback

www.ti.com DEVICE INFORMATION THERMAL CHARACTERISTICS SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 Table DRIVER FUNCTION TABLE (1) INPUTS OUTPUTS BUS STATE TXD STB CANH CANL L L H L DOMINANT H L Z Z RECESSIVE Open X Z Z RECESSIVE X H or Open Z Z RECESSIVE (1) H high level; L low level; X irrelevant; Z high impedance Table RECEIVER FUNCTION TABLE (1) DIFFERENTIAL INPUTS STB OUTPUT BUS STATE V ID CANH CANL RXD V ID 0.9 V L L DOMINANT V ID 1.15 V H or Open L DOMINANT 0.5 V V ID 0.9 V X V ID 0.5 V X H RECESSIVE Open X H RECESSIVE (1) H high level; L low level; X irrelevant; indeterminate; Z high impedance over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Low-K Thermal Resistance (1) 211 C/W θ JA Thermal Resistance, Junction-to-Air High-K Thermal Resistance 131 C/W θ JB Thermal Resistance, Junction-to-Board C/W θ JC Thermal Resistance, Junction-to-Case R L Ω S at P D Device Power Dissipation 112 170 mW Input to TXD a 500kHz 50% duty-cycle square wave T JS Junction Temperature, Thermal Shutdown (2) 190 C (1) Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. (2) Extended operation in thermal shutdown may affect device reliability, see the Application Information section. Submit Documentation Feedback

www.ti.com DEVICE INFORMATION SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 Table Parametric Cross Reference With the TJA1040 TJA1040 (1) PARAMETER HVD10xx TJA1040 DRIVER SECTION V IH High-level input voltage Recommended V IH V IL Low-level input voltage Recommended V IL I IH High-level input current Driver I IH I IL Low-level input current Driver I IL TJA1040 BUS SECTION V th(dif) Differential input voltage Receiver V IT and recommended V ID V hys(dif) Differential input hysteresis Receiver V hys V O(dom) Dominant output voltage Driver V O(D) V O(reces) Recessive output voltage Driver V O(R) V i(dif)(th) Differential input voltage Receiver V IT and recommended V ID V O(dif0(bus) Differential bus voltage Driver V OD(D) and V OD(R) I LI Power-off bus input current Receiver I I(off) I O(SC) Short-circuit output current Driver I OS(SS) R i(cm) CANH, CANL input resistance Receiver R IN R i(def) Differential input resistance Receiver R ID R i(cm) (m) Input resistance matching Receiver R I (m) C i(cm) Input capacitance to ground Receiver C I C i(dif) Differential input capacitance Receiver C ID TJA1040 RECEIVER SECTION I OH High-level output current Recommended I OH I OL Low-level output current Recommended I OL TJA1040 SPLIT PIN SECTION V O Reference output voltage V O TJA1040 TIMING SECTION t d(TXD-BUSon) Delay TXD to bus active Driver t PLH t d(TXD-BUSoff) Delay TXD to bus inactive Driver t PHL t d(BUSon-RXD) Delay bus active to RXD Receiver t PHL t d(BUSoff-RXD) Delay bus inactive to RXD Receiver t PLH t PD(TXD RXD) Prop delay TXD to RXD Device t LOOP1 and t LOOP2 t d(stb-norm) Enable time from standby to dominant Driver t en TJA1040 STB PIN SECTION V IH High-level input voltage Recommended V IH V IL Low-level input voltage Recommended V IL I IH High-level input current I IH I IL Low-level input current I IL (1) From TJA1040 Product Specification, Philips Semiconductors, 2003 February 19. Submit Documentation Feedback

www.ti.com Equivalent Input and Output Schematic Diagrams Vcc RXD□Output 6 V Output 15 /c87 Vcc SPLIT□Output Output 2 k /c87 2 k /c87 40 V STB□Input Vcc 6 V Input /c87 Vcc 40 V Output CANH□and□CANL Outputs CANH□Input Vcc 20 k 40 V Input 10 k /c87 10 k/c87 /c87 TXD□Input Vcc 4. 3 k 6 V Input /c87 CANL Input Vcc 20 k 40 V Input 10 k /c87 10 k/c87 /c87 4.3 k SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 Submit Documentation Feedback

www.ti.com TYPICAL CHARACTERISTICS 120 125 130 135 140 145 150 −40 0 25 70 125 VCC =□4.75□V VCC =□5□V VCC =□5.25□V Recessive-to-Dominant□Loop□T ime − ns tLOOP1 TA − Free-Air□T emperature − /c176C S□at□0□V, R =□60 , C =□100□pF, Air□Flow□at□7□cf/m, 50%□Duty□Cycle□Pulse L L /c87 140 145 150 155 160 165 170 −40 0 25 70 125 VCC =□5.25□V − Dominant-to-Recessive□Loop□T ime − ns tLOOP2 TA − Free-Air□T emperature − /c176C VCC =□5□V VCC =□4.75□V S□at□0□V, R =□60 , C =□100□pF, Air□Flow□at□7□cf/m, 50%□Duty□Cycle□Pulse L L /c87 −10 0 1 2 3 4 5 TA = 25/C0053C, VCC = 5 V, S at 0 V, TXD Input is a 125 kHz 1% Duty Cycle Pulse IOL − Low-Level Output Current − mA VO CANL − Low-Level Output Voltage − V 200 400 500 600 800 1000 Signaling Rate − kbps ICC − RMS Supply Current − mA TA = 25/C0053C, VCC = 5 V, S at 0 V, R L = 60 /C0087, RXD = 15 pF SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 RECESSIVE-TO-DOMINANT LOOP TIME DOMINANT-TO-RECESSIVE LOOP TIME vs vs FREE-AIR TEMPERATURE (across V CC FREE-AIR TEMPERATURE (across V CC Figure 14. Figure 15. SUPPLY CURRENT (RMS) DRIVER LOW-LEVEL OUTPUT VOLTAGE vs vs SIGNALING RATE LOW-LEVEL OUTPUT CURRENT Figure 16. Figure 17. Submit Documentation Feedback

www.ti.com -10 -20 -30 -40 -50 -60 -70 -80 0 1 2 3 4 5 TA =□25 C, VCC =□5□V , S□at□0□V , 1%□Duty□Cycle□Pulse IOH − High-Level□Output□Current − mA VOCANH − High-Level□Output□V oltage − V 0.5 1.5 2.5 −40 0 25 70 125 S at 0 V, R L = 60 /C0087, Air Flow at 7 cf/m, TXD Input is a 125 kHz 1% Duty Cycle Pulse TA − Free-Air Temperature − °C VCC = 5 V VCC = 4.75 V VCC = 5.25 V Dominant Driver Differential Output Voltage − V 1 2 3 3.5 4 4.5 5 5.25 TA = 25/C0053C, VCC = 5 V, S at 0 V, R L = 60 /C0087, TXD Input is a 125 kHz 1% Duty Cycle Pulse IO − Differential Driver Output Current − mA VCC − Supply Voltage − V 0.60 0.65 0.70 0.75 0.80 0.85 0.85 0.80 0.75 0.70 0.65 0.60 VIT+ VIT− VCM = 12 V VCM = 2.5 V VCM = −12 V TA = 25/C0053C, VCC = 5 V, S at 0 V, RXD = 15 pF − Receiver Output Voltage − VVO VID − Differential Input Voltage − V SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) DRIVER HIGH-LEVEL OUTPUT VOLTAGE DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs vs HIGH-LEVEL OUTPUT CURRENT FREE-AIR TEMPERATURE (across V CC Figure 18. Figure 19. DRIVER OUTPUT CURRENT RECEIVER OUTPUT VOLTAGE vs vs SUPPLY VOLTAGE DIFFERENTIAL INPUT VOLTAGE Figure 20. Figure 21. Submit Documentation Feedback

www.ti.com DB V /c109 0.1 1 10 100 1000 f − Frequency − MHz dBm SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 TYPICAL CHARACTERISTICS (continued) TYPICAL ELECTROMAGNETIC EMISSIONS TYPICAL ELECTROMAGNETIC UP TO MHZ (Peak Amplitude) IMMUNITY PERFORMANCE Figure 22. Frequency Spectrum of Common-Mode Figure 23. Direct Power Injection (DPI) Response vs Emissions Frequency Submit Documentation Feedback

www.ti.com APPLICATION INFORMATION CAN Basics SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 The basics of arbitration require that the receiver at the sending node designate the first bit as dominant or recessive after the initial wave of the first bit of a message travels to the most remote node on a network and back again. Typically, this sample is made at 75% of the bit width, and within this limitation, the maximum allowable signal distortion in a CAN network is determined by network electrical parameters. Factors to be considered in network design include the approximately ns/m propagation delay of typical twisted-pair bus cable; signal amplitude loss due to the loss mechanisms of the cable; and the number, length, and spacing of drop-lines (stubs) on a network. Under strict analysis, variations among the different oscillators in a system also need to be accounted for with adjustments in signaling rate and stub and bus length. Table lists the maximum signaling rates achieved with the SN65HVD1040 with several bus lengths of category shielded twisted pair (CAT STP) cable. Table Maximum Signaling Rates for Various Cable Lengths Bus Length (m) Signaling Rate (kbps) 1000 100 500 250 250 500 125 1000 62.5 The ISO 11898 Standard specifies a maximum bus length of m and maximum stub length of 0.3 m with a maximum of nodes. However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus. (Note: Non-standard application may come with a trade-off in signaling rate.) A large number of nodes requires a transceiver with high input impedance such as the HVD1040. The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120 Ω characteristic impedance O Resistors equal to the characteristic impedance of the line terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines connect nodes to the bus and should be kept as short as possible to minimize signal reflections. Connectors, while not specified by the standard should have as little effect as possible on standard operating parameters such as capacitive loading. Although unshielded cable is used in many applications, data transmission circuits employing CAN transceivers are usually used in a rugged interconnection with a wide common-mode voltage range. Therefore, shielded cable is recommended in these electronically harsh environments, and when coupled with the Standard s 2-V to 7-V common-mode range of tolerable ground noise, helps to ensure data integrity. The HVD1040 enhances the Standard s insurance of data integrity with an extended V to V range of common-mode operation. Submit Documentation Feedback

www.ti.com 75% SAMPLE POINT 500 mV Threshold 900 mV Threshold ALLOWABLE JITTER NOISE MARGIN NOISE MARGIN RECEIVER DETECTION WINDOW /c87120 /c87120 CANH CANL TMS320LF243 SN65HVD1040 D R STB SPLIT CANTX CANRX Sensor, Actuator, or Control Equipment TMS320LF243 D R 0.1/c109F Vcc GNDSTB CANTX CANRX Sensor, Actuator, or Control Equipment TMS320LF2407A SN65HVD230 D R Rs Vref CANTX CANRX Sensor, Actuator, or Control Equipment 5 V 0.1/c109F Vcc GND 5 V 0.1/c109F Vcc GND 3.3 V Stub Lines -- 0.3 m max Bus Lines -- 40 m max SN65HVD1040 SPLIT SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 Figure 24. Typical CAN Differential Signal Eye-Pattern An eye pattern is a useful tool for measuring overall signal quality. As displayed in Figure the differential signal changes logic states in two places on the display, producing an eye. Instead of viewing only one logic crossing on the scope, an entire bit of data is brought into view. The resulting eye pattern includes all of the effects of systemic and random distortion, and displays the time during which a signal may be considered valid. The height of the eye above or below the receiver threshold voltage level at the sampling point is the noise margin of the system. Jitter is typically measured at the differential voltage zero-crossing during the logic state transition of a signal. Note that jitter present at the receiver threshold voltage level is considered by some to be a more effective representation of the jitter at the input of a receiver. As the sum of skew and noise increases, the eye closes and data is corrupted. Closing the width decreases the time available for accurate sampling, and lowering the height enters the 900 mV or 500 mV threshold of a receiver. Different sources induce noise onto a signal. The more obvious noise sources are the components of a transmission circuit themselves; the signal transmitter, traces and cables, connectors, and the receiver. Beyond that, there is a termination dependency, cross-talk from clock traces and other proximity effects, V CC and ground bounce, and electromagnetic interference from near-by electrical equipment. The balanced receiver inputs of the HVD1040 mitigate most all sources of signal corruption, and when used with a quality shielded twisted-pair cable, help insure data integrity. Figure 25. Typical HVD1040 Application Submit Documentation Feedback

www.ti.com Thermal Shutdown SN65HVD1040 SLLS631B MARCH 2007 REVISED APRIL 2007 The SN65HVD1040 has a thermal shutdown that turns off the driver outputs when the junction temperature nears 190 This shutdown prevents catastrophic failure from bus shorts, but does not protect the circuit from possible damage. The user should strive to maintain recommended operating conditions, and not exceed absolute maximum ratings at all times. If the SN65HVD1040 is subjected to many or long durations faults that can put the device into thermal shutdown, it should be replaced. Submit Documentation Feedback

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN65HVD1040D ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1040DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1040DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN65HVD1040DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 7-May-2007 Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 1

Device Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant SN65HVD1040DR D 8 TAI 330 12 6.4 5.2 2.1 8 12 PKGORN T1TR-MS P TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN65HVD1040DR D 8 TAI 346.0 346.0 29.0 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2007 Pack Materials-Page 2

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