OMNIFET II fully autoprotected Power MOSFET
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 21
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 2 Electrical specifications
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Electrical characteristics
- 2.4 Electrical characteristics curves
- 3 Protection features
- 3.1 Overvoltage clamp protection
- 3.2 Linear current limiter circuit
- 3.3 Overtemperature and short circuit protection
- 3.4 Status feedback
- 4 Package and packing information
- 4.1 ECOPACK ® packages
- 4.2 SO-8 Package mechanical data
- 4.3 SO-8 Packing information
- 5 Revision history
Features
■ Linear current limitation ■ Thermal shut down ■ Short circuit protection ■ Integrated clamp ■ Low current drawn from input pin ■ Diagnostic feedback through input pin ■ Esd protection ■ Direct access to the gate of the power mosfet (analog driving) ■ Compatible with standard power mosfet
Description
The VNS3NV04D-E is a device formed by two monolithic OMNIFET II chips housed in a standard SO-8 package. The OMNIFET II are designed in STMicroelectronics VIPower M0-3 Technology: they are intended for replacement of standard Power MOSFETS from DC up to 50KHz applications. Built in thermal shutdown, linear current limitation and overvoltage clamp protects the chip in harsh environments. Fault feedback can be detected by monitoring the voltage at the input pin. Max On-State resistance (per ch.) R ON 120m Current limitation (typ) I LIMH 3.5A Drain-Source clamp voltage V CLAMP 40V SO-8 Table 1. Device summary
1 Block diagram and pin description
Figure 1. Block diagram Figure 2. Configuration diagram (top view)
2 Electrical specifications
Figure 3. Current and voltage conventions
2.1 Absolute maximum ratings
program and other relevant quality document. Table 2. Absolute maximum ratings
2.2 Thermal data
2.3 Electrical characteristics
Values specified in this section are for -40°C< Tj <150°C, unless otherwise stated. Table 3. Thermal data
- When mounted on a standard single-sided FR4 board with 50mm 2 of Cu (at least 35 m thick) connected
Table 4. Off Table 5. On
Table 6. Dynamic Table 7. Switching Table 8. Source Drain diode
- Pulsed: Pulse duration = 300 s, duty cycle 1.5%
Figure 4. Switching time test circuit for resistive load Table 9. Protections (-40°C < Tj < 150°C, unless otherwise specified)
2.4 Electrical characteristics curves
Figure 9. Source-Drain diode forward Figure 10. Static Drain-Source On Figure 11. Derating curve Figure 12. Static Drain-Source On Figure 13. Static Drain-Source On Figure 14. Transconductance
Protection features VNS3NV04D-E
3 Protection features
During normal operation, the INPUT pin is electrically connected to the gate of the internal power MOSFET through a low impedance path. The device then behaves like a standard power MOSFET and can be used as a switch from DC up to 50KHz. The only difference from the user’s standpoint is that a small DC current I ISS (typ. 100A) flows into the INPUT pin in order to supply the internal circuitry. The device integrates:
3.1 Overvoltage clamp protection
Internally set at 45V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads.
3.2 Linear current limiter circuit
Limits the drain current ID to Ilim whatever the INPUT pin voltages. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold T jsh.
3.3 Overtemperature and short circuit protection
These are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs in the range 150 to 190 °C, a typical value being 170 °C. The device is automatically restarted when the chip temperature falls of about 15°C below shut-down temperature.
3.4 Status feedback
In the case of an overtemperature fault condition (Tj > Tjsh), the device tries to sink a diagnostic current Igf through the INPUT pin in order to indicate fault condition. If driven from a low impedance source, this current may be used in order to warn the control circuit of a device shutdown. If the drive impedance is high enough so that the INPUT pin driver is not able to supply the current I gf, the INPUT pin will fall to 0V. This will not however affect the device operation: no requirement is put on the current capability of the INPUT pin driver except to be able to supply the normal operation drive current I ISS. Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit. Obsolete Product(s) - Obsolete Product(s)
4 Package and packing information
4.1 ECOPACK ® packages
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Obsolete Product(s) - Obsolete Product(s)
4.2 SO-8 Package mechanical data
Figure 30. SO-8 Package mechanical data & package outline exceed 0.15mm in total (both side).
- Dimension “E1” does not include interlead flash
4.3 SO-8 Packing information
Figure 31. SO-8 Tube shipment (no suffix) Figure 32. SO-8 Tape and reel shipment (suffix “TR”)
5 Revision history
Table 10. Document revision history 28-Oct-2005 1 Initial release. 25-Jun-2007 2 Document reformatted and converted into new ST template. 25-Sep-2013 3 Updated disclaimer.