Quad channel high-side driver with MultiSense analog feedback for automotive applications

Document overview

  • Manufacturer or author: STMICROELECTRONICS
  • PDF pages: 42

Technical content

Datasheet sections

  • 1 Block diagram and pin description
  • 2 Electrical specification
  • 2.1 Absolute maximum ratings
  • 2.2 Thermal data
  • 2.3 Main electrical characteristics
  • 2.4 Waveforms
  • 2.5 Electrical characteristics curves
  • 3 Protections
  • 3.1 Power limitation
  • 3.2 Thermal shutdown
  • 3.3 Current limitation
  • 3.4 Negative voltage clamp
  • 4 Application information
  • 4.1 GND protection network against reverse battery
  • 4.1.1 Diode (DGND) in the ground line
  • 4.2 Immunity against transient electrical disturbances
  • 4.3 MCU I/Os protection
  • 4.4 CS - analog current sense
  • 4.4.1 Principle of CurrentSense signal generation
  • 4.4.2 Short to VCC and OFF-state open-load detection
  • 5 Maximum demagnetization energy (VCC = 16 V)
  • 6 Package and PCB thermal data
  • 6.1 PowerSSO-16 thermal data
  • 7 Package information
  • 7.1 PowerSSO-16 package information
  • 7.2 PowerSSO-16 packing information
  • 7.3 PowerSSO-16 marking information
  • 8 Order codes
  • 9 Revision history

Features

Max transient supply voltage VCC 40 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per Ch) RON 50 mΩ Current limitation (typ) ILIMH 27 A Stand-by current (max) ISTBY 0.5 µA

  • Automotive qualified
  • General − Quad channel smart high-side driver with CS analog feedback − Very low standby current − Compatible with 3 V and 5 V CMOS outputs
  • CurrentSense diagnostic functions − Analog feedback of load current with high precision proportional current mirror − Overload and short to ground (power limitation) indication − Thermal shutdown indication − OFF-state open-load detection − Output short to VCC detection − Sense enable/disable
  • Protections − Undervoltage shutdown − Overvoltage clamp − Load current limitation − Self limiting of fast thermal transients − Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin − Loss of ground and loss of VCC − Reverse battery with external components − Electrostatic discharge protection

Applications

  • All types of Automotive resistive, inductive and capacitive loads
  • Specially intended for Automotive Signal Lamps (up to P27W or SAE1156 or LED Rear Combinations)

Description

The device is a quad channel high-side driver manufactured using ST proprietary VIPower® M0-7 technology and housed in PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, providing protection and diagnostics. The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A sense enable pin allows OFF-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices. This is information on a product in full production. www.st.com

VNQ7050AJ Block diagram and pin description

1 Block diagram and pin description

Figure 1: Block diagram Table 1: Pin functions Name Function VCC Battery connection. OUTPUT0,1,2,3 Power output. GND Ground connection. Must be reverse battery protected by an external diode / resistor network. INPUT0,1,2,3 Voltage controlled input pin with hysteresis, compatible with 3 V and 5 V CMOS outputs. They control output switch state. CS Analog current sense output pin delivers a current proportional to the load current. SEn Active high, compatible with 3 V and 5 V CMOS outputs input pin; it enables the CS diagnostic pin. SEL0,1 Active high, compatible with 3 V and 5 V CMOS outputs input pin; They address the CS multiplexer. FaultRST Active low, compatible with 3 V and 5 V CMOS outputs input pin; it unlatches the output in case of fault; If kept low, sets the outputs in auto-restart mode. Channel 3 Channel 2 CH 3 CH 2 Channel 1 Control & Diagnostic Channel0 VCC VON Limitation Current Limitation VCC – OUT Clamp Internal supply CH 1 OUTPUT0 CH 0 MUX Current Sense0 GND Undervoltage shut-down VCC – GND Clamp Fault Short to VCC Open-Load in OFF Overtemperature Power Limitation T VSENSEH INPUT0 SEL0 SEn CS FaultRST INPUT1 OUTPUT1 Gate Driver INPUT2 INPUT3 OUTPUT2 OUTPUT3 SEL1 GAPGCFT00605

Block diagram and pin description VNQ7050AJ Figure 2: Configuration diagram (top view) Table 2: Suggested connections for unused and not connected pins Connection / pin CS N.C. Output Input SEn, SELx, FaultRST Floating Not allowed X (1) X X X To ground Through 1 kΩ resistor X Not allowed Through 15 kΩ resistor Through 15 kΩ resistor Notes: (1)X: do not care.

2 Electrical specification

Figure 3: Current and voltage conventions VFn = VOUTn - VCC during reverse battery condition.

2.1 Absolute maximum ratings

Stressing the device above the rating listed in Table 3: "Absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Table 3: Absolute maximum ratings Symbol Parameter Value Unit VCC DC supply voltage 38 V -VCC Reverse DC supply voltage 0.3 VCCPK Maximum transient supply voltage (ISO 16750-2:2010 Test B clamped to 40 V; RL = 4 Ω) 40 V VCCJS Maximum jump start voltage for single pulse short circuit protection 28 V -IGND DC reverse ground pin current 200 mA IOUT OUTPUT0,1,2,3 DC output current Internally limited A -IOUT Reverse DC output current 16 IIN INPUT0,1,2,3 DC input current -1 to 10 mA ISEn SEn DC input current ISEL SEL0,1 DC input current IFR FaultRST DC input current VFR FaultRST DC input voltage 7.5 V

Symbol Parameter Value Unit ISENSE CS pin DC output current (VGND = VCC and VSENSE < 0 V) 10 mA CS pin DC output current in reverse (VCC < 0 V) -20 EMAX Maximum switching energy (single pulse) (TDEMAG = 0.4 ms; Tjstart = 150°C) 30 mJ VESD Electrostatic discharge (JEDEC 22A-114F)

  • INPUT0,1,2,3
  • CS
  • SEn, SEL0,1, FaultRST
  • OUTPUT0,1,2,3
  • VCC 4000 2000 4000 4000 4000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V Tj Junction operating temperature -40 to 150 Tstg Storage temperature -55 to 150

2.2 Thermal data

Table 4: Thermal data Symbol Parameter Typ. value Unit Rthj-board Thermal resistance junction-board (JEDEC JESD 51-5 / 51-8) (1)(2) 6.3 °C/W Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-5)(1)(3) 57.3 Rthj-amb Thermal resistance junction-ambient (JEDEC JESD 51-7)(1)(2) 23.5 Notes: (1)One channel ON. (2)Device mounted on four-layers 2s2p PCB. (3)Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace.

2.3 Main electrical characteristics

7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified. All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified. Table 5: Power section Symbol Parameter Test conditions Min. Typ. Max. Unit VCC Operating supply voltage 4 13 28 V VUSD Undervoltage shutdown VUSDReset Undervoltage shutdown reset VUSDhyst Undervoltage shutdown hysteresis 0.3 RON On-state resistance (1) IOUT = 2 A; Tj = 25°C mΩ IOUT = 2 A; Tj = 150°C 100 IOUT = 2 A; VCC = 4 V; Tj = 25°C

Symbol Parameter Test conditions Min. Typ. Max. Unit Vclamp Clamp voltage IS = 20 mA; Tj = -40°C 38 V IS = 20 mA; 25°C < Tj < 150°C 41 46 52 ISTBY Supply current in Standby at VCC = 13 V (2) VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 25°C 0.5 µA VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 85°C (3) 0.5 µA VCC = 13 V; VIN = VOUT = VFR = VSEn = 0 V; VSEL0,1 = 0 V; Tj = 125°C 3 µA tD_STBY Standby mode blanking time VCC = 13 V VIN = VOUT = VFR = VSEL0,1 = 0 V; VSEn = 5 V to 0 V 60 300 550 µs IS(ON) Supply current VCC = 13 V; VSEn = VFR = VSEL0,1 = 0 V; VIN0,1,2,3 = 5 V; IOUT0,1,2,3 = 0 A 10 16 mA IGND(ON) Control stage current consumption in ON state. All channels active. VCC = 13 V; VSEn = 5 V; VFR = VSEL0,1 = 0 V; VIN0,1,2,3 = 5 V; IOUT0,1,2,3 = 1 A 20 mA IL(off) Off-state output current at VCC = 13 V(1) VIN = VOUT = 0 V; VCC = 13 V; Tj = 25°C 0 0.01 0.5 µA VIN = VOUT = 0 V; VCC = 13 V; Tj = 125°C 0 VF Output - VCC diode voltage(1) IOUT = -2 A; Tj = 150°C 0.7 V Notes: (1)For each channel. (2)PowerMOS leakage included. (3)Parameter specified by design; not subject to production test. Table 6: Switching (VCC = 13 V; -40°C < Tj < 150°C, unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit td(on)(1) Turn-on delay time at Tj = 25°C RL = 6.5 Ω 10 35 120 µs td(off)(1) Turn-off delay time at Tj = 25°C 10 45 100 (dVOUT/dt)on(1) Turn-on voltage slope at Tj = 25°C RL = 6.5 Ω 0.1 0.28 0.7 V/µs (dVOUT/dt)off(1) Turn-off voltage slope at Tj = 25°C 0.1 0.31 0.7 WON Switching energy losses at turn-on (twon) RL = 6.5 Ω — 0.26 0.35 (2) mJ WOFF Switching energy losses at turn-off (twoff) RL = 6.5 Ω — 0.23 0.31(2) mJ tSKEW(1) Differential Pulse skew (tPHL - tPLH) RL = 6.5 Ω -40 10 60 µs Notes: (1)See Figure 4: "Switching times and Pulse skew". (2)Parameter guaranteed by design and characterization, not subject to production test

Table 7: Logic Inputs (7 V < VCC < 28 V; -40°C < Tj < 150°C) Symbol Parameter Test conditions Min. Typ. Max. Unit INPUT0,1,2,3 characteristics VIL Input low level voltage 0.9 V IIL Low level input current VIN = 0.9 V 1 µA VIH Input high level voltage 2.1 V IIH High level input current VIN = 2.1 V 10 µA VI(hyst) Input hysteresis voltage 0.2 V VICL Input clamp voltage IIN = 1 mA 5.3 7.2 V IIN = -1 mA -0.7 FaultRST characteristics VFRL Input low level voltage 0.9 V IFRL Low level input current VIN = 0.9 V 1 µA VFRH Input high level voltage 2.1 V IFRH High level input current VIN = 2.1 V 10 µA VFR(hyst) Input hysteresis voltage 0.2 V VFRCL Input clamp voltage IIN = 1 mA 5.3 7.5 V IIN = -1 mA -0.7 SEL0,1 characteristics (7 V < VCC < 18 V) VSELL Input low level voltage 0.9 V ISELL Low level input current VIN = 0.9 V 1 µA VSELH Input high level voltage 2.1 V ISELH High level input current VIN = 2.1 V 10 µA VSEL(hyst) Input hysteresis voltage 0.2 V VSELCL Input clamp voltage IIN = 1 mA 5.3 7.2 V IIN = -1 mA -0.7 SEn characteristics (7 V < VCC < 18 V) VSEnL Input low level voltage 0.9 V ISEnL Low level input current VIN = 0.9 V 1 µA VSEnH Input high level voltage 2.1 V ISEnH High level input current VIN = 2.1 V 10 µA VSEn(hyst) Input hysteresis voltage 0.2 V VSEnCL Input clamp voltage IIN = 1 mA 5.3 7.2 V IIN = -1 mA -0.7 Table 8: Protections (7 V < VCC < 18 V; -40°C < Tj < 150°C) Symbol Parameter Test conditions Min. Typ. Max. Unit ILIMH DC short circuit current VCC = 13 V 21 27 38 A 4 V < VCC < 18 V (1) ILIML Short circuit current during thermal cycling VCC = 13 V; TR < Tj < TTSD

Symbol Parameter Test conditions Min. Typ. Max. Unit TTSD Shutdown temperature 150 175 200 TR Reset temperature(1) TRS + 1 TRS + 7 TRS Thermal reset of fault diagnostic indication VFR = 0 V; VSEn = 5 V; 135 THYST Thermal hysteresis (TTSD - TR)(1) ΔTJ_SD Dynamic temperature Tj = -40°C; VCC = 13 V K tLATCH_RST Fault reset time for output unlatch(1) VFR = 5 V to 0 V; VSEn = 5 V

  • E.g. Ch0 VIN0 = 5 V; VSEL0,1 = 0 V 3 10 20 µs VDEMAG Turn-off output voltage clamp IOUT= 2 A; L = 6 mH; Tj = -40°C VCC - 38 V IOUT= 2 A; L = 6 mH; Tj = 25°C to 150°C VCC - 41 VCC - 46 VCC - 52 V VON Output voltage drop limitation IOUT = 0.2 A mV Notes: (1)Parameter guaranteed by design and characterization; not subject to production test. Table 9: CurrentSense (7 V < VCC < 18 V; -40°C < Tj < 150°C) Symbol Parameter Test conditions Min. Typ. Max. Unit VSENSE_CL Current sense clamp voltage VSEn = 0 V; ISENSE = 1 mA -17 -12 V VSEn = 0 V; ISENSE = -1 mA Current Sense characteristics KOL IOUT/ISENSE IOUT = 0.01 A; VSENSE = 0.5 V; VSEn = 5 V 425 dKcal/Kcal(1)(2) Current sense ratio drift at calibration point IOUT = 0.01 A to 0.05 A; Ical = 30 A; VSENSE = 0.5 V; VSEn = 5 V -30 30 % KLED IOUT/ISENSE IOUT = 0.05 A; VSENSE = 0.5 V; VSEn = 5 V 530 1390 2120 dKLED/KLED(1)(2) Current sense ratio drift IOUT = 0.05 A; VSENSE = 0.5 V; VSEn = 5 V -30 30 % K0 IOUT/ISENSE IOUT = 0.2 A; VSENSE = 0.5 V; VSEn = 5 V 730 1280 1700 dK0/K0(1)(2) Current sense ratio drift IOUT = 0.2 A; VSENSE = 0.5 V; VSEn = 5 V -25 25 % K1 IOUT/ISENSE IOUT = 0.4 A; VSENSE = 4 V; VSEn = 5 V 830 1180 1545 dK1/K1(1)(2) Current sense ratio drift IOUT = 0.4 A; VSENSE = 4 V; VSEn = 5 V -20 20 % K2 IOUT/ISENSE IOUT = 1.5 A; VSENSE = 4 V; VSEn = 5 V 885 1120 1335

Symbol Parameter Test conditions Min. Typ. Max. Unit dK2/K2(1)(2) Current sense ratio drift IOUT = 1.5 A; VSENSE = 4 V; VSEn = 5 V -15 15 % K3 IOUT/ISENSE IOUT = 4.5 A; VSENSE = 4 V; VSEn = 5 V 990 1110 1210 dK3/K3(1)(2) Current sense ratio drift IOUT = 4.5 A; VSENSE = 4 V; VSEn = 5 V -10 10 % ISENSE0 Current sense leakage current Current sense disabled: VSEn = 0 V; 0 0.5 µA Current sense disabled: -1 V < VSENSE < 5 V(1) -0.5 0.5 Current sense enabled: VSEn = 5 V All channels ON; IOUTX = 0 A; ChX diagnostic selected:

  • E.g. Ch0: VIN0,1,2,3 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 0 A; IOUT1,2,3 = 2 A Current sense enabled: VSEn = 5 V; ChX OFF; ChX diagnostic selected:
  • E.g. Ch0: VIN0 = 0 V; VIN1,2,3 = 0 V; VSEL0 = 5V; VSEL1 = 0 V; IOUT1,2,3 = 2 A VOUT_MSD(1) Output Voltage for Current sense shutdown VSEn = 5 V; RSENSE = 2.7 kΩ
  • E.g. Ch0: VIN0 = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT0 = 2 A V VSENSE_SAT CS saturation voltage VCC = 7 V; RSENSE = 2.7 kΩ; VSEn = 5 V; VIN0 = 5 V; VSEL0,1 = 0 V; IOUT0 = 4.5 A; Tj = 150°C V ISENSE_SAT(1) CS saturation current VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V; VSEn = 5 V; VSEL0,1 = 0 V; Tj = 150°C mA IOUT_SAT(1) Output saturation current VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V; VSEn = 5 V; VSEL0,1 = 0 V; Tj = 150°C 4.8 A OFF-state diagnostic VOL OFF-state open-load voltage detection threshold VSEn = 5 V; ChX OFF; ChX diagnostic selected
  • E.g: Ch0 VIN0 = 0 V; VSEL0,1 = 0 V 2 3 4 V IL(off2) OFF-state output sink current VIN = 0 V; VOUT = VOL; Tj = -40°C to 125°C -100 -15 µA

Symbol Parameter Test conditions Min. Typ. Max. Unit tDSTKON OFF-state diagnostic delay time from falling edge of INPUT (see Figure 6: "TDSKON") VSEn = 5 V; ChX ON to OFF transition; ChX diagnostic selected:

  • E.g: Ch0 VIN0 = 5 V to 0 V; VSEL0,1 = 0 V; VOUT0 = 4 V; IOUT0 = 0 A 100 350 700 µs tD_OL_V Settling time for valid OFF- state open-load diagnostic indication from rising edge of SEn VIN0,1,2,3 = 0 V; VFR = 0 V; VSEL0,1 = 0 V; VOUT0 = 4 V; VSEn = 0 V to 5 V 60 µs tD_VOL OFF-state diagnostic delay time from rising edge of VOUT VSEn = 5 V; ChX OFF; ChX diagnostic selected:
  • E.g: Ch0 VIN0 = 0 V; VSEL0,1 = 0 V; VOUT0 = 0 V to 4 V 5 30 µs Fault diagnostic feedback (see Table 10: "Truth table") VSENSEH Current sense output voltage in fault condition VCC = 13 V; RSENSE = 1 kΩ
  • E.g: Ch0 in open load VIN0 = 0 V; VSEn = 5 V; VSEL0,1 = 0 V; IOUT0 = 0 A; VOUT0 = 4 V 6.6 V ISENSEH Current sense output current in fault condition VCC = 13 V; VSENSE = 5 V 7 20 30 mA Current sense timings (current sense mode - see Figure 5: "Current sense timings (current sense mode)") tDSENSE1H Current sense settling time from rising edge of SEn VIN = 5 V; VSEn = 0 V to 5 V; RSENSE = 1 kΩ; RL = 6.5 Ω 60 µs tDSENSE1L Current sense disable delay time from falling edge of SEn VSEn = 5 V to 0 V; RSENSE = 1 kΩ; RL = 6.5 Ω 5 20 µs tDSENSE2H Current sense settling time from rising edge of INPUT VIN = 0 V to 5 V; VSEn = 5 V; RSENSE = 1 kΩ; RL = 6.5 Ω 100 250 µs ΔtDSENSE2H Current sense settling time from rising edge of IOUT (dynamic response to a step change of IOUT) VIN = 5 V; VSEn = 5 V; RSENSE = 1 kΩ; ISENSE = 90 % of ISENSEMAX; RL = 6.5 Ω 100 µs tDSENSE2L Current sense turn-off delay time from falling edge of INPUT VIN = 5 V to 0 V; VSEn = 5 V; RSENSE = 1 kΩ; RL = 6.5 Ω 50 250 µs Notes: (1)Parameter defined by design. Not subject to production test. (2)All values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified.

Figure 6: TDSKON Table 10: Truth table Mode Conditions INX FR SEn SELX OUTX Current sense Comments Standby All logic inputs low L L L L L Hi-Z Low quiescent current consumption Normal Nominal load connected; T j < 150°C L X See (1) L See (1) H L H See (1) Outputs configured for auto-restart H H H See (1) Outputs configured for Latch-off Overload Overload or short to GND causing: Tj > TTSD or ΔTj > ΔTj_SD L X See (1) L See (1) H L H See (1) Output cycles with temperature hysteresis H H L See (1) Output latches-off Under-voltage VCC < VUSD (falling) X X X X L L Hi-Z Hi-Z Re-start when VCC > VUSD + VUSDhyst (rising) OFF-state diagnostics Short to VCC L X See (1) H See (1) Open-load L X H See (1) External pull-up Negative output voltage Inductive loads turn- off L X See (1) < 0 V See (1) Notes: (1)Refer to Table 11: "Current sense multiplexer addressing" TDSTKON VINPU T VOUT MultiSense VOUT > VOL GAPG2609141140CFT

Table 11: Current sense multiplexer addressing SEn SEL1 SEL0 MUX channel Current sense output Nomal mode Overload OFF-state diag. (1)(2)(3) Negative output L X X Hi-Z H L L Channel 0 diagnostic ISENSE = 1/K * IOUT0 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H L H Channel 1 diagnostic ISENSE = 1/K * IOUT1 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H H L Channel 2 diagnostic ISENSE = 1/K * IOUT2 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z H H H Channel 3 diagnostic ISENSE = 1/K * IOUT3 VSENSE = VSENSEH VSENSE = VSENSEH Hi-Z Notes: (1)In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low, CS pin delivers feedback according to OFF-State diagnostic. (2)Example 1: FR = 1; IN0 = 0; OUT0 = L (latched); MUX channel = channel 0 diagnostic; CS = 0 (3)Example 2: FR = 1; IN0 = 0; OUT0 = latched, VOUT0 > VOL; MUX channel = channel 0 diagnostic; CS = VSENSEH

2.4 Waveforms

Figure 7: Latch functionality - behavior in hard short circuit condition (TAMB << TTSD)

2.5 Electrical characteristics curves

Figure 12: OFF-state output current Figure 13: Standby current Figure 14: IGND(ON) vs Tcase Figure 15: Logic Input high level voltage Figure 16: Logic Input low level voltage Figure 17: High level logic input current 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.1 1.2 -50 -25 0 25 50 75 100 125 150 175 T [°C] ISTBY [µA] Vcc = 13V GAPG0512131558CFT

3 Protections

3.1 Power limitation

The basic working principle of this protection consists of an indirect measurement of the junction temperature swing ΔTj through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo-mechanical fatigue.

3.2 Thermal shutdown

In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to T R (FaultRST = Low) or remains off (FaultRST = High).

3.3 Current limitation

The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region.

3.4 Negative voltage clamp

In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the device.

4 Application information

Figure 32: Application diagram

4.1 GND protection network against reverse battery

Figure 33: Simplified internal structure VDD OUT OUT OUT OUT ADC in OUT GND GND GND GND Logic OUTPUT GND FaultRST INPUT SEn SEL VCC CS Current mirror Rprot Rprot Rprot Rprot Rprot +5V R GND Rsense D GND Cext GND GND Dld GAPGCFT00829 MCU INPUT SEn CS FaultRST Vcc OUTPUT GND Rprot Rprot Rprot Rprot Dld Rsense RGND DGND GND GAPGCFT00830

4.1.1 Diode (DGND) in the ground line

A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (≈600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network.

4.2 Immunity against transient electrical disturbances

The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. The related function performance status classification is shown in Table 12: "ISO 7637- 2 - electrical transient conduction along supply line". Test pulses are applied directly to DUT (Device Under Test) both in ON and OFF-state and in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the present device only, without components and accessed through VCC and GND terminals. Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: “The function does not perform as designed during the test but returns automatically to normal operation after the test”. Table 12: ISO 7637-2 - electrical transient conduction along supply line Test Pulse 2011(E) Test pulse severity level with Status II functional performance status Minimum number of pulses or test time Burst cycle / pulse repetition time Pulse duration and pulse generator internal impedance Level US(1) min max

1 III -112V 500 pulses 0,5 s

2ms, 10Ω 2a III +55V 500 pulses 0,2 s 5 s 50µs, 2Ω 3a IV -220V 1h 90 ms 100 ms 0.1µs, 50Ω 3b IV +150V 1h 90 ms 100 ms 0.1µs, 50Ω 4 (2) IV -7V 1 pulse 100ms, 0.01Ω Load dump according to ISO 16750-2:2010 Test B (3) 40V 5 pulse 1 min 400ms, 2Ω Notes: (1)US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6. (2)Test pulse from ISO 7637-2:2004(E). (3)With 40 V external suppressor referred to ground (-40°C < Tj < 150°C).

4.3 MCU I/Os protection

If a ground protection network is used and negative transients are present on the V CC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins to latch-up and to protect the HSD inputs.

The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax Calculation example: For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V 7.5 kΩ ≤ Rprot ≤ 140 kΩ. Recommended values: Rprot = 15 kΩ

4.4 CS - analog current sense

Diagnostic information on device and load status are provided by an analog output pin (CS) delivering the following signals:

  • Current monitor: current mirror of channel output current Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in MultiSense multiplexer addressing Table. Figure 34: CurrectSense and diagnostic – block diagram SEL1 SEn CS RSENSE RPROT To uC ADC OUT Current Sense Fault Fault Diagnostic VSENSEH MUX ISENSE IOUT K factor CURRENT MONITOR Gate Driver VCC – OUT Clamp T VCC – GND Clamp Internal Supply Undervoltage shut-down VON Limitation Current Limitation Power Limitation Overtemperature Short to VCC Open-Load in OFF SEL0 Control & Diagnostic GND VCC INPUT FaultRST GAPGCFT00831

4.4.1 Principle of CurrentSense signal generation

Figure 35: CurrentSense block diagram Current sense This current mode is selected in the MultiSense, this output is capable to provide:

  • Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to known ratio named K
  • Diagnostics flag in fault conditions delivering fixed voltage VSENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted to a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by CS output: ISENSE = IOUT/K Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K Where:
  • VSENSE is voltage measurable on RSENSE resistor
  • ISENSE is current provided from CS pin in current output mode
  • IOUT is current flowing through output
  • K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of the overall circuitry the specifying ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the CS pin which is switched to a “current limited” voltage source, V SENSEH. In any case, the current sourced by the CS in this condition is limited to ISENSEH. The typical behavior in case of overload or hard short circuit is shown in Waveforms section. Figure 36: Analogue HSD – open-load detection in off-state 15k 15k 15k 15k 15k +5V RGND 4.7k Vbat Rsense 15k VDD OUT OUT OUT OUT ADC in GND OUT 100nF GND GND GND GND GND GND 100nF/50V CEXT DGND 10nF/100V GND Microcontroller OUTPUT Vbat Rpull-up External Pull-Up switch Logic GND FaultRST INPUT SEn SEL VCC CS Currentmirror OUTPUT GAPG1201151432CFT

Figure 37: Open-load / short to VCC condition Table 13: CurrentSense pin levels in off-state Condition Output CS SEn Open-load VOUT > VOL Hi-Z L VSENSEH H VOUT < VOL Hi-Z L 0 H Short to VCC VOUT > VOL Hi-Z L VSENSEH H Nominal VOUT < VOL Hi-Z L 0 H

4.4.2 Short to VCC and OFF-state open-load detection

A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. OFF-state open-load with external circuitry Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive supply voltage VPU. It is preferable VPU to be switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected.

RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation: Equation RPU < VPU - 4 IL(off2)min @ 4V

VNQ7050AJ Maximum demagnetization energy (VCC = 16 V)

5 Maximum demagnetization energy (VCC = 16 V)

Figure 38: Maximum turn off current versus inductance Values are generated with RL = 0 Ω. In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.

6 Package and PCB thermal data

6.1 PowerSSO-16 thermal data

Figure 39: PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) Figure 40: PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) Table 14: PCB properties Dimension Value Board finish thickness 1.6 mm +/- 10% Board dimension 77 mm x 86 mm Board Material FR4 Copper thickness (top and bottom layers) 0.070 mm Copper thickness (inner layers) 0.035 mm Thermal vias separation 1.2 mm Thermal via diameter 0.3 mm +/- 0.08 mm Copper thickness on vias 0.025 mm Footprint dimension (top layer) 2.2 mm x 3.9 mm Heatsink copper area dimension (bottom layer) Footprint, 2 cm2 or 8 cm2

Figure 41: Rthj-amb vs PCB copper area in open box free air condition (one channel on) Figure 42: PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) Equation: pulse calculation formula ZTHδ = RTH · δ + ZTHtp (1 - δ) where δ = tP/T 100 0 2 4 6 8 10 RTHjamb RTHjamb GAPG2307131254CFT GAPG2307131257CFT 0.1 100 0.0001 0.001 0.01 0.1 1 10 100 1000 ZTH (°C/W) Time (s) Cu=8 cm2 Cu=2 cm2 Cu=foot print

4 Layer

Figure 43: Thermal fitting model of a double-channel HSD in PowerSSO-16 The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 15: Thermal parameters Area/island (cm2) Footprint 2 8 R3 (°C/W) 7 7 7 7 R4 (°C/W) 16 6 6 4 R5 (°C/W) 30 20 10 3 R6 (°C/W) 26 20 18 7 C3 (W.s/°C) 0.14 C6 (W.s/°C) 3 5 7 18

7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

7.1 PowerSSO-16 package information

Figure 44: PowerSSO-16 package dimensions Table 16: PowerSSO-16 mechanical data Symbol Millimeters Min. Typ. Max. Θ 0° Θ1 0° Θ2 5° 15° Θ3 5° 15° A 1.70 A1 0.00 0.10 A2 1.10 1.60

Min. Typ. Max. b 0.20 0.30 b1 0.20 0.25 0.28 c 0.19 0.25 c1 0.19 0.20 0.23 D 4.9 BSC D1 3.60 4.20 e 0.50 BSC E 6.00 BSC E1 3.90 BSC E2 1.90 2.50 h 0.25 0.50 L 0.40 0.60 0.85 L1 1.00 REF N 16 R 0.07 R1 0.07 S 0.20 Tolerance of form and position aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.08 eee 0.10 fff 0.10 ggg 0.15

7.2 PowerSSO-16 packing information

Figure 45: PowerSSO-16 reel 13" Table 17: Reel dimensions Description Value(1) Base quantity 2500 Bulk quantity 2500 A (max) 330 B (min) 1.5 C (+0.5, -0.2) 13 D (min) 20.2 N 100 W1 (+2 /-0) 12.4 W2 (max) 18.4 Notes: (1)All dimensions are in mm.

7.3 PowerSSO-16 marking information

Figure 48: PowerSSO-16 marking information Engineering Samples: these samples can be clearly identified by a dedicated special symbol in the marking of each unit. These samples are intended to be used for electrical compatibility evaluation only; usage for any other purpose may be agreed only upon written authorization by ST. ST is not liable for any customer usage in production and/or in reliability qualification trials. Commercial Samples: fully qualified parts from ST standard production with no usage restrictions. GAPG0401151415CFT 1 2 3 4 5 6 7 8 Special function digit &: Engineering sample <blank>: Commercial sample PowerSSO-16 TOP VIEW (not in scale) Marking area

8 Order codes

Table 19: Device summary Package Order codes Tape and reel PowerSSO-16 VNQ7050AJTR

9 Revision history

Table 20: Document revision history Date Revision Changes 04-Jun-2015 1 Initial release.