STEVAL-VNH5019A STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 12
Technical content
Features
- Handling up to 30 A of maximum motor current output
- Undervoltage and overvoltage shutdown
- Device thermal protection
- Cross-conduction protection
- Very low standby power consumption
- Programmable PWM operation (up to 20 kHz)
- Protection against loss of ground and loss of VCC
- Motor current monitoring (thanks to VNH5019A current sense output)
- On-board charge pump output for reverse polarity protection
- Device output protected against short to ground and short to VCC
- Graphic User Interface (GUI)
Description
STEVAL-VNH5019A offers dedicated power stage and controls suitable for electric DC motor driving. This evaluation board comes pre-assembled with VNH5019A H-bridge belonging to the VNH Motor Driver series based on VIPower ® proprietary technology. Typical applications are Windows Lift, Sliding Door, Seat regulation. This Evaluation Board consists of a motherboard (STM8 Universal Board) and a daughterboard. The motherboard, based on STM8 microcontroller, provides the logic section for monitoring and driving the VNH5019A assembled in the daughterboard. With the aim to make simpler the board usage and settings, ST provides a dedicated and user- friendly software with a Graphic User Interface (GUI). This enables the user to set VNH5019A parameters (PWM, Motor direction…) and at the same time it shows real time device diagnostic information like current output evolution, battery voltage monitoring, board temperature and much more. Type R DS(on) Iout VCC(max) VNH5019A-E 18 mΩ typ (per leg) 30 A 41 V Table 1. Device summary
1.1 VNH5019A daughterboard
Figure 1. VNH5019A daughterboard top layer
Figure 2. VNH5019A daughterboard bottom layer
+5V_DBA1 PB0/AI N0/TI M1_NCC1A3 PB1/AI N1/TI M1_NCC2A4 PB2/AI N2/TI M1_NCC3A5 PB3/AI N3A6 PB4/AI N4A7 PB5/AI N5A8 PB6/AI N6A9 PB7/AI N7A10 PE7/AI N8A11 PE6/AI N9A12 +5V_P ermA2 PF0/AIN10A13 PF3/AIN11A14 PF4/AIN12A15 PF5/AIN13A16 PF6/AIN14A17 PF7/AIN15A18 PA3/TI M2_CC3A19 PC1(HS)/TI M1_CC1A21 PC2(HS)/TI M1_CC2A22 PC3(HS)/TI M1_CC3A23 PC4(HS)/TI M1_CC4A24 PD0(HS)/TI M3_CC2A25 PD2(HS)/TI M3_CC1A26 PD3(HS)/TI M2_CC2A27 PD4(HS)TI M2_CC1A28 PD7/TL IA29 PE0/CL K _CCOA30 PE3/TI M1_BK INA31 PE4A32 PC0/ADC_ETRA20 PH0(HS)A40 PH1(HS)A39 PH2A38 PH3A37 PH4/TI M1_ETRA36 PH5/TI M1_NCC3A35 PH6/TI M1_NCC2A34 PH7/TI M1_NCC1A33 PE5/SPI_NSSB9 PC5/SPI_SCKB1 0 PC6/SPI_MOSIB1 1 PC7/SPI_MISOB1 2 PD5 /LINUART_TXB5 PD6/LINUART_RXB6 PG0/CAN_TXB7 PG1/CAN_RXB8 PA4/USART_R XB4PA5 /USART_TXB3PA6/USART_CXB2 PE1/I2C_SCLB1 3 PE2/I2C_SDAB1 4 NRESETB1 +5V _S WB2 1 USB_CB2B1 7LIN_ P UB1 6 USB_CB3B1 8 LIN B1 5 BTN_COMB2 2 CAN_HI B1 9 BTN_A B2 3 CAN_LOB2 0 BTN_B B2 4 LED1 B2 5 LED2 B2 6 LED3 B2 7 LED4 B2 8 IO_CON1B2 9 CPD1 Vs _ P e rD2 VS_ BD3 Vs _ BD4 Vs _ BD5 Vs _ BD6 Vs _ BD7 Vs _ BD8 Vs _ BD9 Vs _ BD10 Vs _ BD11 Vs _ BD12 Vs _ BD13 Vs _ BD14 Vs _ BD15 Vs _ BD16 Vs _ AD17 Vs _ AD18 Vs _ AD19 GND_VIPD20 GNDD21 GNDD22 GNDD23 GNDD24 GNDD25 GNDD26 GNDD27 GNDD28 GNDD29 GNDD30 ext10D31 ext9D32 ext8D33 ext7D34 ext6D35 ext5D36 ext4D37 ext3D38 ext2D39 ext1D40 IO_CON2B3 0 IO_CON3B3 1 IO_CON4B3 2 IO_CON5B3 3 IO_CON6B3 4 IO_CON7B3 5 IO_CON8B3 6 IO_CON9B3 7 IO_CON10B3 8 IO_CON11B3 9 IO_CON12B4 0 Daughterboard Socket1 STM8UB_DB1 IN_A/INPUT1 IN_B/I NPUT2 EN/DI G_A/STATUS3 EN/DI G_B/STATUS4 CS (I N_)P WM CS_DI S ID0 ID1 ID2 ID3 INPUT3 INPUT4 VBAT_SENSE DGND +5V TEMP VCC2 1
Figure 4. VNH5019A daughterboard application schematic (part 2)
1.2 STM8 motherboard
Figure 5. STM8 motherboard top layer
Figure 6. STM8 motherboard bottom layer
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Figure 8. STM8 motherboard - STM8 & Supply application schematic
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2 Revision history
Table 2. Document revision history 22-Jul-2013 1 Initial release. 16-Sep-2013 3 Updated disclaimer.