VNH100N04

VNH100N04 STMICROELECTRONICS | Alldatasheet

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”OMNIFET”: FULLY AUTOPROTECTED POWER MOSFET TARGET DATA September 1994 BLOCK DIAGRAM TYPE V clamp R DS(on) Ilim VNH100N04 42 V 0.012 Ω 100 A n LINEAR CURRENT LIMITATION n THERMAL SHUT DOWN n SHORT CIRCUIT PROTECTION n INTEGRATED CLAMP n LOW CURRENT DRAWN FROM INPUT PIN n DIAGNOSTIC FEEDBACK THROUGH INPUT PIN n ESD PROTECTION n DIRECT ACCESS TO THE GATE OF THE POWER MOSFET (ANALOG DRIVING) n COMPATIBLE WITH STANDARD POWER MOSFET n STANDARD TO-218 PACKAGE

DESCRIPTION

The VNH100N04 is a monolithic device made using SGS-THOMSON Vertical Intelligent Power M0 Technology, intended for replacement of standard power MOSFETS in DC to 50 KHz applications. Buit-in thermal shut-down, linear current limitation and overvoltage clamp protect the chip in harsh enviroments. Fault feedback can be detected by monitoring the voltage at the input pin. TO-218

Symbol Parameter Value Unit V DS Drain-source Voltage (Vin = 0) Internally Clamped V V in Input Voltage 18 V ID Drain Current Internally Limited A IR Reverse DC Output Current -50 A V esd Electrostatic Discharge (C= 100 pF, R=1.5 KΩ ) 2000 V P tot Total Dissipation at Tc =2 5 oC2 0 8 W Tj Operating Junction Temperature Internally Limited oC Tc Case Operating Temperature Internally Limited oC Tstg Storage Temperature -55 to 150 oC THERMAL DATA R thj-case R thj-amb Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max 0.6 oC/W oC/W ELECTRICAL CHARACTERISTICS (Tcase =2 5oC unless otherwise specified) OFF Symbol Parameter Test Conditions Min. Typ. Max. Unit V CLAMP Drain-source Clamp Voltage ID =3 0A V in = 0 36 42 48 V V CLTH Drain-source Clamp Threshold Voltage ID =2m A V in=0 3 5 V V INCL Input-Source Reverse Clamp Voltage Iin =- 1m A - 1 - 0 . 3 V IDSS Zero Input Voltage Drain Current (Vin =0 ) V DS =1 3V V DS =2 5V 200 µA µA IISS Supply Current from Input Pin V DS =0V V in = 10 V 250 500 µA ON (∗) Symbol Parameter Test Conditions Min. Typ. Max. Unit VIS(th) Input Threshold Voltage V DS =V in ID =1m A 0 . 8 3 V R DS(on) Static Drain-source On Resistance V in =1 0V I D =3 0A V in=5V I D =3 0A 0.012 0.015 Ω Ω DYNAMIC Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (∗)F o r w a r d Transconductance V DS =1 3V I D =3 0A 4 0 S C oss Output Capacitance V DS =1 3V f=1M H z V in = 0 1800 3000 pF VNH100N04

ELECTRICAL CHARACTERISTICS (continued) SWITCHING Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr td(off) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time V DD =1 5V I d =3 0A V gen =1 0V R gen =1 0 Ω (see figure 3) 100 400 900 400 TBD TBD TBD TBD ns ns ns ns t d(on) tr td(off) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time V DD =1 5V I d =3 0A V gen =1 0V R gen =1 0 Ω T j=1 2 5oC (see figure 3) TBD TBD TBD TBD ns ns ns ns td(on) tr td(off) tf Turn-on Delay Time Rise Time Turn-off Delay Time Fall Time V DD =1 5V I d =3 0A V gen =1 0V R gen =1 0 0 0Ω (see figure 3) TBD TBD TBD TBD µs µs µs µs (di/dt) on Turn-on Current Slope V DD =1 5V I D =3 0A V in =1 0V TBD A/ µs Q g Total Gate Charge V DD =1 2V I D =3 0A V in=1 0V T B D n C SOURCE DRAIN DIODE Symbol Parameter Test Conditions Min. Typ. Max. Unit V SD (∗) Forward On Voltage I SD =3 0A V in =0 T B D V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 30 A di/dt = 100 A/µs V DD =V T j= 150 oC (see test circuit, figure 5) TBD TBD TBD ns µC A PROTECTION Symbol Parameter Test Conditions Min. Typ. Max. Unit Ilim Drain Current Limit V in =1 0V V DS = 13 V 70 100 140 A tdlim Step Response Current Limit V in =1 0V V DS =1 3 V T B D µs Tjsh Overtemperature Shutdown 150 170 190 oC Tjrs Overtemperature Reset 135 oC Igf Fault Sink Current V in =1 0V V DS =1 3V 5 0 m A E as Single Pulse Avalanche Energy starting Tj =2 5 oCV DD =2 0V V in =1 0V R gen =1K Ω L= m H TBD J (∗) Pulsed: Pulse duration = 300µ s, duty cycle 1.5 % VNH100N04

During normal operation, the Input pin is electrically connected to the gate of the internal power MOSFET. The device then behaves like a standard power MOSFET and can be used as a switch from DC to 50 KHz. The only difference from the user’s standpoint is that a small DC current (I iss) flows into the Input pin in order to supply the internal circuitry. The device integrates: – OVERVOLTAGE CLAMP PROTECTION: internally set at 42V, along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability. This feature is mainly important when driving inductive loads. – LINEAR CURRENT LIMITER CIRCUIT: limits the drain current Id to Ilim whatever the Input pin voltage. When the current limiter is active, the device operates in the linear region, so power dissipation may exceed the capability of the heatsink. Both case and junction temperatures increase, and if this phase lasts long enough, junction temperature may reach the overtemperature threshold T jsh. – OVERTEMPERATURE AND SHORT CIRCUIT PROTECTION: these are based on sensing the chip temperature and are not dependent on the input voltage. The location of the sensing element on the chip in the power stage area ensures fast, accurate detection of the junction temperature. Overtemperature cutout occurs in the range 150 to 190 oC, a typical value being 170oC. The device is automatically restarted when the chip temperature falls below 135oC. – STATUS FEEDBACK: In the case of an overtemperature fault condition, a Status Feedback is provided through the Input pin. The internal protection circuit disconnects the input from the gate and connects it instead to ground via an equivalent resistance of 200Ω . The failure can be detected by monitoring the voltage at the Input pin, which will be close to ground potential. Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL Logic circuit (with a small increase in R DS(on)). PROTECTION FEATURES VNH100N04

Fig. 2:Unclamped Inductive Waveforms Fig. 3:Switching Times Test Circuits For Resistive Load Fig. 4:Input Charge Test Circuit Fig. 1:Unclamped Inductive Load Test Circuits Fig. 5:Test Circuit For Inductive Load Switching And Diode Recovery Times Fig. 6:Waveforms VNH100N04

DIM. mm inch A 4.7 4.9 0.185 0.193 C 1.17 1.37 0.046 0.054 D 2.5 0.098 E 0.5 0.78 0.019 0.030 F 1.1 1.3 0.043 0.051 G 10.8 11.1 0.425 0.437 H 14.7 15.2 0.578 0.598 L2 – 16.2 – 0.637 L3 18 0.708 L5 3.95 4.15 0.155 0.163 L6 31 1.220 R – 12.2 – 0.480 Ø 4 4.1 0.157 0.161 R A C D E H F G Ø 123 TO-218 (SOT-93) MECHANICAL DATA P025A VNH100N04

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.Specificationsmentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronicsproducts are not authorizedfor use as critical components in life supportdevices or systems without express written approval of SGS-THOMSON Microelectonics.  1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A VNH100N04