Datasheet - VNF1048F - High-side switch controller with intelligent fuse protection for 12 V, 24 V and 48 V automotive applications
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 49
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 2 Electrical specification
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Main electrical characteristics
- 4 Self-test
- 4.1 Current sense self-test
- 4.2 External FET VDS detection self-test
- 4.3 External FET stuck-on self-test
- 5 Protections
- 5.1 Battery undervoltage shutdown
- 5.2 Device overtemperature shutdown
- 5.3 External MOSFET overtemperature shutdown
- 5.4 External MOSFET desaturation shutdown
- 5.5 Hard short circuit latch-off
- 5.6 Current vs time latch-off
- 5.7 Low current bypass desaturation shutdown
- 6 SPI functional description
- 6.1 SPI Communication
- 6.2 Signal description
- 6.3 SPI protocol
- 6.4 Operating code definition
- 6.5 Write mode
- 6.6 Read mode
- 6.7 Read and clear status command
- 6.8 SPI device information
- 6.9 Special commands
- 6.10 Global status byte
- 6.11 Address map
- 6.12 ROM memory map
- 6.13 Control registers
- 6.14 Status registers
- 6.15 Timeout watchdog
Features
Maximum transient supply voltage VS 70 V Operating voltage range VS 6 V to 60 V Operating voltage range (extended) VS 6 V to 70 V Standby current (max.) IS_Q 70 µA SPI I/O supply voltage VSPI 3 V to 5.5 V SPI standby current (max.) I_STBY 5 µA
- AEC-Q100 qualified
- General – High-side switch control IC with eFuse protection for 12 V, 24 V, and
48 V automotive applications
– SPI secondary interface for host control – 32-bit ST-SPI interface compatible with 3.3 V and 5 V CMOS level – 2 stage charge pump – Gate drive for an external MOSFET in high-side configuration – High precision uni-directional digital current sense via SPI through an external high-side shunt resistor – Input for an NTC resistor to monitor the external MOSFET temperature – Very low standby current – Robust fail-safe functionality through internal and external controls – SPI register lock-out by a dedicated digital input pin – Integrated ADC for TJ, VNTC, VOUT, and VDS conversion
- Protections – Battery undervoltage shutdown – External MOSFET desaturation shutdown configurable via SPI – Hard short circuit latch-off configurable via SPI – Current vs time latch-off configurable via SPI (fuse-emulation) – Device overtemperature shutdown – External MOSFET overtemperature shutdown
- Intelligent high current fuse replacement for automotive applications
- Especially, intended for automotive power distribution applications
Description
The VNF1048F is an advanced controller for Power MOSFET in high-side configuration, designed for the implementation of an intelligent high-side switch for 12 V, 24 V, and 48 V automotive applications. The control IC is interfaced to a host microcontroller through a 3.3 V and 5 V CMOS-compatible SPI interface and provides protection and diagnostics to the system. QFN32L Epad (5.0x5.0x1.0 mm) Product status link VNF1048F Product summary Order code VNF1048FTR Packing Tape and reel High-side switch controller with intelligent fuse protection for 12 V, 24 V and 48 V automotive applications VNF1048F Datasheet DS13084 - Rev 8 - November 2023 For further information contact your local STMicroelectronics sales office.
1 Block diagram and pin description
Figure 1. Block diagram Figure 2. Device pin connection diagram (top through view - not in scale)
Table 1. Pin functions 1 VSPI DC supply input for the SPI interface. 3.3 V and 5 V compatible. 5 SCK Serial clock for SPI communication. It is a CMOS compatible input. 7 TEST1 Test mode pin 1- must be connected to the ground. 8 TEST2 Test mode pin 2- must be connected to the ground. registers are locked from writing.
12 V3V3
Output of the 3.3 V internal LDO voltage regulator (logic and I/O supply). Connect a low ESR capacitor (1 μF) close to this pin. 18 NTC_M Negative input pin for external NTC resistor. 19 NTC Positive input pin for external NTC resistor. 20 ISNS_N Current sense amplifier negative input. 21 ISNS_P Current sense amplifier positive input. 23 OUT External FET source connection. 24 HS_GATE Output of the gate driver for the external FET. 25 VS Input supply pin. Connect to the 12 V, 24 V, 48 V battery voltage. 28 CP2P Charge pump–Positive terminal of the flying capacitor CP2. 29 CP2M Charge pump–Negative terminal of the flying capacitor CP2. 30 CP1P Charge pump–Positive terminal of the flying capacitor CP1. 31 CP1M Charge pump–Negative terminal of the flying capacitor CP1.
2 Electrical specification
2.1 Absolute maximum ratings
periods may affect device reliability. Table 2. Absolute maximum ratings
2.2 Thermal data
Table 3. Thermal data
- Device mounted on two-layer 2s0p PCB with 2 cm² heatsink copper trace
2.3 Main electrical characteristics
6 V < VS < 60 V; -40 °C < TJ < 150 °C, unless otherwise specified. All typical values refer to VS = 48 V; TJ = 25 °C, unless otherwise specified. Table 4. Supply specification
- Measured in test mode with the charge pump off.
Table 5. SPI logic inputs (CSN, SCK, and SDI) specification
2.1 IIL
2.2 IIH
2.6 VICL SCK and SDI clamping voltage
Table 6. SPI logic outputs (SDO) specification Table 7. HWLO logic input pin specification Table 8. DIAG logic output pin specification Table 9. Device thermal shutdown
Table 10. ST-SPI timings specification Table 11. Charge pump specification Table 12. External FET gate driver specification
Table 13. Current sense amplifier with integrated ADC Table 14. External FET VDS protection
Table 15. Hard short circuit protection
Table 16. Overcurrent protection
Note: Overcurrent protection is based on the same 10-bit ADC used for hard short protection. Table 17. External FET thermal shutdown via NTC input
- RNTC = B57232V5103F360 (10 kΩ at 25 °C)
- RT-REF = 10 kΩ ±1%
Figure 3. NTC bridge Table 18. Bypass switch
Table 19. VOUT A-to-D conversion
Protection of wire harness and PCB can be performed by defining an ideal time to fuse curve as a result of a maximum power dissipation over the time in the wire or copper PCB traces themselves. This function can guarantee that the insulation of wires and PCB are subject to a limited temperature and time budget that is below the reliability specified values. Not respecting such specified limits can lead to the formation of a conducting path by carbonization across the organic insulation materials and therefore local hot spot can conduct to sparking and fire ignition. The VNF1048F embeds the ST proprietary eFuse functionality for the implementation of a robust and flexible overcurrent protection mechanism. The eFuse functionality features an intelligent circuit breaking aimed at protecting PCB traces, connectors and wire harness from overheating, with no impact on load transients like inrush currents and capacitance charging. This function is set by two parameters called INOM and tNOM. The value of INOM corresponds to the maximum continuous current while tNOM will determine a current versus time-to-fuse curve when load current is higher than INOM. The expression of current versus time-to-fuse is approximated by an optimized stepwise function, which can be adjusted in a range between the wire I2-t limit on one side and load transient characteristics on the other side. The value of tNOM corresponds to the first step up of the curve. The current time curve is always active in combination with very fast overcurrent protection that will be triggered when the current reaches a defined threshold for hard short circuit condition. When the current in the load is pulse wide modulated the eFuse function calculates the mean square root of the current. Mean square root of the current is also calculated when switching on/off the power switch during normal operation or after a switch off due to short circuit/overload condition. So if for example the circuit is broken due to an overload and after a while the circuit is activated again, the eFuse keeps in memory the previous condition and still avoids that maximum IRMS is higher than INOM. VIP-Fuse is programmed via SPI as follows:
- VOC_THRS sets INOM = VOC_THRS/RSENSE
- VHSC_THRS sets hard short circuit current = VHSC_THRS/RSENSE
- T_NOM sets tNOM from 1 to 511 s No intervention occurs for VSENSE < VOC_THRS, whilst an immediate shut-off occurs for VSENSE > VHSC_THRS. The eFuse functionality operating range is defined between VOC_THRS and VHSC_THRS. In that range, the circuit breaking profile is defined by the stepwise function reported in Figure 4. The number of steps is consequential to the selection of VOC_THRS and VHSC_THRS, the maximum being 15, when VOC_THRS = 6 mV and VHSC_THRS = 160 mV. This corresponds to a 1:26.67 ratio between the maximum allowed continuous current and hard short circuit. The Figure 5 shows the I2-t curve when VOC_THRS = 26.5 mV and VHSC_THRS = 105.60 mV. The number of steps is reduced to 9 accordingly. VNF1048F eFuse function DS13084 - Rev 8 page 14/49
4 Self-test
The following sections describe how the device supports the execution of the in-application tests, needed to verify the proper behavior of the hardware diagnostic verification during product lifetime. Configuration, control, and check for each of the tests are performed in close relationship with the microcontroller, through SPI interface communication. Activities related to self-test are possible in a specific device state (self-test) in order to distinguish it from operating modes (standby, wake-up, unlocked and locked modes), allowing to manage differently diagnostic faults according to the hardware feature under test. Self-test control interface The initialization of the self-test sequence (selection of the self-test, start and stop command) is done through the control register 1 (CR#1). Results are accessible through the status register 5 (SR#5), status register 6 (SR#6) and status register 7 (SR#7).
4.1 Current sense self-test
The purpose of the current sense self-test is to verify the proper behavior of the full current sense chain, from the analog input to the digital output. Starting from the unlocked state, the current sense self-test is activated through a dedicated SPI frame. The duration of this test is around 10 µs; the first 5 µs are intended to convert the value of the voltage across the RSENSE. Once the self-test is started, an internal current generator provides a current sink able to produce an additional voltage drop of 100 mV at the input pin of the internal comparator. The result of the self-test is the difference between this converted value and the value already stored in SR#8 (HSHT), corresponding to the normal measurement performed during operation; such result is stored in SR#7 together with the self-test status. The transition from self-test state to unlocked state is automatically guaranteed after the test is completed (around 10 µs) or if the test is stopped through S_T_STOP = 1 (self-test aborted). The transition from the self-test state to the locked state occurs in case of watchdog timeout or HWLO = 1 (self- test aborted). VNF1048F Self-test DS13084 - Rev 8 page 16/49
Figure 6. Current sense self-test flow sequence
4.2 External FET VDS detection self-test
monitor chain (sense/process/detection), from the analog input to the digital output. the overall VDS sensed by the monitor circuit below the maximum scale range (VDS_ADC_CONV). operation; such delta measure result is stored in SR#5 (S_T_VDS field) together with the self-test status.
SR#5 (S_T_VDS_MAX1 bit field). the others are kept enabled. 10 μs) or if the test is stopped through S_T_STOP = 1 (self-test aborted). Figure 7. VDS monitor self-test flow sequence
4.3 External FET stuck-on self-test
(CR#1, S_T_START & S_T_CFG fields). in order to allow the user to monitor VDS evolution in time. one (UPDT_S_T_STUCK bit). Status of self-test execution is available in the same register. (SR#6, S_T_VDS_MAX2 bit). In both cases, device FSM performs the transition from self-test to unlocked state. all the others are kept enabled; bypass switch control is left to the user. Figure 8. External FET stuck-on self-test - flow sequence for entry
5 Protections
5.1 Battery undervoltage shutdown
The device is able to operate down to VS = 6 V, with the charge pump still active. If the battery supply voltage VS falls below the undervoltage shutdown threshold, the device enters in battery undervoltage mode. The current sense diagnostic is not available. The charge pump, the output stage and the bypass switch are off regardless of the SPI status. If VS rises above the threshold (VS_USD + VS_USD_hys) the device returns to the last mode. An undervoltage flag is set in the SPI register when VS < VS_USD, and automatically reset when VS > VS_USD + VS_USD_hys.
5.2 Device overtemperature shutdown
The device temperature is internally monitored. An overtemperature shut-down of the device occurs when TJ exceeds TTSD. The charge pump, the output stage and the bypass switch are off. A fault indication is given via SPI. The device restarts when TJ decreases below TTSD - TTSD_HYS. VTJ is converted by a dedicated ADC converter. The converted result is stored in the Status register and can be read via SPI.
5.3 External MOSFET overtemperature shutdown
The external MOSFET temperature is monitored through a 10 kΩ NTC thermistor with one terminal connected to the Drain of the MOSFET, in order to allow optimal component placement. RNTC is part of a VBG (VBG = VSenseN - VNTC_M; typ. 1.2 V) voltage divider through NTC and NTC_M pins: V N TC = V B G × R N TC R T _ REF + R NTC (1) VNTC is converted by a dedicated ADC converter. The converted result is stored in the Status register and can be read via SPI. An overtemperature shutdown of the MOSFET occurs when VNTC voltage decreases under a preset threshold. The threshold can be set via SPI in the range from 100 °C to 150 °C in steps of 5 °C. In this case both output stages and bypass switch are turned off. The MOSFET and the bypass switch are re-armed via SPI by clearing latched fault NTC_OVT bit. This protection is not active in case of external MOSFET in OFF state.
5.4 External MOSFET desaturation shutdown
The external MOSFET drain-source voltage is monitored by the Control IC. A desaturation shutdown of the MOSFET occurs when the VDS exceeds the preset threshold. In this case both output stage and bypass switch are turned off. The threshold can be set via SPI in the range 0.3 V to 1.80 V in steps of 50 mV (default = 300 mV). The MOSFET and bypass switch are re-armed via SPI by clearing latched fault VDS_MAX bit. VDS is converted by a dedicated ADC converter. The converted result is stored in the Status register and can be read via SPI. This protection is not active in case of external MOSFET in OFF state. VNF1048F Protections DS13084 - Rev 8 page 20/49
5.5 Hard short circuit latch-off
The external MOSFET drain-source current is monitored by the control IC through the current sense amplifier, which reads the voltage drop across a high-side shunt resistor. A hard short circuit shutdown of the MOSFET occurs when the current sense voltage exceeds the preset threshold. In this case, both output stage and bypass switch are turned off. The threshold can be set via SPI in the range from 20 mV to 160 mV. The MOSFET is re-armed via SPI by clearing the HSHT latched fault bit. VHSHT is converted by a dedicated ADC converter. The converted result is stored in the status register and can be read via SPI. This protection is not active in case the external MOSFET is in OFF state.
5.6 Current vs time latch-off
The external MOSFET drain-source current is monitored by the control IC through the current sense amplifier, which reads the voltage drop across a high-side shunt resistor. The overload detection circuitry emulates the response of a traditional fuse. An overcurrent shutdown of the MOSFET occurs when the current sense voltage exceeds the preset threshold for longer than the preset time. In this case, both output stages and bypass switch are turned off. The threshold can be set via SPI in the range 6 mV to 90 mV, while the nominal trip time can be programmed in the range from 1 s to 511 s. The MOSFET is re-armed via SPI by clearing the FUSE_LATCH latched fault bit. This protection is not active in case the external MOSFET is in OFF state. In case of hard short protection event occurrence, reported by the HSHT flag bit, the FUSE_LATCH bit is set as well.
5.7 Low current bypass desaturation shutdown
Internal bypass switch VDS voltage (VS - VOUT) is monitored by the IC, to protect the switch from load current sink changes. A desaturation shutdown of the bypass occurs when its VDS exceeds a fixed threshold (~1.3 V); in this situation, the bypass switch is turned off while the external FET is turned on through the HS_GATE output, directly by the hardware, regardless of their software controlled bit status, in order to protect the bypass and provide the requested current capability to the connected load. This represents the so-called AUTO-ON event and it is flagged by bit #4 (AUTOON) of the global status byte that corresponds to the BYPASS_SAT flag of status Register #1. Bypass switch can be re-armed through SPI control by clearing the BYPASS_SAT fault latched bit. This protection is not active in case the bypass switch is in OFF state. A particular case is represented by standby wake-up event occurrence, with FSM state transition to wake up state, due to bypass switch desaturation: only in this situation, in addition to the previously mentioned actions on the bypass switch and external FET, the device signals, by driving the DIAG pin low, that it has been woken up by the hardware event (load current increase), in order to allow host control to take proper actions. It is important to notice that the bypass switch cannot be used to charge any type of load, even those requesting small currents capability: on the contrary, it shall be used to keep powered application loads, previously charged by external FET, when they switch to low-power consumption modes (that is, standby). VNF1048F Protections DS13084 - Rev 8 page 21/49
6 SPI functional description
6.1 SPI Communication
The SPI communication is based on the “ST-SPI Specification”. A SPI Master device (Host Microcontroller) initiates the communication. Input data are shifted into SDI, MSB first while output data are shifted out on SDO, MSB first. Figure 9. SPI functional diagram
6.2 Signal description
on the rising edge of Serial Clock (SCK). when a valid frame was sent. During communication start and stop the Serial Clock (SCK) has to be logically low.
6.3 SPI protocol
Table 20. Command byte Table 21. Input data byte 1 Table 22. Input data byte 2 Table 23. Input data byte 3 Table 24. Global status byte details on bit0 - bit7). This byte is followed by three output data bytes (D23 : D16), (D15 : D8) and (D7 : D0).
Table 25. Output data byte 1 Table 26. Output data byte 2 Table 27. Output data byte 3
6.4 Operating code definition
The SPI interface features four different addressing modes which are listed in Table 28. Table 28. Operating codes
6.5 Write mode
Figure 10. SPI write operation
6.6 Read mode
The read mode of the device allows to read and to check the state of any registers. Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first. content of the addressed register.Unused bits will be always read as 0. contents are frozen during SPI communication. Figure 11. SPI read operation
6.7 Read and clear status command
Table 33. RAM memory map). A read and clear status operation with address 0x3Fh clears all Status registers register which have to be cleared. of the addressed register. Unused bits will be always read as 0. contents are frozen during SPI communication. Figure 12. SPI read and clear operation
6.8 SPI device information
Specific information can be read but not modified during this mode. determine which information is read, whilst the other three data bytes are "don’t care". addressed register, third and forth bytes are 0x00. Figure 13. SPI read device information
6.9 Special commands
third and forth bytes are "don't care" provided that at least one bit is zero. recognized as a frame error and SPIE bit of GSB is set. Table 29. 0xFF: (SW_Reset) When an OpCode ‘10’ (read and clear operation) at address b’111111 is performed.
Table 30. Clear all status registers (RAM access)
6.10 Global status byte
As per the STMicroelectronics SPI 4.1 specification, the device features an in-frame response mechanism. Table 31. Global status byte Table 32. Global status byte - bit description
31 GSBN
present directly after pulling CSN low.
30 RSTB
29 SPIE
28 AUTOON
from wake up to unlocked mode.
27 DIAGS
25 OVC
6.11 Address map
Table 33. RAM memory map
6.12 ROM memory map
Table 34. ROM memory map
6.13 Control registers
Table 35. CR#1: control register 1 (read/write); address 01h will have no effects and it maintains its previous value. GOSTBY can be reset to 0 also when UNLOCK = 0. 2nd SPI write operation to set GOSTBY bit to 1 and EN bit to 0. A transition to standby state causes GOSTBY to be reset to 0. no effects and it maintains its previous value. EN can be reset to 0 also when UNLOCK = 0. 2nd SPI write operation to set GOSTBY bit to 0 and EN bit to 1. A transition to unlocked state causes EN to be set to 1. A transition to locked state causes EN to be reset to 0. When it is set to 1, starts selected self-test. This bit is automatically reset. When it is set to 1, stops execution of selected self-test. This bit is automatically reset.
2 Unused
Table 36. CR#2: control register 2 (read/write); address 02h overcurrent threshold (OVC_THR). Configures the value of nominal overcurrent threshold. Configures a threshold for hard short circuit latch-off. The threshold can be set in the range from 20 mV to 160 mV.
0 Parity bit Odd parity bit check
Table 37. CR#3: control register 3 (read/write); address 03h 1: bits GOSTBY, EN can be set to 1, but only with the next valid SPI frame. When UNLOCK = 1, it is automatically reset with the next valid SPI frame. threshold can be set in the range 37.50 to 110.92.
period equal to tWD to refresh the watchdog.
6.14 Status registers
Table 38. SR#1: status register 1; address 11h When DIS_OUT_FAULT = 1, both high-side and bypass are switched off. bypass switch are switched off. exceeds the preset threshold. The MOSFET and the bypass switch are re-armed via SPI. the preset threshold when HS is in on-state after VDS_DEGLITCH time. The MOSFET and the bypass switch are re-armed via SPI. threshold when HS is in off-state and bypass is in on-state. independently of OUTCTL bit value.
causes this bit to be set to 1. curve emulating a traditional fuse). The MOSFET and bypass switch are rearmed via SPI. restarts and current is again above OVC_THR). this case user can expect that trip time will be lower than expected. turned off. The MOSFET and the bypass switch are rearmed via SPI. mode through the GoToUnlocked sequence this bit must be cleared. Table 39. SR#2: status register 2; address 12h
Table 40. SR#3: status register 3; address 13h
23 Unused
Table 41. SR#4: status register 4; address 14h 10 bit ADC conversion of the voltage across HS switch (VS-OUT). This register is not refreshed during VDS self-test execution. Table 42. SR#5: status register 5; address 15h Table 43. SR#6: status register 6; address 16h
Table 44. SR#7: status register 7; address 17h HSHT_SAR register latched during self-test execution. Table 45. SR#8: status register 8; address 18h from 0 V to 160 mV; unidirectional current through an external sense resistor. This register is not refreshed during current sense self-test execution.
6.15 Timeout watchdog
Figure 14. Timeout watchdog
7 Operating modes
7.1 State diagram
Figure 15. State diagram (***) Transition to locked resets "EN" bit to 1 and sets 'DIS_OUT_FAULT' to 1 only if 'DIS_OUT_MODE' = 1. (**) Transition to unlocked sets "EN' bit to 1. (*) Transition to wakeup sets 'BYPASS_SAT' status bit to 1. When there are more then one possibletransitions out of one state, priority number is indicated in brackets for each transition.
7.2 Power-on mode
The power-on mode is the device reset state at VS power-on, due to device startup or power-on reset conditions. At power-on, the registers are loaded with the default values and the RSTB is set to 1. External FET, BYPASS switch, and charge pump are in the OFF state.
7.3 Standby mode
In standby mode, the device is in quiescent power consumption and operates under the following conditions:
- High current path through external FETs is off
- Protections for the external FETs are disabled
- All diagnostics are disabled, but BYPASS switch saturation is monitored, if BYPASS switch is in ON state during standby mode, in order to detect potential desaturation
- Low-current bypass can be ON or OFF according to the ‘BYPASSCTL’ bit
- The device is self-protected
- Charge pump is OFF The standby mode characteristics are:
- VSPI and VS low consumption
- SPI inactive
- Registers are frozen (powered but with the clock stopped) allowing to keep either previous configuration, in case of transition from unlocked state, or default reset configuration, in case of transition from power-on state The standby mode is reached in case of power-on state transition from unlocked mode through the following SPI frame sequence: 1. Frame #1 to set UNLOCK bit in CR#3 2. Frame #2 to reset EN and set GOSTBY in CR#1 Exit from standby mode occurs in any of the following cases:
- CSN Low for a time t > tSTBY_OUT Or
- BYPASS switch in ON state and desaturation event occurrence
7.4 Wake-up mode
The device enters in wake-up mode from standby when the VS - VOUT > VDS_BYPASS_SAT. In wake-up mode, the device fuse functionality is armed and the device operates under the following conditions:
- High current path through external FETs is ON
- Protections for the external FETs are enabled
- Low-current bypass is OFF
- All diagnostics are enabled
- Control registers are locked to write operations
- The device is self-protected
- SPI is active
- Charge pump is ON
7.5 Unlocked mode
In unlocked mode, the device fuse functionality is armed and SPI communication is allowed. The device operates under the following conditions:
- High current path through external FETs can be ON or OFF, depending on the SPI setting
- Protections for the external FETs are enabled
- All diagnostics are enabled
- Low-current bypass can be ON or OFF, depending on the SPI setting
- The device is self-protected
- SPI is active
- Charge pump is ON VNF1048F Operating modes DS13084 - Rev 8 page 38/49
7.6 Locked mode
In locked mode, the device fuse functionality is armed. The device operates under the following conditions:
- External FETs status is defined by 'OUTCTL' and 'DIS_OUT_MODE' control bits
- Protections for the external FETs are enabled
- All diagnostics are enabled
- Low-current bypass is defined by 'BYPASSCTL' and 'DIS_OUT_MODE' control bits
- The device is self-protected
- SPI is active, all registers can be read, control registers are locked to write operations
- Charge pump is ON
7.7 Self-test mode
See Section 4 Self-test in this document. VNF1048F Operating modes DS13084 - Rev 8 page 39/49
8 Application information
Figure 16. Application diagram Table 46. Component value
Application information
DS13084 - Rev 8 page 40/49
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. 9.1 QFN32L Epad (5.0x5.0x1.0 mm) package information Figure 17. QFN32L Epad (5.0x5.0x1.0 mm) package outline
Package information
DS13084 - Rev 8 page 41/49
Table 47. QFN32L Epad (5.0x5.0x1.0 mm) package mechanical data DS13084 - Rev 8 page 42/49
Revision history
Table 48. Document revision history 16-Oct-2019 1 Initial release.
- Section 3 eFuse function - Section 4.2 External FET VDS Detection Self Test - Section 5.4 External MOSFET desaturation shutdown - Section 6.14 Status Registers - Section 7 Operating modes - Figure 16. Application diagram 06-May-2022 5 Updated :
- Features in cover page
- Figure 2. Configuration diagram (top view)
- Table 2. Absolute maximum rating
- Table 4. Supply specification
- Table 13. Current sense amplifier with integrated ADC
- Section 4.1 Current Sense Self Test
- Figure 6. Current sense self test flow sequence
- Section 4.2 External FET VDS Detection Self Test
- Figure 7. VDS monitor self test flow sequence
- Figure 8. External FET Stuck-on self test - flow sequence for entry
- Section 5.1 Battery under-voltage shutdown
- Table 34. ROM Memory Map (ID 12.2) Minor text changes. 27-May-2022 6 Modified Table 2. Absolute maximum ratings. Modified Figure 14. Timeout watchdog. Minor text changes. 14-Jul-2023 7 Updated Table 2. Absolute maximum ratings. Minor text changes. 17-Nov-2023 8 Updated Package silhouette on cover page. Updated Section 1 Block diagram and pin description. Removed column "ID" in all tables of Section 2.3 Main electrical characteristics. Updated Figure 6, Figure 7 and Figure 8. Updated Section 5.3 External MOSFET overtemperature shutdown. Updated Section 6.12 ROM memory map and Section 6.14 Status registers. Updated Section 7 Operating modes. Minor text changes. VNF1048F DS13084 - Rev 8 page 44/49
Contents
DS13084 - Rev 8 page 46/49
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