VND9008AJ STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 38
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 2 Electrical specifications
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Main electrical characteristics
- 2.4 Waveforms
- 3 Protections
- 3.1 Power limitation
- 3.2 Thermal shutdown
- 3.3 Current limitation
- 3.4 Negative voltage clamp
- 4 Application information
- 4.1 GND protection network against reverse battery
- 4.1.1 Diode (DGND) in the ground line
- 4.2 Immunity against transient electrical disturbances
- 4.3 MCU I/Os protection
- 4.4 CS - analog current sense
- 4.4.1 Principle of current sense signal generation
- 4.4.2 Short to VCC and OFF-state open-load detection
- 5 Maximum demagnetization energy (VCC = 16 V)
- 6 Package and PCB thermal data
- 6.1 PowerSSO-16 thermal data
- 7 Package information
- 7.1 PowerSSO-16 package information
- 7.2 PowerSSO-16 packing information
- 7.3 PowerSSO-16 marking information
Features
Max. transient supply voltage VCC 36 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per channel) RON 9.4 mΩ Current limitation (typ.) ILIMH 67 A Standby current (max.) ISTBY 0.5 µA
- AEC-Q100 qualified
- Extreme low voltage operation for deep cold cranking applications (compliant with LV124, revision 2013)
- General – Double channel smart high-side driver with current sense analog feedback – Very low standby current – Compatible with 3 V and 5 V CMOS outputs
- Current sense diagnostic functions – Multiplexed analog feedback of load current with high precision proportional current mirror – Overload and short to ground (power limitation) indication – Thermal shutdown indication – OFF-state open-load detection – Output short to V CC detection – Sense enable/disable
- Protections – Undervoltage shutdown – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients – Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin – Loss of ground and loss of V CC – Reverse battery through self turn-on – Electrostatic discharge protection
Applications
- Automotive resistive, inductive and capacitive loads
- Protected supply for ADAS systems: radars and sensors
- Automotive headlamps (up to H7) PowerSSO-16 Product status link VND9008AJ Product summary Order code VND9008AJTR Package PowerSSO-16 Packing Tape and reel Double channel high-side driver with current sense analog feedback for automotive applications VND9008AJ Datasheet DS12148 - Rev 4 - December 2022 For further information contact your local STMicroelectronics sales office.
Description
The device is a double channel high-side driver manufactured using ST proprietary VIPower M0-9 technology and housed in PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, providing protection and diagnostics. The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A dedicated multifunction multiplexed analog output pin delivers diagnostic functions including high precision proportional load current sense, in addition to the detection of overload and short circuit to ground, short to VCC and OFF-state open-load. A sense enable pin allows OFF-state diagnosis to be disabled during the module low-power mode as well as external sense resistor sharing among similar devices. VND9008AJ DS12148 - Rev 4 page 2/38
1 Block diagram and pin description
Figure 1. Block diagram Table 1. Pin functions GND Ground connection. Must be reverse battery protected by an external diode / resistor network. CS Multiplexed analog sense output pin; it delivers a current proportional to the selected load current. SEn Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the CS diagnostic pin. SEL Active high compatible with 3 V and 5 V CMOS outputs pin; it addresses the CS multiplexer. sets the outputs in auto-restart mode.
Figure 2. Configuration diagram (top view) Table 2. Suggested connections for unused and not connected pins
2 Electrical specifications
Figure 3. Current and voltage conventions Note: V Fn = VOUTn - VCC during reverse battery condition.
2.1 Absolute maximum ratings
below for extended periods may affect the device reliability. Table 3. Absolute maximum ratings
2.2 Thermal data
Table 4. Thermal data
- Device mounted on a four-layer 2s2p PCB.
- Device mounted on a two-layer 2s0p PCB with 2 cm2 heatsink copper trace.
2.3 Main electrical characteristics
7 V < VCC < 28 V; -40 °C < TJ < 150 °C, unless otherwise specified. All typical values refer to VCC = 13 V; TJ = 25 °C, unless otherwise specified. Table 5. Power section
- Power MOSFET leakage included.
- Parameter specified by design; not tested in production.
Table 6. Switching
- See Figure 4. Switching time and pulse skew.
- Parameter specified by design and evaluated by characterization; not tested in production.
Table 7. Logic inputs
7 V < VCC < 28 V; -40 °C < TJ < 150 °C
Table 8. Protections
7 V < VCC < 18 V; -40 °C < TJ < 150 °C
- for example Ch 0: VIN0 = 5 V; VSEL = 0 V 3 10 20 µs tD_Restart Latch-OFF delay time before automatic restart 50 75 ms VDEMAG Turn-off output voltage clamp IOUT = 1 A; L = 6 mH; TJ = -40 °C VCC - 36 V IOUT = 1 A; L = 6 mH; TJ = 25 °C to 150 °C VCC - 36 VCC - 38 VCC - 45 V 1. I LIMH, guaranteed beteween 7 V and 16 V, -40 °C < TJ < 150 °C. 2. I LIMH2, guaranteed beteween 16 V and 19 V, -40 °C < TJ < 150 °C. 3. Parameter specified by design and evaluated by characterization; not tested in production. VND9008AJ Main electrical characteristics DS12148 - Rev 4 page 9/38
Table 9. Current sense
7 V < VCC < 18 V; -40°C < TJ < 150°C
- for example Ch 0: VIN0 = 5 V; VIN1 = 5 V; VSEL = 0 V; IOUT0 = 0 A; IOUT1 = 4.6 A 0 10 CS enabled: VSEn = 5 V; ChX OFF; ChX diagnostic selected:
- for example Ch 0: VIN0 = 0 V; VIN1 = 5 V; VSEL = 0 V; IOUT0 = 0 A; IOUT1 = 4.6 A 0 1 VOUT_MSD (1) Output Voltage for CS shutdown VSEn = 5 V; RSENSE = 2.7 kΩ;
- for example Ch 0: VIN0 = 5 V; VSEL = 0 V; IOUT0 = 4.6 A 5 V VSENSE_SAT CS saturation voltage VCC = 7 V; RSENSE = 10 kΩ; VSEn = 5 V; VIN0 = 5 V; VSEL = 0 V; IOUT0 = 13.8 A; TJ = -40 °C 4.8 V ISENSE_SAT (1) CS saturation current VCC = 7 V; VSENSE = 3.5 V; VIN0 = 5 V; VSEn = 5 V; VSEL = 0 V; TJ = 150 °C 2 mA IOUT_SAT (1) Output saturation current VCC = 7 V; VSENSE = 3.5 V; VIN0 = 5 V; VSEn = 5 V; VSEL = 0 V; TJ = 150 °C 30 A OFF-state diagnostic VOL OFF-state open-load voltage detection threshold VSEn = 5 V; ChX OFF; ChX diagnostic selected
- for example: Ch 0 VIN0 = 0 V; VSEL = 0 V; 2 3 4 V VND9008AJ Main electrical characteristics DS12148 - Rev 4 page 10/38
Figure 6. TDSTKON )
- for example: Ch 0 VIN0 = 5 V to 0 V; VSEL = 0 V; IOUT0 = 0 A; VOUT0 = 4 V 150 260 400 µs tD_OL_V Settling time for valid OFF-state open load diagnostic indication from rising edge of SEn VIN0 = 0 V; VIN1 = 0 V; VFR = 0 V; VSEL = 0 V; VOUT0 = 4 V; VSEn = 0 V to 5 V 60 µs tD_VOL OFF-state diagnostic delay time from rising edge of VOUT VSEn = 5 V; ChX OFF; ChX diagnostic selected
- for example: Ch 0 VIN0 = 0 V; VSEL = 0 V; VOUT = 0 V to 4 V 5 30 µs Fault diagnostic feedback (see Table 10. Truth table) VSENSEH Current sense output voltage in fault condition
13 V < VCC < 18 V; Ch0 in open load;
13 V < VCC < 18 V; VSENSE = 5 V;
- Parameter specified by design and evaluated by characterization; not tested in production.
- All values refer to V CC = 13 V; TJ = 25°C, unless otherwise specified.
- Transition delay is measured up to ±10% of final conditions.
Figure 4. Switching time and pulse skew
Table 10. Truth table
- Refer to Table 11. Current sense multiplexer addressing
Table 11. Current sense multiplexer addressing
2.4 Waveforms
Figure 7. Latch-off mode - Intermittent short circuit Figure 8. Auto-restart mode - Intermittent short circuit
3 Protections
3.1 Power limitation
The basic working principle of this protection consists of an indirect measurement of the junction temperature swing ΔTJ through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as ΔTJ exceeds the safety level of ΔTJ_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo- mechanical fatigue.
3.2 Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High).
3.3 Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (for example bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region.
3.4 Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the device. VND9008AJ Protections DS12148 - Rev 4 page 17/38
4 Application information
Figure 12. Application diagram
4.1 GND protection network against reverse battery
Figure 13. Simplified internal structure
Application information
DS12148 - Rev 4 page 18/38
4.1.1 Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an inductive load. the same diode/resistor network.
4.2 Immunity against transient electrical disturbances
into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. conduction along supply line. does not perform as designed during the test but returns automatically to normal operation after the test”. Table 12. ISO 7637-2 - electrical transient conduction along supply line
- U S is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
- With 35 V external suppressor referred to ground (-40°C < T j < 150 °C).
Figure 14. M0-9 application schematic
4.3 MCU I/Os protection
latching-up and to protect the HSD inputs. required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.
4.4 CS - analog current sense
- Current monitor: current mirror of channel output current Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in Table 11. VND9008AJ MCU I/Os protection DS12148 - Rev 4 page 20/38
Figure 15. CurrentSense and diagnostic – block diagram
4.4.1 Principle of current sense signal generation
Figure 16. CurrentSense block diagram
The output is capable of providing:
- Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to known ratio named K
- Diagnostics flag in fault conditions delivering fixed voltage V SENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted to a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by MultiSense output: ISENSE = IOUT/K Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K Where:
- V SENSE is voltage measurable on RSENSE resistor
- I SENSE is current provided from CurrentSense pin in current output mode
- I OUT is current flowing through output
- K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the CurrentSense pin which is switched to a “current limited” voltage source, VSENSEH. In any case, the current sourced by the CurrentSense in this condition is limited to ISENSEH. The typical behavior in case of overload or hard short circuit is shown in Waveforms. VND9008AJ CS - analog current sense DS12148 - Rev 4 page 22/38
Table 13. CS pin levels in off-state
4.4.2 Short to VCC and OFF-state open-load detection
current consumption to increase in normal conditions, that is when load is connected.
5 Maximum demagnetization energy (VCC = 16 V)
Figure 19. Maximum turn off current versus inductance Figure 20. Maximum turn off energy versus inductance
6 Package and PCB thermal data
6.1 PowerSSO-16 thermal data
Figure 21. PowerSSO-16 on two-layer PCB (2s0p to JEDEC JESD 51-5) Figure 22. PowerSSO-16 on four-layer PCB (2s2p to JEDEC JESD 51-7) Table 14. PCB properties
Figure 23. RthJA vs PCB copper area in open box free air condition (one channel on) Figure 24. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
4 Layer
Figure 25. Thermal fitting model of a double-channel HSD in PowerSSO-16 (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 15. Thermal parameters
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
7.1 PowerSSO-16 package information
Figure 26. PowerSSO-16 package dimensions
Package information
DS12148 - Rev 4 page 29/38
Table 16. PowerSSO-16 mechanical data
7.2 PowerSSO-16 packing information
Figure 27. PowerSSO-16 reel 13" Table 17. Reel dimensions
- All dimensions are in mm.
7.3 PowerSSO-16 marking information
Figure 30. PowerSSO-16 marking information engineering samples to run a qualification activity.
Revision history
Table 19. Document revision history 06-Dec-2017 1 Initial release. 13-Dec-2017 2 No content changed, removed the watermark "Restricted".
- Section 5 Package information. Updated:
- Figure 1. Block diagram;
- Table 5. Power section;
- Table 6. Switching;
- Table 8. Protections;
- Table 9. Current sense;
- Section Features;
- Section Applications;
- Section 2.4 Waveforms. Minor text changes in:
- Table 7. Logic inputs;
- Table 3. Absolute maximum ratings. 23-Dec-2022 4 Update Section 2.1 Absolute maximum ratings and Section 2.2 Thermal data. Updated Table 5. Power section, Table 6. Switching,Table 8. Protections and Table 9. Current sense. Updated Section 4 Application information. Added Section 5 Maximum demagnetization energy (VCC = 16 V). Added Section 6 Package and PCB thermal data. Minor text changes. VND9008AJ DS12148 - Rev 4 page 34/38
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