VND7E050AJ STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 48
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 2 Electrical specification
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Main electrical characteristics
- 2.4 Waveforms
- 2.5 Electrical characteristics curves
- 3 Protections
- 3.1 Power limitation
- 3.2 Thermal shutdown
- 3.3 Current limitation
- 3.4 Negative voltage clamp
- 4 Application information
- 4.1 GND protection network against reverse battery
- 4.1.1 Diode (DGND) in the ground line
- 4.2 Immunity against transient electrical disturbances
- 4.3 MCU I/Os protection
- 4.4 CS - analog current sense
- 4.4.1 Principle of CurrentSense signal generation
- 4.4.2 Short to VCC and OFF-state open-load detection
- 5 Maximum demagnetization energy (Vcc = 16 V)
- 6 Package and PCB thermal data
- 6.1 PowerSSO-16 thermal data
- 7 Package information
- 7.1 PowerSSO-16 package information
- 7.2 PowerSSO-16 packing information
- 7.3 PowerSSO-16 marking information
Features
Max transient supply voltage VCC 40 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per Ch) RON 50 mΩ Current limitation (typ) ILIMH 40 A Standby current (max) ISTBY 0.5 µA Minimum cranking supply voltage (VCC decreasing) VUSD_cranking 2.85 V
- AEC-Q100 qualified
- Extreme low voltage operation for deep cold cranking applications (compliant with LV124, revision 2013)
- General – Double channel smart high-side driver with CurrentSense analog feedback – Very low standby current – Compatible with 3 V and 5 V CMOS outputs
- CurrentSense diagnostic functions – Analog feedback of load current with high precision proportional current mirror – Overload and short to ground (power limitation) indication – Thermal shutdown indication – OFF-state open-load detection – Output short to V CC detection – Sense enable/disable
- Protections – Undervoltage shutdown – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients – Configurable latch-off on overtemperature or power limitation – Loss of ground and loss of V CC – Reverse battery with external components – Electrostatic discharge protection
Applications
- Automotive resistive, inductive and capacitive loads
- Protected supply for ADAS systems: radars and sensors
- Automotive lamps Product status VND7E050AJ Product summary Order code VND7E050AJTR Package PowerSSO-16 Packing Tape and reel Double channel high-side driver with CurrentSense analog feedback for automotive applications VND7E050AJ Datasheet DS12566 - Rev 2 - November 2018 For further information contact your local STMicroelectronics sales office.
Description
The device is a dual channel high-side driver manufactured with proprietary ST VIPower® M0-7 technology, in a PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, providing protection and diagnostics. The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A multiplexed current sense pin delivers high precision proportional load current sense in addition to the detection of overload and short circuit to ground, short to VCC and OFF-state open-load. A sense enable pin allows OFF-state diagnosis to be disabled during the module low- power mode as well as external sense resistor sharing among similar devices. VND7E050AJ DS12566 - Rev 2 page 2/48
1 Block diagram and pin description
Figure 1. Block diagram Table 1. Pin functions OUTPUT0,1 Power outputs; all the pins must be connected together. GND Ground connection; must be reverse battery protected by an external diode / resistor network. chip temperature diagnostic. SEn Active high compatible with 3 V and 5 V CMOS outputs pin; enables the CS diagnostic pin. SEL0 Active high compatible with 3 V and 5 V CMOS outputs pin; it addresses the CS multiplexer. sets the outputs in auto-restart mode.
Figure 2. Configuration diagram (top view) Table 2. Suggested connections for unused and not connected pins
2 Electrical specification
Figure 3. Current and voltage conventions Note: V Fn = VOUTn - VCC during reverse battery condition.
2.1 Absolute maximum ratings
Forcing the device to operate above absolute maximum ratings may cause permanent damage. extended periods may affect device reliability. Table 3. Absolute maximum ratings
2.2 Thermal data
Table 4. Thermal data
- Device mounted on four-layer 2s2p PCB
- Device mounted on two-layer 2s0p PCB with 2 cm² heatsink copper trace
2.3 Main electrical characteristics
7 V < VCC < 28 V; -40 °C < Tj < 150 °C, unless otherwise specified. All typical values refer to VCC = 13 V; Tj = 25 °C, unless otherwise specified. Table 5. Electrical characteristics during cranking
- Parameter guaranteed by design and characterization; not subject to production test
Table 6. Power section
- Parameter guaranteed only at V cc = 4 V and Tj = 25 °C
- PowerMOS leakage included
- Parameter specified by design; not subject to production test.
Table 7. Switching
- See Figure 6. Switching time and pulse skew
- Parameter guaranteed by design and characterization; not subject to production test.
Table 8. Logic inputs
7 V < VCC < 28 V; -40°C < Tj < 150°C
Table 9. Protections
7 V < VCC < 18 V; -40°C < Tj < 150°C
4 V < VCC < 18 V (1)
- Parameter guaranteed by design and characterization; not subject to production test.
Table 10. CurrentSense
Symbol Parameter Test conditions Min. Typ. Max. Unit IOUT_SAT (1) Output saturation current VCC = 7 V; VSENSE = 4 V; VIN0 = 5 V; VSEn = 5 V; VSEL0 = 0 V; Tj = 150°C 5 A OFF-state diagnostic VOL OFF-state open-load voltage detection threshold VSEn = 5 V; ChX OFF; ChXdiagnostic selected; - E.g. Ch0 VIN0 = 0 V; VSEL0 = 0 V; 2 3 4 V IL(off2) (3) OFF-state output sink current VIN = 0 V; VOUT = VOL; Tj = -40°C to 125°C -100 -15 µA tDSTKON OFF-state diagnostic delay time from falling edge of INPUT (see Figure 8. TDSTKON ) VSEn = 5 V; ChX ON to OFF transition; ChXdiagnostic selected; - E.g. Ch0 VIN0 = 5 V to 0 V; VSEL0 = 0 V; IOUT0 = 0 A; VOUT = 4 V 100 350 700 µs tD_OL_V Settling time for valid OFF- state open load diagnostic indication from rising edge of SEn VIN0 = 0 V; VIN1 = 0 V; VFR = 0 V; VSEL0 = 0 V; VOUT = 4 V; VSEn = 0 V to 5 V 60 µs tD_VOL OFF-state diagnostic delay time from rising edge of VOUT VSEn = 5 V; ChX OFF; ChX diagnostic selected; - E.g. Ch0 VIN0 = 0 V; VSEL0 = 0 V; VOUT = 0 V to 4 V 5 30 µs Fault diagnostic feedback (see Table 11. Truth table) VSENSEH CurrentSense output voltage in fault condition VCC = 13 V; RSENSE = 1 kΩ - E.g. Ch0 in open load VIN0 = 0 V; VSEn = 5 V VSEL0 = 0 V; IOUT0 = 0 A VOUT = 4 V 5 6.6 V ISENSEH CurrentSense output current in fault condition VCC = 13 V; VSENSE = 5 V 7 20 30 mA CurrentSense timings (current sense mode - see Figure 7. CurrentSense timings (current sense mode)) (4) tDSENSE1H Current sense settling time from rising edge of SEn VIN = 5 V; VSEn = 0 V to 5 V; RSENSE = 1 kΩ; RL = 8.67 Ω 60 µs tDSENSE1L Current sense disable delay time from falling edge of SEn VIN = 5 V; VSEn = 5 V to 0 V; RSENSE = 1 kΩ; RL = 8.67 Ω 5 20 µs tDSENSE2H Current sense settling time from rising edge of INPUT VIN = 0 V to 5 V; VSEn = 5 V; RSENSE = 1 kΩ; RL = 8.67 Ω 100 250 µs VND7E050AJ Main electrical characteristics DS12566 - Rev 2 page 12/48
- Parameter specified by design and characterization; not subject to production test.
- All values refer to V CC = 13 V; Tj = 25°C, unless otherwise specified.
- Parameter granted at -40 °C < T j < 125 °C
- Transition delay are measured up to +/- 10% of final conditions.
Figure 4. IOUT/ISENSE versus IOUT
Table 11. Truth table
- Refer to Table 12. CurrentSense multiplexer addressing
Table 12. CurrentSense multiplexer addressing
- If the output channel for the selected MUX channel is latched off while the relevant input is low, the CS pin
2.4 Waveforms
Figure 9. Latch functionality - behavior in hard short-circuit condition (TAMB << TTSD) Figure 10. Latch functionality - behavior in hard short-circuit condition
Figure 13. Standby state diagram
2.5 Electrical characteristics curves
Figure 14. OFF-state output current Figure 15. Standby current Figure 16. IGND(ON) vs. Iout Figure 17. Logic input high level voltage Figure 18. Logic input low level voltage Figure 19. High level logic input current
3 Protections
3.1 Power limitation
The basic working principle of this protection consists of an indirect measurement of the junction temperature swing ΔTj through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo- mechanical fatigue.
3.2 Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High).
3.3 Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region.
3.4 Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the device. VND7E050AJ Protections DS12566 - Rev 2 page 24/48
4 Application information
Figure 34. Application diagram
Application information
DS12566 - Rev 2 page 25/48
4.1 GND protection network against reverse battery
Figure 35. Simplified internal structure
4.1.1 Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an inductive load. the same diode/resistor network.
4.2 Immunity against transient electrical disturbances
into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. conduction along supply line. through VCC and GND terminals. does not perform as designed during the test but returns automatically to normal operation after the test”. Table 13. ISO 7637-2 - electrical transient conduction along supply line
2011(E) Test pulse severity level with Status II functional performance status Minimum number of pulses or test time Burst cycle / pulse repetition time Pulse duration and pulse generator internal impedance Level US (1) min max 2a(3) III +55 V 500 pulses 0.2 s 5 s 50 µs, 2 Ω 3a IV -220 V 1h 90 ms 100 ms 0.1 µs, 50 Ω 3b IV +150 V 1h 90 ms 100 ms 0.1 µs, 50 Ω 4 (2) IV -7 V 1 pulse 100 ms, 0.01 Ω Load dump according to ISO 16750-2:2010 Test B (3) 40 V 5 pulse 1 min 400 ms, 2 Ω 1. U S is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6. 2. Test pulse from ISO 7637-2:2004(E). 3. With 40 V external suppressor referred to ground (-40°C < T j < 150 °C).
4.3 MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line both to prevent the microcontroller I/O pins from latching-up and to protect the HSD inputs. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. Equation VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC - VIH - VGND) / IIHmax Calculation example: For VCCpeak = -150 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V 7.5 kΩ ≤ Rprot ≤ 140 kΩ. Recommended values: Rprot = 15 kΩ
4.4 CS - analog current sense
Diagnostic information on device and load status are provided by an analog output pin (CS) delivering the following signals:
- Current monitor: current mirror of channel output current These signals are routed through an analog multiplexer which is configured and controlled through SELx and SEn pins according to the address map in Table 8. VND7E050AJ MCU I/Os protection DS12566 - Rev 2 page 27/48
Figure 36. CurrentSense and diagnostic – block diagram
4.4.1 Principle of CurrentSense signal generation
Figure 37. CurrentSense block diagram
- Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to a known ratio named K
- Diagnostics flag in fault conditions delivering fixed voltage V SENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted into a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by CS output: ISENSE = IOUT/K Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K Where:
- V SENSE is the voltage measurable on RSENSE resistor VND7E050AJ CS - analog current sense DS12566 - Rev 2 page 29/48
- I SENSE is the current provided from CS pin in current output mode
- I OUT is the current flowing through output
- K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of the overall circuitry, specifying the ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the CS pin which is switched to a “current limited” voltage source, VSENSEH. In any case, the current sourced by the CS in this condition is limited to ISENSEH.
Figure 38. Analog HSD – open-load detection in off-state
Figure 39. Open-load / short to VCC condition Table 14. CurrentSense pin levels in off-state
4.4.2 Short to VCC and OFF-state open-load detection
A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the device off-state. Small or no current is delivered by the current sense during the on-state depending on the nature of the short circuit. OFF-state open-load with external circuitry Detection of an open-load in off mode requires an external pull-up resistor RPU connecting the output to a positive supply voltage VPU. It is preferable that VPU is switched off during the module standby mode in order to avoid the overall standby current consumption to increase in normal conditions, i.e. when load is connected. RPU must be selected in order to ensure VOUT > VOLmax in accordance with the following equation: Equation R PU < V PU - 4 IL(off2)min @ 4V VND7E050AJ CS - analog current sense DS12566 - Rev 2 page 32/48
5 Maximum demagnetization energy (Vcc = 16 V)
Figure 41. Maximum turn off current versus inductance Figure 42. Maximum turn off energy versus inductance Note: Values are generated with R L = 0 Ω. temperature specified above for curves A and B.
6 Package and PCB thermal data
6.1 PowerSSO-16 thermal data
Figure 43. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) Figure 44. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7)
Table 15. PCB properties Figure 45. Rthj-amb vs PCB copper area in open box free air condition (one channel on)
Figure 46. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
4 L ayer
Figure 47. Thermal fitting model of a double-channel HSD in PowerSSO-16 (power limitation or thermal cycling during thermal shutdown) are not triggered.
Table 16. Thermal parameters
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
7.1 PowerSSO-16 package information
Figure 48. PowerSSO-16 package dimensions
Package information
DS12566 - Rev 2 page 38/48
Table 17. PowerSSO-16 mechanical data
7.2 PowerSSO-16 packing information
Figure 49. PowerSSO-16 reel 13" Table 18. Reel dimensions
- All dimensions are in mm.
7.3 PowerSSO-16 marking information
Figure 52. PowerSSO-16 marking information engineering samples to run a qualification activity.
Revision history
Table 20. Document revision history 09-May-2018 1 Initial release. Table 10. CurrentSense.