VND5T100LAJ-E STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 38

Technical content

Datasheet sections

  • 1 Block diagram and pin description
  • 2 Electrical specifications
  • 2.1 Absolute maximum ratings
  • 2.2 Thermal data
  • 2.3 Electrical characteristics
  • 2.4 Electrical characteristics curves
  • 3 Application information
  • 3.1 GND protection network against reverse battery
  • 3.1.1 Solution 1: resistor in the ground line (RGND only)
  • 3.1.2 Solution 2: diode (DGND) in the ground line
  • 3.2 Load dump protection
  • 3.3 MCU I/Os protection
  • 3.4 Maximum demagnetization energy (V CC = 24 V)
  • 4 Package and PCB thermal data
  • 4.1 PowerSSO-12 thermal data
  • 4.2 SO-16N thermal data
  • 5 Package and packing information
  • 5.1 ECOPACK ®
  • 5.2 PowerSSO-12 mechanical data
  • 5.3 SO-16N package information
  • 6 Packing information
  • 6.1 PowerSSO-12 packing information
  • 6.2 SO-16N packing information
  • 7 Order code
  • 8 Revision history

Features

 AEC-Q100 qualified  General – Very low standby current – 3.0 V CMOS compatible input – Optimized electromagnetic emission – Very low electromagnetic susceptibility – Compliant with European directive 2002/95/EC – Fault reset standby pin (FR_Stby) – Optimized for LED application  Diagnostic functions – Proportional load current sense – High current sense precision for wide range currents – Off-state open-load detection – Output short to V CC detection – Overload and short to ground latch-off – Thermal shutdown latch-off – Very low current sense leakage  Protection – Undervoltage shutdown – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients – Protection against loss of ground and loss of V CC – Thermal shutdown – Electrostatic discharge protection Application All types of resistive, inductive and capacitive loads

Description

The VND5T100LAJ-E and VND5T100LAS-E are monolithic devices made using STMicroelectronics ® VIPower® technology, intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the devices against low energy spikes. These devices integrate an analog current sense which d elivers a current proportional to the load current. Fault conditions such as overload, ov ertemperature or short to VCC are reported via the current sense pin. Output current limitation protect s the devices in overload condition. The devices latch off in case of overload or thermal shutdown. The devices are reset by a low level pass on the fault reset standby pin. A permanent low level on the inputs and fault re set standby pin disables all outputs and sets the devices in standby mode. Max transient supply voltage V CC 58 V Operating voltage range V CC 8 to 36 V Typ on-state resistance (per ch.) R ON 100 m Current limitation (typ) ILIM 22 A Off-state supply current I S 2 µA(1) 1. Typical value with all loads connected. PowerSSO-12 SO-16N

1 Block diagram and pin description

Figure 1. Block diagram Table 1. Pin function FR_Stby pin is needed to reset the channel. The device enters in standby mode if all inputs and the FR_Stby pin are low.

Figure 2. Configuration diagram PowerSSO-12 (top view) Figure 3. Configuration diagram SO-16N (top view) Table 2. Suggested connections for unused and not connected pins

10 Kresistor

2 Electrical specifications

Figure 4. Current and voltage conventions

2.1 Absolute maximum ratings

itions above those indicated in the operating sections of this specification is not implied. Table 3. Absolute maximum ratings

2.2 Thermal data

Table 3. Absolute maximum ratings (continued) Table 4. Thermal data

2.3 Electrical characteristics

8 V < VCC < 36 V; -40°C < Tj < 150°C, unless otherwise specified. Table 5. Power section

  1. PowerMos leakage included

Table 6. Switching (VCC = 24 V; Tj = 25 °C) Table 7. Logic inputs

Figure 5. Tstandby definition Table 7. Logic inputs (continued)

Figure 6. Treset definition Table 8. Protections and diagnostics

5 V < VCC < 36 V 30 A

Table 9. Current sense (8 V < VCC < 36 V)

0.07 A < IOUT < 6 A;

Figure 7. Current sense delay characteristics

  1. Parameter guaranteed by design; it is not tested.
  2. Fault condition includes: power limitation, overtemperature and open-load in OFF-state condition.

Table 10. Open-load detection Table 9. Current sense (8 V < VCC < 36 V) (continued)

Table 11. Truth table

Table 12. Electrical transient requirements (part 1) Table 13. Electrical transient requirements (part 2)

  1. Without capacitor between V CC and GND.
  2. With 10 nF between V CC and GND.
  3. External load dump clamp, 58 V maximum, referred to ground.

Table 14. Electrical transient requirements (part 3) C All functions of the device are performed as designed after exposure to disturbance.

2.4 Electrical char acteristics curves

Figure 14. Off-state output current Figure 15. High level input current Figure 16. Input clamp voltage Figure 17. Input high level voltage Figure 18. Input low level voltage Figure 19. Input hysteresis voltage

3 Application information

Figure 25. Application schematic

3.1 GND protection network against reverse battery

3.1.1 Solution 1: resist or in the ground line (RGND only)

This solution can be used with any type of load. The following is an indication on how to select the RGND resistor. maximum rating section of the device datasheet. maximum on-state currents of the different devices. side drivers sharing the same RGND. same resistor then ST suggests Solution 2 is used (see below).

3.1.2 Solution 2: diode (D GND) in the ground line

A resistor (RGND = 4.7 kshould be inserted in p arallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the pr esence of the ground network produces a shift (600 mV) in the input threshold and in the status output values, if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds to VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/2 table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transient are present on the VCC line, the control pins are pulled negative. ST suggests that a resistor (Rprot) be inserted in line to prevent the microcontroller I/O pins from latching-up. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. -VCCpeak/Ilatchup  Rprot  (VOHC-VIH-VGND) / IIHmax Calculation example: For V CCpeak= -600 V and Ilatchup  20 mA; VOHC  4.5 V 30 k  Rprot  180 k. Recommended Rprot value is 60 k

3.4 Maximum demagnetization energy (V CC = 24 V)

Figure 26. Maximum turn-off current versus inductance

  1. Values are generated with R L =0 .

exceed the temperature specified above for curves A and B.

4 Package and PCB thermal data

4.1 PowerSSO-12 thermal data

Figure 27. PowerSSO-12 PC board

  1. Layout condition of R th and Zth measurements (Board finish thickness 1.6 mm +/- 10 %; Board double

Figure 28. Rthj-amb vs PCB copper area in open box free air condition (one channel ON)

Table 15. Thermal parameters

4.2 SO-16N thermal data

Figure 31. SO-16N PC board

  1. Layout condition of Rth and Zth measurements (B oard finish thickness 1.6 mm +/- 10%; Board double

Figure 32. Rthj-amb vs PCB copper area in open box free air condition (one channel

Table 16. Thermal parameters

5 Package and packing information

5.1 ECOPACK ®

specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

5.2 PowerSSO-12 mechanical data

Figure 35. PowerSSO-12 package dimensions

Table 17. PowerSSO-12 mechanical data

5.3 SO-16N package information

Figure 36. SO-16N package dimensions

Table 18. SO-16N mechanical data

6 Packing information

6.1 PowerSSO-12 packing information

Figure 37. PowerSSO-12 tube shipment (no suffix) Figure 38. PowerSSO-12 tape and reel shipment (suffix “TR”)

6.2 SO-16N packing information

Figure 39. SO-16N tube shipment (no suffix) Figure 40. SO-16N tape and reel shipment (suffix “TR”)

7 Order code

Table 19. Device summary

8 Revision history

Table 20. Document revision history 25-Jun-2012 1 Initial release. 18-Sep-2013 2 Updated disclaimer. 30-Apr-2014 3 Added SO-16N package and related details. 23-Aug-2016 5 Added indication of AEC-Q100 qualification in Features. Updated Figure 3: Configuration diagram SO-16N (top view).