VND5050J-E_V01 STM | Alldatasheet
Document overview
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- PDF pages: 37
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 2 Electrical specifications
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Electrical characteristics
- 2.4 Electrical characteristics curves
- 3 Application information
- 3.1 GND protection network against reverse battery
- 3.1.1 Solution 1: resistor in the ground line (RGND only)
- 3.1.2 Solution 2: a diode (DGND) in the ground line
- 3.2 Load dump protection
- 3.3 Microcontroller I/Os protection
- 3.4 Open-load detection in off-state
- 4 Package and PCB thermal data
- 4.1 PowerSSO-12™ thermal data
- 4.2 PowerSSO-24™ thermal data
- 5 Package and packing information
- 5.1 ECOPACK ® packages
- 5.2 PowerSSO-12™ package information
- 5.3 PowerSSO-24™ package information
- 5.4 PowerSSO-12™ packing information
- 5.5 PowerSSO-24™ packing information
- 6 Revision history
Features
■ Main – Inrush current active management by power limitation – Very low standby current – 3.0 V CMOS compatible input – Optimized electromagnetic emission – Very low electromagnetic susceptibility – In compliance with the 2002/95/EC European directive ■ Diagnostic functions – Open drain status output – On-state open load detection – Off-state open load detection – Thermal shutdown indication ■ Protections – Undervoltage shutdown – Overvoltage clamp – Output stuck to V CC detection – Load current limitation – Self limiting of fast thermal transients – Protection against loss of ground and loss of VCC – Thermal shutdown – Reverse battery protection (see Figure 28) – Electrostatic discharge protection
Applications
■ All types of resistive, inductive and capacitive loads
Description
The VND5050K-E and VND5050J-E are monolithic devices made using STMicroelectronics VIPower M0-5 technology. they are intended for driving resistive or inductive loads with one side connected to ground. Active V CC pin voltage clamp protects the devices against low energy spikes (see ISO7637 transient compatibility table). The devices detect open load condition both in on and off-state, when STAT_DIS is left open or driven low. Output shorted to V CC is detected in the off-state. When STAT_DIS is driven high, STATUS pin is in high impedance state. Output current limitation protects the devices in overload condition. In case of long overload duration, the devices limit the dissipated power to a safe level up to thermal shutdown intervention. Thermal shutdown with automatic restart allows the devices to recover normal operation as soon as fault conditions disappear. Max supply voltage V CC 41 V Operating voltage range V CC 4.5 to 36 V Max on-State resistance (per ch.) R ON 50 mΩ Current limitation (typ) I LIMH 18 A Off-state supply current I S 2µ A(1) 1. Typical value with all loads connected. PowerSSO-24 PowerSSO-12 Table 1. Device summary
Table 8. Status pin (V
1 Block diagram and pin description
Figure 1. Block diagram Table 2. Pin function STATUSn Open drain digital diagnostic pin. STAT_DIS Active high CMOS compatible pin, to disable the STATUS pin.
Figure 2. Configuration diagram (top view) Table 3. Suggested connections for unused and not connected pins
2 Electrical specifications
Figure 3. Current and voltage conventions Note: V Fn = VOUTn - VCCn during reverse battery condition.
2.1 Absolute maximum ratings
and other relevant quality document. Table 4. Absolute maximum ratings
2.2 Thermal data
2.3 Electrical characteristics
8V < VCC< 3 6V ; - 4 0° C < Tj<150 °C, unless otherwise specified. Table 4. Absolute maximum ratings (continued) Table 5. Thermal data Table 6. Power section
- PowerMOS leakage included.
Table 7. Switching (V CC = 13V; Tj = 25°C) Table 8. Status pin (V SD=0V) Table 6. Power section (continued)
Figure 4. Status timings Table 11. Logic input
Figure 5. Switching characteristics Table 12. Truth table
- If the V CSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
- The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge.
- The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
Figure 6. Output voltage drop limitation Table 13. Electrical transient requirements (part 1/3) Table 14. Electrical transient requirements (part 2/3)
- The above test levels must be considered referred to V CC = 13.5V except for pulse 5b.
- Valid in case of external load dum p clamp: 40V maximum referred to ground.
Table 15. Electrical transient requirements (part 3/3) C All functions of the device are performed as designed after exposure to disturbance.
Figure 7. Waveforms
2.4 Electrical characteristics curves
Figure 8. Off-state output current Figure 9. High level input current Figure 10. Input clamp voltage Figure 11. Input high level Figure 12. Input low level Figure 13. Input hysteresis voltage
Figure 26. High level STAT_DIS voltage Figure 27. Low level STAT_DIS voltage
3 Application information
Figure 28. Application schematic Note: Channel 2 has the same internal circuit as channel 1.
3.1 GND protection network against reverse battery
3.1.1 Solution 1: resistor in the ground line (R GND only)
This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. maximum rating section of the device datasheet. maximum on-state currents of the different devices.
VND5050J-E / VND5050K-E Application information Doc ID 12266 Rev 7 21/37 If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2 Solution 2: a diode (D GND) in the ground line
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (≈600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.2 Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 Microcontroller I/Os protection
If a ground protection network is used and negative transient are present on the V CC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of μC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of μC I/Os. -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHμC ≥ 4.5V 5kΩ ≤ Rprot ≤ 180kΩ Recommended values: Rprot =10kΩ.
3.4 Open-load detection in off-state
Off-state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1. no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT=(VPU/(RL+RPU))RL<VOlmin. 2. no misdetection when load is disconnected: in this case the V OUT has to be higher than VOLmax; this results in the following condition RPU<(VPU–VOLmax)/IL(off2).
Figure 29. Open-load detection in off-state
Figure 30. Maximum turn-off current versus inductance (for each channel)
4 Package and PCB thermal data
4.1 PowerSSO-12™ thermal data
Figure 31. PowerSSO-12™ PC board Copper areas: from minimum pad lay-out to 8cm2). Figure 32. R thj-amb vs PCB copper area in open box free air condition (one channel
Table 16. PowerSSO-12™ thermal parameters
4.2 PowerSSO-24™ thermal data
Figure 35. PowerSSO-24™ PC board Figure 36. R thj-amb vs PCB copper area in open box free air condition (one channel
Table 17. PowerSSO-24™ thermal parameters
5 Package and packing information
5.1 ECOPACK ® packages
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
5.2 PowerSSO-12™ package information
Figure 39. PowerSSO-12™ package dimensions
Table 18. PowerSSO-12™ mechanical data
5.3 PowerSSO-24™ package information
Figure 40. PowerSSO-24™ package dimensions Table 19. PowerSSO-24™ mechanical data
Table 19. PowerSSO-24™ mechanical data (continued)
5.4 PowerSSO-12™ packing information
Figure 41. PowerSSO-12™ tube shipment (no suffix) Figure 42. PowerSSO-12™ tape and reel shipment (suffix “TR”)
5.5 PowerSSO-24™ packing information
Figure 43. PowerSS0-24™ tube shipment (no suffix) Figure 44. PowerSSO-24™ tape and reel shipment (suffix “TR”)
6 Revision history
Table 20. Document revision history 30-Mar-2006 1 Initial release. 11-Jan-2007 2 Minor formatting changes. Reformatted and restructured. Contents and lists of tables and figures added. Table 4: Absolute maximum ratings: EMAX entries updated. channel HSD in PowerSSO-24™ : added notes. Features table updated: ILIMH changed from 19 to 18A. box free air condition (one channel on). junction ambient single pulse (one channel on). R3 value changed from 7 to 4 °C/W. Figure 40: PowerSSO-24™ package dimensions . – Added O, Q, S, T and U rows. 23-Sep-2013 7 Updated Disclaimer.