Double channel high side driver with analog current sense for automotive applications
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 37
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 2 Electrical specifications
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Electrical characteristics
- 2.4 Electrical characteristics curves
- 3 Application information
- 3.1 GND protection network against reverse battery
- 3.1.1 Solution 1: resistor in the ground line (RGND only)
- 3.1.2 Solution 2: diode (DGND) in the ground line
- 3.2 Load dump protection
- 3.3 Microcontroller I/Os protection
- 4 Package and PCB thermal data
- 4.1 PowerSSO-12™ thermal data
- 4.2 PowerSSO-24™ thermal data
- 5 Package and packing information
- 5.1 ECOPACK ® packages
- 5.2 PowerSSO-12™ package information
- 5.3 PowerSSO-24™ package information
- 5.4 PowerSSO-12™ packing information
- 5.5 PowerSSO-24™ packing information
- 6 Revision history
Features
■ Main – Inrush current active management by power limitation – Very low standby current – 3.0 V CMOS compatible input – Optimized electromagnetic emission – Very low electromagnetic susceptibility – In compliance with the 2002/95/ec european directive ■ Diagnostic functions – Proportional load current sense – High current sense precision for wide range currents – Current sense disable – Thermal shutdown indication – Very low current sense leakage ■ Protections – Undervoltage shutdown – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients – Protection against loss of ground and loss of V CC – Thermal shutdown – Reverse battery protection (see Application schematic on page 21) – Electrostatic discharge protection
Applications
■ All types of resistive, inductive and capacitive loads ■ Suitable as LED driver
Description
The VND5050AJ-E, VND5050AK-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the current sense pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shutdown intervention. Thermal shutdown with automatic restart allows the device to recover normal operation as soon as fault condition disappears. Max transient supply voltage V CC 41 V Operating voltage range V CC 4.5 to 36 V Max on-state resistance (per ch.) R ON 50 mΩ Current limitation (typ) I LIMH 18 A Off-state supply current I S 2µ A(1) 1. Typical value with all loads connected Table 1. Device summary
Table 10. Current sense (8V<V
1 Block diagram and pin description
Figure 1. Block diagram Table 2. Pin function CS_DIS Active high CMOS compatible pin, to disable the current sense pin.
Figure 2. Configuration diagram (top view) Table 3. Suggested connections for unused and not connected pins
10 KΩ resistor
2 Electrical specifications
Figure 3. Current and voltage conventions Note: V Fn = VOUTn - VCC during reverse battery condition.
2.1 Absolute maximum ratings
and other relevant quality document. Table 4. Absolute maximum ratings
2.2 Thermal data
2.3 Electrical characteristics
8V < VCC< 3 6V ; - 4 0° C < Tj<150 °C, unless otherwise specified. Table 4. Absolute maximum ratings (continued) Table 5. Thermal data Table 6. Power section
- PowerMOS leakage included.
Table 7. Switching (V CC = 13V; Tj = 25°C) Table 8. Logic input Table 6. Power section (continued)
Table 9. Protections and diagnostics (1)
- To ensure long term reliability under heavy overload or short circuit conditions, protection and related
abnormal conditions, this software must limit the duration and number of activation cycles. Table 10. Current sense (8V<V CC<16V) Table 8. Logic input (continued)
Table 10. Current sense (8V<V CC<16V) (continued)
Figure 4. Current sense delay characteristics
- Parameter guaranteed by design; it is not tested.
Figure 5. Delay response time between rising edge of output current and rising
Table 12. Electrical transient requirements (part 1/3)
- The above test levels must be considered referred to V CC = 13.5V except for pulse 5b.
Table 13. Electrical transient requirements (part 2/3)
- The above test levels must be considered referred to V CC = 13.5V except for pulse 5b.
- Valid in case of external load dum p clamp: 40V maximum referred to ground.
Table 14. Electrical transient requirements (part 3/3) C All functions of the device are performed as designed after exposure to disturbance. disturbance and cannot be returned to proper operation without replacing the device.
Figure 10. Waveforms
2.4 Electrical characteristics curves
Figure 11. Off-state output current Figure 12. High level input current Figure 13. Input clamp voltage Figure 14. Input high level Figure 15. Input low level Figure 16. Input hysteresis voltage
3 Application information
Figure 26. Application schematic Note: Channel 2 has the same internal circuit as channel 1.
3.1 GND protection network against reverse battery
3.1.1 Solution 1: resistor in the ground line (R GND only)
This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. maximum rating section of the device datasheet. maximum on-state currents of the different devices.
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2 Solution 2: diode (D GND) in the ground line
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (≈600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.2 Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 Microcontroller I/Os protection
If a ground protection network is used and negative transient are present on the V CC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os. CCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V 5kΩ ≤ Rprot ≤ 180kΩ. Recommended values: Rprot =10kΩ, CEXT=10nF.
Figure 27. Maximum turn-off current versus inductance (for each channel)
4 Package and PCB thermal data
4.1 PowerSSO-12™ thermal data
Figure 28. PowerSSO-12™ PC board Copper areas: from minimum pad lay-out to 8 cm2). Figure 29. R thj-amb vs PCB copper area in open box free air condition (one channel
Table 15. PowerSSO-12™ thermal parameter
4.2 PowerSSO-24™ thermal data
Figure 32. PowerSSO-24™ PC board Figure 33. R thj-amb vs PCB copper area in open box free air condition (one channel
Table 16. PowerSSO-24™ thermal parameter
5 Package and packing information
5.1 ECOPACK ® packages
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
5.2 PowerSSO-12™ package information
Figure 36. PowerSSO-12™ package dimensions
Table 17. PowerSSO-12™ mechanical data
5.3 PowerSSO-24™ package information
Figure 37. PowerSSO-24™ package dimensions Table 18. PowerSSO-24™ mechanical data
Table 18. PowerSSO-24™ mechanical data (continued)
5.4 PowerSSO-12™ packing information
Figure 38. PowerSSO-12™ tube shipment (no suffix) Figure 39. PowerSSO-12™ tape and reel shipment (suffix “TR”)
5.5 PowerSSO-24™ packing information
Figure 40. PowerSS0-24 TM tube shipment (no suffix) Figure 41. PowerSSO-24 TM tape and reel shipment (suffix “TR”)
6 Revision history
Table 19. Document revision history 30-Mar-2006 1 Initial release. 14-Apr-2006 2 PowerSSO-24 dimensions table update. Table 4: corrected EMAX value. Table 10: added dk1/k1, dk2/k2, dk3/k3, ΔtDSENSE2H. HSD in PowerSSO-24™ : added notes. – changed t DSENSE2H max value from 300 µs to 250µs. air condition (one channel on). ambient single pulse (one channel on). R3 value changed from 7 to 4 °C/W. changed IOL test condition from VIN = 0V to VIN = 5V. Updated Figure 37: PowerSSO-24™ package dimensions . 23-Sep-2013 10 Updated Disclaimer.