VN9E30FTR

VN9E30F STM | Alldatasheet

Document overview

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• PDF pages: 97

Technical content

Datasheet sections

• 1 Block diagram and pin description
• 2 Functional description
• 2.1 Device interfaces
• 2.2 Operating modes
• 2.2.1 Startup transition phase
• 2.2.2 Reset mode
• 2.2.3 Fail-safe mode
• 2.2.4 Normal mode
• 2.2.5 Standby mode
• 2.2.6 Sleep mode
• 2.2.7 Sleep mode
• 2.2.8 Battery undervoltage mode
• 2.2.9 Limp-home mode
• 3 Protections
• 3.1 Pre-warning
• 3.2 Junction overtemperature (OT)
• 3.3 Power limitation (PL)
• 4 SPI functional description
• 4.1 SPI communication
• 4.1.1 Signal description
• 4.1.2 Connecting to the SPI bus
• 4.1.3 SPI mode
• 4.2 SPI protocol
• 4.2.1 SDI, SDO format
• 4.2.2 Operating code definition
• 4.2.3 Special commands
• 4.3 Register map
• 4.3.1 Global Status byte description
• 4.3.2 RAM
• 4.3.3 ROM
• 4.3.4 SPI modes
• 4.4 Outputs control
• 4.4.1 Procedure to turn on the outputs in PWM operations
• 4.4.2 OTP programming
• 4.4.3 Procedure to turn on the outputs with the direct input DIx

Features

Channel VCC RON typ. ILIMH typ. 0-5 28 V 30 mΩ 35 A

• AEC-Q100 qualified
• General – Extremely low voltage operation for deep cold cranking applications (compliant with LV124, revision 2013) – Integrated PWM engine with independent phase shift and frequency generation (for each channel) – 24-bit ST-SPI for full diagnostics and digital current sense feedback – Integrated 10-bit ADC for digital current sense – Programmable bulb/LED mode for all channels – Advanced limp-home functions for robust fail-safe system – Very low standby current – Optimized electromagnetic emissions – Very low electromagnetic susceptibility – Control through direct inputs and/or SPI – Compliant with European directive 2002/95/EC
• Diagnostics functions – Digital proportional load current sense – Synchronous diagnostics of overload and short-to-GND, output shorted to VCC and OFF-state open-load events – Programmable case overtemperature warning
• Protection – Two-level load current limitation – Self-limiting of fast thermal transients – Undervoltage shutdown – Overvoltage clamp – Latch-off or programmable time-limited auto-restart (power limitation and overtemperature shutdown) – Load dump protected – Protection against loss of ground QFN 6x6 Product status link VN9E30F Product summary Order code VN9E30FTR Package QFN 6X6 Packing Tape and reel 6-channel high-side driver with 24-bit SPI interface for automotive applications VN9E30F Datasheet DS12745 - Rev 5 - April 2025 For further information, contact your local STMicroelectronics sales office.

Description

The VN9E30F is a device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads directly connected to ground. The device is protected against voltage transient on the VCC pin (see ISO7637 transient compatibility table). Programming, control and diagnostics are implemented via the SPI bus. A digital current sense feedback for each channel is provided through an integrated 10-bit ADC with 0.1% of FSR. Dedicated trimming bits allow to adjust the ADC reference current. The device is equipped with 6 outputs controllable via SPI or with the 2-OTP assignable direct inputs. The device detects open-load in OFF-state conditions. Real time diagnostics is available through the SPI bus (open-load, output short to VCC, overtemperature, communication error, power limitation or latch off). Output current limitation protects the device in an overload condition. The device can limit the dissipated power to a safe level up to thermal shutdown intervention. Thermal shutdown can be configured as latched off or programmable time-limited auto-restart. The device enters a limp home mode in case of loss of digital supply (VDD), reset of digital memory or watchdog monitoring time-out event. In limp home mode, each output is set according to the programmed register to be always OFF or according to the 2x direct inputs pins. VN9E30F DS12745 - Rev 5 page 2/97

1 Block diagram and pin description

Figure 1. Block diagram Figure 2. Connection diagram (top view) *: Electrically connected to TAB. Those pins are intended for thermo-mechanical purposes only. They have to be soldered, but must be electrically isolated at PCB level.

Table 1. Pin functionality description This is the backside TAB and is the direct connection to drain Power MOSFET switches.

17 GND

This pin serves as the ground connection for the logic part of the device. combination with the relevant SPI OUTx Control bit in Normal mode. It is the direct connection to the source Power MOSFET switch No. 0. It is the direct connection to the source Power MOSFET switch No. 1. It is the direct connection to the source Power MOSFET switch No. 2. It is the direct connection to the source Power MOSFET switch No. 3. It is the direct connection to the source Power MOSFET switch No. 4. It is the direct connection to the source Power MOSFET switch No. 5.

12 CSN

Chip select not (active low). It is the selection pin of the device. It is a CMOS compatible input.

13 SCK

It is a CMOS compatible input.

14 SDI

Transfers data to be written serially into the device on SCK rising edge.

15 SDO

Transfers data serially out of the device on SCK falling edge.

16 VDD

DC supply input for the digital control part and SPI interface. 3.3 V and 5 V compatible, this is the input of the internal Voltage Regulator.

11 PWM_CLK

4xPWM divider ratios: from 1/512 to 1/4096.

2 Functional description

2.1 Device interfaces

• SPI: bi-directional interface, accessing RAM/ROM registers (CSN, SCK, SDI, SDO)
• DIx: input pins for outputs control while device is in Fail Safe mode, Standby mode or Reset mode (usable also in Normal mode according to "Direct Input Enable Control Register" - DIENCR, setting)
• VDD: 5 V supply or 3.3 V supply. The internal regulator block which delivers internal logic supply voltage from Vdd input is able to handle both 3.3 V and 5 V. VN9E30F Functional description DS12745 - Rev 5 page 5/97

2.2 Operating modes

• Reset mode
• Fail-safe mode
• Normal mode
• Standby mode
• Sleep mode 1
• Sleep mode 2
• Battery undervoltage mode The reset mode, the fail-safe mode and the sleep mode 1 are combined into the limp-home mode. In this mode the chip is able to operate without the connection to the SPI. All transitions between the states in limp-home mode are driven by VDD and DIx. The outputs are controlled by the direct inputs DIx according to the internally programmed outputs assignment. By default, DI0 drives OUTPUT0,5 , DI1 drives OUTPUT1,2,3,4.

Table 2. Operating modes

• VCC > VUSD: reset
• (VDD > VDD_POR_ON) and (VCC > VUSD): fail-safe
• Outputs: OFF
• SPI: inactive
• Registers: reset values
• Diagnostics: not available
• Reset bit = X Reset (limp-home mode)
• Startup mode: VCC > VUSD
• Sleep 1: • DIx low to high
• Any other mode: VDD < VDD_POR_OFF
• All DIx low: sleep 1
• VDD > VDD_POR_ON: fail-safe
• Outputs: according to DIx
• SPI: inactive
• Registers: reset values
• Diagnostics: not available
• Reset bit = X Sleep 1 (limp-home mode) Reset: all DIx = 0
• VDD > VDD_POR_ON: fail-safe
• DIx low to high: reset
• Outputs: OFF
• SPI: inactive
• Registers: reset values
• Diagnostics: not available
• Low supply current from VCC
• Reset bit = X Fail-safe (limp-home mode)
• Reset or sleep 1: VDD > VDD_POR_ON
• Standby or sleep 2: CSN low for t > tstdby_out
• Normal: EN = 0 or WDTB toggling timeout or SW-reset
• VDD < VDD_POR_OFF: reset
• SPI sequence 1. UNLOCK = 1 2. GOSTBY = 0 and EN = 1: normal
• SPI sequence 1. UNLOCK = 1 2. GOSTBY = 1 and EN = 0: standby
• Outputs: according to DIx
• SPI: active
• Registers: read/write possible, cleared if entered after SW reset
• Diagnostics: SPI possible, ADC conversion possible only in asynchronous mode
• Reset bit = 1 if entered after SW reset or POR, else reset bit = 0 VN9E30F Functional description DS12745 - Rev 5 page 6/97

Operating mode Entering conditions Leaving conditions Characteristics Normal

• Fail-safe: SPI sequence 1. UNLOCK = 1 2. GOSTBY = 0 and EN = 1
• VDD < VDD_POR_OFF: reset
• SPI sequence 1. UNLOCK = 1 & EN = 1 2. GOSTBY = 1 and EN = 0: standby
• EN = 0 or WDTB time-out or SW reset: fail-safe
• Outputs: according to SPI register settings and/or DIx
• SPI: active
• Registers: read/write is possible
• Diagnostics: SPI and ADC conversion in all modes (sampled and asynchronous) are possible
• Regular toggling of WDTB is necessary within timeout period tWDTB
• Reset bit = 0 Standby
• Normal: SPI sequence 1. UNLOCK = 1 & EN = 1 2. GOSTBY = 1 and EN = 0
• Fail-safe: SPI sequence 1. UNLOCK = 1 2. GOSTBY = 1 and EN = 0
• Sleep 2: DIx low to high
• VDD < VDD_POR_OFF: reset
• CSN low for t > tstdby_out: fail-safe
• All DIx low: sleep 2
• Outputs: according to DIx
• SPI: inactive
• Registers: frozen
• Diagnostics: not available
• Low supply current from VDD
• CSN: High
• Reset bit = 0 Sleep 2 Standby: all DIx = 0
• VDD < VDD_POR_OFF: reset
• CSN low for t > tstdby_out: fail-safe
• DIx low to high: standby
• Outputs: OFF
• SPI: inactive
• Registers: frozen
• Diagnostics: not available
• Low supply current from VDD and VCC
• CSN: high
• Reset bit = 0 Battery undervoltage (this is not an operating mode) Any mode: VCC < VUSD VCC > VUSD + VUSDhyst: back to last mode
• Outputs: OFF and independent from DIx and SPI
• SPI: as the last mode
• Reset bit: as the last mode VN9E30F Functional description DS12745 - Rev 5 page 7/97

Figure 3. Device state diagram

2.2.1 Startup transition phase

This is not an operation mode but a transition step to Reset operation mode from the power-ON. In this phase, neither digital supply voltage VDD nor VCC are available (VDD < VDD_POR_ON and VCC < VUSD). This phase has not to be confused with Undervoltage mode where also the power supply is not available (VCC < VUSD) after an operation mode. The device leaves this phase to Reset mode as soon as VCC > VUSD. In case (VCC < VUSD) but (VDD > VDD_POR_ON) then the device leaves this phase to Fail-Safe-Mode.

2.2.2 Reset mode

The device is in limp-home state. Reset mode is entered after startup but also each time the digital supply voltage VDD falls below VDD_POR_OFF (VDD < VDD_POR_OFF and VCC > VUSD). The outputs are controlled by the direct inputs DIx according to internally programmed outputs assignment. At least one DIx is in logic high. The SPI is inactive (no read/write possible) and the diagnostics are not available. The registers have the reset values. The device leaves this mode only if VDD > VDD_POR_ON or all DIx go low. The reset bit inside the global status byte is unreadable since the SPI is inactive (for more information refer to the Section 4.3.1: Global Status byte description). The diagnostics is not available, but the protections are fully functional. In case of overtemperature or power limitation, the outputs work in unlimited autorestart. The device enters reset mode under three conditions:

• Automatically during startup
• If it is in any other mode and if VDD falls below VDD_POR_OFF
• If it is in sleep mode 1, and if one input DIx is set to 1 The device exits reset mode under two conditions:
• If VDD rises above VDD_POR_ON, the device enters fail-safe mode
• If all inputs DIx are 0, the device enters sleep mode 1.

2.2.3 Fail-safe mode

The device is in limp-home state. The digital supply voltage VDD is available. (VDD > VDD_POR_ON) and the SPI registers are active (SPI read/write). In fail-safe mode, the digital current sense is available only in asynchronous mode and the digital fault diagnostics is available through the SPI bus. The outputs are controlled by the direct inputs DIx regardless of the SPI commands. The registers are cleared to their reset value if fail-safe is entered through a software reset. The reset bit is 1 if the last state was reset mode or the last command was a software reset and it is reset to 0 after the first SPI access (for more information refer to Section 4.3.1: Global Status byte description). The protections are fully functional. In case of overtemperature or power limitation, the outputs work in unlimited autorestart. The device exits fail-safe mode under five conditions:

• If it is in reset mode or in sleep mode 1 and VDD rises above VDD_POR_ON (VDD > VDD_POR_ON)
• If it is in standby mode or in sleep mode 2 and CSN is low for t > tstdby_out
• If it is in normal mode and bit EN is cleared
• If it is in normal mode and WDTB is not toggled within tWDTB (watchdog timeout)
• If it is in normal mode and the SPI sends a software reset The device exits fail-safe mode under three conditions:
• If the SPI sends the go to normal mode sequence, the device enters normal mode: – In a first communication set bit UNLOCK = 1 – In the consecutive communication set bit GOSTBY = 0 and bit EN = 1 This mechanism avoids entering the normal mode unintentionally. VN9E30F Functional description DS12745 - Rev 5 page 9/97

• If the SPI sends the go to standby mode sequence, the device enters standby mode: – In a first communication set bit UNLOCK = 1 – In the consecutive communication set bit GOSTBY = 1 and bit EN = 0 This mechanism avoids entering the standby mode unintentionally.
• If VDD falls below VDD_POR_OFF, the device enters reset mode. Transition to fail-safe mode from normal mode, using the SPI register Only one frame is needed: Write “CTRL” 0x0001.

Table 3. Frame 1 (write CTRL 0x0001) reserved ROM address 0x3F. This is the equivalent of sending a 0xFF command. Only one frame is needed: read “ROM” 0x3F. Table 4. Frame 1: read (ROM) 0x3F 0x--

1. X: do not care. At least one of these bits must be zero, as 0xFFFF frame is not allowed.

The entry to the fail-safe mode can occur due to the CSN timeout.

• Removing the cause of the CSN stuck
• Toggling the CSN pin for a min tSHCH (time to release the SDO line), see parameter in Table 48. Dynamic characteristics.
• Sending the SPI frames If the above procedure is not respected, the first SPI frame is rejected and the state transition failed. VN9E30F Functional description DS12745 - Rev 5 page 10/97

2.2.4 Normal mode

Outputs can be driven by SPI commands or a combination of SPI command and direct inputs DIx. the watchdog timeout period tWDTB (see Table 48. Dynamic characteristics). Diagnosis and current sense are available through the SPI bus (digital). The protections are fully functional. The outputs can be set to latch-off or programmable time-limited autorestart.

• In time-limited autorestart, the outputs are switched on again automatically after an overtemperature or power limitation event within the limited programmed time frame (refer to Section 6.2: Blanking window values).
• In latch mode, the relevant status register has to be cleared to switch the outputs on again (refer to Section 6.2: Blanking window values). The device enters normal mode under one condition:
• If it is in fail-safe mode and the SPI sends the go to normal mode sequence: – In a first communication set bit UNLOCK = 1 – Write “CTRL” 0x4000; – In the consecutive communication set bit GOSTBY = 0 and bit EN = 1 – Write “CTRL” 0x8000; Transition from fail-safe mode to normal mode is performed by two special SPI sequences.
• Frame 1: Write “CTRL” 0x4000
• Frame 2: Write “CTRL” 0x8000

Table 5. Frame 1 (Write CTRL 0x4000) Table 6. Frame 2 (Write CTRL 0x0800)

• If VDD falls below VDD_POR_OFF, the device enters reset mode.
• If the SPI sends the go to standby sequence, the device enters standby mode: – In a first communication set UNLOCK = 1 – In the consecutive communication set GOSTBY = 1 and EN = 0 VN9E30F Functional description DS12745 - Rev 5 page 11/97

This mechanism avoids entering standby mode unintentionally.

• If the SPI clears the EN bit (EN = 0), the device enters fail-safe mode.
• Watchdog time out: If WDTB is not toggled within the monitoring timeout period tWDTB, the device enters fail-safe mode.
• If the SPI sends a software reset command (command byte = 0xFFh), all registers are cleared and the device enters fail-safe mode.

2.2.5 Standby mode

The device is in the low consumption state of the digital part. The outputs are controlled by the direct inputs DIx only. The current from VDD is nearly 0. the SPI registers are frozen to their last state before entering standby mode). During standby mode, the above conditions are kept if at least one DIx in logic high. The CSN is inactive in high state (independent of MCU). The diagnostics is not available. The protections are fully functional. The outputs are set to unlimited autorestart mode.

• If it is in fail-safe mode and the SPI sends the go to standby sequence: – In a first communication set UNLOCK = 1 – In the consecutive communication set GOSTBY = 1 and EN = 0 This mechanism avoids entering standby mode unintentionally.
• If it is in normal mode and the SPI sends the go to standby sequence: – In a first communication set UNLOCK = 1 – In the consecutive communication set GOSTBY = 1 and EN = 0 This mechanism avoids entering standby mode unintentionally.
• If it is in sleep mode 2, and one input DIx is set to one. The device exits standby mode under three conditions:
• If VDD falls below VDD_POR_OFF, the device enters reset mode.
• If CSN is low for t > tstdby_out, the device wakes up. As the device is in fail-safe mode, the outputs are controlled through DIx pins, the ADC conversion is possible only in asynchronous mode and the digital diagnostics is available through the SPI bus.
• If all direct inputs DIx are 0, the device enters sleep mode 2 resulting in minimal supply current from VCC and VDD. Transition from fail-safe-mode to standby mode using SPI: two frames needed.
• Frame 1: write “CTRL” 0x4000
• Frame 2: write “CTRL” 0x8000

Table 7. Frame 1 (write CTRL 0x4000)

Table 8. Frame 2 (write CTRL 0x8000)

• Frame 1: write “CTRL” 0x4801
• Frame 2: write “CTRL” 0x8000

Table 9. Frame 2 (write CTRL 0x4801) Table 10. Frame 2 (write CTRL 0x8000)

2.2.6 Sleep mode 1

The device is in limp-home state. The device has very low consumption for both digital and power parts. Current consumption from the digital part is nearly zero and the current consumption on VCC is supply current in sleep mode 1. The digital supply voltage VDD is not available (VDD < VDD_POR_OFF) and SPI is inactive (the read and write functions are not possible and all registers are cleared and have the reset values).

• The diagnostics is not available.
• The output stages are all off.
• Protections are inactive. The device enters sleep mode 1 under one condition:
• If from reset mode, all direct inputs DIx are going low. The device exits sleep mode 1 under two conditions:
• If VDD rises above VDD_POR_ON, the device enters fail-safe mode.
• If one of the inputs DIx is set to 1, the device enters reset mode.

2.2.7 Sleep mode 2

The device is in very low consumption state for both digital and power parts. Current consumption from the digital part is IDDstd and the current consumption on VCC is supply current in sleep mode 2. The digital supply voltage VDD is available (VDD > VDD_POR_ON) but SPI is not active (the read and write functions are not possible and all registers are frozen). The CSN is in inactive high state (independent of MCU). In sleep mode 2 the following limitations must be considered:

• The diagnostics is not available
• The output stages are all off
• Protections are inactive The device enters sleep mode 2 under one condition:
• If from standby mode, all direct inputs DIx are going low Sleep mode 2 can be left with three conditions:
• If VDD falls below VDD_POR_OFF, the device enters reset mode
• If CSN is low for t > tstdby_out, the device enters fail-safe mode
• If one of the inputs DIx is set to 1, the device enters standby mode

2.2.8 Battery undervoltage mode

This is not an operation mode but a transition step, where the power supply voltage is (VCC < VUSD). If the battery supply voltage VCC falls below the undervoltage shutdown threshold (VCC < VUSD) the device enters battery undervoltage mode. The CurrentSense diagnostics is not available. The output stages are off regardless of SPI status or DIx. Three different cases occur, depending on the operating mode: 1. From normal mode and from fail-safe mode: In this mode, the digital supply voltage VDD is available (VDD > VDD_POR_ON). The SPI is active and read/write functions are possible. The SPI diagnostics is available. After entering the undervoltage mode, the information about the undervoltage is saved in a flag (VCCUV) in the OUTSRx register, the SPI register contents are retained. The SPI-register reading is always possible. If VCC rises above the threshold (VUSD + VUSDhyst) the device returns to the last mode and the flag is cleared (VCCUV). If during this state VDD decreases to VDD < VDD_POR_OFF, the device is reset completely. The last operation mode information is lost. The device logic part is unpowered, therefore after increasing the supply voltage to (VCC > VUSD + VUSDhyst) the operation mode is the reset mode. If during this state the DIx is changed, the operation mode is not changed and the output state is changed accordingly after VCC recovering. VN9E30F Functional description DS12745 - Rev 5 page 14/97

1. From standby and sleep mode-2 modes:

information about the undervoltage is not saved in a flag (VCCUV). (VCC > VUSD + VUSDhyst) the operation mode is the reset mode. recovering, this new operation mode is taken into account.

1. From reset mode or Sleep-mode1:

mode, the information about the undervoltage is not saved in a flag (VCCUV). VUSDhyst), there will be a startup transition.

• Reset mode
• Sleep mode 1
• Sleep mode 2
• Standby mode

Figure 4. Battery undervoltage shutdown diagram

Figure 5. Undervoltage shutdown

2.2.9 Limp-home mode

are driven by VDD and DIx. The outputs are controlled by the direct inputs DIx. to be always OFF in the limp-home, or according to DI0 pin state or according to DI1 pin state.

• DI0 drivers OUT 0, 5
• DI1 drivers OUT 1, 2, 3, 4 For a direct entry to the limp-home mode during normal operating mode, the MCU uses the watchdog toggle bit (WDTB) or a dedicated SPI command. Changing the polarity of the WDTB within watchdog timeout (tWDTB) keeps the device in normal mode. VN9E30F Functional description DS12745 - Rev 5 page 16/97

3 Protections

3.1 Pre-warning

If the case-temperature rises above the case-thermal detection pre-warning threshold TCSD, the bit TCASE in the Global Status Byte is set. TCASE is cleared automatically when the case-temperature drops below the case- temperature reset threshold TCR.

3.2 Junction overtemperature (OT)

If the junction temperature of one channel rises above the shutdown temperature TTSD, an overtemperature event (OT) is detected. The channel is switched OFF and the corresponding bit in the address OUTSRx register - channel feedback status register (CHFBSRx) is set. Consequently, the thermal shutdown bit (bit 4) in the global status byte and the global error flag are set. Each output channel can be either set as latch-off or programmable time-limited autorestart operations in case of junction overtemperature event.

• In latched OFF operating mode, the output is switched OFF and the corresponding bit “CHLOFFSRx” in the OUTSRx register is set. If, after a time >tD_Restart , the junction temperature falls below TRS and a write command to the addressed latched OFF channel is sent (CHLOFFTCRx) the output switches ON again automatically. The action clears the corresponding bit “CHLOFFSRx” in the OUTSRx register and bit 4 in the global status byte. Bit 4 only remains stuck at logic high if another fault condition is present at the same time.
• In time limited auto-restart operating mode, if tblanking < tD_Restart see Figure 33. Normal mode - Short circuit – PBW < tD_Restart, during the programmed time, the output is switched off as described and after tD_Restart switches ON again automatically, when the junction temperature falls below the reset temperature TRS. If the junction temperature is still above TTSD after tblanking, channel is latched OFF and the corresponding bit “CHLOFFSRx” in the OUTSRx register is set with bit 4 in the global status byte. If tblanking > tD_Restart see Figure 34. Normal mode - Short circuit – PBW > tD_Restart, the output is switched OFF as described and switches ON again automatically, when the junction temperature falls below the reset temperature TRS. If junction temperature is still above TTSD after tD_Restart, the channel is latched OFF and the corresponding bit “CHLOFFSRx” in the OUTSRx register is set with bit 4 in the global status byte. VN9E30F Protections DS12745 - Rev 5 page 17/97

3.3 Power limitation (PL)

If the difference between junction temperature and case temperature (ΔT = TJ - TC) rises above the power limitation threshold ΔTPLIM, a power limitation event is detected. The corresponding bit in the OUTSRx register - channel feedback status bit (CHFBSR) is set. The channel is switched OFF and therefore the bit 4 in the global status byte is set. Each output channel can be either set as latch-off or as programmable time-limited autorestart operations in case of the power limitation event.

• In latched OFF operation, the output remains switched OFF and the corresponding bit “CHLOFFSRx” in the OUTSRx register is set, until the junction temperature falls below TR and a write command to the addressed latched OFF channel is sent (CHLOFFTCRx). The action clears the corresponding bit “CHLOFFSRx” in the OUTSRx register and bit 4 in the global status byte. Bit 4 only remains stuck at logic high if another fault condition is present at the same time.
• In time-limited auto restart, during the programed time, the output is switched off as described and switches on again automatically when the difference of junction temperature and case temperature (ΔT = TJ - TC) decreases below ΔTR. The status bit “CHLOFFSR” is latched during the OFF-state of the channel in order to allow asynchronous diagnostics and it is automatically cleared when the difference of junction temperature and case temperature (ΔT = TJ - TC) decreases below ΔTRS. After the programmed time expiration, the output remains switched OFF and acts as the latch-off mode described above. VN9E30F Protections DS12745 - Rev 5 page 18/97

4 SPI functional description

4.1 SPI communication

Input data are shifted into SDI, MSB first while output data are shifted out on SDO, MSB first.

4.1.1 Signal description

During all operations, VDD must be held stable and within the specified valid range: VDD min to VDD max. Table 11. SPI signal description change after the falling edge of Serial Clock (SCK). Serial data input SDI This input signal is used to transfer data serially into the device. It receives data to be written. Values are sampled on the rising edge of Serial Clock (SCK). falling edge of Serial Clock (SCK). option) have been shifted in.

• CSN Stuck @HIGH: – If the device is in Normal Mode, a WDTB Timeout will force the device into Fail-safe mode. The Serial Data-Out (SDO) will stay in High impedance (High Z). Any valid communication arrived after this event will be accepted by the device.
• CSN Stuck @LOW: – in this case and whatever the mode of the device, a CSN Timeout protection will be activated and force the device to release the SPI bus. Then the Serial Data-Out (SDO) will go into High impedance (High Z). A reset of the CSN Timeout (described as tSHCH parameter in Table 48. Dynamic characteristics) is activated with a transition Low to High on CSN pin (or with a Power On Reset or Software reset). With this reset, the Serial Data-Out (SDO) will be released and any valid communication will be accepted by the device. Without this reset, next communication will not be taken into account by the device.

4.1.2 Connecting to the SPI bus

devices in a normal configuration. device on the falling edge of SCK, MSB first on the first falling edge of the Chip Select (CSN).

4.1.3 SPI mode

Figure 6. Supported SPI mode

• CPOL = 0, CPHA = 0

Figure 7. Bus master and two devices in a normal configuration

4.2 SPI protocol

4.2.1 SDI, SDO format

Table 12. Command byte Table 13. Input data byte 1 Table 14. Input data byte 2 Table 22. Global status byte for more details of bit0-bit7). This byte is followed by two output data bytes (D15:D8) Table 15. Global status byte Table 16. Output data byte 1 Table 17. Output data byte 2

4.2.2 Operating code definition

The SPI interface features four different addressing modes which are listed in Table 18. Operating codes. Table 18. Operating codes and the second to the previous content of the addressed register. Figure 8. SPI write operation The read mode of the device allows to read and to check the state of any register. Incoming data are sampled on the rising edge of the serial clock (SCK), MSB first. contents are frozen during SPI communication.

Figure 11. SPI read device information

4.2.3 Special commands

and third bytes are "don't care" provided that at least one bit is zero. frame error and SPIE bit of GSB is set. Table 19. 0xFF: SW_Reset When an OpCode ‘10’ (read and clear operation) at address b’111111 is performed. Table 20. Clear all status registers (RAM access) Note: Reset value = the value of the register after a power on. Default value = the default value of the register. Currently this is equivalent to the Reset value. Cleared register = explicitly read and clear of the register, if it is not write protected.

4.3 Register map

4.3.1 Global Status byte description

The data shifted out on SDO during each communication starts with a specific byte called Global Status Byte.

Table 21. Global Status Byte (GSB) Table 22. Global status byte Flag without starting a complete communication frame as it is present directly after pulling CSN low.

6 Reset bit 1

default and kept in that state until the bit is cleared.

5 SPI Error 0

The SPIE bit is automatically set when SDI is stuck at High or Low. The SPIE is automatically cleared by a valid SPI communication. detected on any channel. The contribution of high VDS failure is maskable.

3 TCASE 0

the case-temperature reset threshold (TCR).

0 The Device Error bit is set in case when one or more channels are latched OFF

0 The Open-load at off state bit is set when an Open-load off state or an Output shorted to Vcc

4.3.2 RAM

• Init: the register is read/written during the initialization phase (single shot action)
• Continuous: the read/write/read and clear registers often accessed, applying outputs control and diagnostics
• Rare: the read/read and clear status of device registers accessed on demand (in case of failure)

Table 23. RAM memory map

of what has been written previously to this address. remains at “0” independent of the data written to these bits.

4.3.3 ROM

This memory is used for device identification. Table 24. ROM memory map

4.3.4 SPI modes

Table 25. SPI mode Table 26. SPI burst read

0 BR disabled

1 BR enabled

The burst read is implemented in this product so this bit is enabled.

The SPI data length value indicates the length of the SCK count monitor, which runs for all the accesses to the device application registers. In case a communication frame with an SCK count is not equal to the reported one, the device leads to an SPI error and the data are rejected. The frame length is specified on 3 bits in the SPI mode register located in the ROM part. The 24-bit SPI communication is implemented in this product so these bits are ‘010’. Table 27. SPI data length Data consistency check (Parity/CRC) For some devices, a Data Consistency Check is required. Therefore, either a parity-check or for very sensitive systems a CRC may be implemented. It is defined on 2 bits, in the SPI mode register located in the ROM part. A check is then applied on the incoming frame (SDI) while a calculation elaborated on one/multiple bits is done and integrated on the outgoing frame (SDO). Table 28. SPI data consistency check In case either the parity or the CRC check is implemented, it is always located at the end of the communication. The device is equipped with the parity control check. In the Tx device, the parity bit is calculated based on the first 23 bits: even number of "1" will set the parity bit to "1", whilst the odd number of "1" will set the parity bit to "0". In the Rx device, the parity bit is calculated in the same way and compared with the received one. In the case of different parity bit, the received SPI frame is discharged. VN9E30F SPI functional description DS12745 - Rev 5 page 29/97

4.4 Outputs control

Depending on the actual device mode, outputs can be controlled by the SPI register or the direct input DIx.

1. SPI register SOCR - in normal mode outputs can be turned ON/OFF, applying Bit[n] = 1/0

Table 29. Write SOCR 0x13

4.4.1 Procedure to turn on the outputs in PWM operations

Table 30. Output control truth table

0 X 0 X% OFF

0 X 1 X% PWM (1)

1 L 0 X% OFF

1 L 1 X% PWM (1)

1 H X X% PWM (1)

1. In case of DUTYCR = 100%, PWM = DC ON .

access the relevant registers and to configure them.

• Select the PWM frequency by using the 2 bits PWMFCYx;
• Select the PHASE information by using the 5 bits CHPHAx;
• Select the switching slope by using the 2 bits SLOPECRx;
• Select the channels configuration Bulb/LED by using the bit CCR;
• Select the DUTYCYCLE information by using the 10 bits of the OUTCTRCRx registers;
• Select the channel through the dedicated register “SOCR” in the channel control register.
• Select the PWM triggering mode by using the single bit PWM_TRIG of the CTRL register The PWMSYNC bit resets the internal 12 bits clock counter. This allows having a known time base and to synchronize different devices among each other. The signal on the PWM_CLK is divided internally by a factor from 4096 to 512 depending on the PWMFCY register to generate the base frequency for the output.
• PWM signal is generated by properly selecting 10 of 12 bits on the clock counter. PWM engine has a virtual 10-bit granularity except when the PWM divider is set to 512, in this case only a 9-bit granularity is possible (LSB of 10-bit generated PWM is fixed to zero). Duty cycle step can be modified with the granularity related to the 9-bit register. The duty cycle of the output signal is configured for each OUTPUTx with the OUTCTRCR register using 10 bits (MSB first).
• Programming an output duty cycle at 000h results in a 0% duty cycle that means the channel is always OFF depending on the SOCR/DIx bit setting.
• Programming an output duty cycle, at 3FFh results in a 100% duty cycle (4095/4096), that means the channel is always ON when the SOCR/DIx bit is set. – In normal mode the outputs are driven according to the SPI register setting and the INx pins (DIx in OR with SPI) if the related DIENCR bit is set. Set PWMSYNC bit in the control register “CTRL” (to synchronize the internal PWM counter to the selected channels). The internal PWM counter has a 12 bits depth, it is active whatever the state of the channels if VDD > VDD_POR_ON. The setting of the PWMSYNC bit allows resetting the PWM counter. Setting the PWM_TRIG bit in the control register “CTRL” forces the device to calculate the falling edge of the PWM window in advance compared with the end of the PWM period, while with a reset value for this bit, the rising edge of the PWM window will be calculated through a delay at the start of the PWM period.
• PWM_TRIG = 0 means channel switch on = PWM counter + phase shift counter (see examples 1 to 3)
• PWM_TRIG = 1 means channel switch off = PWM counter (max) - phase shift counter - duty cycle (see example 4) The phase shift of the output signal is configured for each OUTPUTx by internally concatenating the CHPHAx 5 bits with '00000' in order to get 10 bits. Granularity of the phase shift is 5 bits. CHPHA = 00000b means a phase shift of 0 (internal 10bit phase shift is 0x000=0000000000b), while CHPHA = 11111b results in a maximum phase shift of 31/32 =(internal 10bit phase shift is 0x3E0=0000000000b) The phase shift is relative to the base frequency of the selected channel. Thus, the exact point in time when the channel switches on also depends on the operating mode of the selected channel.

Table 31. Phase shift configuration

A change in phase/duty will be taken in account after the next zero-crossing of the PWM counter. frequency of approximately 400 kHz. In this case, the PWMCLOCKLOW bit in OUTSRx is set.

• 65% duty cycle results in a DUTYCRx register content equal to 665 = Ch (65% x 1023 = 665 - 299).
• 25% phase results in a CHPA register content equal to 8 (25% x 31 = 8), equivalent to a content of 256 = 100h for a 10 bit register.
• With an input frequency at PWM_CLK pin of 400 kHz, the output frequency is 195 Hz.

Figure 12. Resulting waveform 1

• 65% duty cycle results in a DUTYCRx register content equal to 665 = Ch (65% x 1023 = 665 - 299).
• 45% phase results in a CHPA register content equal to 14 (45% x 31 = 14), equivalent to a content of 448 = 1C0h for a 10 bit register.
• With an input frequency at PWM_CLK pin of 400 kHz, the output frequency is 390 Hz. VN9E30F SPI functional description DS12745 - Rev 5 page 32/97

• 65% duty cycle results in a DUTYCRx register content equal to 665 (65% x 1023 = 665) equivalent to a content of 299h.
• 45% phase results in a CHPA register content equal to 14 (45% x 31 = 14), equivalent to a content of 448 = 1C0h for a 10-bit register.
• With an input frequency at PWM_CLK pin of 400 kHz, the output frequency is 400/1024 = 390 Hz
• Due to PWM sampling mode on the falling edge, the PWM window has a start at 3A6h (not (299h +1C0h)) and a stop at 23Fh (not 1C0h).

Figure 15. Resulting waveform 4

4.4.2 OTP programming

Table 32. OTP memory map Note: "00" represents the default configuration. customized OTP configuration, for each channel, is possible by changing the two dedicated bits. Table 33. OTP programming direct input signal to the channel. safety level for the stored configurations and to prevent from unwanted changing. Further information about the OTP programming mode is provided in the dedicated user manual.

4.4.3 Procedure to turn on the outputs with the direct input DIx

standby, and reset modes. In normal mode, the DIx effect is ORed with SPI configuration when DIENCR bit is set. Table 34. Truth table configured in LED mode (default value is 0).

Figure 16. 6-channel direct input block diagram

4.5 Output switching slopes control

Table 35. Switching slopes

00 Standard Standard

01 Fast Fast

10 Faster Faster

11 Fastest Fastest

4.6 Control registers and Status registers

OUTCTRCRx Outputs control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED DUTYCR9 DUTYCR8 DUTYCR7 DUTYCR6 DUTYCR5 DUTYCR4 DUTYCR3 DUTYCR2 DUTYCR1 DUTYCR0 RESERVED OLOFFCR WDTB PARITY R R RW RW RW RW RW RW RW RW RW RW R RW RW R Address: 0x00h to 0x05h Type: RW Reset: 0 Description: Outputs control register [15:14] RESERVED [13:4] DUTY_CR[9:0]: set the duty cycle value. Bit 9 (MSB) - Bit 0 (LSB) [3] RESERVED [2] OLOFFCR: enables an internal pull-up current generator to distinguish between the two faults: open-load OFF-state vs the output shorted to VCC fault. 1: pull-up current generator enabled 0: pull-up current generator disabled [1] WDTB: watchdog toggle bit [0] PARITY: parity bit VN9E30F SPI functional description DS12745 - Rev 5 page 37/97

OUTCFGRx Outputs configuration register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLOPECR1 SLOPECR0 RESERVED CHPHA4 CHPHA3 CHPHA2 CHPHA1 CHPHA0 SPCR1 SPCR0 PWMFCY1 PWMFCY0 CCR DIENCR VDSMASK PARITY RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R Address: 0x08h to 0x0Dh Type: RW Reset: 0 Description: The “Output configuration register” allows setting the following important parameters for each channel:

• Switching related parameters – Switching slopes; – Phase of each channel; – PWM ratio;
• Channel configuration – Bulb/LED mode; – Control through SPI/DIx pins; – Masking the VDS control at turn-off;
• Diagnostic configuration – Set the current sampling point for the digital conversion; [15:14] SLOPECR[1:0]: Switching slope control bit 1 (MSB) and 0 (LSB) [13] RESERVED [12:8] CHPHA[4:0]: Set the Channel phase value[4:0] 00000: Resulting phase = 0/32 00001: Resulting phase = 1/32 .... 11110: Resulting phase = 30/32 11111: Resulting phase = 31/32 [7:6] SPCR[1:0]: Current sampling Point[1:0] SPCR1:0 SPCR0:0 stop mode: authorizes digital conversion to be launched just before the end of on phase of the selected channel. SPCR1:0 SPCR0:1 START mode: authorizes digital conversion to be launched at each beginning of on phase of the selected channel. SPCR1:1 SPCR0:0 CONTINUOUS mode: authorizes digital conversion during all on phase of the selected channel. SPCR1:1 SPCR0:1 FILTERED mode: authorizes digital conversion like CONTINUOUS mode with the use of low pass filter to filter data coming from the conversion. It is useful at low level output current. [5:4] PWMFCY[1:0]: PWM frequency selection[1:0] Each output has a specific ratio for its PWM functionality. This mode is defined through two dedicated bits PWMFCY1 and PWMFCY0 of OUTCFGRx registers. PWMFCY1:0 PWMFCY0:0 = PWM freq ratio: 1024 VN9E30F SPI functional description DS12745 - Rev 5 page 38/97

PWMFCY1:0 PWMFCY0:1 = PWM freq ratio: 2048 PWMFCY1:1 PWMFCY0:0 = PWM freq ratio: 4096 PWMFCY1:1 PWMFCY0:1 = PWM freq ratio: 512 When a combination is selected, the output frequency of the selected channel will be the PWM clock input frequency divided by the defined ratio. [3] CCR: set the channel configuration (Bulb-LED) 0: Bulb mode 1: LED mode [2] DIENCR: Direct input signal enable in normal mode (according to OTP allocation) Each output has an OTP programmed direct input assignment for limp-home operation. Any output can be programmed to be always OFF in the limp-home, or according to DI0 pin state or according to DI1 pin state. This programmed assignment can be read from DIOTP bits of OUTSRx status register. When DIENCR bit is set, DIx pin state assigned to the output is ORed with the SOCR/PHASE/DUTYCYCLE combination to control output state. In fail-safe, standby and reset modes applying log.1/0 to pin turns ON/OFF the associated OTP selected outputs. [1] VDSMASK: VDS detection at turn-off masking bit [0] PARITY: parity bit VN9E30F SPI functional description DS12745 - Rev 5 page 39/97

CHLOFFTCR0 Channel Latch OFF Timer Control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHLOFFTCR23 CHLOFFTCR22 CHLOFFTCR21 CHLOFFTCR20 CHLOFFTCR13 CHLOFFTCR12 CHLOFFTCR11 CHLOFFTCR10 CHLOFFTCR03 CHLOFFTCR02 CHLOFFTCR01 CHLOFFTCR00 RESERVED RESERVED RESERVED PARITY RW RW RW RW RW RW RW RW RW RW RW RW R R R R Address: 0x10h Type: RW Reset: 0 Description: The output behavior in case of power limitation or thermal shut-down is programmable, as latch-off or Time limited auto-restart (tblanking). The default mode is the latch-off one which corresponds to have 0x0h in the register. In Time limited autorestart, when the channel is turned ON, after a transition from 0 to 1 of the corresponding SOCR bit or activation through associated DIx input when DIENCR bit is set, power limitation and thermal shutdown latches are inhibited for a programmed tblanking time. See Programmable blanking window (PBW) for more details. Two Registers are used for setting the tblanking values for each channel:

• CHLOFFTCR0 for channels 2,1,0;
• CHLOFFTCR1 for channel 5,4,3. [15:12] CHLOFFTCR[23:20]: It configures the output behavior in case of power limitation for the corresponding channel 2. [11:8] CHLOFFTCR[13:10]: It configures the output behavior in case of power limitation for the corresponding channel 1. [7:4] CHLOFFTCR[03:00]: It configures the output behavior in case of power limitation for the corresponding channel 0. [3:1] RESERVED [0] PARITY: parity bit VN9E30F SPI functional description DS12745 - Rev 5 page 40/97

are inhibited for a programmed tblanking time. See Programmable blanking window (PBW) for more details.

• CHLOFFTCR0 for channels 2,1,0;
• CHLOFFTCR1 for channel 5,4,3. [15:12] CHLOFFTCR[53:50]: It configures the output behavior in case of power limitation for the corresponding channel 5. [11:8] CHLOFFTCR[43:40]: It configures the output behavior in case of power limitation for the corresponding channel 4. [7:4] CHLOFFTCR[33:30]: It configures the output behavior in case of power limitation for the corresponding channel 3. [3:1] RESERVED [0] PARITY: parity bit The blanking window duration in case of power limitation or thermal shutdown events can be set according to the following table:

Table 36. Programmable tblanking values

SOCR Channel control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED SOCR5 SOCR4 SOCR3 SOCR2 SOCR1 SOCR0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED WDTB PARITY R R RW RW RW RW RW RW R R R R R R RW R Address: 0x13h Type: RW Reset: 0 Description: The SOCR register is used to turn ON/OFF the related channel. The WDTB bit that must be toggled within tWDBT (watchdog timeout) to avoid entering in fail-safe mode. This bit is already present in the output control register and it is duplicated in the SOCR register to simplify the SPI usage. [15:14] RESERVED [13] SOCR5 bit controls output state of channel 5 1 - output enabled 0 - output disabled [12] SOCR4 bit controls output state of channel 4 1 - output enabled 0 - output disabled [11] SOCR3 bit controls output state of channel 3 1 - output enabled 0 - output disabled [10] SOCR2 bit controls output state of channel 2 1 - output enabled 0 - output disabled [9] SOCR1 bit controls output state of channel 1 1 - output enabled 0 - output disabled [8] SOCR0 bit controls output state of channel 0 1 - output enabled 0 - output disabled [7:2] RESERVED [1] Watchdog toggle bit [0] PARITY: parity bit VN9E30F SPI functional description DS12745 - Rev 5 page 42/97

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GOSTBY UNLOCK CTDTH1 CTDTH0 EN PWM_TRIG RESERVED RESERVED RESERVED LOCKEN4 LOCKEN3 LOCKEN2 LOCKEN1 LOCKEN0 PWMSYNC PARITY RW RW RW RW RW RW R R R RW RW RW RW RW W R Address: 0x14h Type: RW Reset: 0 Description: Control register [15] GOSTBY: Go to standby. It is necessary to do 2 write accesses to enter standby: 1. Write UNLOCK = 1 2. Write GOSTBY = 1 and EN = 0 [14] UNLOCK: unlock bit UNLOCK bit allows protected SPI transactions. It means that the next SPI communication will automatically clear this bit and prevent any change of protected data (like slope control or BULB/LED mode for example). As a consequence, modifying a protected data requires to set UNLOCK bit in a first communication and write the protected data during the next communication. [13:12] CTDTH[1:0]: Case thermal detection threshold. These bits allow to configure the case thermal detection of the device. Three temperature thresholds are available by programming these two bits. 1. CTDTH1:0 CTDTH0:0 = detection temperature:120 °C 2. CTDTH1:0 CTDTH0:1 = detection temperature:130 °C 3. CTDTH1:1 CTDTH0:X = detection temperature:140 °C [11] EN: enter normal mode 1: normal mode 0: fail-safe mode It is necessary to do 2 write accesses to enter normal mode: 1. Write UNLOCK = 1 2. Write EN = 1 [10] PWM_TRIG: PWM triggering mode 0: PWM trigger according to the rising edge of PWM period and phase shift configuration 1: PWM trigger according to the falling edge of PWM period and phase shift configuration [9:7] RESERVED [6:2] LOCKEN[4:0]: Protected transaction mode LOCKEN4: Lock enable for slope control SLOPECRx LOCKEN3: Lock enable for BULB/LED mode CCRx LOCKEN2: Lock enable for phase shift CHPHAx LOCKEN1: Lock enable for configurable blanking time CHLOFFTCRx LOCKEN0: Lock enable for PWM clock synchronization When the bit is set (LOCKENx = 1), it is used to have a protected transaction:

• setting UNLOCK bit
• modify the relevant configuration register When LOCKENx=0 (reset value), the related configuration registers are altered with a simple write command. VN9E30F SPI functional description DS12745 - Rev 5 page 43/97

[1] PWMSYNC: PWM clock synchronization. PWMSYNC =1 clears PWM internal counter. It automatically resets at next SPI communication [0] PARITY: parity bit VN9E30F SPI functional description DS12745 - Rev 5 page 44/97

OUTSRx Output status channels 0 to 5 register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DIENSR DIOTP1 DIOTP0 CHFBSRx VDSFSRx STKFLTRx OLPUSRx CHLOFFSRx RST SPIE PWMCLOCKLOW VCCUV RESERVED RESERVED RESERVED PARITY R R R RC RC RC R R RC RC RC R R R R R Address: 0x20h to 0x25h Type: RC Reset: 0 Description: The output status register reports the status of the selected channel based on the configuration register and in case of fault condition. [15] DIENSR: direct input status, image of associated DI logic level according to OTP allocation. [14] DIOTP1: associated DIx input description bit 1 [13] DIOTP0: associated DIx input description bit 0 [12] CHFBSRx: channel feedback status. Channel feedback status. Combination of power limitation, OT, OVERLOAD detection (VDS at turn-off). The CHFBSRx provides a logical "OR" combination of VDS (overload), PL (power limitation), OT (overtemperature) failure flags related to OUTPUTx, and it is cleared by a read and clear command. [11] VDSFSRx: VDS feedback status. This bit is ‘1’ if VDS is high at turn-off, indicative of a potential overload condition [10] STKFLTRx: output stuck to VCC/open-load off state status. [9] OLPUSRx: output pull-up generator status. [8] CHLOFFSRx: channel latch-off status. This bit is set when overload blanking time has elapsed and the channel is latched off. [7] RST: chip reset [6] SPIE: SPI error [5] PWMCLOCKLOW: PWM clock frequency too low. [4] VCCUV: VCC undervoltage [3:1] RESERVED [0] PARITY: parity bit VN9E30F SPI functional description DS12745 - Rev 5 page 45/97

ADCxSR Digital Current Sense register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RESERVED ADCxSR9 (MSB) ADCxSR8 ADCxSR7 ADCxSR6 ADCxSR5 ADCxSR4 ADCxSR3 ADCxSR2 ADCxSR1 ADCxSR0 (LSB) RESERVED SOCRx UPDTSR PARITY R R R R R R R R R R R R R R R R Address: 0x28h to 0x2Dh Type: R Reset: 0 Description: The register contains the digital value of the current flowing on the selected channel. It reports the result of the digital current conversion. It is updated according to the modes set by the two bits (SPCR1 and SPCR0) of the OUTCFGRx. [15:14] RESERVED [13:4] ADCxSR[9:0]: The 10 bit register contains the digital value of OUTPUTx current. ADCxSR9 (MSB) ADCxSR0 (LSB) [3] RESERVED [2] SOCRx: SOCR Bit controls output state of channel x. 1 - output enabled 0 - output disabled [1] UPDTSR: updated status bit. This bit is set when a value is updated and cleared when register is read. [0] PARITY: parity bit VN9E30F SPI functional description DS12745 - Rev 5 page 46/97

Description: The register contains the result of the digital conversion of the case temperature. ADC9SR[9:0]: The 10 bit register contains the digital value of case temperature sensor voltage. This bit is set when a value is updated and cleared when register is read. OTP is automatically read into registers at Reset. Table 37. OTP memory map (reserved)

5 Diagnostics

Device is capable to provide digital diagnostics information through SPI interface.

5.1 Digital current sense diagnostics

5.1.1 ADC characteristics

Figure 17. ADC characteristics and error definition

1 LSB (Ideal)

1 LSB Ideal – V DO_ADC / 1024

5.1.2 ADC operating principle

Note: The internal ADC is able to work in both normal and fail-safe conditions. the read process of dedicated RAM register. An analog multiplexer has been implemented to connect the different channels to the amplifier and ADC block. Figure 18. Conversion window generation at maximum can be sampled in the same time window.

5.1.3 Registers

• ADCxSR (address from 28h to 2Dh) - for digital Outputx current (one register x channel)
• ADC9SR (address 31h) - Digital case temperature sensor voltage sense register

Table 38. Registers

5.1.4 Synchronous, asynchronous modes

5.1.4.1 Normal mode

Table 39. Sampling mode configuration

5.1.4.2 Synchronous mode

• Sampling is done according to the PWM rising and falling edge (see Figure 21. Sequence of channels). See Table 39. Sampling mode configuration for more details about the registers configuration.
• The sampling priority will be always allocated at higher priority. Registers configuration
• SPCR10=0h: Synchronous triggered by rising edge on internal PWM. Conversion is executed on rising edge of conversion window (see Figure 21. Sequence of channels).
• ADC real sampling is managed to trigger the sampling point with margin versus falling edge.
• SPCR10=1h: Synchronous triggered by falling edge of the internal PWM signal. Conversion is executed on falling edge of conversion window (see Figure 21. Sequence of channels). Note: ADC real sampling is managed to trigger the sampling point with margin versus rising edge. VN9E30F Diagnostics DS12745 - Rev 5 page 51/97

Figure 21. Sequence of channels

5.1.4.3 Asynchronous mode

complete conversion window except the priority arbitration. Since the ADC register is continuously refreshed, its conversion priority is always lower than sampled channels. through those channels, always interrupted when higher priority synchronous sampling requests occur. conversion priority is always lower than sampled channels.

• The integrated LP filter is activated
• This component filters data coming from the ADC conversion reducing the effect of random noise coming from the analog current sense amplifier SPCR10 = 3h, SOCRx = x and DIx = high: if a channel is commanded off through SOCR, but commanded on through the direct input, the asynchronous sampling mode is forced - asynchronous with continuous sampling. The thermal case sampling has always low priority for the ADC conversion, and so it can be interrupted by any channel in simple mode. Thermal case conversion is always in asynchronous continuous mode. In fail-safe condition the ADC conversion is always in asynchronous/continuous mode.
• Conversion is executed during the complete conversion window.
• No priority management is applied, channels are converted according to their position in the stack. No interruption and no priority management are possible. In the case of multiple channels active at the same time, the conversion starts with the first one in the stack. VN9E30F Diagnostics DS12745 - Rev 5 page 52/97

Figure 22. Asynchronous with continuous sampling

5.1.4.4 Sampling concept

• PWM mode (internal engine) → All the synchronous modes are available (start, stop, continuous or filtered)
• DC mode (internal engine) → ADC works in Continuous Mode. The conversion window follows the channel control input signal – DC mode by/without DI: No difference, since this condition is equivalent to PWM with 100% of duty (the sampling will be always in continuous mode).
• PWM mode by DI (external source) → the DIx information is combined (O-red) with the channel control signal. Sampling will be executed according to the PWM mode settings. – With SPCRx=2h,3h, sampling is possible (continuous/filtered mode).

5.1.4.5 Synchronous mode in DC condition (PWM with 100% duty cycle) – equivalent to asynchronous mode

This mode is equivalent to the asynchronous mode. Table 40. ADC Configuration registers

1 X X 00 Synchronous triggered by falling edge on internal PWM Output current

1 X X 01 Synchronous triggered by rising edge of the internal PWM signal Output current

1 X X 10 Asynchronous with continuous sampling Output current

1 X X 11 Asynchronous with continuous sampling and digital LP filter Output current

5.2 Integrated LP (Progressive Average) Filter

reducing the effect of random noise coming from the analog Current Sense amplifier.

• 1st order LP filter on 16 samples
• 1st result after 1 sample with progressive averaging of 16 successive samples d ata N = d ata N − 1 ∙ 15 16 + d ata i / 16
• Continues to accumulate samples during PWM operation
• Keeps digitalized value when channel is turned off

5.3 Digital diagnostics

device. It informs about the device actual mode (normal/fail-safe). Figure 23. Status registers

5.3.1 Status registers

Table 41. Status registers Digital current sense registers. 31h ADC9SR Read Digital case temperature sensor current sense register.

5.4 Overload (VDS high voltage, overload (OVL))

overload state so that a false warning is issued. Figure 24. Diagnostics flowchart for digital overload detection in OUTSRx Register and Section 5.11: VDS feedback status bit (VDSFSR) in the OUTSRx register.

5.5 Open-load ON-state detection

5.6 Open-load OFF-state detection

open-load in OFF state/stuck to VCC event is reported. OLOFF bit in the global status register and the global status bit are not set accordingly. the bit in ON-state, it is necessary to send a Read and Clear command. the outputs control registers “OUTCTRCR”(address from 0x00 to 0x05 depending on the channel). The activated pull-up current generators are active in normal mode, in fail-safe mode, and in standby mode. register contents and hence the current generators are switched off. Figure 25. Open-load OFF-state detection Table 42. STKFLTR state

Figure 26. Diagnostics flowchart for open-load off-state respectively stuck to Vcc failure

5.7 DIENSR: direct input status bit in OUTSRx register (address from 0x20 to 0x25)

5.8 CHFBSR: Channel Feedback Status bit in OUTSRx Register

The CHFBSRx provides a logical "OR" combination of VDS (overload), PL (power limitation), OT (over temperature) failure flags related to OUTPUTx. The contributions of VDS failure flags to the channel feedback status register and Global Status Byte can be mask-able through VDSmaskx bit in OUTCFGRx registers. CHFBSRx = 1: Channel OUTPUTx on failure CHFBSRx = 0: Channel OUTPUTx no failure The bits are refreshed continuously in ON-state and latched in OFF-state. In order to clear the bit in OFF-state, it is necessary to send a Read-Clear command.

5.9 Open-load in OFF-State / Stuck to VCC Status bit “STKFLTR” in OUTSRx

This bit is set when the output voltage of the selected channel exceeds the detection threshold at turn-OFF. The STKFLTRx bit is set in OFF-state if VOUT> VOL and the tDOLOFF (turn-off delay time) is elapsed. It gives information about open load or a stuck to VCC which depends on the configuration of the OUTCTRCRx OLOFFCR bit register. The bit is continuously refreshed in OFF-state and it is latched during ON-state. In order to clear the bit in ON-state it is necessary to send a Read and Clear command. STKFLTRx=1: Open-load in OFF-state or stuck to VCC condition occurred for OUTPUTx STKFLTRx=0: No fault detected

5.10 Channels latch-off status bit (CHLOFFSR) in OUTSRx register

The CHLOFFSR bit is set as soon as there is a fault condition identified as Power-limitation or over-temperature. Latch OFF flag register. There is one bit per channel. In case that the latch-off condition occurs, the faulty channel can be reactivated after clearing the related CHLOFFSR bit through a write operation. A SW reset event clears the content of the register.

5.11 VDS feedback status bit (VDSFSR) in the OUTSRx register

This bit represents the VDS Feedback status. The device is equipped with one VDS bit per channel. The bit is set in case that an overload condition is detected on the related channel. The bit is set independently of the OT.PL. flag. The VDSFSRx bit is set if, at the instant when the channel is commanded off or is latched off, the VCC - VOUT voltage drop exceeds the VDS_OVL threshold. The bit is latched until the next turn OFF. In order to clear the bit, it is necessary to send a read and clear command. The VDSFSRx bit is set to: 1: overload event occurred for OUTPUTx 0: no fault detected Note: As the status register is not updated while CSN is low, it is possible that the update of the VDSFSR is delayed until the next time it is commanded off, if the PowerMOS is turned off during an SPI-frame. The contributions of “VDSFSR” failure flags to the channel feedback status register and Global Status Byte can be mask-able through the VDSmaskx bit in OUTCFGRx registers. VN9E30F Diagnostics DS12745 - Rev 5 page 59/97

6 Programmable blanking window (PBW)

register (CHLOFFTCR1 or CHLOFFTCR0). The MCU can keep the device in auto-restart forever artificially by refreshing the programmed blanking time.

6.1 Timer

LSBs are filled with 0xF. The 8-bit value refers to an analog timer value. Figure 27. Internal timer process limitation or overtemperature phase lasts for less than tSTEP the counter is decreased by one step. end of the timer’s step, the flag is checked. It will be reset if the event is not present. stop counting down and will reset the flag. through direct input or the SOCR register. The timer can stay with an already down-counted value for a long time. It is up to the MCU to reset it. The following figure is related to the one timer step. The actions are performed after the rising and falling edges.

Figure 28. One timer step actions

6.2 Blanking window values

• 0x0: It configures the channel in Latch-OFF mode without blanking time. Consequently, the channel will latch-off upon the first occurrence of power limitation or overtemperature event.
• 0x1 to 0xF: This value represents the time duration, it will be written by the MCU in the register (Latch-Off timer register) “CHLOFFTCRx” (Address 0x10h and 0x11h). During this time, the device is allowed to stay in power-limitation and/or over-temperature state before latching off if the “event” is still active or present. The minimum value of the timer, known as Zero, is 0x0F. When the timer reaches this value the latch-off action will be triggered The following table shows the time values written by MCU and their real value in timer register.

Table 43. Time values written by MCU and their real value in timer register

6.3 Power limitation counter

The flowchart below displays the flow of the events and states. It does not include the timer update by MCU. Figure 29. Power limitation counter flowchart

6.4 Limp-home mode

full independence of the limp-home mode operation.

6.5 Registers

For more details refer to the SPI register and Diagnostics.

• Address 0x10h - Channel Latch OFF Timer Control Register (CHLOFFTCR0)
• Address 0x11h - Channel Latch OFF Timer Control Register (CHLOFFTCR1) Two 16-bit registers (Latch-OFF timer: R/W) are used for channel behavior configuration and the timer value settings. For each channel 4 bits are used. The value is written by MCU from 0x0 to 0xF.

Figure 30. Example of behavior channel configuration

• Write command – store new value, read-back (during write command) old value equal to the timer down- counting. – Any write command will clear the flag in the latch-OFF flag register and reset the timer. – This function will be used by MCU to clear the flag in the Latch-OFF flag register, which is read only register.
• Read command – reads currently down-counted timer value. If the channel was latched due to the timer expiration, the channel is kept latched after read command.
• Channels latch-off status bit – CHLOFFSRx in OUTSRx (Address 0x20 to 0x25 depending on the channel) Each channel has one CHLOFFSR flag. In case of latch-OFF of a channel, this flag will be set and be readable by the MCU. This bit must be cleared to allow the channel to resume operation through a read/clear operation. VN9E30F Programmable blanking window (PBW) DS12745 - Rev 5 page 63/97

7 Electrical specifications

7.1 Absolute maximum ratings

rating conditions for extended periods may affect device reliability. Table 44. Absolute maximum ratings

7.2 Thermal data

Table 45. Thermal data

1. Device mounted on four-layers 2s2p PCB.

7.3 SPI electrical characteristics

Mode 1: 2.7 V < VDD < 5.5 V, -40 °C < TJ < 150 °C, unless otherwise specified. Table 46. DC characteristics Power-on shutdown threshold. Supply of digital part in shutdown.

Table 47. AC characteristics (SDI, SCK, CSN, SDO, PWM_CLK pins) - Mode 1 Table 48. Dynamic characteristics

1. Parameter specified by design, not tested in production.

Figure 31. SPI dynamic characteristics

0.2 V CC

0.8 V CC

7.4 Electrical characteristics

7 V < VCC < 28 V; –40 °C < TJ < 150 °C, unless otherwise specified. Table 49. Power section Table 50. Logic inputs (DI0,1 pins)

Table 51. Protection

1. Zthj-case x P = ΔTPLIM, Zth-case is the thermal impedance, P is the Power.
2. Parameter specified by design and evaluated by characterization, not tested in production.

Table 52. Open-load detection (7 V < VCC < 18 V)

7.5 PWM unit

2.7 V < VDD < 5.5 V; –40 °C < TJ < 150 °C, unless otherwise specified. Table 53. PWM unit pin is longer than PWM_Clk_flbk_del. the minimum value of PWM_Clk_flbk_del) this flag is never set. to substitute the external one.

7.6 BULB mode

Table 54. BULB - power section Table 55. BULB - switching (VCC = 13 V; normal switch mode)

1. see Figure 32. Switching characteristics
2. Parameter specified by design and evaluated by characterization, not tested in production.

Table 56. BULB - protection and diagnostics (7 < VCC < 19 V)

1. ILIMH, guaranteed between 7 V and 16 V, -40°C < TJ < 150°C.
2. ILIMH2, guaranteed between 16 V and 19 V, -40°C < TJ < 150°C.

Table 57. BULB - Digital current sense (7 V < VCC < 18 V, TJ = -40 °C to 150 °C)

1. Parameter specified by design and evaluated by characterization, not tested in production.

7.7 LED mode

7 V < VCC < 18 V; –40 °C < TJ < 150 °C, unless otherwise specified. Table 58. LED - power section Table 59. LED - switching (VCC = 13 V; Normal switch mode)

1. See Figure 32. Switching characteristics
2. Parameter specified by design and evaluated by characterization, not tested in production.

Table 60. LED - protection and diagnosis

1. ILIMH, guaranteed between 7 V and 16 V, -40 °C < TJ < 150 °C.
2. ILIMH2, guaranteed between 16 V and 19 V, -40 °C < TJ < 150 °C.

Table 61. LED - Digital Current Sense (7 V < VCC < 18 V, TJ = -40 °C to 150 °C)

1. All values refer to VCC = 13 V; TJ = 25 °C, unless otherwise specified.

Figure 32. Switching characteristics

7.8 Waveforms

Figure 33. Normal mode - Short circuit – PBW < tD_Restart

Figure 34. Normal mode - Short circuit – PBW > tD_Restart

8 ISO Pulse

into the VCC pin, is tested in accordance with ISO7637-2:2011(E) and ISO 16750-2:2010. conduction along supply line. as shown in Figure 35. M0-9 SPI application schematic. does not perform as designed during the test but returns automatically to normal operation after the test". Table 62. ISO 7637-2 - electrical transient conduction along supply line

1. US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
2. With 35 V external suppressor referred to ground (-40 °C < TJ < 150 °C).

9 Application schematics

Figure 35. M0-9 SPI application schematic Table 63. Component values

330 Ohm for VDD=5V

D2 Suppressor 20 V Negative transient protection. D3 Suppressor 36 V Overvoltage protection.

10 Maximum demagnetization energy (VCC = 16 V)

Figure 36. Maximum turn-off current versus inductance - Bulb mode all channels Figure 37. Maximum turn-off energy versus inductance - Bulb mode all channels

11.1 QFN 6x6 thermal data

Figure 40. QFN 6x6 PCB footprint Figure 41. QFN 6x6 PCB 2 cm²

Table 64. PCB properties Figure 44. RthJA vs PCB copper area in open box free air conditions

Table 65. Thermal parameters

To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product status are available at: www.st.com. ECOPACK is an ST trademark.

12.1 QFN 6x6 package information

Figure 47. QFN 6x6 package outline

Package information

DS12745 - Rev 5 page 86/97

Table 66. QFN 6x6 mechanical data Table 67. QFN 6x6 tolerance of form and position Table 68. QFN 6x6 variations DS12745 - Rev 5 page 87/97

12.2 QFN 6x6 packing information

Figure 48. QFN 6x6 reel 13" Table 69. Reel dimensions

1. All dimensions are in mm.

Figure 49. QFN 6x6 carrier tape DS12745 - Rev 5 page 88/97

Table 70. QFN 6x6 carrier tape dimensions

1. All dimensions are in mm.

12.3 QFN 6x6 marking information

Figure 50. QFN 6x6 marking information engineering samples to run a qualification activity. DS12745 - Rev 5 page 89/97

Revision history

Table 71. Document revision history Updated Features and Device summary on cover page. Updated Section 3.2 Junction overtemperature (OT) and Section 3.3 Power limitation (PL). removed Figure 24. Diagnostics registers. Updated Table 43 and Section 6.5 Registers. = 16 V) and Section 11 Package and PCB thermal data. conduction along supply line. QFN 6x6 marking information. 20-Dec-2024 4 Updated Table 44. Absolute maximum ratings and Table 54. BULB - power section.

Contents

DS12745 - Rev 5 page 92/97

DS12745 - Rev 5 page 93/97

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