Datasheet - VN9004AJ - Single channel high-side driver with Current Sense analog feedback for automotive applications
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 42
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 2 Electrical specification
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Main electrical characteristics
- 2.4 Waveforms
- 2.5 Electrical characteristics (curves)
- 3 Protections
- 3.1 Power limitation
- 3.2 Thermal shutdown
- 3.3 Current limitation
- 3.4 Negative voltage clamp
- 4 Application information
- 4.1 GND protection network against reverse battery
- 4.1.1 Diode (DGND) in the ground line
- 4.2 Immunity against transient electrical disturbances
- 4.3 MCU I/Os protection
- 4.4 CS - analog current sense
- 4.4.1 Principle of current sense signal generation
- 4.4.2 Short to VCC and OFF-state open-load detection
- 5 Maximum demagnetization energy (VCC = 16 V)
- 6 Package and PCB thermal data
- 6.1 PowerSSO-16 thermal data
- 7 Package information
- 7.1 PowerSSO-16 package information
- 7.2 PowerSSO-16 packing information
- 7.3 PowerSSO-16 marking information
Features
Description Parameter Value Max. transient supply voltage VCC 36 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per channel) RON 4.2 mΩ Current limitation (typ.) ILIMH 108 A Standby current (max.) ISTBY 0.5 µA
- AEC-Q100 qualified
- Extreme low voltage operation for deep cold cranking applications (compliant with LV124, revision 2013)
- General – Single channel smart high-side driver with current sense analog feedback – Very low standby current – Compatible with 3 V and 5 V CMOS outputs
- Current sense diagnostic functions – Multiplexed analog feedback of: load current with high precision proportional current mirror – Overload and short to ground (power limitation) indication – Thermal shutdown indication – OFF-state open-load detection (with external pull-up) – Output short to VCC detection – Sense enable/disable
- Protections – Undervoltage shutdown – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients – Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin – Loss of ground and loss of VCC – Reverse battery through self turn-on – Electrostatic discharge protection
Applications
- Specially intended for Automotive smart power distribution
- Glow plugs, heating systems, DC motors, relay replacement and high power resistive and inductive actuators PowerSSO-16 Product status link VN9004AJ Product summary Order code VN9004AJTR Package PowerSSO-16 Packing Tape and reel Single channel high-side driver with Current Sense analog feedback for automotive applications VN9004AJ Datasheet DS12483 - Rev 5 - January 2025 For further information, contact your local STMicroelectronics sales office.
Description
The VN9004AJ is a single channel high-side driver manufactured using ST proprietary VIPower M0-9 technology and housed in a PowerSSO-16 package. The device is designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, providing protection and diagnostics. The device integrates advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions including high precision proportional load current sense, supply voltage feedback and chip temperature sense, in addition to the detection of overload and short circuit to ground, short to VCC and OFF-state open-load. VN9004AJ DS12483 - Rev 5 page 2/42
1 Block diagram and pin description
Figure 1. Block diagram Table 1. Pin functions GND Ground connection. Must be reverse battery protected by an external diode / resistor network. controls output switch state. SEn Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the CS diagnostic pin. fault; If kept low, sets the outputs in auto-restart mode.
Figure 2. Configuration diagram (top view) Table 2. Suggested connections for unused and not connected pins
2 Electrical specification
Figure 3. Current and voltage conventions Note: VFn = VOUTn - VCC during reverse battery condition.
2.1 Absolute maximum ratings
below for extended periods may affect device reliability. Table 3. Absolute maximum ratings
- INPUT0
- CS
- SEn, FaultRST
- OUTPUT0
- VCC 2000 2000 2000 4000 4000 V VESD Charge device model (CDM-AEC-Q100-011) 750 V TJ Junction operating temperature -40 to 150 °C Tstg Storage temperature -55 to 150 °C VN9004AJ Electrical specification DS12483 - Rev 5 page 5/42
2.2 Thermal data
Table 4. Thermal data
- Device mounted on four-layers 2s2p PCB.
- Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace.
2.3 Main electrical characteristics
7 V < VCC < 28 V, -40 °C < TJ < 150 °C, unless otherwise specified. All typical values refer to VCC = 13 V, TJ = 25 °C, unless otherwise specified. Table 5. Power section
- PowerMOS leakage included.
- Parameter specified by design, not subjected to production test.
Table 6. Switching
- See Figure 4. Switching time and pulse skew.
- Parameter guaranteed by design and characterization, not subjected to production test.
Table 7. Logic inputs
7 V < VCC < 28 V, -40 °C < TJ < 150 °C
Table 8. Protections
7 V < VCC < 18 V, -40°C < TJ < 150°C
- ILIMH, guaranteed between 7 V and 16 V, -40°C < TJ < 150°C.
- ILIMH2, guaranteed between 16 V and 19 V, -40°C < TJ < 150°C.
- Specified by design and evaluated by characterization, not tested in production.
Table 9. CurrentSense
7 V < VCC < 18 V; -40 °C < TJ < 150 °C
Symbol Parameter Test conditions Min. Typ. Max. Unit CurrentSense characteristics KLED IOUT/ISENSE IOUT = 0.25 A; VSENSE = 0.5 V; VSEn = 5 V -35% 19050 +35% dKLED/KLED (1) (2) Current sense ratio drift IOUT = 0.25 A; VSENSE = 0.5 V; VSEn = 5 V -25 25 % K0 IOUT/ISENSE IOUT = 1.8 A; VSENSE = 0.5 V; VSEn = 5 V -20% 19050 20% dK0/K0 (1) (2) Current sense ratio drift IOUT = 1.8 A; VSENSE = 0.5 V; VSEn = 5 V -15 15 % K1 IOUT/ISENSE IOUT = 10 A; VSENSE = 3.5 V; VSEn = 5 V -7% 19050 7% dK1/K1 (1) (2) Current sense ratio drift IOUT = 10 A; VSENSE = 3.5 V; VSEn = 5 V -7 7 % K2 IOUT/ISENSE IOUT = 15 A; VSENSE = 3.5 V; VSEn = 5 V -7% 19050 7% dK2/K2 (1) (2) Current sense ratio drift IOUT = 15 A; VSENSE = 3.5 V; VSEn = 5 V -7 7 % K3 IOUT/ISENSE IOUT = 27 A; VSENSE = 3.5 V; VSEn = 5 V -6% 19050 6% dK3/K3 (1) (2) Current sense ratio drift IOUT = 27 A; VSENSE = 3.5 V; VSEn = 5 V -5 5 % ISENSE0 CurrentSense leakage current CS disabled: VSEn = 0 V 0 0.5 µA CS disabled: -1 V < VSENSE < 5 V(1) -0.5 0.5 CS enabled: VSEn = 5 V; Channel ON; VIN0 = 5 V; IOUT0 = 0 A; 0 3 CS enabled: VSEn = 5 V; Channel OFF; VIN0 = 0 V; IOUT0 = 0 A 0 1 VOUT_MSD (1) Output voltage for CS shutdown VSEn = 5 V; RSENSE = 2.7 kΩ; VIN0 = 5 V; IOUT0 = 15 A 5 V VSENSE_SAT Multisense saturation voltage VCC = 7 V; RSENSE = 10 kΩ; VSEn = 5 V; VIN0 = 5 V; IOUT0 = 27 A; TJ = -40°C 4.8 V ISENSE_SAT (1) CS saturation current VCC = 7 V; VSENSE = 3.5 V; VIN0 = 5 V; VSEn = 5 V; TJ = 150°C 2 mA IOUT_SAT (1) Output saturation current VCC = 7 V; VSENSE = 3.5 V; VIN0 = 5 V; VSEn = 5 V; TJ = 150 °C 37 A OFF-state diagnostic VOL OFF-state open-load voltage detection threshold VSEn = 5 V; Ch OFF; VIN0 = 0 V; 2 3 4 V VN9004AJ Electrical specification DS12483 - Rev 5 page 9/42
Symbol Parameter Test conditions Min. Typ. Max. Unit IL(off2) OFF-state output sink current VIN = 0 V; VOUT = VOL; TJ = -40 °C to 125 °C -150 -40 -5 µA tDSTKON OFF-state diagnostic delay time from falling edge of INPUT (see Figure 6. TDSTKON ) VSEn = 5 V; Ch ON to OFF transition; VIN0 = 5 V to 0 V; IOUT0 = 0 A; VOUT = 4 V 150 260 400 µs tD_OL_V Settling time for valid OFF- state open load diagnostic indication from rising edge of SEn VIN = 0 V; VFR = 0 V; VOUT0 = 4 V; VSEn = 0 V to 5 V 60 µs tD_VOL OFF-state diagnostic delay time from rising edge of VOUT VSEn = 5 V; Ch OFF; VIN0 = 0 V; VOUT = 0 V to 4 V 5 30 µs Fault diagnostic feedback (see Table 10. Truth table) VSENSEH MultiSense output voltage in fault condition
13 V < VCC < 18 V; Ch0 in open load;
RSENSE = 0.7 kΩ; VIN0 = 0 V; VSEn = 5 V; IOUT0 = 0 A; VOUT0 = 4 V 5 7.5 V VCC = 7 V; Ch0 in open load; RSENSE = 0.7 kΩ; VIN0 = 0 V; VSEn = 5 V; IOUT0 = 0 A; VOUT0 = 4 V 4.3 ISENSEH CurrentSense output current in fault condition
13 V < VCC < 18 V; VSENSE = 5 V;
Ch0 in open load; VIN0 = 0 V; VSEn = 5 V; IOUT0 = 0 A; VOUT0 = 4 V 7 8.6 12 mA VCC = 7 V; VSENSE = 5 V; Ch0 in open load; VIN0 = 0 V; VSEn = 5 V; IOUT0 = 0 A; VOUT0 = 4 V 4.4 CurrentSense timings (current sense mode - see Figure 5. CurrentSense timings (current sense mode))(3) tDSENSE1H Current sense settling time from rising edge of SEn VIN = 5 V; VSEn = 0 V to 5 V; RSENSE = 1 kΩ; RL = 0.87 Ω 60 µs tDSENSE1L Current sense disable delay time from falling edge of SEn VIN = 5 V; VSEn = 5 V to 0 V; RSENSE = 1 kΩ; RL = 0.87 Ω 5 20 µs tDSENSE2H Current sense settling time from rising edge of INPUT VIN = 0 V to 5 V; VSEn = 5 V; RSENSE = 1 kΩ; RL = 0.87 Ω 100 200 µs ΔtDSENSE2H Current sense settling time from rising edge of IOUT (dynamic response to a step change of IOUT) VIN = 5 V; VSEn = 5 V; RSENSE = 1 kΩ; ISENSE = 90 % of ISENSEMAX; RL = 0.87 Ω 100 µs tDSENSE2L Current sense turn-off delay time from falling edge of INPUT VIN = 5 V to 0 V; VSEn = 5 V; RSENSE = 1 kΩ; RL = 0.87 Ω 70 250 µs tDSENSE3H Current sense latch-OFF filtering time 1.4 2.0 2.6 ms 1. Specified by design and evaluated by characterization, not tested in production. 2. All values refer to VCC = 13 V; TJ = 25°C, unless otherwise specified. VN9004AJ Electrical specification DS12483 - Rev 5 page 10/42
Figure 6. TDSTKON Table 10. Truth table
- Refer to Table 11. CurrentSense multiplexer addressing
Table 11. CurrentSense multiplexer addressing
2.4 Waveforms
Figure 7. Latch-off mode - Intermittent short circuit
Figure 8. Auto-restart mode - Intermittent short circuit
Figure 11. Standby state diagram
2.5 Electrical characteristics (curves)
Figure 12. OFF-state output current Figure 13. Standby current Figure 14. IGND(ON) vs. Iout Figure 15. Logic input high level voltage Figure 16. Logic input low level voltage Figure 17. High level logic input current
3 Protections
3.1 Power limitation
The basic working principle of this protection consists of an indirect measurement of the junction temperature swing ΔTJ through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as ΔTJ exceeds the safety level of ΔTJ_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remain off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo-mechanical fatigue.
3.2 Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175 °C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High).
3.3 Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (for example bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short-circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region.
3.4 Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the device. VN9004AJ Protections DS12483 - Rev 5 page 21/42
4 Application information
Figure 32. Application diagram
4.1 GND protection network against reverse battery
Figure 33. Simplified internal structure
Application information
DS12483 - Rev 5 page 22/42
4.1.1 Diode (DGND) in the ground line
A resistor (typ. RGND = 4.7 kΩ) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (≈600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network.
4.2 Immunity against transient electrical disturbances
The immunity of the device against transient electrical emissions, conducted along the supply lines and injected into the VCC pin, is tested in accordance with ISO7637-2:2011 (E) and ISO 16750-2:2010. The related function performance status classification is shown in Table 12. ISO 7637-2 - electrical transient conduction along supply line. Test pulses are applied directly to DUT (device under test) both in ON and OFF state and in accordance to ISO 7637-2:2011(E), chapter 4. The DUT is intended as the current device only, with external components as shown in Figure 34. M0-9 application schematic. Status II is defined in ISO 7637-1 Function Performance Status Classification (FPSC) as follows: “The function does not perform as designed during the test but returns automatically to normal operation after the test”. Table 12. ISO 7637-2 - electrical transient conduction along supply line
- US is the peak amplitude as defined for each test pulse in ISO 7637-2:2011(E), chapter 5.6.
- With 35 V external suppressor referred to ground (-40°C < Tj < 150 °C).
DS12483 - Rev 5 page 23/42
Figure 34. M0-9 application schematic
4.3 MCU I/Os protection
latching-up and to protect the HSD inputs. required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os.
4.4 CS - analog current sense
- Current monitor: current mirror of channel output current Those signals are routed through an analog multiplexer which is configured and controlled by means of SELx and SEn pins, according to the address map in Table 7. VN9004AJ
DS12483 - Rev 5 page 24/42
Figure 35. CurrentSense and diagnostic – block diagram
4.4.1 Principle of current sense signal generation
Figure 36. CurrentSense block diagram DS12483 - Rev 5 page 25/42
The output is capable of providing:
- Current mirror proportional to the load current in normal operation, delivering current proportional to the load according to known ratio named K
- Diagnostics flag in fault conditions delivering fixed voltage VSENSEH The current delivered by the current sense circuit, ISENSE, can be easily converted into a voltage VSENSE by using an external sense resistor, RSENSE, allowing continuous load monitoring and abnormal condition detection. Normal operation (channel ON, no fault, SEn active) While device is operating in normal conditions (no fault intervention), VSENSE calculation can be done using simple equations Current provided by MultiSense output: ISENSE = IOUT/K Voltage on RSENSE: VSENSE = RSENSE · ISENSE = RSENSE · IOUT/K Where:
- VSENSE is voltage measurable on RSENSE resistor
- ISENSE is current provided from CurrentSense pin in current output mode
- IOUT is current flowing through output
- K factor represents the ratio between PowerMOS cells and SenseMOS cells; its spread includes geometric factor spread, current sense amplifier offset and process parameters spread of overall circuitry specifying the ratio between IOUT and ISENSE. Failure flag indication In case of power limitation/overtemperature, the fault is indicated by the CurrentSense pin which is switched to a “current limited” voltage source, VSENSEH. In any case, the current sourced by the CurrentSense in this condition is limited to ISENSEH. The typical behavior in case of overload or hard short circuit is shown in Section 2.4: Waveforms. VN9004AJ
DS12483 - Rev 5 page 26/42
Table 13. CS pin levels in off-state
4.4.2 Short to VCC and OFF-state open-load detection
current consumption to increase in normal conditions, that is when load is connected. DS12483 - Rev 5 page 28/42
5 Maximum demagnetization energy (VCC = 16 V)
Figure 39. Maximum turn off current versus inductance Figure 40. Maximum turn off energy versus inductance
6 Package and PCB thermal data
6.1 PowerSSO-16 thermal data
Figure 41. PowerSSO-16 on two-layer PCB (2s0p to JEDEC JESD 51-5) Figure 42. PowerSSO-16 on four-layer PCB (2s2p to JEDEC JESD 51-7) Table 14. PCB properties
Figure 43. Rthj-amb vs PCB copper area in open box free air condition (one channel on) Figure 44. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
4 Layer
Figure 45. Thermal fitting model of a double-channel HSD in PowerSSO-16 (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 15. Thermal parameters
7 Package information
To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product status are available at: www.st.com. ECOPACK is an ST trademark.
7.1 PowerSSO-16 package information
Figure 46. PowerSSO-16 package outline
Package information
DS12483 - Rev 5 page 33/42
Table 16. PowerSSO-16 package mechanical data DS12483 - Rev 5 page 34/42
7.2 PowerSSO-16 packing information
Figure 47. PowerSSO-16 reel 13" Table 17. Reel dimensions
- All dimensions are in mm.
Figure 48. PowerSSO-16 carrier tape DS12483 - Rev 5 page 35/42
Table 18. PowerSSO-16 carrier tape dimensions
- All dimensions are in mm.
Figure 49. PowerSSO-16 schematic drawing of leader and trailer tape DS12483 - Rev 5 page 36/42
7.3 PowerSSO-16 marking information
Figure 50. PowerSSO-16 marking information engineering samples to run a qualification activity. DS12483 - Rev 5 page 37/42
Revision history
Table 19. Document revision history 01-Mar-2018 1 Initial release. Updated Features in cover page. Updated Section 1 Block diagram and pin description. Updated Figure 3. Current and voltage conventions. Updated Section 2.1 Absolute maximum ratings. Updated Section 2.3 Main electrical characteristics. Updated Section 2.4 Waveforms. Added Section 5 Package information. Added Section 2.5: Electrical characteristics (curves). reverse battery, Section 4.2: Immunity against transient electrical disturbances and Figure 37. Analog HSD – open-load detection in off-state. Section 5: Maximum demagnetization energy (VCC = 16 V). 17-Jan-2025 5 Updated Table 3. Absolute maximum ratings and Table 9. CurrentSense. DS12483 - Rev 5 page 38/42
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