VN820_V01 STM | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 43
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 2 Electrical specifications
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Electrical characteristics
- 2.4 Electrical characteristics curves
- 3 Application information
- 3.1 GND protection network against reverse battery
- 3.1.1 Solution 1: resistor in the ground line (RGND only)
- 3.1.2 Solution 2: diode (DGND) in the ground line
- 3.2 Load dump protection
- 3.3 MCU I/Os protection
- 3.4 Open load detection in off-state
- 3.5 PowerSO-10, P
- 4 Package and PCB thermal data
- 4.1 P 2PAK thermal data
- 4.2 PPAK thermal data
- 4.3 PowerSO-10 thermal data
- 5 Package and packing information
- 5.1 ECOPACK ®
- 5.2 PENTAWATT mechanical data
- 5.3 P 2PAK mechanical data
- 5.4 PPAK mechanical data
- 5.5 PowerSO-10 mechanical data
- 5.6 PENTAWATT packing information
- 5.8 PPAK packing information
Features
■ Very low standby current ■ CMOS compatible input ■ On-state open-load detection ■ Off-state open-load detection ■ Thermal shutdown protection and diagnosis ■ Undervoltage shutdown ■ Overvoltage clamp ■ Output stuck to VCC detection ■ Load current limitation ■ Reverse battery protection ■ Electrostatic discharge protection
Description
The VN820 is a monolithic device designed in STMicroelectronic's VIPower® M0-3 technology. The VN820 is intended for driving any type of load with one side connected to ground. The active V CC pin voltage clamp protects the device against low energy spikes. Active current limitation combined with thermal shutdown and automatic restart protects the device against over-load. The device detects the open-load condition in both the on-state and off- state. In the off-state the device detects if the output is shorted to V CC. The device automatically turns off in the case where the ground pin becomes disconnected. Type R DS(on) IOUT VCC VN820 VN820SP VN820-B5 VN820PT 40 mΩ 9A 3 6V PENTAWATT P2PAK PowerSO-10 PPAK Table 1. Device summary
Doc ID 7370 Rev. 6 3/43 Obsolete Product(s) - Obsolete Product(s)
Table 6. Switching (V Table 18. P
1 Block diagram and pin description
Figure 1. Block diagram Figure 2. Configuration diagram (top view) Table 2. Suggested connections for unused and not connected pins
2 Electrical specifications
Figure 3. Current and voltage conventions
2.1 Absolute maximum ratings
conditions above those indicated in the operating sections of this specification is not implied. Table 3. Absolute maximum ratings
2.2 Thermal data
Table 3. Absolute maximum ratings (continued) Table 4. Thermal data
- When mounted on a standard single-sided FR-4 board with 0.5 cm 2 of Cu (at least 35 µm thick).
- When mounted on a standard single-sided FR-4 board with 6 cm 2 of Cu (at least 35 µm thick).
2.3 Electrical characteristics
Table 5. Power Table 6. Switching (V CC=13V) Table 7. Input pin
Table 8. V CC output diode Table 9. Status pin Table 10. Protections (1)
- To ensure long term reliability under heavy over-load or short circuit conditions, protection and related
abnormal conditions this software must limit the duration and number of activation cycles.
5.5 V < VCC < 36 V 20 A
Table 7. Input pin (continued)
Table 12. Truth table Table 13. Electrical transient requirements
- All functions of the device are performed as designed after exposure to disturbance.
- One or more functions of the device is not perfo rmed as designed after exposure and cannot be returned to
proper operation without replacing the device.
Figure 6. Waveforms
2.4 Electrical characteristics curves
Figure 7. Off-state output current Figure 8. High level input current Figure 9. Input clamp voltage Figure 10. Status leakage current Figure 11. Status low output voltage Figure 12. Status clamp voltage
3 Application information
Figure 24. Application schematic
3.1 GND protection network against reverse battery
3.1.1 Solution 1: resistor in the ground line (R GND only)
This can be used with any type of load. The following is an indication on how to size the RGND resistor. maximum rating section of the device datasheet. maximum on-state currents of the different devices. the same resistor then ST suggests to utilize Solution 2 (see below).
Doc ID 7370 Rev. 6 19/43
3.1.2 Solution 2: diode (D GND) in the ground line
A resistor (RGND = 1 kΩ) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network produces a shift (≈ 600 mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift does not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the absolute maximum rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.
3.2 Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 MCU I/Os protection
If a ground protection network is used and negative transient are present on the V CC line, the control pins are pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the microcontroller I/O pins from latching-up. The value of these resistors is a compromise between the leakage current of microcontroller and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of microcontroller I/Os. CCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V 5kΩ ≤ Rprot ≤ 65kΩ. Recommended values: Rprot =10kΩ .
3.4 Open load detection in off-state
Off-state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1. no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT= (VPU / (RL+RPU)) RL < VOlmin. 2. no misdetection when load is disconnected: in this case the V OUT has to be higher than VOLmax; this results in the following condition RPU < (VPU – VOLmax) / IL(off2). Obsolete Product(s) - Obsolete Product(s)
Figure 25. Open load detection in off-state
3.5 PowerSO-10, P2PAK, PPAK, PENTAWATT maximum
Figure 26. PowerSO-10, P2PAK, PPAK, PENTAWATT maximum turn-off current
4 Package and PCB thermal data
4.1 P 2PAK thermal data
Figure 27. PC board thickness = 2 mm, Cu thickness = 35 µm , Copper areas: 0.97 cm2, 8 cm2). Figure 28. R thj-amb vs PCB copper area in open box free air condition
Table 14. Thermal parameter
4.2 PPAK thermal data
Figure 31. PC board thickness = 2 mm, Cu thickness=35 µm , Copper areas: 0.44 cm 2, 8 cm2).
Figure 34. Thermal fitting model of a single channel Table 15. Thermal parameter
4.3 PowerSO-10 thermal data
Figure 35. PowerSO-10 PC board Figure 36. R thj-amb vs PCB copper area in open box free air condition
Table 16. Thermal parameters
5 Package and packing information
5.1 ECOPACK ®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
5.2 PENTAWATT mechanical data
Figure 39. PENTAWATT package dimensions
Table 17. PENTAWATT mechanical data
5.3 P 2PAK mechanical data
Figure 40. P 2PAK package dimensions
Table 18. P 2PAK mechanical data
5.4 PPAK mechanical data
Figure 41. PPAK package dimensions
Table 19. PPAK mechanical data
5.5 PowerSO-10 mechanical data
Figure 42. PowerSO-10 package dimensions
Table 20. PowerSO-10 mechanical data
5.6 PENTAWATT packing information
Figure 43. PENTAWATT tube shipment (no suffix)
5.7 P 2PAK packing information
Figure 44. P 2PAK tube shipment (no suffix)
Figure 45. P 2PAK tape and reel (suffix “13TR”)
5.8 PPAK packing information
Figure 46. PPAK suggested pad layout
5.9 PowerSO-10 packing information
Figure 51. PowerSO-10 tape and reel shipment (suffix “TR”) Figure 49. PowerSO-10 suggested Figure 50. PowerSO-10 tube shipment
6 Revision history
Table 21. Document revision history 07-Jul-2004 1 Initial release. Current and voltage convention update (page 2). unused and n.c. pins insertion (page 2). 6 cm2 Cu condition insertion in thermal data table (page 3). CC - output diode section update (page 4). Revision history table insertion (page 34). Disclaimers update (page 35). Document reformatted and restructured. Added content, list of figures and tables. 20-Sep-2013 6 Updated Disclaimer.