Datasheet - VN7040AJ, VN7040AS - High-side driver with MultiSense analog feedback for automotive applications
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 45
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 2 Electrical specification
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Main electrical characteristics
- 2.4 Waveforms
- 2.5 Electrical characteristics curves
- 3 Protections
- 3.1 Power limitation
- 3.2 Thermal shutdown
- 3.3 Current limitation
- 3.4 Negative voltage clamp
- 4 Maximum demagnetization energy (VCC = 16 V)
- 5 Package and PCB thermal data
- 5.1 PowerSSO-16 thermal data
- 5.2 SO-8 thermal data
- 6 Package information
- 6.1 PowerSSO-16 package information
- 6.2 SO-8 package information
- 6.3 PowerSSO-16 packing information
- 6.4 SO-8 packing information
- 6.5 PowerSSO-16 marking information
- 6.6 SO-8 marking information
- 7 Order codes
Features
Max transient supply voltage VCC 40 V Operating voltage range VCC 4 to 28 V Typ. on-state resistance (per Ch) RON 40 mΩ Current limitation (typ) ILIMH 34 A Standby current (max) ISTBY 0.5 µA
- AEC-Q100 qualified
- General – Single channel smart high-side driver with MultiSense analog feedback – Very low standby current – Compatible with 3 V and 5 V CMOS outputs
- MultiSense diagnostic functions – Multiplexed analog feedback of: load current with high precision proportional current mirror, VCC supply voltage and TCHIP device temperature – Overload and short to ground (power limitation) indication – Thermal shutdown indication – OFF-state open-load detection – Output short to V CC detection – Sense enable/disable
- Protections – Undervoltage shutdown – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients – Configurable latch-off on overtemperature or power limitation with dedicated fault reset pin – Loss of ground and loss of V CC – Reverse battery with external components – Electrostatic discharge protection
Applications
- All types of Automotive resistive, inductive and capacitive loads
- Specially intended for Automotive Turn Indicators (up to P27W or SAE1156 and R5W paralleled or LED Rear Combinations)
- Protected supply for ADAS systems: radars and sensors
Description
The devices are single channel high-side drivers manufactured using ST proprietary VIPower M0-7 technology and housed in PowerSSO-16 and SO-8 packages. The Product status link VN7040AJ VN7040AS High-side driver with MultiSense analog feedback for automotive applications VN7040AJ, VN7040AS Datasheet DS10829 - Rev 5 - April 2019 For further information contact your local STMicroelectronics sales office.
devices are designed to drive 12 V automotive grounded loads through a 3 V and 5 V CMOS-compatible interface, and to provide protection and diagnostics. The devices integrate advanced protective functions such as load current limitation, overload active management by power limitation and overtemperature shutdown with configurable latch-off. A FaultRST pin unlatches the output in case of fault or disables the latch-off functionality. A dedicated multifunction multiplexed analog output pin delivers sophisticated diagnostic functions including high precision proportional load current sense, supply voltage feedback and chip temperature sense, in addition to the detection of overload and short circuit to ground, short to VCC and OFF-state open-load. A sense enable pin allows OFF-state diagnosis to be disabled during the module low- power mode as well as external sense resistor sharing among similar devices. VN7040AJ, VN7040AS DS10829 - Rev 5 page 2/45
1 Block diagram and pin description
Figure 1. Block diagram Table 1. Pin functions GND Ground connection. Must be reverse battery protected by an external diode / resistor network. supply voltage or chip temperature. SEn Active high compatible with 3 V and 5 V CMOS outputs pin; it enables the MultiSense diagnostic pin. SEL0,1 Active high compatible with 3 V and 5 V CMOS outputs pin; they address the MultiSense multiplexer. the outputs in auto-restart mode.
Figure 2. Configuration diagram (top view) Table 2. Suggested connections for unused and not connected pins
2 Electrical specification
Figure 3. Current and voltage conventions Note: V F = VOUT - VCC during reverse battery condition.
2.1 Absolute maximum ratings
below for extended periods may affect device reliability. Table 3. Absolute maximum ratings
- INPUT
- MultiSense
- SEn, SEL 0,1, FaultRST
- OUTPUT
- V CC 4000 2000 4000 4000 4000 V V V V V VESD Charge device model (CDM-AEC-Q100-011) 750 V Tj Junction operating temperature -40 to 150 Tstg Storage temperature -55 to 150
2.2 Thermal data
Table 4. Thermal data
- Device mounted on four-layers 2s2p PCB
- Device mounted on two-layers 2s0p PCB with 2 cm2 heatsink copper trace
2.3 Main electrical characteristics
7 V < VCC < 28 V; -40°C < Tj < 150°C, unless otherwise specified. All typical values refer to VCC = 13 V; Tj = 25°C, unless otherwise specified. Table 5. Power section
- PowerMOS leakage included.
- Parameter specified by design; not subjected to production test.
Table 6. Switching
- See Figure 6. Switching time and Pulse skew.
- Parameter guaranteed by design and characterization; not subjected to production test.
Table 7. Logic inputs
7 V < VCC < 28 V; -40°C < Tj < 150°C
Symbol Parameter Test conditions Min. Typ. Max. Unit VIH Input high level voltage 2.1 V IIH High level input current VIN = 2.1 V 10 µA VI(hyst) Input hysteresis voltage 0.2 V VICL Input clamp voltage IIN = 1 mA 5.3 7.2 V IIN = -1 mA -0.7 FaultRST characteristics (VN7040AJ only) VFRL Input low level voltage 0.9 V IFRL Low level input current VIN = 0.9 V 1 µA VFRH Input high level voltage 2.1 V IFRH High level input current VIN = 2.1 V 10 µA VFR(hyst) Input hysteresis voltage 0.2 V VFRCL Input clamp voltage IIN = 1 mA 5.3 7.5 V IIN = -1 mA -0.7 SEL0,1 characteristics (7 V < VCC < 18 V) (VN7040AJ only) VSELL Input low level voltage 0.9 V ISELL Low level input current VIN = 0.9 V 1 µA VSELH Input high level voltage 2.1 V ISELH High level input current VIN = 2.1 V 10 µA VSEL(hyst) Input hysteresis voltage 0.2 V VSELCL Input clamp voltage IIN = 1 mA 5.3 7.2 V IIN = -1 mA -0.7 SEn characteristics (7 V < VCC < 18 V) VSEnL Input low level voltage 0.9 V ISEnL Low level input current VIN = 0.9 V 1 µA VSEnH Input high level voltage 2.1 V ISEnH High level input current VIN = 2.1 V 10 µA VSEn(hyst) Input hysteresis voltage 0.2 V VSEnCL Input clamp voltage IIN = 1 mA 5.3 7.2 V IIN = -1 mA -0.7 VN7040AJ, VN7040AS Main electrical characteristics DS10829 - Rev 5 page 8/45
Table 8. Protections
7 V < VCC < 18 V; -40°C < Tj < 150°C
4 V < VCC < 18 V (1)
- Parameter guaranteed by design and characterization; not subjected to production test.
Table 9. MultiSense
Symbol Parameter Test conditions Min. Typ. Max. Unit dK1/K1 (1) (2) Current sense ratio drift IOUT = 0.5 A; VSENSE = 4 V; VSEn = 5 V -15 15 % K2 IOUT/ISENSE IOUT = 1.5 A; VSENSE = 4 V; VSEn = 5 V 1140 1350 1710 dK2/K2 (1) (2) Current sense ratio drift IOUT = 1.5 A; VSENSE = 4 V; VSEn = 5 V -10 10 % K3 IOUT/ISENSE IOUT = 4.5 A; VSENSE = 4 V; VSEn = 5 V 1200 1340 1470 dK3/K3 (1) (2) Current sense ratio drift IOUT = 4.5 A; VSENSE = 4 V; VSEn = 5 V -5 5 % ISENSE0 MultiSense leakage current MultiSense disabled: VSEn = 0 V 0 0.5 µA MultiSense disabled: -1 V < VSENSE < 5 V(1) -0.5 0.5 MultiSense enabled: VSEn = 5 V; Channel ON; IOUT = 0 A; Diagnostic selected; VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A 0 2 MultiSense enabled: VSEn = 5 V; Channel OFF; Diagnostic selected: VIN = 0 V; VSEL0 = 0 V; VSEL1 = 0 V 0 2 VOUT_MSD (1) Output voltage for MultiSense shutdown VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; RSENSE = 2.7 kΩ; IOUT = 2.5 A 5 V VSENSE_SAT Multisense saturation voltage VCC = 7 V; RSENSE = 2.7 kΩ; VSEn = 5 V; VIN = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 4.5 A; Tj = 150°C 5 V ISENSE_SAT (1) CS saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; Tj = 150°C 4 mA IOUT_SAT (1) Output saturation current VCC = 7 V; VSENSE = 4 V; VIN = 5 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; Tj = 150°C 6 A OFF-state diagnostic VOL OFF-state open-load voltage detection threshold VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V 2 3 4 V IL(off2) OFF-state output sink current VIN = 0 V; VOUT = VOL -100 -15 µA tDSTKON OFF-state diagnostic delay time from falling edge of INPUT (see )Figure 9. TDSTKON VIN = 5 V to 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A; VOUT = 4 V 100 350 700 µs tD_OL_V Settling time for valid OFF- state open load diagnostic indication from rising edge of SEn VIN = 0 V; VFR = 0 V; VSEL0 = 0 V; VSEL1 = 0 V; VOUT = 4 V; VSEn = 0 V to 5 V 60 µs tD_VOL OFF-state diagnostic delay time from rising edge of VOUT VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; VOUT = 0 V to 4 V 5 30 µs Chip temperature analog feedback (VN7040AJ only) VN7040AJ, VN7040AS Main electrical characteristics DS10829 - Rev 5 page 10/45
Symbol Parameter Test conditions Min. Typ. Max. Unit VSENSE_TC MultiSense output voltage proportional to chip temperature VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 kΩ; Tj = -40°C 2.325 2.41 2.495 V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 kΩ; Tj = 25°C 1.985 2.07 2.155 V VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 kΩ; Tj = 125°C 1.435 1.52 1.605 V dVSENSE_TC/dT(1) Temperature coefficient Tj = -40°C to 150°C -5.5 mV/ K Transfer function VSENSE_TC (T) = VSENSE_TC (T0) + dVSENSE_TC / dT * (T - T0) VCC supply voltage analog feedback (VN7040AJ only) VSENSE_VCC MultiSense output voltage proportional to VCC supply voltage VCC = 13 V; VSEn = 5 V; VSEL0 = 5 V; VSEL1 = 5 V; VIN = 0 V; RSENSE = 1 kΩ 3.16 3.23 3.3 V Transfer function (3) VSENSE_VCC = VCC / 4 Fault diagnostic feedback (see Table 10. Truth table) VSENSEH MultiSense output voltage in fault condition VCC = 13 V; VIN = 0 V; VSEn = 5 V; VSEL0 = 0 V; VSEL1 = 0 V; IOUT = 0 A; VOUT = 4 V; RSENSE = 1 kΩ; 5 6.6 V ISENSEH MultiSense output current in fault condition VCC = 13 V; VSENSE = 5 V 7 20 30 mA MultiSense timings (current sense mode - see Figure 7. MultiSense timings (current sense mode)) (4) tDSENSE1H Current sense settling time from rising edge of SEn VIN = 5 V; VSEn = 0 V to 5 V; RSENSE = 1 kΩ; RL = 5.2 Ω 60 µs tDSENSE1L Current sense disable delay time from falling edge of SEn VIN = 5 V; VSEn = 5 V to 0 V; RSENSE = 1 kΩ; RL = 5.2 Ω 5 20 µs tDSENSE2H Current sense settling time from rising edge of INPUT VIN = 0 V to 5 V; VSEn = 5 V; RSENSE = 1 kΩ; RL = 5.2 Ω 100 250 µs ΔtDSENSE2H Current sense settling time from rising edge of IOUT (dynamic response to a step change of IOUT) VIN = 5 V; VSEn = 5 V; RSENSE = 1 kΩ; ISENSE = 90 % of ISENSEMAX; RL = 5.2 Ω 100 µs tDSENSE2L Current sense turn-off delay time from falling edge of INPUT VIN = 5 V to 0 V; VSEn = 5 V; RSENSE = 1 kΩ; RL = 5.2 Ω 50 250 µs MultiSense timings (chip temperature sense mode - see Figure 8. Multisense timings (chip temperature and VCC sense mode) (VN7040AJ only))(4) tDSENSE3H VSENSE_TC settling time from rising edge of SEn VSEn = 0 V to 5 V; VSEL0 = 0 V; VSEL1 = 5 V; RSENSE = 1 kΩ 60 µs tDSENSE3L VSENSE_TC disable delay time from falling edge of SEn VSEn = 5 V to 0 V; VSEL0 = 0 V; VSEL1 = 5 V; RSENSE = 1 kΩ 20 µs MultiSense timings (VCC voltage sense mode - see Figure 8. Multisense timings (chip temperature and VCC sense mode) (VN7040AJ only)) (4) tDSENSE4H VSENSE_VCC settling time from rising edge of SEn VSEn = 0 V to 5 V; VSEL0 = 5 V; VSEL1 = 5 V; RSENSE = 1 kΩ 60 µs tDSENSE4L VSENSE_VCC disable delay time from falling edge of SEn VSEn = 5 V to 0 V; VSEL0 = 5 V; VSEL1 = 5 V; RSENSE = 1 kΩ 20 µs VN7040AJ, VN7040AS Main electrical characteristics DS10829 - Rev 5 page 11/45
- Parameter specified by design; not subjected to production test.
- All values refer to V CC = 13 V; Tj = 25°C, unless otherwise specified.
- V CC sensing and TC are referred to GND potential.
- Transition delays are measured up to +/- 10% of final conditions.
Figure 4. IOUT/ISENSE versus IOUT
Figure 9. TDSTKON Table 10. Truth table
- Refer to Table 11. MultiSense multiplexer addressing
Table 11. MultiSense multiplexer addressing
- In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is low,
2.4 Waveforms
Figure 10. Latch functionality - behavior in hard short-circuit condition (TAMB << TTSD)
2.5 Electrical characteristics curves
Figure 15. OFF-state output current Figure 16. Standby current Figure 17. IGND(ON) vs. Tcase Figure 18. Logic Input high level voltage
3 Protections
3.1 Power limitation
The basic working principle of this protection consists of an indirect measurement of the junction temperature swing ΔTj through the direct measurement of the spatial temperature gradient on the device surface in order to automatically shut off the output MOSFET as soon as ΔTj exceeds the safety level of ΔTj_SD. According to the voltage level on the FaultRST pin, the output MOSFET switches on and cycles with a thermal hysteresis according to the maximum instantaneous power which can be handled (FaultRST = Low) or remains off (FaultRST = High). The protection prevents fast thermal transient effects and, consequently, reduces thermo- mechanical fatigue.
3.2 Thermal shutdown
In case the junction temperature of the device exceeds the maximum allowed threshold (typically 175°C), it automatically switches off and the diagnostic indication is triggered. According to the voltage level on the FaultRST pin, the device switches on again as soon as its junction temperature drops to TR (FaultRST = Low) or remains off (FaultRST = High).
3.3 Current limitation
The device is equipped with an output current limiter in order to protect the silicon as well as the other components of the system (e.g. bonding wires, wiring harness, connectors, loads, etc.) from excessive current flow. Consequently, in case of short circuit, overload or during load power-up, the output current is clamped to a safety level, ILIMH, by operating the output power MOSFET in the active region.
3.4 Negative voltage clamp
In case the device drives inductive load, the output voltage reaches a negative value during turn off. A negative voltage clamp structure limits the maximum negative voltage to a certain value, VDEMAG, allowing the inductor energy to be dissipated without damaging the device. VN7040AJ, VN7040AS Protections DS10829 - Rev 5 page 23/45
4 Maximum demagnetization energy (VCC = 16 V)
Figure 35. Maximum turn off current versus inductance Note: Values are generated with R L = 0 Ω. temperature specified above for curves A and B.
5 Package and PCB thermal data
5.1 PowerSSO-16 thermal data
Figure 36. PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) Figure 37. PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) Table 12. PCB properties
Figure 38. PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition (one channel on) Figure 39. PowerSSO-16 thermal impedance junction ambient single pulse (one channel on)
4 Layer
Figure 40. Thermal fitting model of a double-channel HSD in PowerSSO-16 (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 13. Thermal parameters
5.2 SO-8 thermal data
Figure 41. S0-8 on two-layers PCB (2s0p to JEDEC JESD 51-5) Figure 42. SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7) Table 14. PCB properties
Figure 43. SO-8 Rthj-amb vs PCB copper area in open box free air condition (one channel on) Figure 44. SO-8 thermal impedance junction ambient single pulse (one channel on)
Figure 45. Thermal fitting model of a double-channel HSD in SO-8 (power limitation or thermal cycling during thermal shutdown) are not triggered. Table 15. Thermal parameters
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
6.1 PowerSSO-16 package information
Figure 46. PowerSSO-16 package outline
Package information
DS10829 - Rev 5 page 31/45
Table 16. PowerSSO-16 mechanical data
6.2 SO-8 package information
Figure 47. SO-8 package outline Table 17. SO-8 mechanical data
6.3 PowerSSO-16 packing information
Figure 48. PowerSSO-16 reel 13" Table 18. Reel dimensions
- All dimensions are in mm.
6.4 SO-8 packing information
Figure 51. Reel for SO-8 Table 20. Reel dimensions
- All dimensions are in mm.
6.5 PowerSSO-16 marking information
Figure 54. PowerSSO-16 marking information engineering samples to run a qualification activity.
6.6 SO-8 marking information
Figure 55. SO-8 marking information production and/or in reliability qualification trials.
7 Order codes
Table 22. Device summary
Revision history
Table 23. Document revision history 04-Jun-2015 1 Initial release.
- Section 6.1: "PowerSSO-16 thermal data"
- Section 6.2: "SO-8 thermal data" 02-Oct-2016 3 Updated the following:
- Features list on the cover page
- Figure 61: "PowerSSO-16 marking information" 02-Jul-2018 4 Minor text changes in TCASE and VCC monitor. 04-Apr-2019 5 Updated Table 16. PowerSSO-16 mechanical data VN7040AJ, VN7040AS DS10829 - Rev 5 page 40/45