Single channel high side driver with analog current sense for automotive applications
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 31
Technical content
Datasheet sections
- 1 Block diagram and pin description
- 2 Electrical specifications
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Electrical characteristics
- 2.4 Electrical characteristics curves
- 3 Application information
- 3.1 GND protection network against reverse battery
- 3.1.1 Solution 1: resistor in the ground line (RGND only)
- 3.1.2 Solution 2: diode (D GND) in the ground line
- 3.2 Load dump protection
- 3.3 MCU I/O protection
- 4 Package and PCB thermal data
- 4.1 PowerSSO-12™ thermal data
- 5 Package information
- 5.1 ECOPACK ® packages
- 5.2 Package mechanical data
- 5.3 Packing information
- 6 Revision history
Features
■ General features – Inrush current active management by power limitation – Very low stand-by current – 3.0V CMOS compatible input – Optimized electromagnetic emission – Very low electromagnetic susceptibility – In compliance with the 2002/95/EC European directive ■ Diagnostic functions – Proportional load current sense – High current sense precision for wide range currents – Current sense disable – Thermal shutdown indication – Very low current sense leakage ■ Protection – Undervoltage shut-down – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients – Protection against loss of ground and loss of V CC – Thermal shut down – Reverse battery protection ( see Application schematic ) – Electrostatic discharge protection Application ■ All types of resistive, inductive and capacitive loads ■ Suitable as LED driver
Description
The VN5050AJ-E is a monolithic device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears. Max supply voltage V CC 41 V Operating voltage range V CC 4.5 to 36V Max On-State resistance R ON 50 mΩ Current limitation (typ) I LIMH 16.5 A Off state supply current I S 2 µA PowerSSO-12 Table 1. Device summary
Table 7. Switching (V
1 Block diagram and pin description
Figure 1. Block diagram Table 2. Pin function CURRENT SENSE Analog current sense pin, delivers a current proportional to the load current. CS_DIS Active high CMOS compatible pin, to disable the current sense pin.
Figure 2. Configuration diagram (top view) these pins should be left unconnected. Table 3. Suggested connections for unused and N.C. pins
2 Electrical specifications
Figure 3. Current and voltage conventions Note: V F = VOUT - VCC during reverse battery condition.
2.1 Absolute maximum ratings
and other relevant quality document. Table 4. Absolute maximum ratings
2.2 Thermal data
Table 4. Absolute maximum ratings (continued) Table 5. Thermal data
2.3 Electrical characteristics
Table 6. Power section
- PowerMOS leakage included.
Table 7. Switching (V CC=13V, Tj=25°C)
Table 8. Logic input Table 9. Protection and diagnostics (1)
- To ensure long term reliability under heavy overload or short circuit conditions, protection and related
abnormal conditions this software must limit the duration and number of activation cycles.
Table 10. Current sense (8V<V CC<16V)
Table 11. Truth table
- If the V CSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
Table 12. Electrical transient requirements
- The above test levels must be considered referred to V CC = 13.5V except for pulse 5b.
- Valid in case of external load dum p clamp: 40V maximum referred to ground.
C All functions of the device are performed as designed after exposure to disturbance. disturbance and cannot be returned to proper operation without replacing the device.
Figure 10. Waveforms
2.4 Electrical characteristics curves
Figure 11. Off state output current Figure 12. High level input current Figure 13. Input clamp voltage Figure 14. Input low level Figure 15. Input high level Figure 16. Input hysteresis voltage
3 Application information
Figure 26. Application schematic
3.1 GND protection network against reverse battery
3.1.1 Solution 1: resistor in the ground line (R GND only)
This can be used with any type of load. maximum rating section of the device datasheet. maximum on-state currents of the different devices.
If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below.
3.1.2 Solution 2: diode (D GND) in the ground line
Note that a resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.2 Load dump protection
Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the VCC maximum DC rating. The same applies if the device is subject to transients on the VCC line that are greater than those shown in the ISO T/R 7637/1 table.
3.3 MCU I/O protection
If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/O pins from latching up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os: -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax Equation 1: For the following conditions: VCCpeak= - 100V Ilatchup ≥ 20mA VOHμC ≥ 4.5V 5kΩ ≤ Rprot ≤ 180kΩ. Recommended values are: Rprot =10kΩ, CEXT=10nF
Figure 27. Maximum turn Off current versus inductance
4 Package and PCB thermal data
4.1 PowerSSO-12™ thermal data
Figure 28. PowerSSO-12™ PC Board Figure 29. R thj-amb Vs. PCB copper area in open box free air condition
Table 13. Thermal parameter
5 Package information
5.1 ECOPACK ® packages
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2 Package mechanical data
Figure 32. PowerSSO-12™ package dimensions
Table 14. PowerSSO-12™ mechanical data
5.3 Packing information
Figure 33. PowerSSO-12™ tube shipment (no suffix) Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”)
6 Revision history
Table 15. Document revision history 24-Jan-2006 1 Initial release. Table 10: Current sense (8V<VCC<16V) tDSENSE2H entry updated. Table 13: Thermal parameter updated. Document reformatted and restructured. Contents and lists of tables and figures added. Table 4: Absolute maximum ratings: updated EMAX entries. Table 10 : added dk1/k1, dk2/k2, dk3/k3, ΔtDSENSE2H. current and rising edge of current sense (CS enabled). Updated Figure 8: IOUT/ISENSE Vs. IOUT (see Table 10. for details). Added Figure 9: Maximum current sense ratio drift vs load current. III and IV for test pulse 5b and notes. Figure 2: Configuration diagram (top view): added note. – changed t DSENSE2H max value from 300 µs to 250µs. R1 value changed from 0.6 to 0.7 °C/W. changed IOL test condition from VIN = 0V to VIN = 5V. 23-Sep-2013 7 Updated Disclaimer.