VN5010AK-E STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 31

Technical content

Datasheet sections

  • 1 Block diagram and pin description
  • 2 Electrical specifications
  • 2.1 Absolute maximum ratings
  • 2.2 Electrical characteristics
  • 2.3 Electrical characteristics curves
  • 3 Application information
  • 3.1 GND protection network against reverse battery
  • 3.1.1 Solution 1 : resistor in the ground line (RGND only)
  • 3.1.2 Solution 2 : diode (DGND) in the ground line
  • 3.2 Load dump protection
  • 3.3 MCU I/Os protection
  • 3.4 Maximum demagnetization energy (V
  • 4 Package and PCB thermal data
  • 4.1 PowerSSO-24 TM thermal data
  • 5 Package information
  • 5.1 ECOPACK ® packages
  • 5.2 Packing information
  • 6 Revision history

Features

■ Main features – Inrush current active management by power limitation – Very low stand-by current – 3.0v CMOS compatible input – Optimized electromagnetic emission – Very low electromag netic susceptibility – In compliance with the 2002/95/EC European directive ■ Diagnostic functions – Proportional load current sense – High current sense precision for wide range currents – Current sense disable – Thermal shutdown indication – Very low current sense leakage ■ Protections – Undervoltage shut-down – Overvoltage clamp – Load current limitation – Self limiting of fast thermal transients – Protection against loss of ground and loss of V CC – Thermal shut down – Reverse battery protection (see Application schematic ) – Electrostatic discharge protection Application ■ All types of resistive, inductive and capacitive loads

Description

The VN5010AK-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut- down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears. Max supply voltage V CC 41V Operating voltage range V CC 4.5 to 36V Max On-State resistance R ON 10 mΩ Current limitation (typ) I LIMH 65A Off state supply current (typ) I S 2 µA PowerSSO-24TM Table 1. Device summary

1 Block diagram and pin description

Figure 1. Block diagram Table 2. Pin function SENSE Analog current sense pin, delivers a current proportional to the load current. CS_DIS Active high CMOS compatible pin, to disable the current sense pin.

Figure 2. Connection diagram (top view) Table 3. Suggested connections for unused and N.C. pins

2 Electrical specifications

Figure 3. Current and voltage conventions Note: V Fn = VOUT - VCC during reverse battery condition.

2.1 Absolute maximum ratings

and other relevant quality documents. Table 4. Absolute maximum ratings

Table 5. Thermal data Table 4. Absolute maximum ratings (continued)

2.2 Electrical characteristics

Table 6. Power section

  1. PowerMOS leakage included.

Table 7. Switching (V CC=13V)

Table 8. Logic input Table 9. Protections and diagnostics (1)

  1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related

abnormal conditions, this software must limit the duration and number of activation cycles.

Table 10. Current sense (8V<V CC<16V)

Figure 4. Current sense delay characteristics

  1. Parameter guaranteed by design; it is not tested.

Table 10. Current sense (8V<V CC<16V) (continued)

Figure 5. Delay response time between rising edge of ouput current and rising

Table 12. Electrical transient requirements

  1. The above test levels must be considered referred to V CC = 13.5V except for pulse 5b.
  2. Valid in case of external load dump clamp: 40V maximum referred to ground.

C All functions of the device are performed as designed after exposure to disturbance. disturbance and cannot be returned to proper operation without replacing the device.

Figure 10. Waveforms

2.3 Electrical characteristics curves

Figure 11. Off State output current Figure 12. High level input current Figure 13. Input clamp voltage Figure 14. Input low level Figure 15. Input high level Figure 16. Input hysteresis voltage

3 Application information

Figure 26. Application schematic

3.1 GND protection networ k against reverse battery

3.1.1 Solution 1 : resistor in the ground line (RGND only)

This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. maximum rating section of the device datasheet. maximum on-state currents of the different devices. high side drivers sharing the same RGND. the same resistor then ST suggests to utilize Solution 2 (see below).

3.1.2 Solution 2 : diode (D GND) in the ground line

A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (≈ 600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.

3.2 Load dump protection

Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.3 MCU I/Os protection

If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os. -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V 5kΩ ≤ Rprot ≤ 180kΩ Recommended values: Rprot =10kΩ, CEXT=10nF.

Figure 27. Maximum turn Off current versus load inductance Note: Values are generated with R L=0 Ω. must not exceed the temperature specified above for curves B and C.

4 Package and PCB thermal data

4.1 PowerSSO-24 TM thermal data

Figure 28. PowerSSO-24 TM PC board Figure 29. R thj-amb Vs. PCB copper area in open box free air condition

Table 13. Thermal parameters

5 Package and packing information

5.1 ECOPACK ® packages

conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 32. PowerSSO-24™ package dimensions

Table 14. PowerSSO-24™ mechanical data

5.2 Packing information

Figure 33. PowerSSO-24 TM tube shipment (no suffix) Figure 34. PowerSSO-24 TM tape and reel shipment (suffix “TR”)

6 Revision history

Table 15. Document revision history 24-Jan-2006 1 Initial release. Reformatted and restructured. Added Contents, List of tables and List of figures. Added Section 3.4: Maximum demagnetization energy (VCC=13.5V). Document reformatted and restructured. – changed tDSENSE2H max value from 600 to 500 µs. – added dk1/k1, dk2/k2, dk3/k3, ∆tDSENSE2H, IOL parameters. current and rising edge of Current Sense (CS enabled). Added Figure 7: Maximum current sense ratio drift vs load current. III and IV for test pulse 5b and notes. changed IOL test condition from VIN = 0V to VIN = 5V.