VHG80A

DP84910_11 TI1 | Alldatasheet

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Technical content

DP84910,DP84910-36,DP84910-50 DP84910 DP84910-36 DP84910-50 Integrated Read Channel Literature Number: SNOS685A

chronizes the data with the system clock. chip frequency setting components or DACs. FIGURE 1. DP84910 in a Typical Disk Drive System MICROWIRETM is a trademark of National Semiconductor Corporation.

General Description (Continued) The pulse detector section detects the peaks of the analog pulses from the read preamplifier and converts them to digi- tal pulses whose leading edges represent the time position of the analog pulses’ peaks. In order to not interpret noise on the baseline as input data, hysteresis is included. The hysteresis level for a data field is set at the SETHYSD pin while the hysteresis level for a servo field is set at the SETHYSS pin. A third pin (SFIELD) is used to select be- tween these two levels of hysteresis. This allows for the setting of different hysteresis levels for these two fields. The data field hysteresis level is also selectable in 8 steps through bits in the control register (HYS ÐVTH0–HYS Ð VTH2) with the level set at the SETHYSD pin as the nominal value. The pulse detector section includes an automatic gain con- trol (AGC) circuit which normalizes the analog data signal to a constant amplitude. The response of the AGC is partially controlled by one of the device’s pins (VAGCIN). Two VAGCIN pins (VAGCIND, VAGCINS) are provided so that different capacitor values can be selected to provide differ- ent AGC time constants for data and servo field information. The switching between these pins/capacitors is controlled by the SFIELD pin. The SERVO control register bit can en- able (or disable) the SFIELD pin’s ability to control the amount of equalization provided to the on-chip channel fil- ter. When enabled, the state of the SFIELD pin selects be- tween two groups of control register bits (EQ0, EQ1, EQ2 and SERVO ÐEQ0, SERVO ÐEQ1, SERVO ÐEQ2) which can separately determine the amount of equalization provid- ed. This feature allows for an adjustment of the channel filter bandwidth in a servo field. Thus the channel filter can have different bandwidths in a servo field and a data field. The pulse detector section has a delayed, low impedance switch at the gain controlled amplifier inputs (AMPIN1, AM- PIN2) which allows for rapid recovery from the write mode. The amount of delay (either 1.7 mso r3 . 4 ms) coming out of the low impedance mode is selectable through a bit in the control register (SLOW ). A pattern insensitive, fast respond- ing AGC circuit (with HOLD function) allows rapid head switch settling and embedded servo normalization. Select- able delay (in four steps) in the qualification channel, along with a ‘‘view internal signals’’ mode, allow the timing and qualification channels to be optimally aligned. Four gated servo detectors are incorporated for recovery of quadrature embedded servo information. The four peak detected val- ues are available at the SERVO CAPACITOR outputs (SCAP1–4). Two servo difference amplifiers are provided. Each difference amplifier output (DIFFAMP1/2) provides the difference between two of the servo peak detectors, centered about an external reference voltage (VDIFF). The channel filter section is a seven-pole 0.05 degree error, equal ripple filter. It utilizes the Kost pulse slimming tech- nique similar to that which is employed on the DP8491/92 integrated read channel devices. The amount of pulse slim- ming is control register selectable in 8 steps up to a maxi- mum of 9 dB measured from the base frequency. The band- width of the filter is derived from the XTLIN frequency; from this point, the b3 dB frequency is selectable via 7 bits in the control register (FILT Ð3d B Ð0–FILT Ð3d B Ð6). The data synchronizer section incorporates zero-phase- start (ZPS) and digitally controlled window strobe functions. The voltage controlled oscillator (VCO) is fully integrated, requiring no external components, and provides a wide dy- namic range necessary for zoned data rate applications. Data windowing is based on precise VCO duty cycle sym- metry (in contrast to delay line based centering). An internal silicon delay line, used to establish the phase detector re- trace angle, automatically tracks zoned data recording data rate changes. The charge pump output (CPO) and voltage controlled oscillator input (VCOI) are provided as separate pins, allowing ample design flexibility in the external loop filter. Frequency lock may be employed within the synchro- nization field. Charge pump (phase detector) gain may be selected to remain constant or to vary either by a factor of two or four as instructed via the charge pump gain pin (CPGAIN) and a bit in the control register (CPRATIO). The frequency synthesizer section, capable of producing a large number of frequencies from a single external refer- ence source, generates the write clock and reference fre- quency for the synchronizer. This section includes a phase locked loop (PLL) with selectable dividers at the input port and in its feedback loop. The values for the dividers are controlled by two control words within the control register. The user has full control over both the input (five bit word, PDATA6–PDATA10) and feedback (six bit word, PDATA0– PDATA5) divider selection. The feedback divider has an ex- tra bit when compared to previous NSC integrated read channel circuits to improve the resolution of frequency set- ting. All blocks within the synthesizer, except the RC loop filter, are fully integrated. The loop filter resides external to the chip giving the user full control over the phase locked loop’s dynamics. This device is available in an 80-pin 12 mm x 12 mm PQFP package and operates off of a single a5V supply.

Features

Y Operates at NRZ data rates up to 50 Mbits/sec (equiv- alent 2/3 (1,7) code data rate) Y Operates with a single a 5V power supply Y Multiple power down modes available with dedicated SLEEP and IDLE/SERVO power down pins Y Sleep mode included where I CC e 2 mA maximum Y Directly addresses zoned data recording requirements Ð Integrated channel filter with selectable equalization and bandwidth eliminates multiple external filter ele- ments Ð Fully integrated frequency synthesizer on-chip to pro- vide write clock and center frequency for the syn- chronizer Y Selectable delay impedance switch (clamp) at pulse de- tector input for rapid recovery from the write mode Y Pattern insensitive fast AGC for rapid head switch set- tling and embedded servo normalization Y Built-in AGC hold for embedded servo Y Two AGC control voltage pins providedÐone for servo field and one for data field Y Four gated detectors for quadrature embedded servo information Y Two servo difference amplifiers on-chip http:/ /www.national.com 2 Obsolete

Features (Continued) Y Reference voltage input pin provided for the servo dif- ference amplifiers Y Two selectable hysteresis control pins providedÐone for servo field and one for data field Y Data field hysteresis level is control register selectable in eight steps Y Logic polarity for write gate assertion is control register selectable Y Capability provided for different channel filter band- widths for servo and data fieldsÐchange on the fly with no settling issues Y Selectable qualification channel delay Y Dual gain synchronizer requiring no external or internal center frequency setting components, external adjust- ments, or precision components Y Digitally controlled synchronizer window strobing Y Zero-phase-start synchronizer lock acquisition Y Two port synchronizer PLL filtering Y Frequency lock option for 2T or 3T synchronization field (preamble) Y TTL compatible inputs and outputs Y Chip configurable through serial port interface General Block Diagram TL/F/11777–2 FIGURE 2 http:/ /www.national.com3 Obsolete

Note: Make no external connections to the NSC test pins. TL/F/11777–3 Order Number DP84910VHG-36 or DP84910VHG-50 See NS Package Number VHG80A FIGURE 3 Pin Definitions Pin Ý Description POWER SUPPLY AND GROUND PINS

16 INPUT/OUPUT BUFFER SUPPLY VOLTAGE (BVCC): 5V a5/b10%

17, 18, 20 INPUT/OUTPUT BUFFER GROUNDS (BGND)

24 PLL DIGITAL SUPPLY VOLTAGE (DVCC): 5V a5/b10%

25 PLL DIGITAL GROUND (DGND)

33 PULSE DETECTOR DIGITAL SUPPLY VOLTAGE (PDVCC): 5V a5/b10%

35 PULSE DETECTOR DIGITAL GROUND (PDGND)

http:/ /www.national.com 4 Obsolete

Pin Definitions (Continued) Pin Ý Description POWER SUPPLY AND GROUND PINS (Continued)

65 PULSE DETECTOR ANALOG SUPPLY VOLTAGE (PAVCC): 5V a5/b10%

66 PULSE DETECTOR ANALOG GROUND (PAGND)

68 FILTER ANALOG SUPPLY VOLTAGE (FVCC): 5V a5/b10%

69 FILTER ANALOG GROUND (FGND)

72 SYNCHRONIZER PLL ANALOG SUPPLY VOLTAGE (SYCVCC): 5V a5/b10%

75 SYNCHRONIZER PLL ANALOG GROUND (SYCGND)

78 SYNTHESIZER PLL ANALOG SUPPLY VOLTAGE (STHVCC): 5V a5/b10%

80 SYNTHESIZER PLL ANALOG GROUND (STHGND)

1 WRITE GATE INPUT (WG): This pin receives the write mode control input signal from the controller. The logic polarity for WG assertion is selectable via a bit in the control register (INV ÐWG, Bank (1,1) bit 5). WG is active low if the control register bit is set to invert (INV ÐWG e 1). When WG is active, the pulse detector inputs (AMPIN1 and AMPIN2) are held in a low impedance state and the automatic gain control of the puIse detector is in the hold mode. There are no setup or hold timing restrictions on WG enabling or disabling. 2 IDLE/SERVO BAR POWER DOWN INPUT (IDLE/SERVO ): This input controls the power status of the servo detection circuitry in the pulse detector. When high (idle mode), this pin powers down all pulse detector circuitry except for biasing circuitry necessary for quick recovery ( k 15 ms) from this mode. When low (servo mode), this pin powers on the circuitry necessary for servo information detection in the puIse detector. The synchronizer and synthesizer power are unaffected by this pin. The controI register power is also unaffected by the IDLE/SERVO pin but its input buffers are. The control register’s input’s are only powered on when the IDLE/SERVO pin is low. Thus, the controI register cannot be loaded when the IDLE/SERVO pin is high. The contents of the controI register is not affected by the state of the IDLE/SERVO pin. 3 SLEEP BAR POWER DOWN INPUT (SLEEP ): This active low input powers down aIl circuitry on the chip. The control register is powered down in this mode thus it does not retain its information. The control register wiII be reset to the initial power-on conditions when exiting the sleep mode. The maximum supply current in the sleep mode is 2 mA.

4 CONTROL REGISTER LATCH/SHIFT BAR INPUT (CRL/S ): A logical low on this input allows the CONTROL

REGISTER CLOCK input to shift data into the control register’s shift register via the CONTROL REGISTER DATA input. A positive transition latches the data into the addressed bank of latches and issues the information to the appropriate circuitry within the device. To minimize power consumption, this pin should be kept at a logical high state except when shifting data into the control register. The SLEEP and IDLE/SERVO pins must be disabled (SLEEP e high and IDLE/SERVO e low) in order to shift data into the control register. 5 CONTROL REGISTER DATA INPUT (CRD): ControI register data input. 6 CONTROL REGISTER CLOCK INPUT (CRC): Positive-edge-active control register clock input. 7 FREQUENCY LOCK CONTROL BAR INPUT (FLC ): This input enables or disables the frequency lock function during a read operation. It has no effect when READ GATE is disabled. Frequency lock is automatically employed for the full duration of the time READ GATE is disabled regardless of the level of this input. When READ GATE is taken to a logical high level while FLC is at a logical low level (frequency lock enabled), the PLL is forced to lock to the pattern frequency (2T or 3T sync. field) selected in the control register (PREAM Ð2T, Bank (1,1) bit 4). When FLC is taken to a logical high level, the frequency lock action is terminated and the PLL employs a pulse gate to accommodate random disk data patterns. There are no setup or hold timing restrictions on the positive-going transition of FLC 8 PREAMBLE DETECTED OUTPUT (PDT): This output issues a logical high state after the following sequence; the enabling of READ GATE, the completion of the zero-phase-start sequence and the detection of approximately 16 sequential pulses of 2T or 3T preamble. Following preamble detection, this output remains latched high until READ GATE is disabled. This output will be at a logical low state whenever READ GATE is inactive (low). 9 READ GATE INPUT (RG): This input receives the read mode control input signal from the controller, active high for a read operation. There are no setup or hold timing restrictions on RG enabling or disabling. 10 DELAY LINE OUTPUT (DLO): This active low, open collector output pin issues encoded read data (ERD) delayed by the selected value in the delay line at the input to the synchronizing latch. By viewing this signal’s phase, the user can directly view the amount of window movement as the control register’s strobe bits are changed. http:/ /www.national.com5 Obsolete

Pin Definitions (Continued) Pin Ý Description TTL LEVEL LOGIC PINS (Continued)

11 ENCODED READ DATA OUTPUT (ERDO): This output issues the raw, pulsed output of the pulse detector when

enabled by the control register bits ERD0 and ERD1 (Bank (1,1), bits 3 and 4). When disabled (see Table III) this output will be high. When enabled, the pulsed data from the pulse detector can continue to be issued to the synchronizer depending on the combination of states of the ERD0 and ERD1 control register bits. When both the ERD0 and ERD1 control register bits are high, the part is put into a test mode where the gain of the GCA is held constant (i.e. fixed gain mode). In this test mode the synchronizer and synthesizer VCOs can be driven by external test signals. 12 ENCODED READ DATA INPUT (ERDIN): This pin is the input to the synchronizer. It is enabled/disabled via control register bits ERD0 and ERD1 (Bank (1,1), bits 2 and 3). When enabled (see Table III), this buffer admits external pulsed data to the synchronizer via this pin and raw data output from the pulse detector is NOT internally fed to the synchronizer. This allows for testing/exercising of the synchronizer, or for external processing of the peak-detected data prior to being fed to the synchronizer. When ERDO is disabled, the pulse detector’s data is fed internally to the synchronizer. When both the ERD0 and ERD1 control register bits are high, the part is put into a test mode where the gain controlled amplifier is put into a fixed gain. In this test mode the synchronizer and synthesizer VCOs can be driven by external test signals. 14 SYNCHRONIZED DATA OUTPUT (SDO): This output issues resynchronized data directly from the synchronizing PLL block. 15 MULTIPLEXED SYNCHRONIZED CLOCK OUTPUT (SCLK): This output issues either the synchronizer or synthesizer clock signal dependent on whether the device is in the read or non-read mode. The synchronizer clock is selected during read mode while the synthesizer clock is selected during non-read mode. Multiplexing is done without glitches. 19 CRYSTAL INPUT (XTLIN): This input is the synthesizer and filter reference frequency input. It is designed for connection from a TTL frequency source. Duty cycle is not critical. An input attenuation resistor is normally used to minimize transient noise at this pin. 21 POLARITY OUTPUT (POLOUT): This TTL output issues a signal that is the output of the pulse detector’s comparator with hysteresis. The logical polarity of this signal corresponds to the polarity of the signal at the channel input pins. 22 SYNTHESIZER REFERENCE OUTPUT (SYNTH): This output issues a continuous reference signal from the frequency synthesizer when enabled. At V CC power up this pin is in the inactive state (a logical high state) and can be enabled via a bit in the control register (ENSTHO , Bank (1,0) bit 5). The output frequency will be the same as the media code clock rate. 23 CONTROL REGISTER DATA OUTPUT (CRDO): This output issues data from the control register. It can be connected to the input of another device’s control register such as the DP84900 (ENDEC) so that the number of data lines from the controller can be minimized. 27–30 SERVO SWITCH INPUTS Ý1, Ý2, Ý3, Ý4 (S1, S2, S3, S4): These pins, in conjunction with the AGC HOLD pin, control the gating action of the gated servo peak detectors and the discharge of the servo channeIs. These pins also enabIe or disabIe the output internal signals, the track follow and the seek modes according to Table IV. 31 SERVO FIELD SELECT INPUT (SFIELD): When at a high logic level, this pin switches the hysteresis threshold control of the puIse detector’s comparator from the SET HYSTERESIS-DATA FIELD (SETHYSD) pin to the SET HYSTERESIS-SERVO FIELD (SETHYSS) pin. It also switches the AGC controI from the AGC control capacitor-data field (VAGCIND) pin to the AGC control capacitor-servo field (VAGCINS) pin. When enabled by a control register bit (SERVO e 1, Bank (0,0) bit 12), this pin can switch the equalization, and consequently the bandwidth of the channel filter, between data equalization control bits (EQ0, EQ1, EQ2, Bank (0,0) bits 9, 10, 11) and servo equalization control bits (SERVO ÐEQ0, SERVO ÐEQ1 SERVO ÐEQ2, Bank (1,1) bits 10, 11, 12). 36 OPTICAL: The optical (unipolar) mode is enabled by the application of ground to this pin. For magnetic operation this pin must be left open (no connection to it). Refer to design guide for details of operation. 67 COAST/AGC HOLD INPUT (HOLD): When high, this input controls an internal switch which freezes the pulse detector AGC level for the reading of the servo burst. Phase comparisons within the synchronizer (read mode only) are also disabled, allowing the PLL to coast. 77 CHARGE PUMP GAIN INPUT (CPGAIN): This input selects the gain of the synchronizer’s charge pump in conjunction with a bit in the control register (CPRATIO, Bank (1,0) bit 12) (see Table VIII). http:/ /www.national.com 6 Obsolete

Pin Definitions (Continued) Pin Ý Description ANALOG SIGNAL PINS 32 VPHASE: An internally generated voltage is present at his pin to control the Q of the integrated filter. An external network (24 k X to FV CC and 18 k X to GND) should be connected to this pin to optimize the filter’s performance. 34 FILTER CHARGE PUMP OUTPUT/VCO INPUT NODE (FCPO/VCOI): This is the filter node for the channel filter PLL. An externaI resistor and capacitor loop filter is tied in series between this pin and ground. 37 SERVO CAPACITOR Ý4 (SCAP4): This pin is the connection point for the peak detector capacitor for the embedded servo gated detector. The DC level on this capacitor represents the amplitude of one of four servo bursts. When the ‘‘output internal signals’’ mode is selected by applying a high logical level to the S2 pin and a low logical level on the HOLD pin, the signal on this pin becomes the output of the seIectable delay block in the qualification channel (see Table IV). 38 SERVO CAPACITOR Ý3 (SCAP3): This pin is the connection point for the peak detector capacitor for the embedded servo gated detector. The DC level on this capacitor represents the amplitude of one of four servo bursts. When the ‘‘output internal signals’’ mode is selected by applying a high logical level to the S2 pin and a low logical level on the HOLD pin, the signal on this pin becomes the output of the time channel zero-cross detector (see Table IV). 39 SERVO CAPACITOR Ý2 (SCAP2): This pin is the connection point for the peak detector capacitor for the embedded servo gated detector. The DC level on this capacitor represents the amplitude of one of four servo bursts. When the ‘‘output internal signals’’ mode is selected by applying a high logical level to the S2 pin and a low logical Ievel on the HOLD pin, the signal on this pin becomes one of the differential outputs of the differentiator (see Table IV). 40 SERVO CAPACITOR Ý1 (SCAP1): This pin is the connection point for the peak detector capacitor for the embedded servo gated detector. The DC level on this capacitor represents the amplitude of one of four servo bursts. When the ‘‘output internal signals’’ mode is selected by applying a high logical level to the S2 pin and a low logical level on the HOLD pin, the signal on this pin becomes one of the differential outputs of the differentiator (see Table IV). 41, 42 SERVO DIFFERENCE AMPLIFIERS OUTPUTS Ý1, Ý2 (DIFAMP1, DIFAMP2): These low impedance pins issue an output signal which is the difference in voltage between SCAP4 and SCAP3 pins (DIFAMP2) and SCAP2 and SCAP1 pins (DIFAMP1). These differences will be centered about a reference level set by the voltage on the VDlFF pin. 43 SERVO DIFFERENCE VOLTAGE REFERENCE INPUT (VDIFF): A voltage applied to this pin provides a reference for the zero-level of the signals issued by the difference amplifiers on DIFAMP1 and DIFAMP2 pins. 45, 46 DIFFERENTIATOR CAPACITOR NODES Ý1, Ý2 (DIFC1, DIFC2): These pins are connection points for the differentiator components (typically a resistor, capacitor, and inductor). 48, 49 GAIN CONTROLLED AMPLIFIER OUTPUTS Ý1, Ý2 (AMPOUT1, AMPOUT2): These pins are complimentary emitter follower outputs from the gain controlled amplifier. They are to be externally capacitively coupIed to the channel filter inputs (FIN1, FIN2). 50, 51 FILTER INPUTS Ý2, Ý1 (FIN2, FIN1): These channel filter inputs are to be externally capacitively coupled to the gain controlled amplifier outputs (AMPOUT1, AMPOUT2). 53, 54 FILTER OUTPUTS Ý1, Ý2 (FOUT1, FOUT2): These pins are complimentary emitter foIIower outputs from the channeI filter. They are to be externally capacitively coupled to the timing-gating channel/AGC sense/servo channel inputs (CHAN1, CHAN2). 55, 56 TIMING-GATING CHANNEL/AGC SENSE/SERVO INPUTS Ý2, Ý1 (CHAN2, CHAN1): These input pins are to be externally capacitively coupled from the channel filter outputs (FOUT1, FOUT2). These pins are the inputs to the differentiator, AGC amplifier, servo channel and qualification channel. 57 SET HYSTERESIS INPUT-SERVO FIELD (SETHYSS): When activated by a logical high level on the SFIELD pin, the voltage applied to this pin determines the amount of hysteresis for the pulse detector’s hysteresis comparator. This level should be set high enough to eliminate noise which might occur in the shoulder region between read pulses from the preamplifier. The SVCC pin is provided to be used as a supply reference for a resistive divider to set this level. 58 SET HYSTERESIS INPUT-DATA FIELD (SETHYSD): When activated by a logical low level on the SFlELD pin, the voltage applied to this pin in conjunction with three control register bits (HYS ÐVTH0, HYS ÐVTH1, HYS ÐVTH2, Bank (1,1), bits 7, 8, 9) determines the amount of hysteresis for the pulse detector’s hysteresis comparator. This level should be set high enough to eliminate noise which might occur in the shouIder region between read pulses from the preamplifier. The SVCC pin is provided to be used as a supply reference for a resistive divider to set this level.

59 SERVO FIELD AUTOMATIC GAIN CONTROL VOLTAGE INPUT (VAGCINS): When activated by a logical high level

on the SFIELD pin, the voltage at this pin controls the gain of the gain controlled amplifier. http:/ /www.national.com7 Obsolete

Pin Definitions (Continued) Pin Ý Description ANALOG SIGNAL PINS (Continued)

60 DATA FIELD AUTOMATIC GAIN CONTROL VOLTAGE INPUT (VAGCIND): When activated by a logical low level on

the SFIELD pin, the voltage at this pin controls the gain of the gain controlled amplifier. 62, 63 AMPLIFIER INPUTS Ý2, Ý1 (AMPIN2, AMPIN1): These inputs accept the preamplified, analog, coded data signal read from the disk. They are to be externally capacitively coupled from the preamplifier. They go to a low impedance state when WRITE GATE is enabled and remain low impedance for either 1.7 mso r3 . 4 ms (selectable by control register bit, SLOW , Bank (1,1) bit 6, 0 e 3.4 ms) after WRITE GATE is disabled. This low impedance state is used to remove DC offsets accumulated across the amplifier input coupling capacitors during the write mode.

64 AGC REFERENCE VOLTAGE INPUT (VREF): This input provides the reference voltage to the AGC circuit for

controlling the peak-to-peak signal swing at the channel input pins. The voltage on this pin corresponds directly to the peak-to-peak channel input signal level. A resistor divider between supply and ground can be used to provide this voltage. The SVCC pin is provided to be used as a supply reference. 70 SWITCHED SUPPLY VOLTAGE (SVCC): This emitter-follower output may be used as the supply for the external VREF resistor voltage divider and for both the external servo and data hysteresis resistor voltage dividers. The voltage at this pin will typically be V CC b 1V. The voltage at this pin goes low in the sleep mode. 71 DISCHARGE CAPACITOR (DISCAP): A capacitor is tied from this pin to ground to establish an RC time constant which sets the minimum operational frequency and decay characteristics of the AGC. The voltage at this pin can also be used for dynamic hysteresis. Note, unlike the DP8491/92 which requires an RC combination tied to this pin, the DISCAP pin has an internal 10 k X resistor connected to ground. Thus, only an external capacitor is required to set the RC time constant. 73 VOLTAGE CONTROLLED OSCILLATOR INPUT (VCOI): This pin is the input to the voltage control block for the synchronizer VCO and is to be connected to the external loop filter output. 74 CHARGE PUMP OUTPUT (CPO): This pin issues the signal from the synchronizer PLL charge pump and is to be connected to the external loop filter input. 76 RNOMINAL (RNOM): A resistor connected from this pin to ground sets the synchronizer charge pump current. 79 TIMING EXTRACTOR FILTER (TEF): This pin is the filter node for the synthesizer phase locked loop (PLL). An external resistor and capacitor loop filter is tied in series between this pin and ground. http:/ /www.national.com 8 Obsolete

The DP84910 has several methods available to control or manage device power consumption. Three control register bits and two pins are provided to control the power status of elements in this device. The control register bits control the power status of the pulse detector (PD ÐPWRÐDN, Bank (1,0) bit 4), synchronizer (SYNC Ð PWRÐDN, Bank (1,0) bit 2) and synthesizer (STH ÐPWRÐDN, Bank (1,0) bit 3). The device is configured to initially power up with the synchroniz- er, synthesizer and pulse detector powered down. The con- trol register power is controlled only by the SLEEP pin. The SLEEP pin is one of the two pins available for power management. This pin powers down all circuitry on the chip including the control register. In this mode the maximum power supply current is 2 mA. The control register latches are preset into specific states when exiting the sleep mode. The shift register flip-flops, however, are in indeterminate states until all 13 bits have been shifted in. Note that if the CRL/S input is given a positive transition after exiting the sleep mode but before valid data has been entered into the shift register, the indeterminate contents of the shift reg- ister will be randomly loaded into one of the four banks of latches. Although the sleep mode can be safely exited with the CRL/S pin either high or low, valid data must be loaded into the shift register before CRL/S is given a positive tran- sition. The IDLE/SERVO pin is the second of the two pins avail- able for power management. This pin toggles the device between the idle and servo modes. In the idle mode, only the control register and pulse detector biasing circuitry nec- essary for a quick recovery from the power down mode are active. In the servo mode, the pulse detector portions need- ed for servo detection are active as well as the control regis- ter. Less than 15 ms is required for the pulse detector to recover from the idle condition. The control register data is not lost when this pin is toggled. This pin does not control the power status of the synchronizer or synthesizer. To achieve maximum power savings during extended servo- only activity, the synchronizer and synthesizer should be powered down. TABLE I. Selective Power Down Truth Table SLEEP Pin SERVO IDLE/ Pin Ctrl Reg. Power Status by BlockBank (1,0) B4 B3 B2 PD & CR SYNCH SYNTHSERVO

0 X X X X OFF OFF OFF OFF

1 1 0 0 0 OFF * ON** ON ON 1 1 0 0 1 OFF * ON** OFF ON 1 1 0 1 0 OFF * ON** ON OFF 1 1 0 1 1 OFF * ON** OFF OFF 10 0 0 0 O N O N O N O N 1 0 0 0 1 ON ON OFF ON 1 0 0 1 0 ON ON ON OFF 1 0 0 1 1 ON ON OFF OFF

1 X 1 0 0 OFF ON ** ON ON

1 X 1 0 1 OFF ON ** OFF ON

1 X 1 1 0 OFF ON ** ON OFF

1 X 1 1 1 OFF ON ** OFF OFF

*Except for pulse detector circuitry biasing necessary for quick recovery from power down mode. **Control register buffers powered down. Data in register will not be affected but new data cannot be loaded into register when IDLE/SERVO is high. http:/ /www.national.com9 Obsolete

Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Char- acterisitics’’ tables are not guaranteed at these ratings. The ‘‘Operating Conditions’’ table will define the conditions for actual device operation. Supply Voltage 7V TTL Input Maximum Voltage 7V Maximum Output Voltage 7V Maximum Input Current (Analog Pins) 2 mA (or as specified on per-pin basis) ESD Susceptibility 1500V (Note 1) Operating Conditions guaranteed over operating temperature and supply voltage ranges unless otherwise speci- fied. Minimum and/or maximum limits are guaranteed by outgoing testing unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units(Note 3) VCC Supply Voltage 4.5 5.0 5.5 V TA Operation Ambient Temperature 0 70 §C TS Storage Temperature b65 150 §C IOH High Logic Level Output Current for TTL Outputs (Note 2) b400 mA IOL Low Logic Level Output Current for TTL Outputs (Note 2) 8 mA VIH High Logic Level Input Voltage 2 V VIL Low Logic Level Input Voltage 0.8 V CL Capacitive Load on Any TTL Output (Note 2) 15 pF fNRZ NRZ Transfer Rate Operating Frequency -36 7.5 36 Mb/s -50 13.7 50 fVCO Synchronizer VCO Operating Frequency (Note 2) 1.5 f NRZ MHz fSTH Synthesizer VCO Operating Frequency (Note 2) 1.5 f NRZ MHz fXTL Crystal Input Operating Frequency (Note 2) 20 MHz tPWH(XTL) Width of XTLIN Pulse (High) 20 ns tPWL(XTL) Width of XTLIN Pulse (Low) 20 ns tPWH(ERDIN) Width of ERDIN Pulse (High) 15 9 ns tPWL(ERDIN) Width of ERDIN Pulse (Low) 10 5 ns tPW(CRL/S) Width of CRL/S Pulse (High or Low) (Note 2) 50 ns tSU(CRD) CRD Setup Time with Respect to CRC (Note 2) 20 ns tH(CRD) CRD Hold Time with Respect to CRC (Note 2) 20 ns tSU(CRL/S) CRL/S Setup Time with Respect to CRC (Note 2) 200 ns tH(CRL/S) CRL/S Hold Time with Respect to CRC (Note 2) 20 ns tPW(CRC) CRC Pulse Width (High or Low) (Note 2) 25 ns IRNOM RNOM Pin Current 90 130 170 mA Note 1: Human body model is used. (120 pF through 1.5 k X) Note 2: Parameter guaranteed by design or correlation data. No outgoing tests are performed. Note 3: Typical values are specified at 25 §C and 5V supply. http:/ /www.national.com 10 Obsolete

erwise specified. Minimum and/or maximum limits are guaranteed by outgoing testing unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units(Note 3) VIC Input Clamp Voltage V CC e Min, I I eb 18 mA b0.65 1 b1.5 V VOH High Logic Level V CC e Min, I OH e Max VCC b 2V CC b 1.6 VOutput Voltage VOL Low Logic Level V CC e Min, I OL e Max 0.25 0.5 VOutput Voltage IIH High Logic Level V CC e Max, V I e 2.7V 12 0 mAInput Current IIL Low Logic Level V CC e Max, V I e 0.4V b60 b200 mAInput Current IO Output Drive Current V CC e Max, V O e 2.125V (Note 1) b12 b110 mA ICPO Charge Pump Output (Note 2) 0.8 K 1IIN K1IIN 1.2 K 1IINCurrent IDRIFT Combined Charge Charge Pump Inactive, CPO and VCOI pins tied togetherPump Output Inactive Current and 1V k VCPO k 2.5V b1.2 1.2 mA VCOI OFFSET Current ITEF TEF Output Current 1V k VTEF k 2.5V 250 800 mA(Absolute Value) ITEF-OFF TEF Output Inactive 1V k VTEF k 2.5V b11 mACurrent VRNOM Voltage at RNOM Pin I RNOM e 125 mA, 25 §C only 0.6 0.75 0.9 V VCPO(PD) CPO Voltage with b5 mA k ICPO k 5 mA 1.1 1.5 2 VSynchronizer Powered Down VTEF(PD) TEF Voltage with b5 mA k ITEF k 5 mA 1.1 1.5 2 VSynthesizer Powered Down ICCR Supply Current in the V(WG) e 0.3V, All Sections 16.7 Mb/s 160 190 mA Read Mode Powered On. V CC e 5.25V 33.3 Mb/s 175 200 mA

50 Mb/s 200 220 mA

ICC(SLEEP) Supply Current in V(SLEEP ) e 0.8V, V CC e 5.25V 1 2.5 mASleep Mode ICC(IDLE) Supply Current in Idle V(WG) e 0.3V Power Down 10 20 mASynchronizer and Synthesizer SectionsMode of the Chip Via Control Register. Power Down Pulse Detector with IDLE Pin. VCC e 5.25V ICC(PD) Pulse Detector V(WG) e 0.3V. Power Down All Sections 110 mAof the Chip Via Control Register ExceptSupply Current with the Pulse Detector. V CC e 5.25VAll Other Sections Powered Down VSVCC Switched Supply SLEEP e HIGH. Pull 1 mA from SVCC VCC b 1.1 V CC b 1V CC b 0.9 Vpin.(SVCC) Output Voltage Note 1: VO e 2.125V produces a current closely approximating one half of the true short circuit current, I OS. Note 2: K1 is the selected charge pump gain constant (2, 4 or 8), I IN e IRNOM,1 V k VCPO k 2.5V. Note 3: Typical values are specified at 25 §C and 5V supply. http:/ /www.national.com11 Obsolete

operating conditions (see table) unless otherwise specified. Minimum and/or maximum limits are guaranteed by outgoing testing unless otherwise specified. Symbol Circuit Parameter Conditions Min Typ Max UnitsBlock (Note 24) ZIN-AL GCA Amplifier Input Impedance Nonwrite Mode (Note 1) 2 2.4 2.8 k X(AMPIN1, AMPIN2) AVA(MAX) GCA Maximum Amplifier Gain V VAGCIN e 1V (Note 2) 50 V/V AVA(MIN) GCA Minimum Amplifier Gain V VAGCIN e 4V (Note 2) 0.1 0.5 V/V AVA(FG) GCA Amplifier Gain in Fixed Control Register Programmed 8 11 13 V/VGain Mode for Fixed Gain Mode (Note 2) VAob GCA Amplifier Output DC Bias 3 3.4 4.4 VLevel VTH(AGC) AGC AGC Threshold Voltage V REF e 0.5V, 425 500 575 mV PPVVAGCIN e 2.5V (Note 3) GmAGC AGC AGC Transconductance V VAGCIN e 2.5V (Note 4) 0.7 1 1.3 mA/V bIAGC(SLEW) AGC AGC Slew Current lVCHAN1 b VCHAN2l e 0.5V, (Flowing out of either V VAGCIN e 2.5V, V REF e 0.5V b400 b240 b180 mA VAGCINS or VAGCIND) IAGC(SLEW) AGC AGC Slew Current lVCHAN1 b VCHAN2l e 0V, (Flowing into either V VAGCIN e 2.5V, V REF e 0.5V 200 240 400 mA VAGCINS or VAGCIND) FSBP AGC Fast Slew Break Point for V VACGIN e 2.5V (Note 5) 20 30 40 %AGC V REF e 0.5V VDISCAP AGC Discharge Capacitor Measurement Made at 1.3 1.8 2.4 VVoltage V THAGC (Note 23) ILEAK(AGC)H AGC AGC Leakage Current in HOLD e High, V VAGCIN e 0.02 0.09 mAAGC Hold Mode 2.5V (Note 6) ILEAK(AGC)W AGC AGC Leakage Current Pulse Detector Placed in Write 0.02 0.03 mAWrite Mode Mode. V VAGCIN e 2.5V (Note 6) ILEAK(AGC)ID AGC AGC Leakage Current in Pulse Detector is in Idle Mode. 0.02 0.07 mAIdle Mode V VAGCIN e 2.5V (Note 6) ZDISCAP AGC DISCAP Pin Impedence Force 2V on the DISCAP Pin 71 1 1 5 k Xand Measure the Impedence ZIN(AL)W AMP. Amplifier Input Impedance (Note 1) 65 100 XCLAMP in Write Mode Iclamp(sink) AMP. Amplifier Input Clamp (Note 7) 91 1 m ACLAMP Sink Current Iclamp(source) AMP. Amplifier Input Clamp (Note 8) 91 2 m ACLAMP Source Current ZIN(CH) CHAN. Channel Input Impedance (Note 1) 4.4 4.7 5 k XINPUTS H/R(D) CHAN. Ratio of the Data Field See Conditions for 0.25 0.37 0.45INPUTS Hysteresis Threshold to V THHYSD(101) and V TH(AGC) the AGC Threshold (Note 10) H/R(S) CHAN. Ratio of the Servo Field See Conditions for 0.25 0.36 0.45INPUTS Hysteresis Threshold to V TH(HYSTS) and V TH(AGC) the AGC Threshold (Note 10) http:/ /www.national.com 12 Obsolete

operating conditions (see table) unless otherwise specified. Minimum and/or maximum limits are guaranteed by outgoing testing unless otherwise specified. (Continued) Symbol Circuit Parameter Conditions Min Typ Max UnitsBlock (Note 24) ISETHYS CHAN. Set Hysteresis Input Bias V SETHYSD e VSETHYSS e 0.45V b38 b24 mAINPUTS Current (Note 11) IVREF CHAN. VREF Input Bias Current V REF e 0.5V b30 b15.5 mAINPUTS Vth(HYSTS) CHAN. Hysteresis Comparator (Note 9) 194 239 mVPPINPUTS Threshold Voltage for Servo Hysteresis Level VthHYSD(111) CHAN. Data Field Hysteresis Ctrl Reg. Bits: HYS ÐVTHO e 1, INPUTS Comparator Threshold HYS ÐVTH1 e HYSÐVTH2 e 1 133 159 mV PP Voltage (Note 9) VthHYSD(110) CHAN. Data Field Hysteresis Ctrl Reg. Bits: HYS ÐVTH0 e 0, INPUTS Comparator Threshold HYS ÐVTH2 e HYSÐVTH1 e 1 166 201 mV PP Voltage (Note 9) VthHYSD(101) CHAN. Data Field Hysteresis Ctrl Reg. Bits: HYST ÐVTH1 e 0, INPUTS Comparator Threshold HYS ÐVTH0 e HYSÐVTH2 e 1 207 246 mV PP Voltage (Note 9) VthHYSD(011) CHAN. Data Field Hysteresis Ctrl Reg. Bits: HYS ÐVTH2 e 0, INPUTS Comparator Threshold HYS ÐVTH0 e HYSÐVTH1 e 1 282 315 mV PP Voltage (Note 9) VthHYSD(000) CHAN. Data Field Hysteresis Ctrl Reg. Bits: HYS ÐVTH0 e INPUTS Comparator Threshold HYS ÐVTH1 e HYÐVTH2 e 0 372 418 mV PP Voltage (Note 9) ZSCAP(DIS) SERVO SCAP Pin Discharge VHOLD e 0.3V, V S4 e 4V, 4 6.2 8.5 k XImpedance V SCAP1–4 e 2V (Note 12) AvQT(gd) SERVO Servo Channel Gain for V HOLD e 3V 4.6 5.5 7.8 V/VQuarter Track Mispositioning (Note 14) VINTERCEPT SERVO Servo Channel Output V HOLD e 4V 1 1.4 %Voltage for 0 V PP Input (Notes 13 and 15) GLgd SERVO Gated Detector Gain V HOLD e 4V 0.3 1 %Linearity (Notes 13, 16 and 17) VOSgd SERVO Gated Detector Output V HOLD e 4V 10 25 mVVoltage Offset (Note 18) ILgd SERVO Gated Detector Leakage V S1 e VS2 e VS3 e VS4 e 0.3V, 0.02 0.05 mACurrent VHOLD e 4V (Note 19) VOS(DA) SERVO Servo Difference (Note 20) 51 2 m VAmplifier Offset Voltage AVDA SERVO Servo Difference Gain is Measured from Amplifier Gain SCAP Pins to Difference 0.45 0.475 0.5 V/V Amplifier Output http:/ /www.national.com13 Obsolete

operating conditions (see table) unless otherwise specified. Minimum and/or maximum limits are guaranteed by outgoing testing unless otherwise specified. (Continued) Symbol Circuit Parameter Conditions Min Typ Max UnitsBlock (Note 24) VDA(MAX) SERVO Maximum Output VCC e 4.5V (Note 3.2 3.37 VVoltage of Servo 21) Difference Amplifier VDA(MIN) SERVO Minimum Output Force SCAP’s to 1.05 1.4 V Voltage of Servo Achieve Minimum Difference Conditions Output from Difference Amplifier ZVDIFF SERVO VDIFF Input Impedance V DIFF e 2.5V 15 33 kX IDA SERVO Difference Amplifier 100 170 mAOutput Drive Capability IGDSEEK SERVO Gated Detector Seek V HOLD e 4V 5 8.5 12 mAMode Pull Down (Note 22) Current AvDF(MAX) FILTER Maximum Filter Gain in Set Pulse Slimming SERV e 0 (CR bit) AvSF(MAX) FILTER Maximum Filter Gain in Set Pulse Slimming SERV e 0 (CR bit) AvDF(MIN) FILTER Minimum Filter Gain in Set Pulse Slimming Data Field to Max. Peaking. 0.4 0.6 1 V/VSFIELD e LOW, SERV e 0 (CR bit) AvSF(MIN) FILTER Minimum Filter Gain in Set Pulse Slimming Servo Field to Max. Peaking. 0.7 1 1.3 V/VSFIELD e HIGH, SERV e 0 (CR bit) ZIN(F) FILTER Filter Input Impedence (Note 1) 3.1 3.8 4.8 k X VFOB FILTER Filter Output DC Bias V CC e Min. for Maximum Spec. KCPF FILTER Charge Pump Current (Negative) 320 420 500 mA Channel Filter PLL KVCOF FILTER VCO Gain, 1.4fXTLIN 1.8fXTLIN 2.3fXTLIN 1/VChannel Filter PLL Note 1: The input pin consists of two resistors tied to a voltage source. This is the resistance of each resistor. Note 2: Gain is measured differentially. Note 3: The AGC threshold voltage is defined as the equivalent differential peak to peak AC voltage swing across the channel input pins that causes the current at VAGCIN pin to equal zero. Note 4: Channel inputs (CHAN1 and CHAN2) are set at V TH(AGC) a 10 mV. Transconductance is measured from the channel inputs (CHAN1 and CHAN2) to the current at the VAGCIN pin. The measurement is made at V TH(AGC).G m AGC e lIVAGCIN/10 mV l Note 5: The Fast Slew Break Point (FSBP) is defined as a positive or negative percentage of the AGC threshold voltage (V TH(AGC)). The break point is that voltage above and below V TH(AGC) where the Gm AGC abruptly increases. This point is found by increasing or decreasing the differential voltage at the channel inputs above and below the AGC threshold, while monitoring the transconductance at the VAGCIN pin. The break point occurs when the transconductance increases by at least 20% above Gm AGC. Note 6: Measure current into or out of VAGCIN pin for both V CHAN1 b VCHAN2 e 0 and V CHAN1 b VCHAN2 e 0.5V. This specification applies to both VAGCINS and VAGCIND pins. V REF e 0.5V. Note 7: The common mode voltage at AMPIN1 and AMPIN2 pins is measured for no current into these pins. Current is then forced into either AMPIN1 or AMPIN2 (not both simultaneously) until the voltage on the pin rises by 1V. Note 8: The common mode voltage at AMPIN1 and AMPIN2 is measured for no current out of these pins. Current is then pulled out of either AMPIN1 or AMPIN2 (not both simultaneously) until the voltage fails by 1V. http:/ /www.national.com 14 Obsolete

Note 9: The hysteresis comparator threshold is defined as the minimum differential AC signal across the channel inputs (CHAN1 and CHAN2) which causes the voltage on the POLOUT pin to change state. V SETHYSD e VSETHYSS e 0.45V. Note 10: The effect that a % change in the H/R ratio has on the qualification threshold, can be calculated by multiplying the H/R % change by the percentage qualification threshold. For example if the qualification threshold is 30% of the channel input signal and the % change in the H/R ratio is 10%, the net effect on the qualification level is 30% c 10% e 3%. Note 11: This specification applies to both SETHYSD and SETHYSS pins. Note 12: SCAP1, SCAP2, SCAP3 and SCAP4 pins are measured. Note 13: S1, S2, S3 and S4 pins are at an appropriate level to gate on the channel under test. VOQTH e The servo output voltage from the SCAP pins with the channel input level set to simulate the read head mispositioned by one quarter of a track in a direction towards the servo burst (i.e. larger amplitude). This is done by setting Vc1 e lVCHAN1 b VCHAN2l e 375 mV PP differential e QTH and measuring the voltage on the SCAP pins. VOQTL e The servo output voltage from the SCAP pins with the channel input level set to simulate the read head mispositioned by one quarter of a track in a direction away from the servo burst (i.e. smaller amplitude). This is done by setting Vc1 e lVCHAN1 b VCHAN2l e 125 mV PP differential e QTL and measuring the voltage on the SCAP pins. Note 14: Av(QT(gd)) e (VOQTH b VOQTL)/(QTH b QTL). Note 15: Expressed as a percentage of V CC. Note 16: S1, S2, S3 and S4 pins are at an appropriate level to gate on the channel under test VOETH e The servo output voltage from the SCAP pins with the channel input level set to simulate the read head mispositioned by one quarter of a track in a direction towards the servo burst (i.e. larger amplitude). This is done by setting Vc1 e lVCHAN1 b VCHAN2l e 312.5 mV PP differential e ETH and measuring the voltage on the SCAP pins. V OETL e The servo output voltage from the SCAP pins with the channel input level set to simulate the read head mispositioned by one quarter of a track in a direction away from the servo burst (i.e. smaller amplitude). This is done by setting Vc1 e lVCHAN1 b VCHAN2l e 187.5 mV PP differential e ETL and measuring the voltage on the SCAP pins. Note 17: GL(gd) e 100[À[lVOEH b VOETLl/lVOQTH b VOQTLl] b0.5Ó/0.5] Note 18: Set the voltage at S1, S2 and S3 pins to gate on the channel under test. Force lVCHAN1 b VCHAN2l e 250 mV PP differential. Measure the voltage at each gated detector output (SCAP pins). V OSgd e glthe maximum difference voltage between (SCAP1–SCAP2) and (SCAP3–SCAP4) l. Note 19: VCHAN1 b VCHAN2 e 0V. Force 3V on each of the gated detector output pins (SCAP pins) and measure the current into or out of the pin. Note 20: Force all SCAP pins to 3V and measure difference between VDIFF and DIFAMP1 and VDIFF and DIFAMP2 pins. Note 21: Force SCAP pins to achieve maximum output from the difference amplifier. Note 22: Program seek mode. Force 3V on SCAP pin under test. Gate on servo channel under test. Measure current into SCAP pin. Note 23: This parameter is V CC dependent. The minimum specification is at the minimum specified V CC, while the maximum specification is at the maximum specified V CC. Note 24: Typical values are specified at 25 §C and 5V supply. limits are guaranteed by outgoing testing unless otherwise specified. Symbol Parameter Conditions (Note 7) Min Typ Max Units(Note 5) DLYdata Delay Variation SFIELD e LOW (Note 1) g1n s BOOSTD(mx) Maximum Filter Boost SFIELD e LOW (Notes 2 and 6) 6.5 8.13 9.5 dB BOOSTS(mx) Maximum Filter Boost SFIELD e HlGH (Notes 2 and 6) 1.5 3.62 5 dBCtrl Reg. Bit: SERVO e 1 BWACD(MXB) Data Field Filter Bandwidth SFIELD e LOW (Note 3) 8 13.8 17 MHzAccuracy at Maximum Boost BWACD(MNB) Data Field Filter Bandwidth SFIELD e LOW (Note 4) 7 9.19 12.5 MHzAccuracy at Minimum Boost BWACS(MXB) Servo Field Filter Bandwidth SFlELD e HIGH (Note 3) 7 11.81 14 MHzAccuracy at Maximum Boost Ctrl Reg. Bit: SERVO e 1 BWACS(MNB) Servo Field Filter Bandwidth SFIELD e HIGH (Note 4) 4.5 5.58 10 MHzAccuracy at Minimum Boost Ctrl Reg. Bit: SERVO e 1 Note 1: With control register bits EQ0, EQ1, EQ2 set to 1 (i.e. no boost), the change in delay is measured from the b3 dB frequency of the filter to one fourth of the b3 dB frequency. The change in delay is measured from the inputs of the filter to the output of the filter. This parameter is measured with the b3 dB frequency set Note 2: b3d B e 10 MHz. Control register bits: EQ2 e 0, EQ1 e 0, EQ0 e 0. The boost is measured relative to the low frequency gain. Note 3: Control register bits: EQ2 e 0, EQ1 e 0, EQ0 e 0, SERV ÐEQ2 e 0, SERV ÐEQ1 e 0, SERV ÐEQ0 e 0, FILT Ð3d B Ð6–FILT Ð3d B Ð0 e 1100010, XTLIN e 16 MHz. Specification indicates bandwidth under these conditions. Note 4: Control register bits: EQ2 e 1, EQ1 e 1, EQ0 e 1, SERV ÐEQ2 e 1, SERV ÐEQ1 e 1, SERV ÐEQ0 e 1, FILT Ð3d B Ð6–FILT Ð3d B Ð0 e 1100010, XTLIN e 16 MHz. Specification indicates bandwidth under these conditions. Note 5: Typical values are specified at 25 §C and 5V supply. Note 6: The limit values have been determined by characterization data. No outgoing tests are performed. Note 7: An external network of 24 k X to FV CC and 18 k X to GND is connected to VPHASE pin. http:/ /www.national.com15 Obsolete

unless otherwise specified. Minimum and/or maximum limits are guaranteed by outgoing testing unless otherwise specified. (Note 1) Symbol From Input To Output Parameter Conditions Min Typ Max Units(Note 2) (Note 2) (Note 12) trecov(s) WGv ERDOu Recovery Time from Write Enable ERD for Pulse Detector Output Via Control RegisterMode with Short Mode 1.7 1.9 2.6 ms Programmed trecov(l) WGv ERDOu Recovery Time from Write Enable ERD for Pulse Detector Output Via Control RegisterMode with Long Mode 3.8 4.1 5.4 ms Programmed trecov(sleep) SLEEPu ERDOu Recovery Time from Sleep Enable ERD for Pulse Detector 300 msOutput Via Control RegisterMode of Pulse Detector (Note 10) trecov(IDLE) IDLE/ ERDO u Pulse Detector Recovery Time (Notes 3 and 11) 20 msSERVOv from the IDLE Mode tcharge S1 to S4 SCAP1– Gated Detector Charge Time (Note 3) 200 340 430 nsSCAP4 tdischarge S1 to S4 SCAP1– Gated Detector Discharge (Note 4) 2.7 3.6 4.5 msSCAP4 Time tON S1 to S4 SCAP1– Gated Detector Turn On Time (Note 5) 33 40 nsSCAP4 tOFF S1 to S4 SCAP1– Gated Detector Turn Off Time (Note 6) 34 45 nsSCAP4 tpw ERD0u ERD0v Encoded Read Data Output Enable ERD0 for Pulse Detector 20 35 nsOutput via Control RegisterPulse Width tGT0 SCAP4v SCAP3u Gate to Time Channel Delay, V(SETHYS) eb 0.1V (Note 7) 70 105 nsf e 5 MHzDelay Step 0 tDS1 SCAP4u SCAP3u Programmable Channel Delay (Note 8) 69 n sStep Size, Delay Step 1 tDS2 SCAP4u SCAP3u Programmable Channel Delay (Note 8) 11 17 nsStep Size, Delay Step 2 tDS3 SCAP4u SCAP3u Programmable Channel Delay (Note 8) 11 17 nsStep Size, Delay Step 3 Note 1: All parameters are specified for the following conditions unless otherwise stated. The device uses the components described in the AC test setup diagram powered on. R DIF e 50X,C DIF e 180 pF. VIN e 100 mV PP differential. Note 2: The symbol ( u) indicates the rising edge of the pulse is used as reference. The symbol ( v) indicates the falling edge of the pulse is used as reference. Note 3: Connect 200 pF capacitors to SCAP pins. With all external capacitors to SCAP pins discharged, measure the time from servo channel enable pins (S1, S2, S3, S4) to 90% of the rising edge of the selected servo channel output. f IN e 5 MHz Note 4: Connect 200 pF capacitors to SCAP pins. With all external capacitors to SCAP pins discharged, measure the time from the servo channel enable pins (S1, S2, S3, S4) to 90% of the falling edge of the selected servo channel output. f IN e 5 MHz Note 5: With no capacitors connected to the SCAP pins, pull 1 mA from each of the SCAP pins. Measure the time from the selection of each servo channel (S1, S2, S3, S4) to the voltage on the selected servo output when it increases by 0.1V. Note 6: With no capacitors connected to the SCAP pins, pull 1 mA from each of the SCAP pins. Measure the time from the selection of each servo channel (S1, S2, S3, S4) to the voltage on the selected servo output when it decreases by 0.1V. Note 7: Enable internal pulse detector signals and program the gate channel delay step 0 through the control register. t GTO includes time contributions from the test frequency and delay introduced by the external differentiator components. The test frequency contribution is the amount of time from the zero crossing at the base line to the peak (which for a 5 MHz signal is 100 ns). The theoretical delay introduced by the differentiator components, R DIF e 50X and C DIF e 180 pF, at this frequency is 13 ns. Consequently, the raw gate to channel delay can be found by subtracting off these external contributions to the delay. http:/ /www.national.com 16 Obsolete

Note 8: Enable internal pulse detector signals through the control register. Measure the time from the falling edge of SCAP4 pin to the rising edge of SCAP3 pin as the programmable gate channel delay step is changed. t DS e the incremental delay change per step. Note 9: Enable pulse detector output at ERDO via the control register. The 3.3 MHz pulse pairing measurement is made with the channel filter programmed for 5 MHz b3 dB bandwidth with 0 dB peaking. The 7 MHz pulse pairing measurement is made with the channel filter programmed for 10 MHz b3 dB bandwith with 0 dB peaking. Note 10: Pulse detector is initially powered down for 25 ms prior to powering on. Note 11: The pulse detector is initially powered down for 2 ms. Recovery time is measured from the deassertion of the IDLE/SERVO pin to the rising edge of ERDO. Note 12: Typical values are specified at 25 §C and 5V supply. Note 13: The limit value has been determined by a characterization data. No outgoing test is performed. ing temperature and supply voltage ranges unless otherwise specified. Minimum and/or maximum limits are guaranteed by outgoing testing unless otherwise specified. Symbol Func. Parameter Conditions Min Typ Max UnitsBlock (Note 8) tT-SYNC Synch. Synchronizer Window Loss Strobe M e 0 16.7 Mb/s b3 g1.3 3 ns33.3 Mb/s b2.5 g1.1 2.5 50 Mb/s b1.25 g0.6 1.25 iLIN-PH Synch. Phase Detector Phase Lock gq radRetrace Angle (Notes 6, 9) KVCO-SYNC Synch. Synchronizer VCO Gain 25 §C Only 0.250o 0.450o 0.650o rad/Vs(Note 1) tSD0 Synch. SCK Negative Edge to (Note 4) 358 n sSD Negative Edge tSD1 Synch. SCK Negative Edge to (Note 4) 358 n sSD Positive Edge tZPSR Synch. Zero-Phase Start Entering READ Mode 2n sAccuracy, Absolute Value (Note 4) tSFIX Synch. Strobe per Step Size, (Note 9) 0.6 nsb2t o a2 tSVAR Synch. Strobe per Step Size, (Notes 2 and 9) .0625 c tVCO nsb2t o b6 ,2t o6 tPW-SCK Synch. SCK Output Pulse Width (Note 5) 0.75 tw tw 1.25 tw ns tb3 dB-KVCO Synch. VCO Control Block (Note 9) 8 MHzb3 dB Rolloff tb3 dB-CP Synch. Charge Pump Block (Note 9) 50 MHzb3 dB Rolloff tPWSTH Synth. Synthesizer Output (Note 5) 33 Mb/s tw b 5t w a 5 nsPulse Width 50 Mb/s tw b 3.25 tw a 3.25 KVCO-SYNTH Synth. Synthesizer VCO Gain (Notes 1 and 5) See graph on next page 1.23 0o 1.40o 1.550o rad/Vs 25§C Only fb3 dB-KSTH Synth. VCO Control Block (Note 9) 8 MHzb3 dB Rolloff Note 1: 0o is the operating frequency of the synchronizer VCO. This parameter is specified at 25 §C ambient only. K VCO varies inversely with absolute (Kelvin) temperature. K VCO (T) e KVCO (25§C) c 298/T where T is in degrees Kelvin. Note 2: tVCO is the period of the synchronizer VCO. The period is equal to the code rate clock period. Note 3: Add to this value the data rate dependent delay time term TBD% c TVCO. Note 2 also applies. Note 4: Parameter guaranteed by design or correlation to characterization data. No outgoing tests are performed. Note 5: tw e 0.5 c respective clock period. Note 6: The parameter is measured with respect to the code rate clock period. Note 7: Using standard, static window measurement. See DP84910 Design Guide, DP8491/92 or DP8458/59 data sheets for description of static window test. Note 8: Typical values are specified at 25 §C and 5V supply. Note 9: This parameter is provided as information only. http:/ /www.national.com17 Obsolete

FIGURE 4. MICROWIRE TM Compatible Control Register Serial Load Timing Diagram

TL/F/11777–5 FIGURE 5a http:/ /www.national.com19 Obsolete

TL/F/11777–6 FIGURE 5b. Sample AC Test Configuration for Bench Evaluation of the DP84910 http:/ /www.national.com 20 Obsolete

be randomly loaded into one of the four banks of latches. is given a positive transition. FIGURE 6. Control Register Block Dlagram

Control Register Description (Continued) TABLE IIa. Control Register Definitions Bit Bit Name POR Block Function BANK (0,0)

0 CR ADDR0 CR Control Register Bank Address LSB (0)

1 CR ADDR1 CR Control Register Bank Address MSB (0)

2 FILT Ð3d B Ð0 1 FILT. Channel Filter Cutoff Frequency Selection Bit0 (LSB) 3 FILT Ð3d B Ð1 1 FILT. Channel Filter Cutoff Frequency Selection Bit1 4 FILT Ð3d B Ð2 1 FILT. Channel Filter Cutoff Frequency Selection Bit2 5 FILT Ð3d B Ð3 1 FILT. Channel Filter Cutoff Frequency Selection Bit3 6 FILT Ð3d B Ð4 0 FILT. Channel Filter Cutoff Frequency Selection Bit4 7 FILT Ð3d B Ð5 1 FILT. Channel Filter Cutoff Frequency Selection Bit5 8 FILT Ð3d B Ð6 1 FILT. Channel Filter Cutoff Frequency Selection Bit6 (MSB)

9 EQ0 1 PD Equalization Select Bit0 (LSB)

10 EQ1 0 PD Equalization Select Bit1

11 EQ2 0 PD Equalization Select Bit2 (MSB)

12 SERVO 0 PD Disable BW/EQ Control Servo Field (0 e Disable)

BANK (0,1)

0 CR ADDR0 CR Control Register Bank Address LSB (1)

2 PDATA0 1 SYNTH Feedback Divider Bit0 (LSB)

3 PDATA1 0 SYNTH Feedback Divider Bit1

4 PDATA2 0 SYNTH Feedback Divider Bit2

5 PDATA3 0 SYNTH Feedback Divider Bit3

6 PDATA4 0 SYNTH Feedback Divider Bit4

7 PDATA5 0 SYNTH Feedback Divider Bit5 (MSB)

8 PDATA6 1 SYNTH Input Divider Bit0 (LSB)

9 PDATA7 0 SYNTH Input Divider Bit1

10 PDATA8 0 SYNTH Input Divider Bit2

11 PDATA9 0 SYNTH Input Divider Bit3

12 PDATA10 0 SYNTH Input Divider Bit4 (MSB)

BANK (1,0)

1 CR ADDR1 CR Control Register Bank Address MSB (1)

2 SYNC ÐPWRÐDN 1 SYNC Selective Power Down of Synchronizer (Power Down e High)

3 STH ÐPWRÐDN 1 SYNTH Selective Power Down of Synthesizer (Power Down e High)

4P D ÐPWRÐDN 1 PD Selective Power Down of Pulse Detector (Power Down e High)

5 ENSTHO 1 SYNTH Enable SYNTH Output (when low)

6 GATE ÐDEL1 0 PD Gating Channel Delay Select Bit 1(LSB)

7 GATE ÐDEL2 1 PD Gating Channel Delay Select Bit 2(MSB)

http:/ /www.national.com 22 Obsolete

Control Register Description (Continued) TABLE IIa. Control Register Definitions (Continued) Bit Bit Name POR Block Function BANK (1,0) 8 STR ÐSIGN 0 SYNC Strobe Sign Bit (0 e pos., 1 e neg.)

9 STR0 0 SYNC Strobe Bit0 (LSB)

10 STR1 0 SYNC Strobe Bit1

11 STR2 0 SYNC Strobe Bit2 (MSB)

12 CPRATIO 0 SYNC Synchronizer Charge Pump Gain Control

BANK (1,1)

2 ERD0 0 PD/SC ERD Control Bit 0 (Note 1)

3 ERD1 0 PD/SC ERD Control Bit 1 (Note 1)

4 PREAM Ð2T 0 SYNC Select 2T Preamble (3T if low)

5 INV ÐWG 1 PD Select WG Polarity (1 e active low)

6 SLOW 1 PD Select 1.7 ms Delay on AMPIN (Low e 3.4 ms delay)

7 HYS ÐVTH0 1 PD Hysteresis Voltage Control Bit0 (LSB)

8 HYS ÐVTH1 0 PD Hysteresis Voltage Control Bit1

9 HYS ÐVTH2 1 PD Hysteresis Voltage Control Bit2 (MSB)

10 SERVO ÐEQ0 1 FILT Filter Bandwidth/Equalization Control-Servo Bit0 (LSB)

11 SERVO ÐEQ1 1 FILT Filter Bandwidth/Equalization Control-Servo Bit1

12 SERVO ÐEQ2 1 FILT Filter Bandwidth/Equalization Control-Servo Bit2 (MSB)

Note 1: When ERD0 and ERD1 are both high. the GCA is put into a fixed gain mode. The synchronizer and synthesizer are put into test modes where their VCO’s are driven by external signals. Pulse Detector Description The purpose of the pulse detector is to convert the timing information contained in the analog peaks of the disk wave- form into a digital signal whose leading edge accurately rep- resents the time position of the analog peaks. Raw disk data from the output of an external read preampli- fier is capacitively coupled to the inputs of the DP84910’s gain controlled amplifier (AMPIN1, AMPIN2). These inputs are switched to low impedance when the WRITE GATE in- put pin is enabled and stays at a low impedance for either 1.7 mso r3 . 4 ms after WRITE GATE is disabled. The amount of delay is selectable via a bit in the control register (SLOW Bank (1,1), bit 6). During this time, any DC offsets accumu- lated across the input coupling capacitors during the write mode are removed. Also during the write mode, the AGC voltage is held fixed and the input signal to the amplifier is blocked. DC offsets at the output of the amplifier are the same for read or write modes. The gain controlled amplifier (GCA) accepts signals in the range of 20 mV to 200 mV peak-to-peak differential and produces a constant 500 mV peak-to-peak differential sig- nal at the channel inputs (CHAN1, CHAN2). The channel input signal amplitude is set by a voltage applied to the VREF pin. There is a one-to-one correspondence between the voltage applied to the VREF pin and the peak-to-peak differential signal at the GCA outputs. The VREF voltage is typically set by a voltage divider between supply and ground. A switched supply pin (SVCC) can be used to pro- vide the supply reference for this divider. The gain of the GCA is controlled by a fast equal-attack, equal decay, pattern insensitive, exponential responding, automatic gain controlled (AGC) amplifier circuit. The AGC allows for fast settling within 3 ms for a 50% change in the input signal level. The exponential response of the AGC al- lows the settling time to be independent of the input signal level. The response is pattern insensitive because the charging or discharging of the AGC capacitor is allowed only in the presence of a signal. Thus, large shoulder re- gions will not cause the AGC voltage to droop. A high im- pedance AGC input pin allows for an AGC hold function with very little leakage of the AGC capacitors’ charge. http:/ /www.national.com23 Obsolete

Pulse Detector Description (Continued) The differentiator extracts the timing information from the peaks of the disk signal. The timing of the peaks is pre- served in the zero-crossing of the signal at the differentiator output. A zero-cross detector is used in conjunction with the qualification channel to provide noise free, encoded data pulses to the data synchronizer. Fully differential circuits are used throughout the pulse detector to minimize pulse pair- ing. In order to not interpret noise on the baseline as input data, a hysteresis comparator is used for qualifying the channel input signal. Two pins set the hysteresis level by the appli- cation of an external voltage. One pin sets the hysteresis level in a data field (SETHYSD) and the other pin sets the hysteresis level in a servo field (SETHYSS). The SFIELD pin controls the selection between these pins. A resistive divid- er between supply and ground is typically used to provide these voltages. A switched supply output pin (SVCC) is available to be used as the supply reference for these divid- ers. The SETHYSD voltage is adjustable in eight steps via bits in the control register (HYS ÐVTH0, HYS ÐVTH1, HYSÐVTH2, Bank (1,1) bits 7, 8, 9) (see Table IIb). TABLE IIb. Hysteresis Threshold Control Ctrl. Reg. Bits % Qual. HYSÐVTH2 HYS ÐVTH1 HYS ÐVTH0 111 2 9 1 1 0 33.5 101 3 8 1 0 0 42.5 011 4 7 0 1 0 51.5 001 5 6 0 0 0 60.5 SETHYSD e 450 mV Two bits in the control register (ERD0, ERD1, Bank (1,1) bits 2, 3) direct the output of the pulse detector to either the input of the data synchronizer section, the ERDOUT pin or both (see Table III). A test mode is entered when both of these control register bits are at a logical high level. In this mode the GCA is put into a fixed gain mode, the VCOs are stopped, the CRD input is redirected to act as a clock source for the synchronizer and the CRC pin as a clock source for the synthesizer. TABLE III. SYNCH./PD I/O Pin Control Ctrl. Reg. Pins Enabled Mode TestBank (1,1) ERD1 ERD0 ERDOUT ERDIN 0 0 NO NO OFF 0 1 YES NO OFF 1 0 YES YES * OFF 1 1 YES YES * ON *Internal pulse detector feed through to synchronizer is disabled; ERDIN is input to the synchronizer. The pulse detector output pulse width is internally fixed to approximately 15 ns, independent of data rate. Four gated peak detectors are used to detect quadrature embedded servo bursts. When gated on, the peak detector charges an external capacitor to a DC level proportional to the amplitude of the servo burst. The output voltage range of these detectors is large enough for 7 bits of resolution. The gating and discharge of the servo capacitors are con- trolled by five TTL level logic pins (S1, S2, S3, S4 and HOLD) as described by Table IV. The servo channel is de- signed for very low servo offsets and good gain linearity. Two servo difference amplifiers (DIFFAMP1, DIFFAMP2) have been added to the DP84910 which were not present in previous NSC integrated read channel circuits. The first dif- ference amplifier (DIFFAMP1) takes the difference between servo channel 1 (SCAP1) and channel 2 (SCAP2). The sec- ond difference amplifier (DIFFAMP2) takes the difference between servo channel 3 (SCAP3) and channel 4 (SCAP4). These differences are centered around an externally sup- plied reference voltage at the VDIFF pin. This reference voltage is typically set at one half the supply voltage. Two modes of servo operation are now available, track fol- low and seek modes. The control or selection of these modes are with the servo switches (S1 through S4) and HOLD pins (see Table IV). The difference between these modes is the amount of charging time the servo peak detec- tor needs to reach its final value, with the same input condi- tions. The track follow mode has a slower charge time than the seek mode. With a slower charge time the peak detec- tors will be less sensitive to noise on the servo signal. Previ- ous NSC integrated read channel devices only provided the track follow mode. An output internal signals mode can be entered by applying a logical high level to the S2 pin and a logical low level to the HOLD pin. In this mode certain selected internal signals of the pulse detector are routed to the four servo output pins (SCAP1–SCAP4) as observation points. These signals in- clude the fully differential analog output of the differentiator (SCAP1 and SCAP2 pins), the output of the zero-cross de- tector at the differentiator output (SCAP3 pin), and the de- layed qualification signal (SCAP4 pin). This mode is useful for the system designer while optimizing the implementation of the pulse detector. This mode would not normally be se- lected in a production drive as it precludes the operation of these pins for embedded servo use. http:/ /www.national.com 24 Obsolete

Channel Filter Description (Continued) VPHASE Pin The voltage on the VPHASE pin is internally generated and controls the Q of the integrated filter. Changing the voltage on this pin has simultaneous effects on the filter group de- lay, peaking and bandwidth. It is recommended that an ex- ternal voltage divider (18 k X to FV CC and 24 k X to ground) be connected to this pin. The following response equations have been created with this divider connected. This resistor divider does not set the voltage at this pin. It modifies the gain and offsets the voltage at this pin. The connection of the divider to this pin improves the filter group delay performance, particularly at higher data rates. Without these resistors there is a high frequency peaking of the group delay characteristic which in turn causes excess peaking in the magnitude characteristic, even with no boost selected. These effects are further exaggerated at low V CC and elevated temperatures. BANDWIDTH CONTROL The filter bandwidth is a user determined value selected using the FILT Ð3dBÐ0–FlLT Ð3dBÐ6 control register bits. To some extent, the filter bandwidth is also determined by the amount of pulse slimming (peaking) desired. Table Va lists a set of equations that yield the control regis- ter setting (i.e., the setting of the FILT Ð3dBÐ0–FILT Ð 3dBÐ6 CR bits) for achieving a particular bandwidth (BW) as a function of the pulse slimming control register setting (i.e., EQ2, EQ1 and EQ0 CR bits) and the external frequen- cy supplied to the XTLIN pin (Fx). Both BW and Fx should be expressed in MHz. The resulting number, when convert- ed to binary, is the correct CR setting. The binary number listed under the CTRL REG BITS column is the EQ2, EQ1 and EQ0 CR bit setting to achieve the indicated amount of pulse slimming in the PEAKING column of the table. TABLE Va. Peaking vs b3 dB Frequency Equations Peaking CR Bits Peaking (dB) b3 dB Equation (Note 1) (Data Field) EQ2 EQ1 EQ0 1 1 1 0.40 BW b 2.1751Fx a 4.8720 b0.016450FX a 0.051574 1 1 0 1.16 BW b 2.3675FX a 4.4670 b0.017828FX a 0.048271 1 0 1 1.93 BW b 2.4876FX a 4.3786 b0.018727FX a 0.048455 1 0 0 3.00 BW b 2.6678FX a 4.8513 b0.020077FX a 0.052433 0 1 1 4.04 BW b 2.8403FX a 5.6269 b0.021422FX a 0.059365 0 1 0 5.25 BW b 3.0278FX a 6.4295 b0.022887FX a 0.066185 0 0 1 6.22 BW b 3.2147FX a 7.3136 b0.024363FX a 0.074151 0 0 0 8.13 BW b 3.4594FX a 8.7398 b0.026331FX a 0.086751 Note 1. Data Field, V CC e 5V, T e 25§C. BW is the desired bandwidth and FX is the XTLIN input frequency (both are expressed in MHz). The resolution of the frequency control DAC is dependent on the frequency input at the XTLIN pin and the amount of pulse slimming selected. Table Vb lists equations that de- scribe the resolution of the frequency control DAC in MHz/step. Fx e XTLlN frequency is expressed in MHz. TABLE Vb. Peaking vs DAC Resolution Peaking CR Bits DAC Resolution Equations (Note 1) (Data Field) EQ2 EQ1 EQ0 1 1 1 0.016450F X b 0.051574 1 1 0 0.017828F X b 0.048271 1 0 1 0.018727F X b 0.048455 1 0 0 0.020077F X b 0.052433 0 1 1 0.021422F X b 0.059365 0 1 0 0.022887F X b 0.066185 0 0 1 0.024363F X b 0.074151 0 0 0 0.026331F X b 0.086751 Note 1. Data Field, V CC e 5V, T e 25§C, F X is the XTLIN input frequency in MHz. http:/ /www.national.com 26 Obsolete

Channel Filter Description (Continued) PULSE SLIMMING CONTROL As in previous NSC integrated read channel circuits, pulse slimming is implemented using the Kost technique. Pulse slimming operates by injecting current internal to the filter which is 180 degrees out of phase with the GCA drive cur- rent to the filter’s inputs. The injected current has the effect of peaking the high frequency response of the filter without affecting the filter’s group delay characteristic. The control register selection for different levels of peaking is shown in Table Va. TABLE Vc. Servo Field Peaking vs b3 dB Frequency Equations Peaking CR Bits Peaking (dB) b3 dB Equation (Note 1) (Servo Field) Servo Servo Servo EQ2 EQ1 EQ0 1 1 1 0.40 BW b 1.0368Fx b 0.4774 b0.007341FX a 0.000213 1 1 0 1.16 BW b 1.2651FX a 0.5037 b0.009182FX a 0.010845 1 0 1 1.93 BW b 1.8836FX a 5.0496 b0.014272FX a 0.050838 1 0 0 3.00 BW b 2.1728FX a 5.5646 b0.016692FX a 0.059598 0 1 1 4.04 BW b 2.3386FX a 5.1777 b0.017666FX a 0.054288 0 1 0 5.25 BW b 2.4648FX a 4.5824 b0.018543FX a 0.049550 0 0 1 6.22 BW b 2.6334FX a 5.1666 b0.019883FX a 0.055912 0 0 0 8.13 BW b 2.7258FX a 4.9201 b0.020475FX a 0.053289 Note 1: VCC e 5V, T e 25§C. BW is the desired bandwidth and F X is the XTLIN input frequency (both are expressed in MHz). SEQ2 e SERVOÐ EQ2, etc. SERVO BANDWIDTH CONTROL The DP84910 has the ability to reduce the b3 dB frequency and peaking characteristic of the filter without addressing the control register. This feature is enabled by a bit in the control register (SERVO , Bank (0,0) bit 12) and controlled by the SFIELD pin. This feature is desirable because the servo field is often written at a lower frequency than the data field. Reducing the bandwidth for a servo field will max- imize the servo signal-to-noise ratio. A side effect of the Kost pulse slimming technique is that the b3 dB frequency of the filter moves as the amount of pulse slimming is changed. This property is used to advan- tage to reduce the channel filter bandwidth in a servo field, by decreasing the amount of pulse slimming. If we define a ratio (K) of the injected slimming signal to the signal at the input of the filter we find that for values of K less the 0.2 there is no peaking in the filter magnitude response. In the data field (i.e., SFIELD e low), K is never allowed to go below 0.2, even when no pulse slimming is selected (i.e., EQ2 e EQ1 e EQ0 e 1). This is illustrated in Table VI which shows the b3 dB bandwidth of the channel filter as a function of peaking. Table VI shows that peaking in the data field is achieved by increasing K above the minimum 0.2 level. However, if control register bit SERVO e 1 and the SFIELD pin is high (i.e., in a servo field) then K is allowed to go to zero. TABLE VI. Pulse Slimming Control Table: Data Field Peaking CR Bits K Peaking (dB) b3d B (MHz) BW Gain (dB) (Data Field) (Note 1) EQ2 EQ1 EQ0 1 1 1 0.22 0.40 18.23 6.000 1 1 0 0.28 1.16 20.60 5.450 1 0 1 0.34 1.93 21.96 4.840 1 0 0 0.41 3.00 23.37 4.200 0 1 1 0.48 4.04 24.55 3.490 0 1 0 0.55 5.25 25.84 2.730 0 0 1 0.62 6.22 27.12 1.886 0 0 0 0.69 8.13 28.52 0.956 Note 1: This table is referenced to a 10 MHz, 7 pole, 0.05 degree equal ripple filter. V CC e 5V, T e 25§C. In the servo field, control register bits SERVO ÐEQ2, SERVOÐEQ1 and SERVO ÐEQ0 are mulitiplexed with the control register bits EQ2, EQ1 and EQ0, to allow for sepa- rate control of the amount of filter peaking and consequent- ly, separate control of the filter bandwidth. Table VII shows the effect these control register bits have on the filter band- width and peaking. Notice that corresponding values of K are 0.2 less in Table VII vs. Table VI. The multiplexing action is controlled by the SFIELD pin if control register bit SERVO e 1. The base frequency gain of the channel filter changes as a function of the peaking. In order to reduce AGC settling time when multiplexing in different levels of peaking between the servo and data fields, a second AGC control pin (VAGCINS) has been added. The SFIELD pin switches control between the VAGCIND and the VAGCINS pins. This switching will occur independent of the state of the SERVO control regis- ter bit. http:/ /www.national.com27 Obsolete

Synchronizer Description (Continued) TABLE VII. Pulse Slimming Control Table: Servo Field Peaking CR Bits K Peaking (dB) b3d B (MHz) BW Gain (dB) (Servo Field) (1) SERVO SERVO SERVO EQ2 EQ1 EQ0 1 1 1 0.00 0.00 10.00 6.000 1 1 0 0.04 0.00 10.89 5.450 1 0 1 0.13 0.00 14.50 4.840 1 0 0 0.18 0.32 16.54 4.200 0 1 1 0.23 0.95 18.46 3.490 0 1 0 0.27 1.76 20.26 2.730 0 0 1 0.32 2.47 21.59 1.886 0 0 0 0.37 3.62 22.78 0.956 Note: This table is referenced to a 10 MHz, 7 pole, 0.05 degree equal ripple filter. SEQ2 e SERVO Ð EQ2 etc. When either the VAGCIND or VAGCINS pin is not selected, the filter is placed into an AGC hold mode. Because of this, the AGC capacitors tied to the VAGCIND and VAGCINS pins remember the correct voltage (and corresponding am- plifier gain) for their respective fields. Thus the channel filter can have different gains (as a result of different levels of peaking) in the servo and data fields, without the penalty of waiting for AGC settling time when the part is rapidly switched between these two fields. Separate AGC control pins also allow for different AGC time constants between the servo and data fields. Typically, prior to the servo bursts, an AGC normalization field is written. This normalization field allows the servo AGC to adjust the servo channel gain to a constant level independent of the position of the read head. In order to minimize the disk space consumed for this function, the normalization field is usually only several microseconds long. Thus a fast AGC time constant is typically used in the servo field to quickly acquire the level of the normalization field. The VAGCIND and VAGCINS pins can be tied together in the event that separate AGC time constants are not desired and the servo channel filter bandwidth reduction feature is not used. This would save one external component by elimi- nating one of the AGC capacitors. Synchronizer Description The DP84910 data synchronizer consists of a phase locked loop (PLL) employing a delay line, a pulse gate, a phase frequency comparator, an analog charge pump, an external passive loop filter, a voltage controlled oscillator (VCO), and supporting logic. The synchronizer extracts the code rate clock from the peak detected disk data, generates bit frames (windows) for bit capture, and reissues phase-stabi- lized data. The synchronization window (with strobe setting at nominal, M e0 position) is centered about the encoded read data (ERD) pulses via the 50% duty cycle of the VCO and the time averaging action of the PLL. The synchronizer incorporates a zero-phase-start (ZPS) block to minimize the phase step seen at the beginning of a lock sequence. Prior to the beginning of a read operation, the synchronizer PLL is locked to the output of the synthe- sizer to maintain the VCO frequency at the operating code rate. Following READ GATE assertion, the ZPS block freezes the synchronizer VCO and restarts it coincidentally with disk data bit. Once the ZPS event is completed, the SCLK output multiplexer is allowed to switch (without glitch- es) from its synthesizer reference to the synchronizer refer- ence. Also, if frequency lock is employed (FLC low), a divid- er is incorporated in the VCO feedback path corresponding to the 2T or 3T sync field being used. This divider is syn- chronously dropped out and the pulse gate enabled once the FLC input is taken to a high logical level (see National Semiconductor Mass Storage Handbook , Application Note AN-414, for a discussion of frequency lock). If frequency lock is not employed, the pulse gate becomes active imme- diately at the end of the ZPS sequence. When READ GATE is disabled, ZPS is momentarily held-off as the SCLK output multiplexer switches from transmission of the synchronizer reference to the synthesizer reference. Once the multiplexer switching is complete, ZPS is enabled and the synchronizer relocks to the synthesizer reference. (The accuracy of the VCO restart phase alignment at RG deassertion is less stringent than when entering a read op- eration.) Note that the SCLK output transmits the synchronizer clock only after ZPS is completed when entering the read mode, and deselects the synchronizer clock prior to the occur- rence of ZPS when exiting the read mode. This makes the ZPS event invisible to the SCLK output. The synchronizer provides two pins for PLL filtering purpos- es, CHARGE PUMP OUTPUT (CPO) and VCO INPUT (VCOI), permitting the use of high-order, two-port filters for optimization of PLL lock characteristics and bit jitter rejec- tion. For basic applications, CPO and VCOI may be tied together (single-node) and a simple lead-lag, C ll (RaC) filter tied between these pins and ground. The synchronizer may be selectively powered-down at the user’s option via a single bit in the control register (SYNC Ð PWRÐDN, Bank (1,0) bit 2). When selective power-down occurs within the synchronizer, an idle-biasing circuit is acti- vated at the CPO pin which will keep the filter voltage at 2 times V BE (approximately 1.5V) above ground potential in order to minimize lock recovery time at the enabling of pow- er. When selective powering occurs, as when V CC power-up occurs, all synchronizer logic is set into the non-read mode and the CPO idle-bias circuit is disabled. The synchronizer pulse gate is partitioned into two sections; the SYNC DATA bit latch and the VCO gate. The bit latch, operating independently of the VCO gate, generates the data synchronization window at the code clock rate based on the 50% duty cycle of the synchronizer VCO clock. 50% duty cycle symmetry in the VCO (or code) clock is produced by division of a 2X oscillator signal by a differential ECL toggle flip-flop. This symmetry-based technique eliminates reliance on the absolute value of the delay line for nominal window centering. The on-chip half-cell silicon delay line is employed in conjunction with the VCO gate to align the phase detector window (retrace angle). The delay magni- tude will track the synthesizer VCO and thus any recording data rate variations automatically, and because it is refer- enced to an external frequency source, it is insensitive to external component tolerance, supply voltage, temperature, and IC process variations. http:/ /www.national.com 28 Obsolete

FIGURE 10. Digital Phase-Frequency Comparator and for issuing the HOLD command to the DP84910. environmental noise immunity.

1988 ISSCC Digest of

rate variations (BW varies with the square root of the gain). cuitry from effecting the VCOI bias point. ing is done with no glitches. strobe response is immediate, requiring no settling time. ed for fine-stepping functions such as window deskewing. sixteenth (6.25%) of the window width.

Synchronizer Description (Continued) TABLE IX. Window Strobe Control Table Control Register Bits Bank (1,1) STR2 STR1 STR0 STR ÐSIGN Typical Window Shift 110 1 b(0.250)tVCO b 1.2 ns 101 1 b(0.188)tVCO b 1.2 ns 100 1 b(0.125)tVCO b 1.2 ns 011 1 b(0.062)tVCO b 1.2 ns 010 1 b 1.2 ns 001 1 b 0.6 ns 0 0 0 1 none 0 0 0 0 none 0 0 1 0 0.6 ns 0 1 0 0 1.2 ns 0 1 1 0 (0.062)t VCO a 1.2 ns 1 0 0 0 (0.125)t VCO a 1.2 ns 1 0 1 0 (0.188)t VCO a 1.2 ns 1 1 0 0 (0.250)t VCO a 1.2 ns Note: Strobe selections not shown in above table are invalid and should not be used. If an invalid state is inadvertently entered, SDO will become inde- terminate, though PLL lock (phase comparator activity) will not be affected. Synthesizer Description The synthesizer block is a phase-locked loop with control register selectable divider values at its input port and in its feedback path. A single, external node (Timing Extractor Fil- ter, or TEF) is provided for passive components for the syn- thesizer PLL filter. The resulting synthesized output, f SYNTH, is the code rate clock used for encoding and as a reference signal for the synchronizer during the non-read mode. The frequency of f SYNTH is the reference input frequency multi- plied by the modulus of the feedback divider and divided by the modulus of the input divider: f SYNTH e fREF c Nfeedback/Ninput The input divider modulus N input is set via control register Bank (0,1), bits 8–12 (LSB–MSB, respectively), and feed- back modulus N feedback is set via control register Bank (0,1), bits 2–7 (LSB–MSB, respectively). The value of each N modulus is equal to the binary value of its control word PLUS 2. This gives the input divider a division range of 3–33 and the feedback divider a division range of 3–65. N input e [Binary value of CR Bank (0,1), bits 8–12 ] a 2 Nfeedback e [Binary value CR Bank (0,1), bits 2–7 ] a 2 A zero value control word (all bits low) for either divider is not allowed (divider operation stops). At V CC power-up, the divider control words are both automatically set to binary 1, and thus the ratio: N feedback/Ninput e (1 a 2)/(1 a 2) e (3)/(3), or unity. The synthesizer may be selectively powered-down via a sin- gle bit in the control register (STH ÐPWRÐDN, Bank (1,0) bit 3). No control register data is lost during selective power- down. When selective power-down occurs, an idle-bias cir- cuit is activated at the TEF pin which keeps the filter voltage at a typical operating bias of 2 times V BE (approximately 1.5V) above ground potential in order to minimize lock re- covery time at reapplication of power. Note: The synchronizer derives key reference signals from the synthesizer; thus, the synthesizer must be powered-on for the synchronizer to operate properly. If the synthesizer is powered-down, the synchroniz- er should be as well. In general, to minimize digital switching noise, it is advised that the SYNC CLOCK (SCLK) output be used for all read/ write clock purposes and the SYNTH output be left dis- abled. For systems which must use a continuous, unmulti- plexed, synthesized master clock, the SYNTH output is made available. Should the SYNTH output be employed as a system clock, care should be taken, as with all switching outputs on the DP84910, to minimize capactive loading (use an external buffer/driver for multiple fan-out applications). The standard, default V CC power-up condition for the SYNTH output pin is the disabled mode (logic high state). This output should always be left disabled if not needed. http:/ /www.national.com 30 Obsolete

http:/ /www.national.com31 Obsolete

DP84910 (-36/-50) Integrated Read Channel Physical Dimensions inches (millimeters) unless otherwise noted 80-Pin PQFP Package Order Number DP84910VHG-36 or DP84910VHG-50 LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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Arlington, TX 76017 Email: europe.support @ nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: a49 (0) 180-530 85 85 Tsimshatsui, Kowloon Fax: 1(800) 737-7018 English Tel: a49 (0) 180-532 78 32 Hong Kong Fran3ais Tel: a49 (0) 180-532 93 58 Tel: (852) 2737-1600 http:/ /www.national.com Italiano Tel: a49 (0) 180-534 16 80 Fax: (852) 2736-9960 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Obsolete

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