VH501

SN74ALVCH16501_06 TI | Alldatasheet

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(TOP VIEW) OEAB LEAB GND V CC GND A10 A11 A12 GND A13 A14 A15 V CC A16 A17 GND A18 OEBA LEBA GND CLKAB GND V CC GND B10 B11 B12 GND B13 B14 B15 V CC B16 B17 GND B18 CLKBA GND Data flow for B to A is similar to that of A to but uses OEBA LEBA, and CLKBA. The output enables are SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024J JULY 1995 REVISED OCTOBER 2004 Member of the Texas Instruments Widebus Family UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Modes Operates From 1.65 V to 3.6 V Max t pd of 3.9 ns at 3.3 V 24-mA Output Drive at 3.3 V Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD ESD Protection Exceeds JESD 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V V CC operation. Data flow in each direction is controlled by output-enable (OEAB and OEBA latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. complementary (OEAB is active high, and OEBA is active low). ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING Tube SN74ALVCH16501DL SSOP DL ALVCH16501 Tape and reel SN74ALVCH16501DLR -40 C to C TSSOP DGG Tape and reel SN74ALVCH16501DGGR ALVCH16501 VFBGA GQL SN74ALVCH16501KR Tape and reel VH501 VFBGA ZQL (Pb-free) 74ALVCH16501ZQLR (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. Widebus, UBT are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 1995 2004, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) GQL OR ZQL PACKAGE (TOP VIEW) A B C D E F G H J K 1 2 3 4 5 6 SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024J JULY 1995 REVISED OCTOBER 2004 To ensure the high-impedance state during power up or power down, OEBA should be tied to V CC through a pullup resistor, and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. TERMINAL ASSIGNMENTS A LEAB OEAB GND CLKAB B GND GND C V CC V CC D GND GND E F A10 A11 B11 B10 G A12 A13 GND GND B13 B12 H A14 A15 V CC V CC B15 B14 J A16 A17 GND GND B17 B16 K A18 OEBA LEBA GND CLKBA B18

www.ti.com CLK CLK OEAB CLKAB LEAB LEBA CLKBA OEBA To 17 Other Channels Pin numbers shown are for the DGG and DL packages. SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024J JULY 1995 REVISED OCTOBER 2004 FUNCTION TABLE (1) INPUTS OUTPUT B OEAB LEAB CLKAB A L X X X Z H H X L L H H X H H H L L L H L H H H L H X B (2) H L L X B (3) (1) A-to-B data flow is shown; B-to-A flow is similar, but uses OEBA LEBA, and CLKBA. (2) Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low (3) Output level before the indicated steady-state input conditions were established space LOGIC DIAGRAM (POSITIVE LOGIC)

www.ti.com ABSOLUTE MAXIMUM RATINGS (1) RECOMMENDED OPERATING CONDITIONS (1) SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024J JULY 1995 REVISED OCTOBER 2004 over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT V CC Supply voltage range -0.5 4.6 V Except I/O ports (2) -0.5 4.6 V I Input voltage range V I/O ports (2) (3) -0.5 V CC 0.5 V O Output voltage range (2) (3) -0.5 V CC 0.5 V I IK Input clamp current V I -50 mA I OK Output clamp current V O -50 mA I O Continuous output current mA Continuous current through each V CC or GND 100 mA DGG package θ JA Package thermal impedance (4) DL package C/W GQL/ZQL package T stg Storage temperature range -65 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) This value is limited to 4.6 V maximum. (4) The package thermal impedance is calculated in accordance with JESD 51-7. MIN MAX UNIT V CC Supply voltage 1.65 3.6 V V CC 1.65 V to 1.95 V 0.65 V CC V IH High-level input voltage V CC 2.3 V to 2.7 V 1.7 V V CC 2.7 V to 3.6 V V CC 1.65 V to 1.95 V 0.35 V CC V IL Low-level input voltage V CC 2.3 V to 2.7 V 0.7 V V CC 2.7 V to 3.6 V 0.8 V I Input voltage V CC V V O Output voltage V CC V V CC 1.65 V V CC 2.3 V -12 I OH High-level output current mA V CC 2.7 V -12 V CC V -24 V CC 1.65 V V CC 2.3 V I OL Low-level output current mA V CC 2.7 V V CC V Δ Δ v Input transition rise or fall rate ns/V T A Operating free-air temperature -40 C (1) All unused control inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004.

www.ti.com ELECTRICAL CHARACTERISTICS TIMING REQUIREMENTS SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024J JULY 1995 REVISED OCTOBER 2004 over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V CC MIN TYP (1) MAX UNIT I OH -100 µ A 1.65 V to 3.6 V V CC 0.2 I OH mA 1.65 V 1.2 I OH mA 2.3 V V OH 2.3 V 1.7 V I OH -12 mA 2.7 V 2.2 V 2.4 I OH -24 mA V I OL 100 µ A 1.65 V to 3.6 V 0.2 I OL mA 1.65 V 0.45 I OL mA 2.3 V 0.4 V OL V 2.3 V 0.7 I OL mA 2.7 V 0.4 I OL mA V 0.55 I I V I V CC or GND 3.6 V µ A V I 0.58 V 1.65 V V I 1.07 V 1.65 V -25 V I 0.7 V 2.3 V I I(hold) V I 1.7 V 2.3 V -45 µ A V I 0.8 V V V I V V -75 V I V to 3.6 V (2) 3.6 V 500 I OZ (3) V O V CC or GND 3.6 V µ A I CC V I V CC or GND, I O 3.6 V µ A Δ I CC One input at V CC 0.6 Other inputs at V CC or GND V to 3.6 V 750 µ A C i Control inputs V I V CC or GND 3.3 V pF C io A or B ports V O V CC or GND 3.3 V pF (1) All typical values are at V CC 3.3 T A (2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. (3) For I/O ports, the parameter I OZ includes the input leakage current. over recommended operating free-air temperature range (unless otherwise noted) (see Figure V CC 2.5 V V CC 3.3 V V CC 2.7 V 0.2 V 0.3 V UNIT MIN MAX MIN MAX MIN MAX f clock Clock frequency 150 150 150 MHz LE high 3.3 3.3 3.3 t w Pulse duration ns CLK high or low 3.3 3.3 3.3 Data before CLK 2.2 2.1 1.7 t su Setup time CLK high 1.9 1.6 1.5 ns Data before LE CLK low 1.3 1.1 Data after CLK 0.6 0.6 0.7 t h Hold time ns Data after LE CLK high or low 1.4 1.7 1.4

www.ti.com SWITCHING CHARACTERISTICS OPERATING CHARACTERISTICS SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024J JULY 1995 REVISED OCTOBER 2004 over recommended operating free-air temperature range (unless otherwise noted) (see Figure V CC 2.5 V V CC 3.3 V V CC 2.7 V FROM TO 0.2 V 0.3 V PARAMETER UNIT (INPUT) (OUTPUT) MIN MAX MIN MAX MIN MAX f max 150 150 150 MHz A or B B or A 4.8 4.5 3.9 t pd LE 1.1 5.7 5.3 1.3 4.6 ns A or B CLK 1.2 6.1 5.6 1.4 4.9 t en OEAB B 5.8 5.3 4.6 ns t dis OEAB B 1.5 6.2 5.7 1.4 ns t en OEBA A 1.3 6.3 1.1 ns t dis OEBA A 1.3 5.3 4.6 1.3 4.2 ns T A C V CC 2.5 V V CC 3.3 V PARAMETER TEST CONDITIONS UNIT TYP TYP Outputs enabled C pd Power dissipation capacitance C L pF, f MHz pF Outputs disabled

www.ti.com PARAMETER MEASUREMENT INFORMATION VM VM VMVM VMVM VMVM VOH VOL thtsu From Output Under Test CL (see Note A) LOAD CIRCUIT S1 Open GND RL RL Output Control (low-level enabling) Output Waveform 1 S1 at VLOAD (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 0 V VOL + VΔ VOH − VΔ 0 V VI 0 V 0 V tw VI VI VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Timing Input Data Input Input tpd tPLZ/tPZL tPHZ/tPZH Open VLOAD GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ /char????????10 MHz, ZO = 50 Ω . D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. 0 V VI VM tPHL VM VM VI 0 V VOH VOL Input Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VM VM tPLH VLOAD VLOAD/2 1.8 V 2.7 V 1 kΩ 500 Ω 500 Ω 500 Ω VCC RL 2 × VCC 6 V 6 V VLOAD CL 30 pF 30 pF 50 pF 50 pF 0.15 V 0.15 V 0.3 V 0.3 V VΔ VCC VCC 2.7 V 2.7 V VI VCC/2 VCC/2 1.5 V 1.5 V VM tr/tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns INPUT SN74ALVCH16501 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS SCES024J JULY 1995 REVISED OCTOBER 2004 Figure Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 74ALVCH16501DGGRG4 ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVCH16501DLG4 ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVCH16501DLRG4 ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 74ALVCH16501ZQLR ACTIVE BGA MI CROSTA R JUNI OR ZQL 56 1000 Green (RoHS & no Sb/Br) SNAGCU Level-1-260C-UNLIM SN74ALVCH16501DGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVCH16501DL ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVCH16501DLR ACTIVE SSOP DL 56 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ALVCH16501KR ACTIVE BGA MI CROSTA R JUNI OR GQL 56 1000 TBD SNPB Level-1-240C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2006 Addendum-Page 1

MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040048/E 12/01

48 PINS SHOWN

0.730 (18,54) 0.720 (18,29) 4828 0.370 (9,40) (9,65) 0.380 Gage Plane DIM 0.420 (10,67) 0.395 (10,03) A MIN A MAX 0.010 (0,25) PINS ** 0.630 (16,00) (15,75) 0.620 0.010 (0,25) Seating Plane 0.020 (0,51) 0.040 (1,02) 0.008 (0,203) 0.0135 (0,343) 0.008 (0,20) MIN A 0.110 (2,79) MAX 0.299 (7,59) 0.291 (7,39) 0.004 (0,10) M0.005 (0,13) 0.025 (0,635) 0°–/C02578° 0.005 (0,13) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-118

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97 0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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