VESD1-S24-D12-SIP

VESD1-SIP_10 CUI | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 3

Technical content

rev. page date rev. page date DESCRIPTION: dc-dc converter 1 of 3 PART NUMBER: VESD1-SIP

features

• isolated 1 W output
• temperature range: -40°C~+85°C
• unregulated
• high efficiency to 80%
• dual voltage output
• small footprint
• SIP package style
• industry standard pinout
• UL94-V0 package
• no heatsink required
• 3K Vdc isolation
• power density 0.85 W/cm³
• no external component required
• low cost

description

Designed to convert fixed volt- ages into an isolated voltage, the VESD1-SIP series is well suited for providing board-mount local supplies in a wide range of appli- cations, including mixed analog/digital circuits, test & measurement equip., process/machine controls, data- com/telecom fields, etc... The semi-regulated output can be followed by 3-terminal regulators to provide output protection, in addition to output regulation. MODEL Input Voltage Output Output Current Package Nominal Range Voltage Max. Min. Efficiency Style UL60950 VESD1-S5-D5-SIP 5 Vdc 4.5~5.5 Vdc ±5 Vdc ±100 mA ±10 mA 72% SIP YES VESD1-S5-D9-SIP 5 Vdc 4.5~5.5 Vdc ±9 Vdc ±56 mA ±6 mA 75% SIP YES VESD1-S5-D12-SIP 5 Vdc 4.5~5.5 Vdc ±12 Vdc ±42 mA ±5 mA 78% SIP YES VESD1-S5-D15-SIP 5 Vdc 4.5~5.5 Vdc ±15 Vdc ±33 mA ±4 mA 79% SIP YES VESD1-S12-D5-SIP 12 Vdc 10.8~13.2 Vdc ±5 Vdc ±100 mA ±10 mA 74% SIP YES VESD1-S12-D9-SIP 12 Vdc 10.8~13.2 Vdc ±9 Vdc ±56 mA ±6 mA 76% SIP YES VESD1-S12-D12-SIP 12 Vdc 10.8~13.2 Vdc ±12 Vdc ±42 mA ±5 mA 79% SIP YES VESD1-S12-D15-SIP 12 Vdc 10.8~13.2 Vdc ±15 Vdc ±33 mA ±4 mA 80% SIP YES VESD1-S15-D5-SIP 15 Vdc 13.5~16.5 Vdc ±5 Vdc ±100 mA ±10 mA 74% SIP NO VESD1-S15-D9-SIP 15 Vdc 13.5~16.5 Vdc ±9 Vdc ±56 mA ±6A 75% SIP NO VESD1-S15-D12-SIP 15 Vdc 13.5~16.5 Vdc ±12 Vdc ±42 mA ±5 mA 79% SIP NO VESD1-S15-D15-SIP 15 Vdc 13.5~16.5 Vdc ±15 Vdc ±33 mA ±4 mA 79% SIP NO VESD1-S24-D5-SIP 24 Vdc 21.6~26.4 Vdc ±5 Vdc ±100 mA ±10 mA 74% SIP YES VESD1-S24-D9-SIP 24 Vdc 21.6~26.4 Vdc ±9 Vdc ±56 mA ±6 mA 76% SIP YES VESD1-S24-D12-SIP 24 Vdc 21.6~26.4 Vdc ±12 Vdc ±42 mA ±5 mA 80% SIP YES VESD1-S24-D15-SIP 24 Vdc 21.6~26.4 Vdc ±15 Vdc ±33 mA ±4 mA 81% SIP YES

rev. page date DESCRIPTION: dc-dc converter 2 of 3 PART NUMBER: VESD1-SIP GENERAL short circuit protection <1 second temperature rise at full load 25°C Max, 15°C typ. cooling free air convection operating temperature range -40°C to +85°C storage temperature range -55°C to +125°C soldering temperature 300°C (1.5mm from case for 10 sec.) storage humidity range <95% case material plastic (UL94-V0) safety 2 approved to UL60950 (E222736) MTBF >3,500,000 hrs. burn-in full load at +85°C, for 4 hours at no-load and 4 hours at full load. ISOLATION SPECIFICATIONS item test conditions min. typ. max units isolation voltage tested for 1 min. 3000 Vdc insulation resistance test at 500 Vdc 1000 M Ω DIMENSIONS (mm) 6.0012 5 6 7 1 2 5 6 7 : All Pins on a 2.54mm pitch; all pin diameters are 0.50mm; all dimensions in mm. Side View Bottom View 19.60 10.00 4.10 12 56 7 15.242.00 1.25 2.54 2.54 Layout 1.00 + 0.15/-00 +Vin -Vin -Vout COM +Vout Pin Function TYPICAL CHARACTERISTICS OUTPUT item test conditions min. typ. max. units output power 0.1 1 W line regulation for Vin change of 1% 1.2 % load regulation 10% to 100% full load 10 15 % output voltage accuracy see tolerance envelope graph temperature drift @ 100% load 0.03 %/°C output ripple 20 MHz bandwidth 100 150 mVp-p switching frequency full load, nominal input 83 100 125 KHz NOTE: 1. All specifications measured at TA=25°C, humidity <75%, nominal input voltage and rated output load unless otherwise specified. 2. See table on page 1 for available models

rev. page date DESCRIPTION: dc-dc converter 3 of 3 PART NUMBER: VESD1-SIP APPLICATION NOTES: - Input filtering To reduce the reflected ripple current and minimize EMI, especially when the converter input is more than 2” away from the DC source, it is recommended to connect a low ESR electrolytic capacitor between Vin and Gnd. The values suggested are as shown in Table 1. If additional filtering is required, the capacitance may be increased, or expanded to an LC network as shown in Figure 1. Input Voltage External Input Capacitance 4.7 μF5 V 12 V 2.2 μF 15 V 2.2 μF 24 V 1.0 μF TABLE 1 Vout External Ouput Capacitance 10 μF5 V 9 V 4.7 μF 12 V 2.2 μF

15 V 1 μF

24 V 0.47 μF TABLE 2 <Figure 1> +Vin -Vin +Vout COMDCC L L DC L C C -Vout +Vin -Vin +Vin -Vin REG +Vout -Vout COM +Vout DC DC DC DC REG REG COM -Vout - Minimum loading The converter needs a minimum of 10% loading to maintain output regulation. Operation under no-load conditions will not cause immediate damages but may reduce reliability, and cause performance not to meet specifications. - Regulation With a semi-regulated design, the converter’s output voltage varies with load current and will change proportionally to the input voltage. If regulated output is needed, an external regulator can be used as shown in Figure 2. - Protection The converter has minimal protection against input over- voltage or output over-load, and may be permanently damaged if exposed to these conditions. An input clamping device can be used for input voltage limiting. An input fuse or an output fuse also be used to protect against over-loading. - Dual outputs used as a single output The +Vout and -Vout can be used to obtain a single output that is the sum of the two outputs. In this case, the COM pin shouldn’t be used. - External Regulator An external 3-terminal regulator can be connected to the output of the converter to achieve full regulation. Make sure the converter’s output voltage provides sufficient head room for the regulator. An additional benefit is that the built-in protection features in the regulator, such as OCP, OTP, etc, will protect the converter also. In a complimentory supply, a negative output regulator must be used to achieve the negative regulated output. - Output filtering An output capacitor is needed to meet output ripple requirements as shown in Table 2.Output capacitance may be increased for additional filtering, but should not exeed 10μF or expanded to an LC network as in Figure 1.