VESD05A6-HAF_V01 VISHAY | Alldatasheet

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www.vishay.com Vishay Semiconductors Rev. 1.7, 07-Jan-2019 1 Document Number: 81311 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 6-Line ESD Protection Diode Array in LLP75 MARKING (example only) Dot = pin 1 marking XX = date code  YY = type code (see table below) DESIGN SUPPORT TOOLS

FEATURES

  • Ultra compact LLP75-7L package
  • 6-line ESD protection
  • Low leakage current I R < 1 μA
  • Low load capacitance CD = 40 pF
  • ESD immunity acc. IEC 61000-4-2 ± 30 kV contact discharge ± 30 kV air discharge
  • Working voltage range VRWM = 5 V
  • e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn)
  • Material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 20517 19371 6 54 1 2 21001 XX YY click logo to get started Available Models

ORDERING INFORMATION

DEVICE NAME ORDERING CODE TAPED UNITS PER REEL (8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY VESD05A6-HAF VESD05A6-HAF-GS08 3000 15 000 PACKAGE DATA DEVICE NAME PACKAGE NAME TYPE CODE WEIGHT MOLDING COMPOUND FLAMMABILITY RATING MOISTURE SENSITIVITY LEVEL SOLDERING CONDITIONS VESD05A6-HAF LLP75-7L AS 4.2 mg UL 94 V-0 MSL level 1 (according J-STD-020) Peak temperature max. 260 °C ABSOLUTE MAXIMUM RATINGS RATING TEST CONDITION SYMBOL VALUE UNIT Peak pulse current BiAs-mode: each input (pin 1 to pin 6) to ground (pin 2); acc. IEC 61000-4-5; t p = 8/20 μs; single shot IPPM 5A Peak pulse power BiAs-mode: each input (pin 1 to pin 6) to ground (pin 2); acc. IEC 61000-4-5; tp = 8/20 μs; single shot PPP 60 W ESD immunity Acc. IEC61000-4-2; 10 pulses BiAs-Mode: each input (pin 1 to pin 6) to ground (pin 2) Contact discharge VESD ± 30 kV Air discharge VESD ± 30 kV Operating temperature Junction temperature T J -40 to +125 °C Storage temperature TSTG -55 to +150 °C

www.vishay.com Vishay Semiconductors Rev. 1.7, 07-Jan-2019 2 Document Number: 81311 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 APPLICATION NOTE: a) With the VESD05A6-HAF 6 different signal or data lines can be clamped to ground. Due to the different clamping levels in forward and reverse direction the VESD05A6-HAF clamping behavior is bidirectional and asymmetrical (BiAs). b) If symmetrical clamping behaviour is required the VESD05A6-HAF can also be used as a bidirectional symmetrical protection device protecting up to 5 lines. In this case pin 7 must not be connected. Note

  • BiAs mode (between pin 1, 2, 3, 4, 5 or 6 and pin 7) ELECTRICAL CHARACTERISTICS (Between pin 1, 2, 3, 4, 5 or 6, and pin 7) (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Protection paths Number of lines which can be protected N channel - - 6 lines Reverse stand-off voltage Max. reverse working voltage V RWM --5 V Reverse voltage at I R = 1 μA V R 5--V Max. reverse current at VR = 5 V I R - < 0.1 1 μA Reverse breakdown voltage at IR = 1 mA V BR 66 . 6 7 . 5V Reverse clamping voltage at IPP = 1 A V C -8 . 1 1 0V at IPP = IPPM = 5 A V C - 11.3 12 V Forward clamping voltage at IPP = 1 A V F -1 . 5 1 . 8V at IPP = IPPM = 5 A V F -3 . 2 4 . 5V Line capacitance at VR = 0 V; f = 1 MHz C D -4 0 5 0 p F at VR = 2.5 V; f = 1 MHz C D -2 4-p F L6 19365 6 54 1 2 19366 6 54 1 2

www.vishay.com Vishay Semiconductors Rev. 1.7, 07-Jan-2019 3 Document Number: 81311 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) Fig. 1 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) Fig. 2 - 8/20 µs Peak Pulse Current Wave Form acc. IEC 61000-4-5 Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR Fig. 6 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP 0 % 20 % 40 % 60 % 80 % 100 % 120 % - 1 0 0 1 02 03 04 05 06 07 0 809 0 1 0 0 Time (ns) Discharge Current IESD Rise time = 0.7 ns to 1 ns 53 % 27 % 20557 0 % 20 % 40 % 60 % 80 % 100 % 01 0 2 0 3 0 4 0 Time (µs) IPPM 20 µs to 50 % 8 µs to 100 % 20548 012345 VR (V) CD (pF) f = 1 MHz 19358 0.001 0.01 0.1 100 VF (V) IF (mA) 19359 0.01 0.1 1 10 100 1000 IR (µA) VR (V) 19360 0 5 10 15 20 25 IPP (A) VC (V) 19361 Measured acc. IEC 61000-4-5 (8/20 µs - wave form) forward reverse VC

www.vishay.com Vishay Semiconductors Rev. 1.7, 07-Jan-2019 4 Document Number: 81311 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Fig. 7 - Typical Clamping Performance at + 8 kV Contact Discharge (acc. IEC 61000-4-2) Fig. 8 - Typical Clamping Performance at - 8 kV Contact Discharge (acc. IEC 61000-4-2) Fig. 9 - Typical Peak Clamping Voltage at ± ESD Contact Discharge (acc. IEC 61000-4-2) - 20 - 10 - 10 0 10 20 30 40 50 60 70 809 0 19363 t (ns) VC-ESD (V) acc. IEC 61000-4-2 + 8 kV contact discharge - 70 - 60 - 50 - 40 - 30 - 20 - 10 - 10 0 10 20 30 40 50 60 70 809 0 19362 t (ns) VC-ESD (V) acc. IEC 61000-4-2 - 8 kV contact discharge - 300 - 250 - 200 - 150 - 100 - 50 100 150 200 250 300 0 5 10 15 20 25 30

19364 VC-ESD (V)

VESD (kV) VC-ESD acc. IEC 61000-4-2 contact discharge

www.vishay.com Vishay Semiconductors Rev. 1.7, 07-Jan-2019 5 Document Number: 81311 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PACKAGE DIMENSIONS in millimeters (Inches): LLP75-7L 1.05 (0.041) 0.5 (0.020) 0.95 (0.037) Heat sink 0.3 (0.012) 0.2 (0.008) 0.3 (0.012) 0.2 (0.008) 0.3 (0.012) 0.2 (0.008) 0.55 (0.022) 0.45 (0.018) 0.6 (0.024) 0.25 (0.010) 0.6 (0.024) 0.54 (0.021) 0.05 (0.002) 0 (0.000) 0.15 (0.006) 1.65 (0.065) 1.55 (0.061) 1.65 (0.065) 1.55 (0.061) Pin 1 marking 0.5 (0.020) 0.5 (0.020) 1 (0.039) 0.25 (0.010) Solder resist mask Solder padDocument no.:S8-V-3906.02-014 (4) 20500 Created - Date: 04. April 2006 Foot print recommendation: 1 (0.039) 1 (0.039)

www.vishay.com Vishay Semiconductors Rev. 1.7, 07-Jan-2019 6 Document Number: 81311 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 LLP75-7x F 5 S 9 Pin 1 - location Pad layout - view from top / seen at bottom side 10.12.2009

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