VECANA01

VECANA01 BURR-BROWN | Alldatasheet

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Technical content

10-Channel, 12-Bit DATA ACQUISITION SYSTEM

FEATURES

l 10 FULLY DIFFERENTIAL INPUTS l 5 SIMULTANEOUS SAMPLED CHANNELS PLUS 2 SYNCHRONIZED SAMPLING CHANNELS l 3 SYNCHRONIZED 12-BIT ADCs l 12.8 ms THROUGHPUT RATE l DIGITALLY SELECTABLE INPUT RANGES l –5V POWER SUPPLIES l SERIAL DIGITAL INPUT/OUTPUTS l 7 SIGN AND 3 DIGITALLY PROGRAMMABLE WINDOW COMPARATOR

APPLICATIONS

l THREE PHASE POWER CONTROL l UNINTERRUPTABLE POWER SUPPLIES l VIBRATION ANALYSIS

DESCRIPTION

The VECANA01 consists of three 12-bit analog-to- digital converters preceded by five simultaneously operating sample-hold amplifiers, and multiplexers for 10 differential inputs. The ADCs have simulta- neous serial outputs for high speed data transfer and data processing. The VECANA01 also offers a programmable gain am- plifier with programmable gains of 1.0V/V, 1.25V/V, 2.5V/V, and 5.0V/V. Channel selection and gain selec- tion are selectable through the serial input control word. The high through put rate is maintained by simulta- neously clocking in the 13-bit input control word for the next conversion while the present conversions are clocked out. The part also contains an 8-bit digital-to-analog con- verter whose digital input is supplied as part of the input control word. Copyright © 2000, Texas Instruments Incorporated SBAS155 Printed in U.S.A. October, 2000 VECANA01 ADC 2 12-BitPGA 2SH 2 MUX 2 ADOUT2B1P/N IVP/N B2P/N ADC 3 12-BitPGA 3SH 3 MUX 3 ADOUT3 AN1P/N IWP/N AN3P/N ADC 1 12-BitPGA 1SH 1 MUX 1 ADOUT1A1P/N IUP/N A2P/N AN2P/N Control Logic 2.5V Ref Input Setup Register DAC 8-Bit DAOUT ADBUSY COMP

3 ILIM

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Full Scale Voltage, Differential G = 1.0V/V –2.5 V G = 1.25V/V –2.0 V G = 2.5V/V –1.0 V G = 5.0V/V –0.5 V Common-Mode Voltage –0.5 See Table VII V Impedance 1012 W Capacitance 20 pF THROUGHPUT SPEED Conversion Time CLK = 1.25MHz 10.4 ms Complete Cycle Acquire and Convert 12.8 ms Throughput Rate 78 kHz SAMPLING DYNAMICS S/H Droop Rate 0.1 mV/ms S/H Acquisition Time 0.5 ms S/H Aperture Delay 50 ns S/H Aperture Jitter 50 ps Sampling Skew, Channel-to-Channel 3n s DC ACCURACY Integral Linearity - ADC –0.5 –2 LSB Differential Linearity - ADC –0.5 –2 LSB No Missing Codes 12 Bits Integral Linearity - Asynchronous, Synchronous 0.5 –3 LSB Differential Linearity - Asynchronous, Synchronous 0.5 –3 LSB Full Scale Error G = 1.0V/V 2 % of FSR Full Scale Error Other Gains 4 % of FSR Full Scale Error Drift G = 1.0V/V –10 –100 ppm/ °C G = 2.5V/V –10 –100 ppm/ °C Zero Error - ADC G = 1.0V/V –0.5 –15 LSB Zero Error - Asynchronous, Synchronous G = 1.0V/V –0.5 –20 LSB Zero Error Drift G = 1.0V/V –0.5 ppm/ °C AC ACCURACY Total Harmonic Distortion f IN = 1kHz 92 dB fIN = 1MHz 70 dB CMR V CM = –0.5V, fCM = 1MHz 50 dB REFERENCE Internal Reference Voltage 2.5 V Internal Reference Accuracy –0.25 –2% Internal Reference Drift –10 ppm/ °C Internal Reference Source Current 10 mA External Reference Voltage Range 2.25 2.5 2.75 V for Specified Linearity External Reference Current Drain 10 mA DIGITAL INPUTS Logic Levels VIL 0 1.5 V VIH +3.5 +5 V IIL –10 mA IIH –10 mA Input Capacitance At All Digital Input Pins 15 pF DIGITAL OUTPUTS Data Format 12-Bit Serial Data Coding BTC VOL ISINK = 1.6mA 0 0.4 V VOH ISOURCE = 500mA 4.2 5 V Leakage Current –5 mA Output Capacitance At All Digital Output Pins 15 pF SPECIFICATIONS At VANA+ = +5V, VANA– = –5V, VDIG+ = +5V, VDIG– = –5V, and TA = –40°C to +85°C, using internal reference, fCLOCK = 1.25MHz. ANALOG-TO-DIGITAL CONVERTER CHANNELS VECANA01N PARAMETER CONDITIONS MIN TYP MAX UNITS

SPECIFICATIONS (Cont.) At VANA+ = +5V, VANA– = –5V, VDIG+ = +5V, VDIG– = –5V, and TA = –40°C to +85°C, using internal reference, fCLOCK = 1.25MHz. ANALOG-TO-DIGITAL CONVERTER CHANNELS POWER SUPPLIES Specified Performance IANA+ 15 mA IANA– –8 mA IDIG+ 12 mA IDIG– –10 mA Power Dissipation 225 mW TEMPERATURE RANGE Specified Performance –40 +85 °C Derated Performance –55 +125 °C Storage –65 +150 °C VECANA01N PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 8-Bits Output Range 0 +2.5 V Output Settling Time 0.5LSB 0.2 1 ms Linearity Error –1 LSB Differential Linearity –1 LSB Output Current 200 mA Offset Error –1 –10 mV Full Scale Error (including REF) –2% DIGITAL-TO-ANALOG CONVERTER VECANA01N PARAMETER CONDITIONS MIN TYP MAX UNITS The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. Differential Input Voltage Range of the –2.5 V Window Comparators Offset Error of the Window Comparators –20 –80 mV Hysteresis of the Window Comparators 60 100 mV Offset Error of the Sign Current Comparators –5 –20 mV Hysteresis of the Sign Current Comparators 10 30 mV Offset Error of the Sign Sensor Signal –5 –30 mV Comparators Hysteresis of the Sign Sensor Signal 75 90 mV Comparators Absolute Input Range of the Comparators –2.9 –3.2 V Delay Time of the Sign Comparators 25 150 ns Delay Time of the Window Comparators 250 1500 ns SIGN AND WINDOW COMPARATORS VECANA01 PARAMETER CONDITIONS MIN TYP MAX UNITS

Power Supply Voltages: SYMBOL DESCRIPTION MIN TYP MAX UNITS t CONV A/D Conversion Time 10.4 6.2 ms CLK A/D Conversion Clock 1.25 2.1 MHz t1 Setup Time for Conversion 50 ns Before Rising Edge of Clock t2 Hold Time for Conversion 50 ns After Rising Edge of Clock t3 Setup Time for Serial Out 125 ns t4 Setup Time for Serial Input 30 ns t5 Hold Time for Serial Input 30 ns CONVERSION AND DATA TIMING ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr- Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degrada- tion to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 4 3 2 1 VECANA01 68 67 66 NC IVN IVP NC B1N B1P NC B2N B2P NC NC B_2 B_1 V_ILIM V_COMP W_ILIM W_COMP NC IUN IUP NC A1N A1P NC A2N A2P NC NC A_2 A_1 U_ILIM U_COMP NC NC IWP IWN NC AN1P AN1N AN2P AN2N AN3P AN3N UP5V AGND UN5V REFGND REFIN REFOUT DAOUT DAIN 65 64 63 62 61 9 8 7 65 32 33 34 35 36 37 38 TP1 TP2 UDP5V DGND UDN5V NC ADOUT2 ADOUT3 ADOUT1 ADCLK ADCONV NPSH ADIN ADBUSY DATACLK NC NC 39 40 41 42 4327 28 29 30 31 PACKAGE SPECIFIED DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER MEDIA VECANA01 PLCC-68 312 –40 °C to +85°C VECANA01 VECANA01 Rails PACKAGE/ORDERING INFORMATION

1 AN3N AI Auxiliary analog input channel 3, Negative Side

2 AN3P AI Auxiliary analog input channel 3, Positive Side

3 AN2N AI Auxiliary analog input channel 2, Negative Side

4 AN2P AI Auxiliary analog input channel 2, Positive Side

5 AN1N AI Auxiliary analog input channel 1, Negative Side

6 AN1P AI Auxiliary analog input channel 1, Positive Side

7 NC — No Connection

8 IWN AI Analog input of phase W current, Negative Side

9 IWP AI Analog input of phase W current, Positive Side

10 NC — No Connection

11 IVN AI Analog input of phase V current, Negative Side

12 IVP AI Analog input of phase V current, Positive Side

13 NC — No Connection

14 B1N AI Signal B analog input of position sensor 1,

15 B1P AI Signal B analog input of position sensor 1,

16 NC — No Connection

17 B2N AI Signal B analog input of position sensor 2,

18 B2P AI Signal B analog input of position sensor 2,

19 NC — No Connection

20 NC — No Connection

21 B_2 DO Sign of signal B position sensor 2 (B2P, B2N). If the value is positive (B2P > B2N) B_2 is 1, if the value is negative (B2P < B2N) B_2 is 0. 22 B_1 DO Sign of signal B position sensor 1 (B1P, B1N). If the value is positive (B1P > B1N) B_1 is 1, if the value is negative (B1P < B1N) B_1 is 0. 23 V_ILIM DO Over-current output of phase V, active low. If IVP-IVN is greater then the positive limiting value or less than the negative limiting value, U_ILIM becomes 0. 24 V_COMP DO Sign of phase V current signal (IVP, IVN). If the value is positive (IVP > IVN) V_COMP is 1, if the value is negative (IVP < IVN) V_COMP is 0. 25 W_ILIM DO Over-current output of phase W, active low. If IWP-IWN is greater then the positive limiting value or less than the negative limiting value, U_ILIM becomes 0. 26 W_COMP DO Sign of phase W current signal (IWP, IWN). If the value is positive (IWP > IWN) W_COMP is 1, if the value is negative (IWP < IWN) W_COMP is 0. 27 TP1 — Test pin, do not connect to in normal operation. 28 TP2 — Test pin, do not connect to in normal operation.

29 UDP5V P Digital Supply Voltage, +5V

30 DGND P Digital Supply Voltage, Ground

31 UDN5V P Digital Supply Voltage, –5V

32 NC — No Connection

33 ADOUT2 DO Serial output signal of A/D converter 2. Rising clock edges of ADCLK outputs the bits of the A/D converter with MSB first. 34 ADOUT3 DO Serial output signal of A/D converter 3. Rising clock edges of ADCLK outputs the bits of the A/D converter with MSB first. 35 ADOUT1 DO Serial output signal of A/D converter 1. Rising clock edges of ADCLK outputs the bits of the A/D converter with MSB first. 36 ADCLK DI Clock for the A/D converters. The nominal clock frequency is 1.25MHz. 37 ADCONV DI Start signal for the A/D converter, active low. The first rising clock edge of ADCLK, when ADCONV is 0, starts the conversion.

38 NPSH DI Sample/hold control for sampling the position

sensor signals. If the value is 1, the signals are sampled, if it is 0 they are stored.

39 ADIN DI Serial input signal for programming the D/A

converter for setting the limit value of the current signals for the input voltage range of the A/D converters and for the input multiplexer of the A/D converters.

40 ADBUSY DO Conversion is executing, active low

41 DATACLK — Test pin, do not connect to in normal operation.

42 NC — No Connection

43 NC — No Connection

44 NC — No Connection

45 NC — No Connection

46 U_COMP DO Sign of phase U current signal (IUP, IUN). If the value is positive (IUP > IUN) U_COMP is 1, if the value is negative (IUP < IUN) U_COMP is 0. 47 U_ILIM DO Over-current output of phase U, active low. If IUP-IUN is greater then the positive limiting value or less than the negative limiting value, U_ILIM becomes 0. 48 A_1 DO Sign of signal A position sensor 1 (A1P, A1N). If the value is positive (A1P > A1N) A_1 is 1, if the value is negative (A1P < A1N) A_1 is 0. 49 A_2 DO Sign of signal A position sensor 2 (A2P, A2N). If the value is positive (A2P > A2N) A_2 is 1, if the value is negative (A2P < A2N) A_2 is 0.

50 NC — No Connection

51 NC — No Connection

52 A2P AI Signal A analog input of position sensor 2,

53 A2N AI Signal A analog input of position sensor 2,

54 NC — No Connection

55 A1P AI Signal A analog input of position sensor 1,

56 A1N AI Signal A analog input of position sensor 1,

57 NC — No Connection

58 IUP AI Analog input of phase U current, Positive Side

59 IUN AI Analog input of phase U current, Negative Side

60 NC — No Connection

61 DAIN AI Input for setting the over-current value. Normally connected to DAOUT

62 DAOUT AO Output of the D/A converter for programming the

over-current limit. Output is programmable from 0V to +2.5V.

63 REFOUT AO Output pin of the integrated reference source,

nominal voltage 2.5V. 64 REFIN AI Input pin for an external reference voltage. 65 REFGND P Ground pin of the reference source.

66 UN5V P Analog Supply Voltage, –5V

67 AGND P Analog Supply Voltage, Ground

68 UP5V P Analog Supply Voltage, +5V

PIN NO NAME TYPE (1) DESCRIPTION PIN NO NAME TYPE (1) DESCRIPTION NOTE: (1) AI is Analog Input, AO is Analog Output, DI is Digital Input, DO is Digital Output, P is Power Supply Connection.

TYPICAL PERFORMANCE CURVES At VANA+ = +5V, VANA– = –5V, VDIG+ = +5V, VDIG– = –5V and TA = 25°C, using internal reference, fCLOCK = 1.25MHz. OFFSET vs TEMPERATURE Temperature (°C) 1.4 1.2 1.0 0.8 0.6 0.4 0.2 –55 –40 –25 0 25 70 85 125 Offset (LSB) FULL SCALE vs TEMPERATURE Temperature (°C) 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 –55 –40 –25 0 25 70 85 125 Full Scale (%) DIFFERENTIAL LINEARITY (MIN) vs TEMPERATURE Temperature (°C) 0.000 –0.100 –0.200 –0.300 –0.400 –0.500 –0.600 –0.700 –55 –40 –25 0 25 70 85 125 Differential Linearity (LSB) DIFFERENTIAL LINEARITY (MAX) vs TEMPERATURE Temperature (°C) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 –55 –40 –25 0 25 70 85 125 Differential Linearity (LSB) INTEGRAL LINEARITY (MIN) vs TEMPERATURE Temperature (°C) 0.000 –0.050 –0.100 –0.150 –0.200 –0.250 –0.300 –0.350 –0.400 –0.450 –55 –40 –25 0 25 70 85 125 Integral Linearity (LSB) INTEGRAL LINEARITY (MAX) vs TEMPERATURE Temperature (°C) 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 –55 –40 –25 0 25 70 85 125 Integral Linearity (LSB)

TYPICAL PERFORMANCE CURVES (Cont.) At VANA+ = +5V, VANA– = –5V, VDIG+ = +5V, VDIG– = –5V and TA = 25°C, using internal reference, fCLOCK = 1.25MHz. DAC OFFSET vs TEMPERATURE Temperature (°C) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 –55 –40 –25 0 25 70 85 125 DAC Offset (mV) DAC FULL SCALE vs TEMPERATURE Temperature (°C) –0.05 –0.10 –0.15 –0.20 –0.25 –0.30 –0.35 –0.40 –0.45 –55 –40 –25 0 25 70 85 125 DAC Full Scale (%)

FIGURE 1. Functional Diagram. the output data rate (see Figure 2).

FIGURE 2. Timing Diagram. NOTE: (1) See the specification table for timing specifications. (2) 50% duty cycle. The VECANA01 contains seven sample-and-hold amplifiers. nously to a reference point. (Table IX gives the analog input/digital output relationships). third channel, only the IW input is gain changed by the PGA.

TABLE IV. Input - Output Relation. CONFIGURABLE PARAMETERS section). (logic “0”), (see Table IV). FIGURE 4. (a) Differential Signal Source. (b) Single-ended positioning sensor measurement.

TABLE V. Over-Current Limit as a Function DAC Input. TABLE VI. The Limiting Value as Function of DAC Input. value), The DAIN value will determine the fixed range. Normally this pin is connected to DAOUT (the DAC output). range of 0V to 2.5V (see Table I). mately 1ms and typical does not disturb most applications. 0-2 and the signals that are converted. input signals IU, IV, and IW. FIGURE 5. Acquisition of the Current Sign and of the Over- NOTE: (1) See Table VIII for Operation. TABLE VII. Input Controls for Synchronous Sample Holds.

FIGURE 6. Basic Circuit Configuration.

0H 5.0V/V –0.5V 1H 2.5V/V –1.0V 2H 1.25V/V –2.0V 3H 1.0V/V –2.5V TABLE X. Gain Select Information. GAIN 5V/V 2.5V/V 1.25V/V 1.0V/V FULL SCALE RANGE –0.5V –1.0V –2.0V –2.5V HEX CODE BINARY CODE +Full Scale (FS –1LSB) +0.49976 +0.9995V +1.999V +2.499 7FF H 0111 1111 1111 One Bit above Mid-Scale +0.244mV +0.488mV +0.976mV +1.22mV 001H 0000 0000 0001 Mid-Scale 0V 0V 0V 0V 000 H 0000 0000 0000 One Bit Below Mid-Scale –0.244V –0.488mV –0.976mV –1.22mV FFF H 1111 1111 1111 –Full Scale –0.500V –1.000V –2.000V –2.500V 800 H 1000 0000 0000 NOTE: The programmable gain function applies to all three input channels for ADC1 and ADC2. However, the programmable gain function only applies to the first input (IW) for ADC3. The other three inputs (AN1, AN2, and AN3) are not affected by the GAIN SEL input. They operate at a fixed gain of 1V/V and thus have a fixed –2.5V full scale input range. ANALOG INPUT BINARY TWO’S COMPLIMENT FORMAT TABLE IX. Analog Input - Digital Output Relationships. DIGITAL OUTPUT Input Select = 1H—Input AN3 is converted by ADC3. The output of the asynchronous sample holds, SH6 and SH7, are converted by PGA1/ADC 1 and PGA 2/ADC 2, respectively. Note that the inputs to SH6 and SH 7 are determined by previous Input Select values (see Table VIII). Thus, to properly convert the output of one of the asynchronous sample holds it is first necessary to choose its input with a previous conversion cycle. Also, the output of SH 6 or SH7 will only be converted if NPSH goes low before the ADCONV command is received. Input Select = 0 H— AN3 is converted by ADC 3. The inputs to PGA1/ADC 1 and PGA2/ADC 2 are undefined. PGA GAIN The PGA gain is determined by the Gain Select portion (bits 8 and 9) in the ADIN word (see Figure 2). There is one gain input that sets the same gain for all three PGAs. The gain values and allowable full-scale inputs are shown in Table X. For channels one and two the PGAs set the gain for all three analog inputs. For the third channel, only the IW input is gain changed by the PGA. Inputs AN1, AN2, and AN3 are connected to A/D converter three at a fixed gain of 1.0V/V regardless of the Gain Select value. CONVERSIONS FROM THE ASYNCHRONOUS SAMPLE HOLDS Decoding the Input Select value also determines which inputs are applied to the two asynchronously controlled sample holds (SH 6 and SH7) (see Table VIII.) One of the three possible inputs is selected by the Input Select value being 4, 5, or 6. The “No Effect” states indicate that these values of Input Select have no effect on the multiplexers at the input of SH 6 and SH7. When one of the “No Effect” values of Input Select is presented, the multiplexers will not be changed (i.e., their condition is determined by the last 4, 5, or 6 value of Input Select that existed prior to the “No Effect” state). Note that Input Select = 1 H presents the output of SH6 and SH7 to PGA1/ADC l and PGA 2/ADC 2, respec- tively (see Table VII). Therefore, in order to properly con- vert the asynchronous sampled signals, it is first necessary to choose an input signal (Input Select equal 5 or 6 in Table VIII) with one load/convert cycle and then convert the sample hold output (Input Select = 4 in Table VII) in a following conversion cycle. POWER SUPPLY The VECANA01 requires an analog and digital supply voltage of –5V. The substrate is connected to UP5V. The voltage difference between the analog and digital supply pin is not allowed to exceed a maximal value of 300mV. For this reason the circuit shown in Figure 7 is recommended for the power supply. The analog and digital power supplies are driven by a common source. Intermediate resistors provide for decoupling. Local current-limited voltage regulators gen- erate the –5V from the analog supply voltages –U B . This guarantees a further noise reduction. The diodes are respon- sible for protecting the regulation and prevent polarity inver- sion. The zener diode protects against over-voltage possible from over-voltages to the analog inputs. Typical values for the resistors and capacitors are: A » 3W

• R D » 3W
• C D » 22mF
• C A » 22mF
• C B » 100nF
• C R » 2.2mF

ORDERABLE DEVICE STATUS(1) PACKAGE TYPE PACKAGE DRAWING PINS PACKAGE QTY VECANA01 NRND PLCC FN 68 20 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. PACKAGE OPTION ADDENDUM www.ti.com 11-Oct-2004

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