VCNL36825T_V01 VISHAY | Alldatasheet

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Technical content

www.vishay.com Vishay Semiconductors Rev. 1.3, 14-Sep-2021 1 Document Number: 80235 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Proximity Sensor With Interrupt, VCSEL, and I2C Interface LINKS TO ADDITIONAL RESOURCES

DESCRIPTION

VCNL36825T integrates a prox imity sensor (PS), and a VCSEL into one small package. It incorporates photodiodes, amplifiers, and analog to digita l converting circuits into a single chip by CMOS process. PS programmable interrupt features of individual high and low thresholds offers the best utilization of resource and power saving on the microcontroller. PIN DEFINITION

FEATURES

  • Package type: surface-mount
  • Dimensions (L x W x H in mm): 2.0 x 1.25 x 0.5
  • Integrated modules: ve rtical cavity surface emitting laser (VCSEL), proximity sensor (PS), and signal conditioning IC
  • Interrupt function
  • 1.6 mm single hole opening design
  • Supply voltage range V DD: 2.64 V to 3.6 V
  • Low power consumption I2C (SMBus compatible interface)
  • Output type: I2C bus
  • Temperature compensation: -40 °C to +85 °C
  • Floor life: 168 h, MSL 3, according to J-STD-020
  • Material categorization: fo r definitions of compliance please see www.vishay.com/doc?99912 PROXIMITY FUNCTION
  • Immunity to red glow (940 nm IRED)
  • Programmable I VCSEL sink current
  • Intelligent cancellation to reduce cross talk phenomenon
  • Smart persistence scheme to reduce PS response time
  • Low power consumption mode
  • Sunlight cancellation up to 100 klx INTERRUPT
  • Programmable interrupt func tion for PS with upper and lower thresholds
  • Adjustable persistence to prevent false triggers for PS

APPLICATIONS

  • Handheld device
  • Consumer device
  • Industrial application
  • True wireless stereo (TWS) earphones 1I N T4V DD 2N C5 S C L 3G N D6S D A Design Tools Related Documents 333DDD3 D 3D Models Application Notes PRODUCT SUMMARY PART NUMBER OPERATING RANGE (mm) OPERATING VOLTAGE RANGE (V) I2C BUS VOLTAGE RANGE (V) VCSEL DRIVING CURRENT (mA) OUTPUT CODE ADC RESOLUTION PROXIMITY / AMBIENT LIGHT VCNL36825T 200 2.64 to 3.6 1.7 to 3.6 20 12 bit, I 2C1 2 b i t / -

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ORDERING INFORMATION

ORDERING CODE PACKAGING VOLUME (1) REMARKS VCNL36825T Tape and reel MOQ: 4500 pcs, 4500 pcs/reel 2.0 mm x 1.25 mm x 0.5 mm ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITION SYMBOL MIN. MAX. UNIT Supply voltage V DD -0.3 3.8 V Operation temperature range T amb -40 +85 °C Storage temperature range T stg -40 +100 °C BASIC CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITION SYMBOL MIN. TYP. MAX. UNIT Supply voltage (1) VDD 2.64 - 3.6 V Supply current Excludi ng VCSEL driving I DD 100 200 300 μA Shutdown current Light condition = dark; VDD = 3.3 V, Tamb = 25 °C IDD (SD) - 1 - μA I2C supply voltage V PULL UP 1.65 - - V I2C signal input, logic high V DD = 3.3 V V IH 1.26 - - V I2C signal input, logic low V DD = 3.3 V V IL - - 0.73 V Peak wavelength of VCSEL I F = 12 mA λp(VCSEL) - 940 - nm PS view angle horizontal - ± 45 - ° PS view angle vertical - ± 60 - ° VCSEL current setting 10 mA 12 mA 14 mA 16 mA 18 mA 20 mA Min. V

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  • Product specification with IEC / EN 60825-1:2014 compliance and above label BLOCK DIAGRAM LASER GND PD PS buffer SCL SDA INT VCSEL PS timing controller DSP Oscillator VDD Pin 4 Current driver Pin 3 Pin 1 Pin 6 Pin 5 I2C bus logic control VDD and anode are internally connected Pin 2 (n.c.)

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  • Data based on standard I 2C protocol requirement, not tested in production Fig. 1 - I2C Bus Timing Diagram I2C BUS TIMING CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) PARAMETER SYMBOL STANDARD MODE FAST MODE UNITMIN. MAX. MIN. MAX. Clock frequency f (I2CCLK) 10 100 10 400 kHz Bus free time between start and stop condition t (BUF) 4.7 - 1.3 - μs Hold time after (repeated) start condition; after this period, the first clock is generated t(HDSTA) 4.0 - 0.6 - μs Repeated start condition setup time t (SUSTA) 4.7 - 0.6 - μs Stop condition setup time t (SUSTO) 4.0 - 0.6 - μs Data hold time t (HDDAT) 0 3450 0 900 ns Data setup time t (SUDAT) 250 - 100 - ns I2C clock (SCK) low period t (LOW) 4.7 - 1.3 - μs I2C clock (SCK) high period t (HIGH) 4.0 - 0.6 - μs Clock / data fall time t (f) - 300 - 300 ns Clock / data rise time t (r) - 1000 - 300 ns VIH VIH t(LOW) VIL t(f) t(HIGH) t(SUDAT) P Stop condition S Start condition PS Start Stop I2C BUS CLOCK (SCLK) I2C BUS DATA (SDAT) I2C BUS CLOCK (SCLK) I2C BUS DATA (SDAT) t(r) t(HDSTA) t(HDDAT) VIL t(BUF) t(SUSTA) t(SUSTO) t(LOSEXT) t(LOWMEXT) t(LOWMEXT) SCLKACK SDAACK t(LOWMEXT)

www.vishay.com Vishay Semiconductors Rev. 1.3, 14-Sep-2021 5 Document Number: 80235 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PARAMETER TIMING INFORMATION Fig. 2 - I2C Bus Timing for Sending Word Command Format Fig. 3 - I2C Bus Timing for Receiving Word Command Format WSA6 SA5 SA4 SA3 SA2 SA1SA7 I C bus slave address byte SA6 SA5 SA4 SA3 SA2 SA0SA7 Command code SA1 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Data byte low Data byte high I2C BUS CLOCK (SCLK) I2C BUS DATA (SDAT) I2C BUS CLOCK (SCLK) I2C BUS DATA (SDAT) Start by master ACK by VCNL36825T ACK by VCNL36825T ACK by VCNL36825T ACK by VCNL36825T Stop by master W I C bus slave address byte Command code SA6 SA5 SA4 SA3 SA2 SA1SA7 SA6 SA5 SA4 SA3 SA2 SA0SA7 SA1 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 Data byte high R I C bus slave address byte Data byte low SA6 SA5 SA4 SA3 SA2 SA6 SA5 SA4 SA3 SA2 SA0SA7 SA1SA1SA7 I2C BUS CLOCK (SCLK) I2C BUS DATA (SDAT) I2C BUS CLOCK (SCLK) I2C BUS DATA (SDAT) I2C BUS CLOCK (SCLK) I2C BUS DATA (SDAT) Start by master ACK by VCNL36825T ACK by VCNL36825T ACK by VCNL36825T ACK by master Start by master Stop by master NACK by master

www.vishay.com Vishay Semiconductors Rev. 1.3, 14-Sep-2021 6 Document Number: 80235 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 TYPICAL PERFORMANCE CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) Fig. 4 - Normalized Spectral Response Fig. 5 - Forward Current vs. Forward Voltage Fig. 6 - VCSEL Profile Fig. 7 - IDD vs. Temperature 100 1000 10000 100 400 500 600 700 800 900 1000 Axis Title 1st line 2nd line 1st line 2nd line Relative Response (%) Wavelength (nm) 100 1000 10000 100 Axis Title 1st line 2nd line 1st line 2nd line IF - Forward Current (mA) VF - Forward Voltage (V) 2.5 100 1000 10000 Axis Title /g77 - Angular Displacement 2nd line 2nd line Ie, rel. - Relative Radiant Intensity 1st line 0.6 00.20.4 0.7 0.8 1.0 0.9 30° 40° 50° 60° 70° 80° 0° 20°10° 100 1000 10000 140 160 180 200 220 240 260 280 -40 -20 0 20 40 80 100 Axis Title 1st line 2nd line 1st line 2nd line IDD - Supply Current (µA) Temperature (°C)

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APPLICATION INFORMATION

Pin Connection With the Host VCNL36825T integrates proximity sensor, and IR VCSEL all together with I 2C interface. It is very easy for the baseband (CPU) to access PS output data via I2C interface without extra software algorithms. The hardware schematic is shown in the following diagram. One additional 1 μF capacitor in the circuit is used for power supply noise rejection, and 2.2 k Ω is proposed for the pull high resistors of I 2C except 10 kΩ applied on INT pin. Fig. 8 - Hardware Pin Connection Diagram Digital Interface VCNL36825T applies single slave address 0x 60 (HEX) of 7-bit addressing following I 2C protocol. All operations can be controlled by the command register. The simple command structure helps users easily program the operation setting and latch the light data from VCNL36825T. As Fig. 9 shows, VCNL36825T’s I2C command format is simple for read and write operations between VCNL36825T and the host. The white sections indicate host activity and the gray sections indicate VCNL36825T’s acknowledgement of the host access activity. Write word and read word protocol is suitable for accessing registers particularly for 12-bit PS data. Interrupt can be cleared by reading data out from register: INT_FLAG. All command codes should follow read word and write word protocols. Fig. 9 - Write Word and Read Word Protocol VDD INT INT SCL 1 µF GND SDA SCL SDA 2.2 kΩ2.2 kΩ 10 kΩ Vpull_up NC VCNL36825TBaseband NC or GND VDD S Slave address Wr A Command code A Data byte low A Data byte high A 17 8 11 1 81 8 P Send byte /g111 write command to VCNL36825T Slave address Wr A Command code A S Slave address Rd A Data byte low A Data byte high N P 11 8 11 7 11 8 1 8 1 1 S Receive byte /g111 read data from VCNL36825T S = start condition P = stop condition A = acknowledge N = not acknowledge Host action VCNL36825T response

www.vishay.com Vishay Semiconductors Rev. 1.3, 14-Sep-2021 8 Document Number: 80235 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Function Description VCNL36825T supports different kinds of mechanical designs to achieve the best proximity detection performance for any color of object with more flexibility. The basic PS function settings, such as measurement period, integration time, interrupt, PS start / stop and persistence, are handle d by the register PS_CONF2_L. PS_PERIOD controls the PS response time. PS_IT represents the duration of the energy being received. The PS_INT is asserted when the PS detection levels higher than the high threshold level setting (register: PS_THDH) or lower than low threshold (register: PS_THDL). If the interrupt function is enabled, the host reads the PS output data from VCNL36825T that save s host loading from periodically reading PS_DATA. More than that, INT_FLAG indicates the be havior of INT triggered unde r different conditions. PS_PERS sets up the PS_INT asserted conditions as long as the PS output value continually exceeds the threshold level. The intelligent cancellation level can be set on register: PS_CANC to reduce the cross talk phenomenon. A smart persistence (register: PS_SMART_PERS) is provided to get faster PS response time and prevent false trigger for PS. Note

  • All of reserved register are used for internal test. Please keep as default setting TABLE 1 - COMMAND CODE AND REGISTER DESCRIPTION COMMAND CODE DATE BYTE LOW / HIGH REGISTER NAME R / W DEFAULT VALUE FUNCTION DESCRIPTION 0x00 L PS_CONF1_L R / W 0x01 Calibration and on / off H PS_CONF1_H R / W 0x00 Initialization 0x03 L PS_CONF2_L R / W 0x01 PS period, persistence, interrupt, smart persistence, and PS start / stop H PS_CONF2_H R / W 0x00 PS integration ti me, multi pulse and interrupt function 0x04 L PS_CONF3_L R / W 0x00 PS force mode and sunlight light protect interrupt setting H PS_CONF3_H R / W 0x00 PS VCSEL current 0x05 L PS_THDL_L R / W 0x00 PS low interrupt threshold setting (data byte low) H PS_THDL_H R / W 0x00 PS low interrupt threshold setting (data byte high) 0x06 L PS_THDH_L R / W 0x00 PS high interrup t threshold setting (data byte low) H PS_THDH_H R / W 0x00 PS high interrupt threshold setting (data byte high) 0x07 L PS_CANC_L R / W 0x00 PS cancella tion setting (data byte low) H PS_CANC_H R / W 0x00 PS cancella tion setting (data byte high) 0x08 L PS_CONF4_L R / W 0x00 PS auto-calibrati on period, number, interrupt setting H PS_CONF4_H R / W 0x00 PS low power mode setting 0xF8 L PS_DATA_L R 0x00 PS channel ou tput data (data byte low) H PS_DATA_H R 0x00 PS channel output data (data byte high) 0xF9 L Reserved R 0x00 Reserved H INT_FLAG R 0x00 PS interrupt flag 0xFA L ID_L R 0x26 Device ID (data byte low) H ID_H R 0x00 Device ID (data byte high) 0xFB L PS_AC_DATA_L R 0x00 PS auto-calib ration data (data byte low) H PS_AC_DATA_H R 0x00 PS auto-calibration data (d ata byte high), busy and sunlight protect

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  • Initialization process: step 1: PS_ON = “1”; step 2: set PS_CAL = “1” Reserved 0 Default = 1, must always stay = 1 TABLE 3 - REGISTER: PS_CONF1_H DESCRIPTION REGISTER NAME COMMAND CODE: 0x 00_H (0x00 DATA BYTE HIGH) Command Bit Description Reserved 15 : 10 Default = (0 : 0 : 0 : 0 : 0 : 0) Reserved 9 Must be set to “1” when power on ready Reserved 8 Default = 0 TABLE 4 - REGISTER: PS_CONF2_L DESCRIPTION REGISTER NAME COMMAND CODE: 0x03_L (0x03 DATA BYTE LOW) Command Bit Description PS measurement period setting PS interrupt persistence setting PS_ INT 3 : 2 (0 : 0) = interrupt disable, (0 : 1) = logic high / low mode, (1 : 0) = first high, (1 : 1) = interrupt enable PS_SMART_PERS 1 0 = disable smart persistence, 1 = enable smart persistence PS_ST 0 0 = PS start, 1 = PS stop, default = 1; for ac tive force mode set AF = 1 before setting PS_ST = 0 TABLE 5 - REGISTER: PS_CONF2_H DESCRIPTION COMMAND CODE: 0x03_H (0x03 DATA BYTE HIGH) Command Bit Description PS multi-pulse setting PS_ITB 11 0: ITB = 25 μs, 1: ITB = 50 μs PS_HG 10 0 = disable, 1 = enable, PS high gain mode Reserved 9 : 8 Default = (0 : 0)

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www.vishay.com Vishay Semiconductors Rev. 1.3, 14-Sep-2021 11 Document Number: 80235 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Initialization VCNL36825T includes default values for each register. As long as power is on, it is ready to be controlled by host via I 2C bus. Proximity Interrupt There are three different Interrupt methods: “normal” interrupt mode, first high mode and so-called “logic high / low” mode. The first high mode is selected by setting (0x03_L, bit 3:2 = 1:0) within register PS_CONF2_L. In this mode, the initial interrupt that is triggered needs to be with regard to the high thresh old (PS_THDH). Passing underneath the low threshold will have no effect until the first high threshold event has occurred. In this mode, the interrupt event will re main set, until it is cleare d, by reading the interrupt register. The “normal” interrupt mode is selected with PS_INT = interrupt enabled (0x03_L, bit 3 : 2 = 1 : 1) within register PS_CONF2_L. Tests with ready-made application will show where to set the value for high threshold (PS_THDH) and low threshold (PS_THDL). For more information and explanation please study also the application note www.vishay.com/doc?80274 The “logic high / low” mode is selected with PS_INT = trigger by logic high/low mode (0x03_L, bit 3 : 2 = 0 : 1) within registe r PS_CONF2_L. When this mode is selected , the interrupt pin is pulled low when th e proximity counts reach the programmed high threshold (PS_THDH) and will return to high level when counts drop below the count value for low threshold (PS_THDL). With help of the function PS persistence one may also improve a reliable detection that not just one short event directly triggers an interrupt, but only when 2 (or up to 4) consecutive proximity measurements are above the programmed threshold value the interrupt will be set; please see also within the application note www.vishay.com/doc?80274. TABLE 12 - REGISTER: PS_CONF4_H DESCRIPTION COMMAND CODE: 0x08_H (0x08 DATA BYTE HIGH) Register Bit Description Reserved 15 : 11 Default = (0 : 0 : 0 : 0 : 0) PS detection period setting at low power mode (PS_LPEN = 1) PS_LPEN 8 0 = disable, 1 = enable = starts proximity low power measurements; now PS_LPPER used as period, but I_VCSEL, PS_IT, PS_ITB, PS_MPS as defined within register 3 and register 4 TABLE 13 - READ OUT REGISTER DESCRIPTION Register Command Code Bit Description PS_DATA_L 0xF8_L (0xF8 data byte low) 7 : 0 0x00 to 0xFF, PS output data (data byte low) PS_DATA_H 0xF8_H (0xF8 data byte high) 11 : 8 0x00 to 0x0F, PS output data (data byte high) INT_FLAG 0xF9_H (0xF9 data byte high) 15 : 14 Reserved PS_ACFLAG, after PS finishing auto-calibration, INT raise PS_SPFLAG, PS entering protection mode Reserved Reserved PS_IF_CLOSE, PS rises above PS_THDH INT trigger event PS_IF_AWAY, PS drops below PS_THDL INT trigger event ID_L 0xFA_L (0xFA data byte low) 7 : 0 Default = 0010 0110, device ID (data byte low) ID_H 0xFA_H (0xFA data byte high) 15 : 14 13 : 12 11 : 8 (0 : 0) (0 : 0) slave address = 0x60 Version code (0 : 0 : 0 : 0) device ID (data byte high) PS_AC_DATA_L 0xFB_L (0xFB data byte low) 7 : 0 0x00 to 0xFF, PS auto-c alibration data (data byte low) PS_AC_DATA_H 0xFB_H (0xFB data byte high) 13 : 12 11 : 8 AC_BUSY, when AC, the bit will be “1” AC_SUN, PS enters sunlight protect during auto-calibration Reserved 0x00 to 0xFF, PS auto-calibration data (data byte high)

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  • I_VCSEL = 10 mA, PS_IT = 1T, PS_ITB = 50 μs PROXIMITY DETECTION HYSTERESIS A PS detection hysteresis is important that keeps PS state in a certain range of detection distance. For example, PS_INT asserts when PS value over PS_THDH. Host switches off panel backlight and then clears INT. When PS value is less than PS_THDL, Host switches on panel backlight. Any PS value lower than PS_THDH or hi gher than PS_THDL, PS_INT will not be asserted. Host does keep the same state. Fig. 10 - VCNL36825T Reference Circuit Connection With Host (proximity detection logic output mode) (VCNL36825T INT pin connecting to host GPIO instead of INT pin) PS period (ms) 40 80 160 320 Low power mode (μA) 18.00 11.50 8.25 6.63 VDD INT INT SCL 1 µF GND SDA SCL SDA 2.2 k/g582.2 k/g58 10 k/g58 Vpull_up NC / GND VCNL36825TBaseband NC VDD

www.vishay.com Vishay Semiconductors Rev. 1.3, 14-Sep-2021 13 Document Number: 80235 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 PACKAGE INFORMATION in millimeters Fig. 11 - VCNL36825T Package Dimensions LAYOUT PAD INFORMATION in millimeters Fig. 12 - VCNL36825T PCB Layout Footprint RECOMMENDED STORAGE AND REBAKING CONDITIONS PARAMETER CONDITIONS MIN. MAX. UNIT Storage temperature -40 85 °C Relative humidity - 60 % Open time - 168 h Total time From the date code on the aluminized envelope (unopened) - 12 months Rebaking Tape and reel: 60 °C - 22 h Tube: 60 °C - 22 h SCL SDA V DD GND NC INT Top view Side view Bottom view 2.00 ± 0.1 0.743 0.129 3 4 6 6 4 3 0.350 ± 0.05 0.450 ± 0.05 0.075 ± 0.050.700 ± 0.05 0.075 ± 0.05 0.400 ± 0.05 0.725 0.500 0.725 0.400 0.300 0.700

www.vishay.com Vishay Semiconductors Rev. 1.3, 14-Sep-2021 14 Document Number: 80235 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 RECOMMENDED INFRARED REFLOW Soldering conditions which are based on J-STD-020 C Recommend Normal Solder Reflow is 235 °C to 265 °C Fig. 13 - VCNL36826S Solder Reflow Profile Chart RECOMMENDED IRON TIP SOLDERING CONDITION AND WARNING HANDLING 1. Solder the device with the following conditions: 1.1. Soldering tempera ture: 400 °C (max.) 1.2. Soldering time: 3 s (max.) 2. If the temperature of the method portion rises in addition to the re sidual stress between the le ads, the possibility that an open or short circuit occurs due to the deformation or destruction of the resin increases 3. The following methods: VPS and wave soldering, have not been suggested for the component assembly 4. Cleaning method conditions: 4.1. Solvent: methyl alcohol, ethyl alcohol, isopropyl alcohol 4.2. Solvent temperatu re < 45 °C (max.) 4.3. Time: 3 min (min.) IR REFLOW PROFILE CONDITION PARAMETER CONDITIONS TEMPERATURE TIME Peak temperature 260 °C + 5 °C / - 5 °C (max.: 265 °C) 10 s Preheat temperature range and timing 150 °C to 200 °C 60 s to 180 s Timing within 5 °C to peak temperature - 10 s to 30 s Timing maintained above temperature / time 217 °C 60 s to 150 s Timing from 25 °C to peak temperature - 8 min (max.) Ramp-up rate 3 °C/s (max.) - Ramp-down rate 6 °C/s (max.) - 200 150 217 260 Temperature (°C) Time (s)t2t1 Max. Temperature Ramp-Up Rate 3 °C/s (max.) Soldering Zone 60 s to 150 s Ramp-Up Rate 3 °C/s (max.) Pre-Heating Time t2 - t1 = 60 s to 180 s Ramp-Down Rate 6 °C/s (max.)

www.vishay.com Vishay Semiconductors Rev. 1.3, 14-Sep-2021 15 Document Number: 80235 For technical questions, contact: sensorstechsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 TAPE PACKAGING INFORMATION in millimeters

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