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TPS55285 TI | Alldatasheet

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Technical content

TPS55285 22V, 8A Buck-Boost Converter with I2C Interface

1 Features

• Programmable power supply (PPS) support for USB power delivery (USB PD) – Wide input voltage range: 2.4V to 22V – 3.0V Minimum input voltage for start-up – Programmable output voltage range: 0.8V to 22V with 10mV step – ±1% reference voltage accuracy – Adjustable output voltage compensation for voltage drop over the cable – Programmable output current limit up to 6.35A with 50mA step
• High efficiency over entire load range – 92.0% efficiency at VIN = 20V, VOUT = 5V and IOUT = 5A – 96.0% efficiency at VIN = 12V, VOUT = 20V and IOUT = 3A
• I2C Programming – Output enable(OE) On/Off – Slew rate of output voltage change – Switching frequency: 400kHz, 800kHz, 1.6MHz, 2.2MHz – Programmable PFM and FPWM mode at light load – Spread spectrum enable/disable – Output discharge enable/disable
• Rich protection features – Input overvoltage protection – Output absolute overvoltage protection – Output relative overvoltage protection – Hiccup mode for output short-circuit protection – Thermal shutdown protection – 8A average inductor current limit
• Small solution size – Four low RDS(ON) internal MOSFETs – Maximum switching frequency up to 2.2MHz – 2.5mm × 3.5mm HotRod™ WQFN package

2 Applications

• USB PD
• Wireless charger
• Docking Station
• Notebook computer
• SSD

3 Description

The TPS55285 is a fully integrated synchronous buck-boost converter that is optimized for converting battery voltage, USB Power Delivery (USB PD) or adaptor voltage into power supply rails. The TPS55285 integrates four 15mΩ MOSFETs to provide a high efficiency and small size solution. The TPS55285 has a wide input voltage range from 2.4V (3.0V rising) to 22V and is capable of outputting 0.8V to 22V voltage with 10mV step to support a variety of applications. It features 8A average inductor current limit and can supply up to 7A output current in buck mode. When working in boost mode, it can deliver 60W from 12V input or 30W from 5V input. Through the I 2C interface, the output voltage of the TPS55285 can be programmed dynamically. The default output voltage is 5V when the device is enabled. The I 2C interface allows for configuration of slew rate of the output voltage change, switching frequency, forced PWM mode operation. The TPS55285 offers input and output over-voltage protection, average inductor current limit, cycle-by- cycle peak current limit and output short circuit protection. The TPS55285 also ensures safe operating with output current limit without external output current sense resistor and hiccup mode protection in sustained overload conditions. The TPS55285 allows the use of small inductor and capacitor with high switching frequency. It is available in 2.5mm × 3.5mm QFN package. Device Information PART NUMBER PACKAGE (1) BODY SIZE TPS55285 WQFN-HR 2.5mm × 3.5mm (1) For all available packages, see the orderable addendum at the end of the data sheet. TPS55285 PGND COMP VOUT VOUT = 0.8V to 22V BOOT1 OFF ON L1 4.7µH SW2 BOOT2 SW1VIN = 2.4 – 22V FB/INT VIN MODE VCC EN/UVLO AGND SCL SDA Typical Application Circuit ADVANCE INFORMATION TPS55285 SLVSI72 – FEBRUARY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

7.1 REF Register (Address = 0h, 1h) [reset =

7.2 IOUT_LIMIT Register (Address = 2h) [reset =

7.3 VOUT_SR Register (Address = 3h) [reset =

7.4 VOUT_FS Register (Address = 4h) [reset =

7.5 CDC Register (Address = 5h) [reset = 11110000b]...28

7.6 MODE Register (Address = 6h) [reset =

7.7 STATUS Register (Address = 7h) [reset =

11 Mechanical, Packaging, and Orderable

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4 Pin Configuration and Functions

FB/INT— SW1 Figure 4-1. 15-pin WQFN-HR, VAL Package (Transparent Top View) Table 4-1. Pin Functions PIN I/O DESCRIPTION NO. NAME

1 MODE I Select the TPS55285 default Output Enable (OE) bit by putting a resistor between this pin and

AGND.

2 SCL I Clock of I2C interface

3 SDA I/O Data of I2C interface

4 EN/UVLO I

Enable logic input and programmable input voltage under voltage lockout (UVLO) input. Logic high level enables the device. Logic low level disables the device and turns it into shutdown mode. After the voltage at EN/UVLO pin is above the logic high voltage of 1.125V, this pin acts as programmable UVLO input with 1.23V internal reference.

5 VIN PWR Input of the buck-boost conveter

6 SW1 PWR The switching node pin of the buck side. It is connected to the drain of the internal buck low-side power MOSFET and the source of internal buck high-side power MOSFET.

7 PGND PWR Power ground of the device

8 SW2 PWR The switching node pin of the boost side. It is connected to the drain of the internal boost low-side power MOSFET and the source of internal boost high-side power MOSFET.

9 VOUT PWR Output of the buck-boost converter

10 FB/INT I/O

When the device is set to use external output voltage feedback, connect to the center tap of a resistor divider to program the output voltage. When the device is set to use internal feedback, this pin is a fault indicator open-drain output. When there is an internal fault happening, this pin outputs logic low level. 11 COMP O Output of the internal error amplifier. Connect the loop compensation network between this pin and the AGND pin. 12 AGND - Signal ground of the device. 13 VCC O Output of the internal regulator. A ceramic capacitor of more than 4.7μF is required between this pin and the AGND pin. 14 BOOT2 O Power supply for high-side MOSFET gate driver in boost side. A ceramic capacitor of 0.1µF must be connected between this pin and the SW2 pin. 15 BOOT1 O Power supply for high-side MOSFET gate driver in buck side. A ceramic capacitor of 0.1µF must be connected between this pin and the SW1 pin. www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TPS55285 ADVANCE INFORMATION

5 Specifications

5.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage range at terminals (2) VIN, VOUT, SW1, SW2 –0.3 27 V BOOT1 SW1–0.3 SW1+6 V BOOT2 SW2–0.3 SW2+6 V EN/UVLO, VCC, SCL, SDA, COMP, FB/INT, MODE –0.3 6 V EN/UVLO, SCL, SDA, COMP, FB/INT, MODE –0.3 VCC+0.3 V TJ Operating Junction, TJ (3) –40 150 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltage values are with respect to network ground terminal. (3) High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.

5.2 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage range (Vout ≥ 3.0V) 2.4 22 V Input voltage range (Vout < 3.0V) 3 22 V VOUT Output voltage range 0.8 22 V L Effective inductance range 1 4.7 10 µH CIN Effective input capacitance range 4.7 22 µF COUT Effective output capacitance range 10 100 1000 µF TJ Operating junction temperature –40 125 °C

5.3 Thermal Information

THERMAL METRIC(1) VAL (WQFN) VAL (WQFN) UNIT15 PINS 15 PINS Standard EVM (2) RθJA Junction-to-ambient thermal resistance 47.6 33 °C/W RθJC(top) Junction-to-case (top) thermal resistance N/A N/A °C/W RθJB Junction-to-board thermal resistance N/A N/A °C/W ΨJT Junction-to-top characterization parameter 0.6 0.7 °C/W YJB Junction-to-board characterization parameter 6.6 11.1 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. (2) Measured on TPS55285EVM, 4-layer, 2oz/1oz/1oz/2oz copper PCB.

5.4 Electrical Characteristics

TJ = -40°C to 125°C, VIN = 12V and VOUT = 20V. Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY VIN Input voltage range 2.4 22 V TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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TJ = -40°C to 125°C, VIN = 12V and VOUT = 20V. Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVIN_UVLO Under voltage lockout threshold VIN rising 2.8 2.9 3.0 V VIN falling, VOUT < 3V 2.6 2.7 2.8 V VIN falling, VOUT ≥ 3V 2.31 2.33 2.37 V VVIN_OVP Input overvoltage protection threshold Rising threshold 22 22.5 23 V VVIN_OVP_HYS Input overvoltage protection hysteresis 0.9 V IQ Quiescent current into VIN pin IC enabled, no load, no switching. VIN = 3.0V to 22V, VOUT = 0.8V, VFB = VREF + 0.1V, Tj up to 125°C 770 µA Quiescent current into VOUT pin IC enabled, no load, no switching, VIN = 3.0V, VOUT = 3V to 22V, VFB = VREF + 0.1V, Tj up to 125°C 770 µA ISD Shutdown current into VIN pin IC disabled, VIN = 3.0V to 22V, Tj up to 125°C 1.3 3.8 µA VCC Internal regulator output VIN = 8V, VOUT = 20V, IVCC = 20mA 5.0 5.2 5.4 V EN/UVLO VEN_H EN Logic high threshold VCC = 3.0V to 5.5V 1.125 V VEN_L EN Logic low threshold VCC = 3.0V to 5.5V 0.4 V VEN_HYS Enable threshold hysteresis VCC = 3.0V to 5.5V 0.04 V VUVLO UVLO rising threshold at the EN/UVLO VUVLO_HYS UVLO threshold hysteresis VCC = 3.0V to 5.5V 13 mV IUVLO Sourcing current at the EN/UVLO pin VEN/UVLO = 1.3V 4.5 5 5.5 µA OUTPUT VOUT Output voltage range 0.8 22 V VVOUT_OVP Output overvoltage protection threshold Rising threshold 22 22.5 23 V VVOUT_OVP_H YS Output overvoltage protection hysteresis 1 V VVOUT_OVP_FB Detected with respect to FB rising 110.5 115 119.5 % VVOUT_OVP_FB _HYS hysteresis 2.3 % IFB_LKG Leakage current at FB pin Tj up to 125°C 100 nA IVOUT_LKG Leakage current into VOUT pin IC disabled, VOUT = 20V, VSW2 = 0V, Tj up to 125°C 1 20 µA IDISCHG Output discharge current, OE shutdown VOUT = 20V, VCC = 5.2V 40 100 170 mA Output discharge current, EN and VIN shutdown VOUT = 20V, VCC = 5.2V 30 60 105 mA INTERNAL REFERENCE DAC Resolution of reference voltage DAC 11 bits VOUT_FULL Output voltage when VREF is set to 1.129V VOUT_FS=03h, REF=0780h, VREF=1.129V 19.7 20 20.3 V VOUT_FS=02h, REF=0780h, VREF=1.129V 14.78 15 15.22 V VOUT_FS=01h, REF=0780h, VREF=1.129V 9.85 10 10.15 V VOUT_FS=00h, REF=0780h, VREF=1.129V 4.93 5 5.07 V www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: TPS55285 ADVANCE INFORMATION

TJ = -40°C to 125°C, VIN = 12V and VOUT = 20V. Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOUT_ZERO Output voltage when VREF is set to 45mV VOUT_FS=03h, REF=0000h, VREF=45mV 0.74 0.8 0.86 V VOUT_FS=02h, REF=0000h, VREF=45mV 0.55 0.6 0.65 V VOUT_FS=01h, REF=0000h, VREF=45mV 0.36 0.4 0.44 V VOUT_FS=00h, REF=0000h, VREF=45mV 0.18 0.2 0.22 V REFERENCE VOLTAGE VREF Reference voltage at the FB/INT pin when using external feedback External feedback with REF=0780H 1.117 1.129 1.141 V External feedback with REF=058CH 0.837 0.846 0.855 V External feedback with REF=0334H 0.502 0.508 0.514 V External feedback with REF=01A4H 0.276 0.282 0.288 V POWER SWITCH RDS(on) Low-side MOSFET on resistance on buck side VOUT = 20V, VCC=5.2V 15.5 mΩ High-side MOSFET on resistance on buck side VOUT = 20V, VCC=5.2V 14.5 mΩ Low-side MOSFET on resistance on boost side VOUT = 20V, VCC=5.2V 15.5 mΩ High-side MOSFET on resistance on boost side VOUT = 20V, VCC=5.2V 14.5 mΩ INTERNAL CLOCK fSW Switching frequency FSW = 00b 400 kHz fSW Switching frequency FSW = 11b 2200 kHz tOFF_min Min. off time Boost mode 90 145 ns tON_min Min. on time Buck mode 90 130 ns CURRENT LIMIT ILIM_AVG Average inductor current limit VIN = 8V, VOUT = 20V, FSW = 400kHz, FPWM 7 8 A VIN = 8V, VOUT = 20V, FSW = 400kHz, PFM 7 8 A ILIM_PK Peak inductor current limit at boost high side VIN = 8V, VOUT = 20V, FSW = 400kHz, FPWM 13 A VIN = 8V, VOUT = 20V, FSW = 400kHz, PFM 13 A OUTPUT CURRENT LIMIT IOUT_LIMIT Output current limit IOUT_LIMIT Register = 1011 1100b 3 A IOUT_LIMIT Register = 1110 0100b 5 A CABLE VOLTAGE DROP COMPENSATION VOUT_CDC VOUT increase for cable drop compensation CDC[2:0]=111, INTFB = 11b, IOUT = 5A 610 700 790 mV CDC[2:0]=111, INTFB = 11b, IOUT = 1A, FPWM 40 140 230 mV CDC[2:0]=001, INTFB = 11b, IOUT = 5A 70 100 115 mV CDC[2:0]=001, INTFB = 11b, IOUT = 1A, FPWM 15 40 mV ERROR AMPLIFIER ISINK COMP pin sink current VFB = VREF + 400mV, VCOMP=1.1V, VCC=5V 20 µA TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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TJ = -40°C to 125°C, VIN = 12V and VOUT = 20V. Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ISOURCE COMP pin source current VFB = VREF - 400mV, VCOMP=1.1V, VCC=5V 60 µA VCCLPH High clamp voltage at the COMP pin 1.2 V VCCLPL Low clamp voltage at the COMP pin 0.7 V GEA Error amplifier transconductance 190 µA/V SOFT START tSS Soft-start time 2.5 3.6 5.2 ms SPREAD SPECTRUM HICCUP tHICCUP Hiccup off time 76 ms MODE IMODE Sourcing current from MODE pin 9 10 11 µA VMODE_DT3 Detection threshold voltage at MODE pin 0.169 0.189 0.209 V LOGIC INTERFACE VI2C_IO IO voltage range for I2C 1.7 5.5 V VI2C_H I2C input high threshold VCC = 3.0V to 5.5V 1.2 V VI2C_L I2C input low threshold VCC = 3.0V to 5.5V 0.4 V IFB/INT_H Leakage current into FB/INT pin when outputting high impedance VFB/INT = 5V 100 nA VFB/INT_L Output low voltage range of the FB/ INT pin Sinking 4mA current 0.03 0.1 V PROTECTION TSD Thermal shutdown threshold TJ rising 175 °C TSD_HYS Thermal shutdown hysteresis TJ falling below Tsd 20 °C

5.5 I2C Timing Characteristics

TJ = -40°C to 125°C, VIN = 12V and VOUT = 20V. Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I2C TIMING fSCL SCL clock frequency 100 1000 kHz tBUF Bus free time between a STOP and START condition Fast mode plus 0.5 µs tHD(STA) Hold time (repeated) START condition 260 ns tLOW Low period of the SCL clock 0.5 µs tHIGH High period of the SCL clock 260 ns tSU(STA) Setup time for a repeated START condition 260 ns tSU(DAT) Data setup time 50 ns tHD(DAT) Data hold time 0 µs tRCL Rise time of SCL signal 120 ns tRCL1 Rise time of SCL signal after a repeated START condition and after an ACK bit 120 ns tFCL Fall time of SCL signal 120 ns tRDA Rise time of SDA signal 120 ns tFDA Fall time of SDA signal 120 ns tSU(STO) Setup time of STOP condition 260 ns www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: TPS55285 ADVANCE INFORMATION

TJ = -40°C to 125°C, VIN = 12V and VOUT = 20V. Typical values are at TJ = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CB Capacitive load for SDA and SCL 200 pF

5.6 Typical Characteristics

VIN = 12V, TA = 25°C, fSW = 400kHz, unless otherwise noted. O u t p u t C u r r e n t ( A ) Efficiency (%) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 V I N = 5 V V I N = 9 V V I N = 1 2 V V I N = 2 0 V Figure 5-1. Efficiency vs Output Current, VOUT = 5V, FPWM O u t p u t C u r r e n t ( A ) Efficiency (%) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 V I N = 5 V V I N = 9 V V I N = 1 2 V V I N = 2 0 V Figure 5-2. Efficiency vs Output Current, VOUT = 5V, PFM O u t p u t C u r r e n t ( A ) Efficiency (%) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 V I N = 5 V V I N = 9 V V I N = 1 2 V V I N = 2 0 V Figure 5-3. Efficiency vs Output Current, VOUT = 9V, FPWM O u t p u t C u r r e n t ( A ) Efficiency (%) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 V I N = 5 V V I N = 9 V V I N = 1 2 V V I N = 2 0 V Figure 5-4. Efficiency vs Output Current, VOUT = 9V, PFM TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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T e m p e r a t u r e ( ° C ) VREF(V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 0 . 2 7 9 0 . 2 7 9 5 0 . 2 8 0 . 2 8 0 5 0 . 2 8 1 0 . 2 8 1 5 0 . 2 8 2 0 . 2 8 2 5 0 . 2 8 3 Figure 5-11. Reference Voltage vs Temperature (VREF = 0.282V) T e m p e r a t u r e ( ° C ) VREF(V - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 . 1 2 1 . 1 2 2 1 . 1 2 4 1 . 1 2 6 1 . 1 2 8 1 . 1 3 1 . 1 3 2 1 . 1 3 4 1 . 1 3 6 Figure 5-12. Reference Voltage vs Temperature (VREF = 1.129V) T e m p e r a t u r e ( ° C ) Quiescent Current (A) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 7 5 0 7 5 5 7 6 0 7 6 5 7 7 0 7 7 5 7 8 0 7 8 5 7 9 0 I n t o V I N , V I N = 2 2 V , V O U T = 3 V I n t o V O U T , V I N = 3 . 1 V , V O U T = 2 2 V Figure 5-13. Quiescent Current vs Temperature T e m p e r a t u r e ( ° C ) UVLO Threshold (V) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 4 0 1 . 2 3 2 1 . 2 3 2 5 1 . 2 3 3 1 . 2 3 3 5 1 . 2 3 4 1 . 2 3 4 5 1 . 2 3 5 1 . 2 3 5 5 1 . 2 3 6 1 . 2 3 6 5 1 . 2 3 7 Figure 5-14. ENABLE/UVLO Rising Threshold vs Temperature TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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6 Detailed Description

6.1 Overview

The TPS55285 is a 8A buck-boost DC to DC converter with integrated four MOSFETs. The TPS55285 can operate over a wide range of 2.4V to 22V input voltage and output 0.8V to 22V. It can transition among buck mode, buck-boost mode, and boost mode smoothly according to the input voltage and the setting output voltage. The TPS55285 operates in the buck mode when the input voltage is greater than the output voltage and in the boost mode when the input voltage is less than the output voltage. When the input voltage is close to the output voltage, the TPS55285 operates in one-cycle buck and one-cycle boost mode alternately. The TPS55285 utilizes an average current mode control scheme. Current mode control provides simplified loop compensation, rapid response to the load transients and inherent line voltage rejection. An error amplifier compares the feedback voltage of the output voltage with the internal reference voltage. The output of the error amplifier determines the average inductor current. The TPS55285 works in fixed-frequency PWM mode at moderate to heavy load currents. In the light load condition, the TPS55285 can be configured to automatically transition to PFM mode or be forced in PWM mode by setting the corresponding bit in an internal register. The TPS55285 can adjust the output voltage by setting the internal register through I 2C interface. An internal 11 bit DAC adjusts the reference voltage related to the value writing into the DAC register. The device also can limit the output current without external current sense resistor, the output current limit can be set by internal register. The TPS55285 provides typical 8A average inductor current limit. In addition, it provides cycle-by-cycle peak inductor current limit as well when the inductor peak current is above peak current limit. A precision voltage threshold of 1.23V with 5µA sourcing current at the EN/UVLO pin supports programmable input under-voltage lockout (UVLO) with hysteresis. When input voltage is higher than 22.5V, the input over- voltage protection (OVP) feature turns off the device to prevent damage. The output over-voltage protection (OVP) feature turns off the high side FETs to prevent damage to the devices powered by the TPS55285. The TPS55285 provides a hiccup mode option to reduce the heating in the power components when the output short circuit happens. When the hiccup mode is enabled, the TPS55285 turns off for 76ms and restarts soft startup. www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TPS55285 ADVANCE INFORMATION

6.2 Functional Block Diagram

VIN UVLO & OVP VOUT Gm BOOT2 R1Vref VIN Iref SW1 I_limit VCC PGNDSDA SCL EN/UVLO VOUT OVP Thermal VIN VOUT IrefDAC DAC COMPMODE AGND BOOT1 VOUT FB/INTGm BUCK BOOST VOUT LDO VIN VCC Buck-Boost Control Logic Core Current Sense VIN ADC TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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6.3 Feature Description

6.3.1 VCC Power Supply

An internal LDO to supply the TPS55285 outputs regulated 5.2V voltage at the VCC pin. When V IN is less than VOUT, the internal LDO selects the power supply source by comparing V IN to a rising threshold of 6.2V with 0.3V hysteresis. When VIN is higher than 6.2V, the supply for LDO is V IN. When VIN is lower than 5.9V, the supply for LDO is VOUT. When VOUT is less than VIN, the internal LDO selects the power supply source by comparing V OUT When VOUT is lower than 5.9V, the supply for LDO is V IN. Table 6-1 shows the supply source selection for the internal LDO. Table 6-1. VCC Power Supply Logic VIN VOUT INPUT for VCC LDO VIN > 6.2V VOUT > VIN VIN VIN < 5.9V VOUT > VIN VOUT VIN > VOUT VOUT > 6.2V VOUT VIN > VOUT VOUT < 5.9V VIN

6.3.2 Default Output Enable(OE) bit Status

By placing different resistors between the MODE pin and the AGND pin, the TPS55285 selects default Output Enable (OE) bit value. Output Enable (OE) bit is logic bit to control device output in 06H register. If default Output Enable (OE) bit is set to 0, when V IN and EN/UVLO pins exceed UVLO threshold, the device doesn't switch until Output Enable (OE) bit is set to 1 in 06H register. If default Output Enable (OE) bit is set to 1, the FB bit in 04H register is also set to 1 automatically to select external feedback network. Once V IN and EN/UVLO pins exceed UVLO threshold, the device starts switching with 282mV VREF. External feedback resistors is needed in this case. Table 6-2. I2C Target Address and Default OE bit Resistor Value (kΩ) I2C TARGET ADDRESS DEFAULT OUTPUT ENABLE (OE) BIT 0 75H 0 24.9 75H 1

6.3.3 Input Undervoltage Lockout

When the input voltage is below 2.4V, the TPS55285 is disabled. When the input voltage is above 3V, the TPS55285 can be enabled by pulling the EN pin to a high voltage above 1.3V. www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPS55285 ADVANCE INFORMATION

6.3.4 Enable and Programmable UVLO

The TPS55285 has a dual function enable and undervoltage lockout (UVLO) circuit. When the input voltage at the VIN pin is above the input UVLO rising threshold of 3V and the EN/UVLO pin is pulled above 1.125V but less than the enable UVLO threshold of 1.23V, the TPS55285 is enabled but still in standby mode. The TPS55285 starts to detect the resistance between MODE pin and ground. After that, the TPS55285 selects the I 2C target address and default OE bit status accordingly. The EN/UVLO pin has an accurate UVLO voltage threshold to support programmable input undervoltage lockout with hysteresis. When the EN/UVLO pin voltage is greater than the UVLO threshold of 1.23V, the TPS55285 is enabled for I 2C communication and switching operation. A hysteresis current I UVLO_HYS is sourced out of the EN/UVLO pin to provide hysteresis that prevents on/off chattering in the presence of noise with a slowly changing input voltage. By using resistor divider as shown in Figure 6-1, the turn-on threshold is calculated using Equation 1. (1) where

• VUVLO is the UVLO threshold of 1.23V at the EN/UVLO pin The hysteresis between the UVLO turn-on threshold and turn-off threshold is set by the upper resistor in the EN/UVLO resistor divider and is given by the Equation 2. (2) where
• IUVLO_HYS is the sourcing current from the EN/UVLO pin when the voltage at the EN/UVLO pin is above VUVLO The EN/UVLO pin voltage needs to be less than 5.5V when using resistor divider to program the VIN UVLO threshold. UVLO Comparator VIN EN/UVLO IUVLO_HYS 1.23V C1 EnableR2 Figure 6-1. Programmable UVLO With Resistor Divider at the EN/UVLO Pin TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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Using an NMOSFET together with a resistor divider can implement both logic enable and programmable UVLO as shown in Figure 6-2 . The EN logic high level must be greater than enable threshold plus the V th of the NMOSFET Q1. The Q1 also eliminates the leakage current from VIN to ground through the UVLO resistor divider during shutdown mode. UVLO Comparator VIN EN/UVLO IUVLO_HYS 1.23V C1 EnableR2 EN Figure 6-2. Logic Enable and Programmable UVLO

6.3.5 Soft Start

When the input voltage is above the UVLO threshold and the voltage at the EN/UVLO pin is above the enable UVLO threshold, the TPS55285 is ready to accept the command from I 2C controller device. An I 2C controller device can configure the internal registers of the TPS55285. Once an I2C controller device sets the OE bit to 1 or device detects the default OE bit is 1, the TPS55285 starts to ramp up the output voltage by ramping an internal reference voltage from 0V to a voltage set in the internal registers 00h and 01h within typical 3.6ms.

6.3.6 Shutdown and Load Discharge

When the EN/UVLO pin voltage is pulled below 0.4V, the TPS55285 is in shutdown mode, and all functions are disabled. All internal registers are reset to default values. When the EN/UVLO pin is at high logic level and the OE bit is cleared to 0, the TPS55285 turns off the switching operation but keeps the I2C interface active. If the DISCHG bit in the register 06h is set to 1, the TPS55285 discharges the output voltage below 0.8V by an internal constant current IDISCHG when the OE bit is cleared to 0. If input voltage UVLO is triggered or EN/UVLO pin is pulled to low logic level, the TPS55285 output voltage is discharged until VCC is below VCC_UVLO. www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TPS55285 ADVANCE INFORMATION

6.3.7 Switching Frequency

The TPS55285 uses a fixed frequency average current control scheme. The switching frequency is set by FSW bit in register 06H with four options: 400kHz, 800kH, 1.6MHz, 2.2MHz. To reduce the switching power loss in high power applications, it is recommended to set the swtiching frequency at 400kHz or 800kHz. If a system requires higher switching frequency at 1.6MHz or 2.2MHz for smaller solution size, it is recommended to operate at lower switch current for better thermal performance. It is recommended to set the switching frequency first before enabling the OE bit.

6.3.8 Switching Frequency Dithering

The TPS55285 provides an optional switching frequency dithering that is enabled by SPREADSPECTRUM bit in 06H register at FPWM mode to minimize EMI interference. The device uses a triangle jitter to spread the switching freequency with ±7% of normal frequency set by FSW bit. The frequency of the triangle jitter is 1.5kHz when normal swtiching frequency is 400kHz. The frequency of the triangle jitter is 9kHz when normal switching frequency is 2.2MHz.

6.3.9 Inductor Current Limit

The TPS55285 implements both peak current and average inductor current limit. The average current mode control loop uses the current sense information at the high-side MOSFET of the boost leg to clamp the maximum average inductor current to 8A (typical). Besides the average current limit, a peak current limit protection is implemented during transient to protect the device against over current condition beyond the capability of the device.

6.3.10 Internal Charge Path

Each of the two high-side MOSFET drivers is biased from its floating bootstrap capacitor, which is normally re-charged by VCC through both the external and internal bootstrap diodes when the low-side MOSFET is turned on. When the TPS55285 operates exclusively in the buck or boost regions, one of the high-side MOSFETs is constantly on. An internal charge path, from VOUT and BOOT2 to BOOT1 or from VIN and BOOT1 to BOOT2, charges the bootstrap capacitor to VCC so that the high-side MOSFET remains on.

6.3.11 Output Voltage Setting

There are two ways to set the output voltage: changing the feedback ratio and changing the reference voltage. The TPS55285 has a 11-bit DAC to program the reference voltage from 45mV to 1.2V. The TPS55285 can also select an internal feedback resistor divider or an external resistor divider by setting the FB bit in register 04h. When the FB bit is set to 0, the output voltage feedback ratio is set in internal register 04h. When the FB bit is set to 1, the output voltage feedback ratio is set by an external resistor divider. When using internal output voltage feedback settings, there are four feedback ratios programmable by writing the INTFB[1:0] bits of register 04H. With this function, the TPS55285 can limit the maximum output voltage to different values. In addition, the minimum step of the output voltage change is also programmed to 10mV, 7.5mV, 5mV, and 2.5mV, accordingly. When using an external output voltage feedback resistor divider as shown in Figure 6-3 , use Equation 3 to calculate the output voltage with the reference voltage at the FB/INT pin. 4($_$6 (3) TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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RFB_BT RFB_UP VOUT Figure 6-3. Output Voltage Setting by External Resistor Divider TI recommends using 100k Ω for the up resistor R FB_UP. The reference voltage V REF at the FB/ INT pin is programmable from 45mV to 1.2V by writing a 11-bit data into register 00H and 01H.

6.3.12 Output Current Limit

The TPS55285 supports output current limit function in buck, buck-boost and boost mode without external current sense resistor. The output current limit is programmable from 500mA to 6.35A by Current_Limit_Setting bit in 02H register. The programmable output current limit step is 50mA. The output current limit can be disabled by reset the Current_Limit_EN bit in the Current_Limit register to 0.

6.3.13 Output Cable Voltage Drop Compensation

To compensate the voltage drop across a cable from the output of the USB port to its powered device, the TPS55285 can lift its output voltage in proportion to the load current. By default, the cable voltage drop compensation function is disabled. Set the CDC_OPTION bit to 1 to enable cable voltage drop compensation function. Write the value into the bit CDC [2:0] in register 05H to get the desired voltage compensation. The output voltage rise versus the sensed output current is shown in Figure 6-4. 1 2 3 4 5 0.2 IOUT(A) VOUT_CDC(V) CDC [2:0] = 111b CDC [2:0] = 100b CDC [2:0] = 001b 0.7V 0.4V 0.1V 0.4 0.6 0.1 0.3 0.5 0.7 0.8 CDC [2:0] = 000b Figure 6-4. Output Voltage Rise versus Output Current

6.3.14 Input Overvoltage Protection

The TPS55285 has input overvoltage protection which avoids any damage to the device in case the current flows from the output to the input and the input source cannot sink current in FPWM mode. When the input voltage at the VIN pin is detected above 22.5V typically, the internal soft-start circuit is reset but all internal www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: TPS55285 ADVANCE INFORMATION

registers values remain unchanged when VIN OVP is triggered. The converter automatically restarts when the input voltage drops the hysteresis value lower than the input overvoltage protection threshold.

6.3.15 Output Overvoltage Protection

The TPS55285 has an absolute output overvoltage protection. When the output voltage at the VOUT pin is detected above 22.5V typically, the TPS55285 turns off two high-side FETs and turns on two low-side FETs until its output voltage drops the hysteresis value lower than the output overvoltage protection threshold. This function prevents overvoltage on the VOUT pin to protect the device. The TPS55285 monitors a resistor-divided feedback voltage to detect output over-voltage condition. When the feedback voltage is over 115% of the target voltage, the device stops switching until output voltage drops the 2.3% hysteresis value, this function secures the circuits connected to the output from excessive overvoltage. When selecting internal feedback resistor, the TPS55285 detects the internal feedback voltage for overvoltage protection.

6.3.16 Output Short Circuit Protection

In addition to the average inductor current limit, the TPS55285 implements the output short-circuit protection by entering hiccup mode. To enable hiccup mode, the HICCUP bit in register 06h must be set. After soft start-up time of 3.6ms, the TPS55285 monitors the average inductor current and output voltage. Whenever the output short circuit happens, causing the average inductor current hitting the set limit and the output voltage below 0.8V, the TPS55285 shuts down the switching for 76ms (typical) and then repeats the soft start for 3.6ms. The hiccup mode helps reduce the total power dissipation on the TPS55285 in the output short-circuit or overcurrent condition.

6.3.17 Thermal Shutdown

The TPS55285 is protected by a thermal shutdown circuit that shuts down the device when the internal junction temperature exceeds 175°C (typical). The internal soft-start circuit is reset but all internal registers values remain unchanged when thermal shutdown is triggered. The converter automatically restarts when the junction temperature drops below the thermal shutdown hysteresis of 20°C (typical) below the thermal shutdown threshold.

6.4 Device Functional Modes

In light load condition, the TPS55285 can work in PFM or forced PWM mode to meet different application requirements. PFM mode decreases switching frequency to reduce the switching loss thus it gets high efficiency at light load condition. The FPWM mode keeps the switching frequency unchanged to avoid undesired low switching frequency but the efficiency becomes lower than that of PFM mode. By default, the TPS55285 works in PFM mode. To set the device works in forced PWM mode, set the 01 bit of the register 06h to 1.

6.4.1 PWM Mode

In FPWM mode, the TPS55285 keeps the switching frequency unchanged in light load condition. When the load current decreases, the output of the internal error amplifier decreases as well to reduce the average inductor current down to deliver less power from input to output. When the output current further reduces, the current through the inductor decreases to zero during the switch-off time. The high-side N-MOSFET is not turned off even if the current through the MOSFET is zero. Thus, the inductor current changes its direction after it runs to zero. The power flow is from output side to input side. The efficiency is low in this condition. However, with the fixed switching frequency, there is no audible noise or other problems that might be caused by low switching frequency in light load condition. TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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6.4.2 Power Save Mode

The TPS55285 improves the efficiency at light load condition with PFM mode. By enabling the PFM function in the internal register, the TPS55285 can work in PFM mode at light load condition. When the TPS55285 operates at light load condition, the output of the internal error amplifier decreases to make the inductor peak current down to deliver less power to the load. When the output current further reduces, the current through the inductor will decrease to zero during the switch-off time. When the TPS55285 works in buck mode, once the inductor current becomes zero, the low-side switch of the buck side is turned off to prevent the reverse current from output to ground. When the TPS55285 works in boost mode, once the inductor current becomes zero, the high side-switch of the boost side is turned off to prevent the reverse current from output to input. The TPS55285 resumes switching until the output voltage drops. Thus PFM mode reduces switching cycles and eliminates the power loss by the reverse inductor current to get high efficiency in light load condition.

6.5 Programming

The TPS55285 uses I 2C interface for flexible converter parameter programming. I 2C is a bi-directional 2-wire serial interface. Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). I 2C devices can be considered as controllers or targets when performing data transfers. A controller is the device that initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a target. The TPS55285 operates as a target device with address 75h. Receiving control inputs from the controller device like a microcontroller or a digital signal processor reads and writes the internal registers 00h through 07h. The I2C interface of the TPS55285 supports both standard mode (up to 100 kbit/s) and fast mode plus (up to 1000 kbit/s). Both SDA and SCL must be connected to the positive supply voltage through current sources or pullup resistors. When the bus is free, both lines are in high voltage. www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TPS55285 ADVANCE INFORMATION

6.5.1 Data Validity

The data on the SDA line must be stable during the high level period of the clock. The high level or low level state of the data line can only change when the clock signal on the SCL line is low level. One clock pulse is generated for each data bit transferred. Data line stable Data valid Change of data allowed SDA SCL Figure 6-5. I2C Data Validity

6.5.2 START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A high level to low level transition on the SDA line while SCL is at high level defines a START condition. A low level to high level transition on the SDA line when the SCL is at high level defines a STOP condition. START and STOP conditions are always generated by the controller. The bus is considered busy after the START condition, and free after the STOP condition. START (S) SDA SCL STOP (P) Figure 6-6. I2C START and STOP Conditions TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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6.5.3 Byte Format

Every byte on the SDA line must be eight bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first. If a target cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the controller into a wait state (clock stretching). Data transfer then continues when the target is ready for another byte of data and release the clock line SCL. 1 2 7 8 9 1 2 8 9 S or Sr P or Sr START or Repeated START STOP or Repeated START MSB Acknowledgement signal from target Acknowledgement signal from receiver SCL SDA Figure 6-7. Byte Format

6.5.4 Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse, are generated by the controller. The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line to low level and it remains stable low level during the high level period of this clock pulse. The Not Acknowledge signal is when SDA remains high level during the 9 th clock pulse. The controller can then generate either a STOP to abort the transfer or a repeated START to start a new transfer.

6.5.5 Target Address and Data Direction Bit

After the START, a target address is sent. This address is seven bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ). 1 - 7 8 9 S START SCL SDA 1 - 7 8 9 1 - 7 8 9 ADDRESS R/W ACK DATA ACK DATA ACK P STOP Figure 6-8. Target Address and Data Direction www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: TPS55285 ADVANCE INFORMATION

6.5.6 Single Read and Write

Figure 6-9 and Figure 6-10 show the single-byte write and single-byte read format of the I2C communication. S 0 ACKTarget Address Register Address ACK Data to Address ACK P 1 7 1 1 8 1 8 1 1 Figure 6-9. Single-byte Write S 0 ACKTarget Address Register Address ACK Data from Address NACK P 1 7 1 1 8 1 8 1 1 S 1 ACKTarget Address 1 7 1 1 From controller to target From target to controller Figure 6-10. Single-byte Read If the register address is not defined, the TPS55285 sends back NACK and goes back to the idle state.

6.5.7 Multi-Read and Multi-Write

The TPS55285 supports multi-read and multi-write. S 0 ACKTarget Address Register Address ACK 1 7 1 1 8 1 Data to Address ACK 8 1 P Data to Address + 1 ACK 8 1 Data to Address + N ACK 8 1 Figure 6-11. Multi-byte Write S 0 ACKTarget Address Register Address ACK Data from Address ACK 1 7 1 1 8 1 8 1 S 1 ACKTarget Address 1 7 1 1 Data from Address + 1 ACK 8 1 Data from Address + N NACK 8 1 P Figure 6-12. Multi-byte Read TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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7 Register Maps

Table 7-1 lists the memory-mapped registers for the device registers. All register offset addresses not listed in Table 7-1 should be considered as reserved locations, and the register contents should not be modified. Table 7-1. Device Registers Address Acronym Register Name Section 0h, 1h REF Reference Voltage Go 2h IOUT_LIMIT Current Limit Setting Go 3h VOUT_SR Slew Rate Go 4h VOUT_FS Feedback Selection Go 5h CDC Cable Compensation Go 6h MODE Mode Control Go 7h STATUS Operating Status Go www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: TPS55285 ADVANCE INFORMATION

7.1 REF Register (Address = 0h, 1h) [reset = 10100100b, 00000001b]

REF is shown in Figure 7-1 and Figure 7-2 described in Table 7-2. Return to Summary Table. REF sets the internal reference voltage of the TPS55285. The 01h register is the high byte and the 00h register is the low byte. One LSB of register 00h stands for 0.5645mV of the internal reference voltage. The default register value is 00000001 10100100b of 282mV. When the register value is 00000000 00000000b, the reference voltage is 45mV. When the register value is 00000111 10000000b, the reference voltage is 1.129V. The output voltage of the TPS55285 also depends on the output feedback ratio, which is either set in register 04h or set by an external resistor divider. When using internal output voltage feedbcak divider, the output voltage VOUT is calculated by Equation 4 V OUT = V RE F INTF B (4) The REF register can be configured by an I 2C controller before setting the OE bit in register 06h. For 5V output voltage, set the REF register value to 00000001 10100100b. To set the internal reference voltage, write the register 00h first, then write the register 01h. Figure 7-1. REF_LSB 7 6 5 4 3 2 1 0 VREF R/W-10100100b Figure 7-2. REF_MSB 15 14 13 12 11 10 9 8 Reserved VREF R-00000b R/W-001b Table 7-2. REF Register Field Descriptions Bit Field Type Reset Description 15-11 Reserved R 00000b Reserved 10-0 VREF R/W 001 10100100b Sets the internal reference voltage 000 00000000b = 45mV reference voltage 000 00000001b = 45.5645mV reference voltage 000 00000010b = 46.129mV reference voltage 001 10100100b = 282mV reference voltage (Default) 011 00110100b = 508mV reference voltage 101 10001100b = 846mV reference voltage 111 10000000b = 1129mV reference voltage 111 11111110b = 1200mV reference voltage TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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7.2 IOUT_LIMIT Register (Address = 2h) [reset = 11100100b]

IOUT_LIMIT is shown in Figure 7-3 and described in Table 7-3. Return to Summary Table. IOUT_LIMIT sets the target output current limit from 500mA to 6.35A. One LSB stands for 50mA output current limit step. The bit7 enables the current limit or disables the current limit. Figure 7-3. IOUT_LIMIT Register 7 6 5 4 3 2 1 0 Current_Limit_EN Current_Limit_Setting R/W-1b R/W-1100100b Table 7-3. IOUT_LIMIT Register Field Descriptions Bit Field Type Reset Description 7 Current_Limit_EN R/W 1b Enable or disable output current limit. 0b = Output current limit disabled 1b = Output current limit enabled (Default) 6-0 Current_Limit_Setting R/W 1100100b Sets the output current limit target 0000000b = 500mA output current limit 0000001b = 500mA output current limit 0000010b = 500mA output current limit 0001010b = 500mA output current limit 0001011b = 550mA output current limit 0001100b = 600mA output current limit 0001101b = 650mA output current limit 0010100b = 1A output current limit 0101000b = 2A output current limit 0111100b = 3A output current limit 1100100b = 5A output current limit (Default) 1111111b =6.35A output current limit www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: TPS55285 ADVANCE INFORMATION

7.3 VOUT_SR Register (Address = 3h) [reset = 00000001b]

VOUT_SR is shown in Figure 7-4 and described in Table 7-4. Return to Summary Table. Register 03h sets the slew rate of the output voltage change and the response delay time after the output current exceeds the setting output current limit. The OCP_DELAY [1:0] bits set the response time of the TPS55285 when the output overcurrent limit is hit. This allows the TPS55285 to output high current in a relative short duration time. The default setting is 128µs so that the TPS55285 immediately limits the output current. The SR [1:0] bits set 1.25mV/μs, 2.5mV/μs, 5mV/μs, and 10mV/μs slew rate for output voltage change. Figure 7-4. VOUT_SR Register 7 6 5 4 3 2 1 0 RESERVED OCP_DELAY RESERVED SR R-0b R/W-00b R-00b R/W-01b Table 7-4. VOUT_SR Register Field Descriptions Bit Field Type Reset Description 7-6 RESERVED R 00b Reserved 5-4 OCP_DELAY R/W 00b Sets the response time of the device when the output overcurrent limit is reached. 00b = 128µs (Default) 01b = Delay 1.024 x 3ms 10b = Delay 1.024 x 6ms 11b = Delay 1.024 x 12ms 3-2 RESERVED R 00b Reserved 1-0 SR R/W 01b Sets slew rate for output voltage change. 00b = 1.25mV/µs output change slew rate 01b = 2.5mV/µs output change slew rate (Default) 10b = 5mV/µs output change slew rate 11b = 10mV/µs output change slew rate TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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7.4 VOUT_FS Register (Address = 4h) [reset = 00000011b]

VOUT_FS is shown in Figure 7-5 and described in Table 7-5. Return to Summary Table. Register 04h sets the selection for the output voltage feedback divider, either by an internal resistor divider or external resistor divider, and sets the internal feedback ratio when using internal feedback resistor divider. Figure 7-5. VOUT_FS Register 7 6 5 4 3 2 1 0 FB FB_OVP RESERVED INTFB R/W-0b R/W-0b R-0000b R/W-11b Table 7-5. VOUT_FS Register Field Descriptions Bit Field Type Reset Description

7 FB R/W 0b Output voltage feedback divider

0b = Use internal output voltage feedback. The FB/INT pin is the indicator for output short circuit protection, overcurrent status, and overvoltage status (Default). 1b = Use external output voltage feedback. The FB/INT pin is the feedback input of the output voltage.

6 FB_OVP R/W 0b 0b = Enable FB 115% OVP (Default)

1b = Disable FB 115% OVP 5-2 RESERVED R 0000b Reserved 1-0 INTFB R/W 11b Internal feedback ratio 00b = Set internal feedback ratio to 0.2256 01b = Set internal feedback ratio to 0.1128 10b = Set internal feedback ratio to 0.0752 11b = Set internal feedback ratio to 0.0564(Default) Table 7-6. Output Voltage vs Internal Reference INTFB1 INTFB0 REF=0000h REF=001Ah REF=0050h REF=00F0h REF=0780h Output Voltage Step 0 0 0.8V 5V 2.5mV 0 1 0.8V 10V 5mV 1 0 0.8V 15V 7.5mV 1 1 0.8V 20V 10mV www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: TPS55285 ADVANCE INFORMATION

7.5 CDC Register (Address = 5h) [reset = 11110000b]

CDC is shown in Figure 7-6 and described in Table 7-7. Return to Summary Table. Register 05h sets masks for SC bit, OCP bit, OVP bit and TSD bit in register 07h. When the mask bit is set and corresponding fault happens, the device will mask the fault indication on FB/INT pin In addition, register 05h sets the voltage rise added to the setting output voltage with respect to the sensed output current. Figure 7-6. CDC Register 7 6 5 4 3 2 1 0 SC_MASK OCP_MASK OVP_MASK TSD_MASK CDC_OPTION CDC R/W-1b R/W-1b R/W-1b R/W-1b R/W-0b R/W-000b Table 7-7. CDC Register Field Descriptions Bit Field Type Reset Description

7 SC_MASK R/W 1b Short circuit mask

0b = Disabled SC indication 1b = Enable SC indication (Default)

6 OCP_MASK R/W 1b Over current mask

0b = Disabled OCP indication 1b = Enable OCP indication (Default)

5 OVP_MASK R/W 1b Over voltage mask

0b = Disabled OVP indication 1b = Enable OVP indication (Default)

4 TSD_MASK R/W 1b Thermal shutdown mask

0b = Disabled TSD indication 1b = Enable TSD indication (Default)

3 CDC_OPTION R/W 0b Disable or enable cable voltage drop compensation function

0b = Disable CDC compensation (Default) 1b = Enable CDC compensation 2-0 CDC R/W 000b Compensation for voltage drop over the cable 000b = 0V output voltage rise with 5A output current (Default) 001b = 0.1V output voltage rise with 5A output current 010b = 0.2V output voltage rise with 5A output current 011b = 0.3V output voltage rise with 5A output current 100b = 0.4V output voltage rise with 5A output current 101b = 0.5V output voltage rise with 5A output current 110b = 0.6V output voltage rise with 5A output current 111b = 0.7V output voltage rise with 5A output current TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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7.6 MODE Register (Address = 6h) [reset = 00100000b]

MODE is shown in Figure 7-7 and described in Table 7-8. Return to Summary Table. MODE controls the operating mode of the TPS55285. DISCHG_2 bit controls the discharge FET enabled or disabled when Vout steps down. When DISCHG_2 is set to 1, the discharge FET current helps reducing the reverse current in FPWM mode when Vout steps down. Figure 7-7. MODE Register 7 6 5 4 3 2 1 0 OE SPREAD SPECTRUM HICCUP DISCHG FSW FPWM DISCHG_2 R/W-0b R/W-0b R/W-1b R/W-0b R/W-00b R/W-0b R/W-0b Table 7-8. MODE Register Field Descriptions Bit Field Type Reset Description

7 OE R/W 0b Output enable

0b = Output disabled (Default) 1b = Output enable

6 SPREADSPECTRUM R/W 0b Spread spectrum function

0b = Disable spread spectrum function (Default) 1b = Enable spread spectrum function

5 HICCUP R/W 1b Hiccup mode

0b = Disable the hiccup during output short circuit protection. 1b = Enable the hiccup during output short circuit protection (Default)

4 DISCHG R/W 0b Output discharge

0b = Disabled VOUT discharge when the device is in shutdown mode (Default) 1b = Enable VOUT discharge. VOUT is discharged to ground by an internal 100mA current sink in shutdown mode 3-2 FSW R/W 00b Switching frequency 00b = 400kHz (Default) 01b = 800kHz 11b = 1.6MHz 11b = 2.2MHz

1 FPWM R/W 0b Select operating mode at light load condition

0b = PFM operating mode at light load condition (Default) 1b = FPWM operating mode at light load condition

0 DISCHG_2 R/W 0b 0b = Output discharge function is enabled when VREF voltage

decreases. (Default) 1b = Output discharge function is disabled when VREF voltage decreases. www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: TPS55285 ADVANCE INFORMATION

7.7 STATUS Register (Address = 7h) [reset = 00000001b]

STATUS is shown in Figure 7-8 and described in Table 7-9. Return to Summary Table. The STATUS register stores the operating status of the TPS55285. When any of the SCP bit, the OCP bit, the OVP bit or the TSD bit are set, and the corresponding mask bit in register 05h is set as well, the FB/ INT pin outputs low logic level to indicate the situation. Reading register 07h clears the SCP bit, OCP bit, OVP bit and TSD bit. The FB/INT pin status and SCP bit, OCP bit, OVP bit or TSD bit are reset until the register 07h is read. If the fault situation still exists, the corresponding bit and FB/INT pin is set again. Figure 7-8. STATUS Register 7 6 5 4 3 2 1 0 SCP OCP OVP TSD Reserved Reserved STATUS R-0b R-0b R-0b R-0b R-0b R-0b R-11b Table 7-9. STATUS Register Field Descriptions Bit Field Type Reset Description

7 SCP R 0b Short circuit protection

0b = No short circuit 1b = Short circuit happens. Does not reset until it is read.

6 OCP R 0b Overcurrent protection

0b = No output overcurrent 1b = Output current hits the current limit. Does not reset until it is read.

5 OVP R 0b Overvoltage protection

0b = No OVP 1b = Output voltage exceeds the OVP threshold. Does not reset until it is read.

4 TSD R 0b Thermal shutdown protection

0b = No TSD 1b = Thermal shutdown happens. Does not reset until it is read

3 RESERVED R 0b Reserved

2 RESERVED R 0b Reserved

1-0 STATUS R 01b Operating status 00b = Boost 01b = Buck 10b = Buck-Boost 11b = Reserved TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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7.8 Register Summary

The Table 7-10 summarizes the default settings of the registers in the TPS55285. Table 7-10. Default Settings of Registers Register Address Register Name R/W Default Values 00h VREF_LSB R/W 10100100 01h VREF_MSB R/W 00000001 02h IOUT_LIMIT R/W 11100100 03h VOUT_SR R/W 00000001 04h VOUT_FS R/W 00000011 05h CDC R/W 11110000 06h MODE R/W 00100000 07h STATUS R 00000001 www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: TPS55285 ADVANCE INFORMATION

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TPS55285 can operate over a wide range of 2.4V to 22V input voltage and output 0.8V to 22V. It can transition among buck mode, buck-boost mode, and boost mode smoothly according to the input voltage and the setting output voltage. The TPS55285 operates in buck mode when the input voltage is greater than the output voltage and in boost mode when the input voltage is less than the output voltage. When the input voltage is close to the output voltage, the TPS55285 operates in one-cycle buck and one-cycle boost mode alternately. To reduce the switching power loss in high power conditions, it is recommended to set the switching frequency below 500kHz. If a system requires higher switching frequency above 500kHz, it is recommended to operate at lower switch current for better thermal performance.

8.2 Typical Application

The TPS55285 provides a small size solution for USB PD power supply application with the input voltage ranging from 5V to 22V. TPS55285 PGND COMP VOUT VOUT = 3.3V to 21V BOOT1 OFF ON L1 4.7µH SW2 BOOT2 SW1VIN = 5 – 22V FB/INT VIN MODE VCC EN/UVLO AGND SCL SDA Figure 8-1. USB PD Power Supply With 5V to 22V Input Voltage TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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8.2.1 Design Requirements

The design parameters are listed in Table 8-1: Table 8-1. Design Parameters PARAMETERS VALUES Input voltage 5V to 22V Output voltage 3.3V to 21V Output current limit 3A Output voltage ripple ±50mV Operating mode at light load FPWM

8.2.2 Detailed Design Procedure

8.2.2.1 Switching Frequency

The switching frequency of the TPS55285 is set by FSW bit in 06H register. To reduce the switching power loss with such a high current application, 400kHz switching frequency is selected for this application.

8.2.2.2 Output Voltage Setting

The TPS55285 has I 2C interface to set the internal reference voltage. A microcontroller can easily set the desired output voltage by writing the proper data into the reference voltage registers through I2C bus.

8.2.2.3 Inductor Selection

Since the selection of the inductor affects steady state operation, transient behavior, and loop stability, the inductor is the most important component in power regulator design. There are three important inductor specifications: inductance, saturation current, and DC resistance. The TPS55285 is designed to work with inductor values between 1µH and 10µH. The inductor selection is based on consideration of both buck and boost modes of operation. The inner current loop uses internal compensationand requires the inductor value must be larger than 1.2/fSW. For buck mode, the inductor selection is based on limiting the peak-to-peak current ripple to the maximum inductor current at the maximum input voltage. In CCM, Equation 5 shows the relationship between the inductance and the inductor ripple current. kVIN(MAX)-VOUTo×VOUT ¨IL(P-P)×fSW×VIN:MAX; (5) where

• VIN(MAX) is the maximum input voltage
• VOUT is the output voltage
• ΔIL(P-P) is the peak to peak ripple current of the inductor
• fSW is the switching frequency For a certain inductor, the inductor ripple current achieves maximum value when VOUT equals half of the maximum input voltage. Choosing higher inductance gets smaller inductor current ripple while smaller inductance gets larger inductor current ripple. For boost mode, the inductor selection is based on limiting the peak-to-peak current ripple to the maximum inductor current at the maximum output voltage. In CCM, Equation 6 shows the relationship between the inductance and the inductor ripple current. VIN×kVOUT(MAX)-VINo ¨IL(P-P)×fSW×VOUT(MAX) (6) www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: TPS55285 ADVANCE INFORMATION

• VIN is the input voltage
• VOUT(MAX) is the maximum output voltage
• ΔIL(P-P) is the peak to peak ripple current of the inductor
• fSW is the switching frequency For a certain inductor, the inductor ripple current achieves maximum value when V IN equals to the half of the maximum output voltage. Choosing higher inductance gets smaller inductor current ripple while smaller inductance gets larger inductor current ripple. For this application example, a 4.7µH inductor is selected, which produces approximate maximum inductor current ripple of 50% of the highest average inductor current in buck mode and 50% of the highest average inductor current in boost mode. In buck mode, the inductor DC current equals to the output current. In boost mode, the inductor DC current can be calculated with Equation 7. IL(DC) = VOUT×IOUT VIN× (7) where
• VOUT is the output voltage
• IOUT is the output current
• VIN is the input voltage
• η is the power conversion efficiency For a given maximum output current of the buck-boost converter TPS55285, the maximum inductor DC current happens at the minimum input voltage and maximum output voltage. Set the inductor current limit of the TPS55285 higher than the calculated maximum inductor DC current to make sure the TPS55285 has the desired output current capability. In boost mode, the inductor ripple current is calculated with Equation 8. ¨IL(P-P)=VIN×:VOUT-VIN; L×fSW×VOUT (8) where
• ΔIL(P-P) is the inductor ripple current
• L is the inductor value
• fSW is the switching frequency
• VOUT is the output voltage
• VIN is the input voltage Therefore, the inductor peak current is calculated with Equation 9. IL(P) = IL(DC)+ ¨IL(P-P) (9) Normally, it is advisable to work with an inductor peak-to-peak current of less than 40% of the average inductor current for maximum output current. A smaller ripple from a larger valued inductor reduces the magnetic hysteresis losses in the inductor and EMI, but in the same way, load transient response time is increased. The selected inductor must have higher saturation current than the calculated peak current. The conversion efficiency is dependent on the resistance of its current path. The switching loss associated with the switching MOSFETs, and the inductor core loss. Therefore, the overall efficiency is affected by the TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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inductor DC resistance (DCR), equivalent series resistance (ESR) at the switching frequency, and the core loss. Table 8-2 lists recommended inductors for the TPS55285. In this application example, the Coilcraft inductor XAL7070-472 is selected for its small size, high saturation current, and small DCR. Table 8-2. Recommended Inductors PART NUMBER L (µH) DCR (MAXIMUM) (mΩ) SATURATION CURRENT / HEAT RATING CURRENT (A) SIZE (L x W x H mm) VENDOR(1) (1) See the Third-party Products disclaimer.

8.2.2.4 Input Capacitor

In buck mode, the input capacitor supplies high ripple current. The RMS current in the input capacitors is given by Equation 10. ICIN:RMS; = IOUT רVOUT×:VIN-VOUT; VIN×VIN (10) where

• ICIN(RMS) is the RMS current through the input capacitor
• IOUT is the output current The maximum RMS current occurs at the output voltage is half of the input voltage, which gives ICIN(RMS) = IOUT / 2. Ceramic capacitors are recommended for their low ESR and high ripple current capability. A total of 20µF effective capacitance is a good starting point for this application.

8.2.2.5 Output Capacitor

In boost mode, the output capacitor conducts high ripple current. The output capacitor RMS ripple current is given by Equation 11, where the minimum input voltage and the maximum output voltage correspond to the maximum capacitor current. ICOUT:RMS; = IOUT רVOUT VIN (11) where

• ICOUT(RMS) is the RMS current through the output capacitor
• IOUT is the output current In this example, the maximum output ripple RMS current is 2.8A. The ESR of the output capacitor causes an output voltage ripple given by Equation 12 in boost mode. VRIPPLE(ESR) = IOUT×VOUT VIN ×RCOUT (12) where
• RCOUT is the ESR of the output capacitance www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: TPS55285 ADVANCE INFORMATION

The capacitance also causes a capacitive output voltage ripple given by Equation 13 in boost mode. When input voltage reaches the minimum value and the output voltage reaches the maximum value, there is the largest output voltage ripple caused by the capacitance. VRIPPLE(CAP) = IOUT× l1- VIN VOUT p COUT×fSW (13) Typically, a combination of ceramic capacitors and bulk electrolytic capacitors is needed to provide low ESR, high ripple current, and small output voltage ripple. From the required output voltage ripple, use Equation 12 and Equation 13 to calculate the minimum required effective capacitance of the COUT.

8.2.2.6 Output Current Limit

The output current limit is set through register 02h with 50mA step. The maximum value of the output current limit is 6.35A and minimum value of the output current limit is 500mA. The default limit voltage is 5A.

8.2.2.7 Loop Stability

The TPS55285 uses average current control scheme. The inner current loop uses internal compensation and requires the inductor value must be larger than 1.2/f SW. The outer voltage loop requires an external compensation. The COMP pin is the output of the internal voltage error amplifier. An external compensation network comprised of resistor and ceramic capacitors is connected to the COMP pin. The TPS55285 operates in buck mode or boost mode. Therefore, both buck and boost operating modes require loop compensations. The restrictive one of both compensations is selected as the overall compensation from a loop stability point of view. Typically for a converter designed either work in buck mode or boost mode, the boost mode compensation design is more restrictive due to the presence of a right half plane zero (RHPZ). The power stage in boost mode can be modeled by Equation 14. GPS(s) = RLOAD×:1-D; 2×RSENSE l1+ s 2N×fESRZ p× l1- s 2N×fRHPZ p 1+ s 2N×fP (14) where

• RLOAD is the output load resistance
• D is the switching duty cycle in boost mode
• RSENSE is the equivalent internal current sense resistor, which is 0.055Ω The power stage has two zeros and one pole generated by the output capacitor and load resistance. Use Equation 15 to Equation 17 to calculate them. fP = 2 2N×RLOAD×COUT (15) fESRZ = 1 2N×RCOUT×COUT (16) fRHPZ=RLOAD×:1-D;2 2N×L (17) The internal transconductance amplifier together with the compensation network at the COMP pin constitutes the control portion of the loop. The transfer function of the control portion is shown by Equation 18. TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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GC(s) = GEA×REA×VREF VOUT l1+ s 2N×fCOMZ p l1+ s 2N×fCOMP1 p × l1 + s 2N×fCOMP2 p (18) where

• GEA is the transconductance of the error amplifier
• REA is the output resistance of the error amplifier
• VREF is the reference voltage input to the error amplifier
• VOUT is the output voltage
• fCOMP1 and fCOMP2 are the pole’s frequency of the compensation network
• fCOMZ is the zero’s frequency of the compensation network The total open-loop gain is the product of G PS(s) and G C(s). The next step is to choose the loop crossover frequency, fC, at which the total open-loop gain is 1, namely 0dB. The higher in frequency that the loop gain stays above 0dB before crossing over, the faster the loop response. It is generally accepted that the loop gain cross over 0dB at the frequency no higher than the lower of either 1/10 of the switching frequency, f SW or 1/5 of the RHPZ frequency, fRHPZ. Then, set the value of RC, CC, and CP by Equation 19 to Equation 21. RC = 2N×VOUT×RSENSE×COUT×fC :1-D;×VREF×GEA (19) where
• fC is the selected crossover frequency CC = RLOAD×COUT 2×RC (20) CP= RCOUT×COUT RC (21) If the calculated CP is less than 10pF, it can be left open. Designing the loop for greater than 45° of phase margin and greater than 10dB gain margin eliminates output voltage ringing during the line and load transient. www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: TPS55285 ADVANCE INFORMATION

8.2.3 Application Curves

5A/div Time Scale: 2 s/div Vout(AC) 20mV/div SW2 5V/div Figure 8-2. Switching Waveforms in VIN = 12V, VOUT = 5V, IO = 5A, FPWM SW1 10V/div IL 2A/div Time Scale: 40ms/div Vout(AC) 100mV/div SW2 5V/div Figure 8-3. Switching Waveforms in VIN = 12V, VOUT = 5V, IO = 0A, PFM SW1 10V/div IL 2A/div Time Scale: 2 s/div Vout(AC) 50mV/div SW2 10V/div Figure 8-4. Switching Waveforms in VIN = 12V, VOUT = 12V, IO = 3A, FPWM SW1 10V/div IL 2A/div Time Scale: 25ms/div Vout(AC) 100mV/div SW2 10V/div Figure 8-5. Switching Waveforms in VIN = 12V, VOUT = 12V, IO = 0A, PFM SW1 10V/div IL 5A/div Time Scale: 2 s/div Vout(AC) 100mV/div SW2 10V/div Figure 8-6. Switching Waveforms in VIN = 12V, VOUT = 20V, IO = 2A, FPWM SW1 10V/div IL 2A/div Time Scale: 10ms/div Vout(AC) 100mV/div SW2 10V/div Figure 8-7. Switching Waveforms in VIN = 12V, VOUT = 20V, IO = 0A, PFM IL 2A/div Time Scale: 2ms/div Vout 2V/div Figure 8-8. Start-up Waveforms in VIN = 12V, VOUT = 5V, RLOAD = 1.5Ω, FPWM IL 2A/div Time Scale: 200 s/div Vout 2V/div Figure 8-9. Shutdown Waveforms in VIN = 12V, VOUT = 5V, RLOAD = 1.5Ω, FPWM TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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Time Scale: 2ms/div Vout 5V/div Figure 8-18. Vout Change Rising in VIN = 12V, VOUT = 5V to 20V with 2.5mV/μS, IOUT = 2A, FPWM IL 2A/div Time Scale: 2ms/div Vout 5V/div Figure 8-19. Vout Change Falling in VIN = 12V, VOUT = 20V to 5V with 2.5mV/μS, IOUT = 2A, FPWM IL 2A/div Time Scale: 4ms/div Vout 5V/div Figure 8-20. Output Discharge in VIN = 12V, VOUT = 5, IOUT = 0A

8.3 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 3.0V to 22V. This input supply must be well regulated. If the input supply is located more than a few inches from the converter, additional bulk capacitance can be required in addition to the ceramic bypass capacitors. A typical choice is an aluminum electrolytic capacitor with a value of 100μF. TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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8.4 Layout

8.4.1 Layout Guidelines

As for all switching power supplies, especially those running at high switching frequency and high currents, layout is an important design step. If layout is not carefully done, the regulator can suffer from instability and noise problems. 1. Place the 0.1-μF small package (0402) ceramic capacitors close to the VIN/VOUT pins to minimize high frequency current loops. This improves the radiation of high-frequency noise (EMI) and efficiency. 2. Use multiple GND vias near PGND pin to connect the PGND to the internal ground plane. This also improves thermal performance. 3. Minimize the SW1 and SW2 loop areas as these are high dv/dt nodes. Use a ground plane under the switching regulator to minimize interplane coupling. 4. Place the BOOT1 bootstrap capacitor close to the IC and connect directly to the BOOT1 to SW1 pins. Place the BOOT2 bootstrap capacitor close to the IC and connect directly to the BOOT2 and SW2 pins. 5. Place the VCC capacitor close to the IC with wide and short trace. The GND terminal of the VCC capacitor should be directly connected with PGND plane through three to four vias. 6. Isolate the power ground from the analog ground. The PGND plane and AGND plane are connected at the terminal of the VCC capacitor. Thus the noise caused by the MOSFET driver and parasitic inductance does not interface with the AGND and internal control circuit. 7. Place the compensation components as close to the COMP pin as possible. Keep the compensation components, feedback components, and other sensitive analog circuitry far away from the power components, switching nodes SW1 and SW2, and high-current trace to prevent noise coupling into the analog signals. 8. To improve thermal performance, it is recommended to use thermal vias close to the VIN pin to a large VIN area, and the VOUT pin to a large VOUT area separately. www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: TPS55285 ADVANCE INFORMATION

8.4.2 Layout Example

FB/INT— EN/UVLO BOOT2 BOOT1 VOUT VIN SW1 PGND SW2 Figure 8-21. Layout Example TPS55285 SLVSI72 – FEBRUARY 2025 www.ti.com

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9 Device and Documentation Support

9.1 Device Support

9.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

9.1.2 Development Support

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

HotRod™ and TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES February 2025 * Initial Release

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com TPS55285 SLVSI72 – FEBRUARY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: TPS55285 ADVANCE INFORMATION

www.ti.com 12-Mar-2025 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples XTPS55285VALR ACTIVE WQFN-HR VAL 15 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

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