VCBU3730GSCUS100

DM3730_17 TI1 | Alldatasheet

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 DM3730, DM3725 DigitalMedia Processors Check forSamples: DM3730 ,DM3725

1 DM3730, DM3725 DigitalMedia Processors

1.1 Features

• Load-StoreArchitectureWith• DM3730/25 DigitalMedia Processors: Non-AlignedSupport– Compatible withOMAP ™ 3 Architecture
• 64 32-BitGeneral-PurposeRegisters– ARM ® Microprocessor(MPU) Subsystem
• InstructionPacking Reduces Code Size• Up to1-GHz ARM ® Cortex™-A8 Core
• AllInstructionsConditionalAlso supports300,600,and 800-MHz operation • AdditionalC64x+ TM Enhancements
• NEON ™ SIMD Coprocessor – ProtectedMode Operation – High Performance Image,Video,Audio – ExpectationsSupport forError (IVA2.2TM )AcceleratorSubsystem Detectionand Program Redirection
• Up to800-MHz TMS320C64x+ TM DSP Core – Hardware Support forModulo Loop Also supports260,520,and 660-MHz Operation operation – C64x+ TM L1/L2Memory Architecture
• Enhanced DirectMemory Access (EDMA) • 32K-Byte L1P Program RAM/Cache Controller(128IndependentChannels) (DirectMapped)
• Video Hardware Accelerators • 80K-Byte L1D Data RAM/Cache (2-Way – POWERVR SGX ™ Graphics Accelerator Set-Associative) (DM3730 only) • 64K-Byte L2 UnifiedMapped RAM/Cache
• TileBased ArchitectureDeliveringup to (4-Way Set-Associative)

20 MPoly/sec • 32K-Byte L2 Shared SRAM and 16K-Byte

• UniversalScalableShader Engine: L2 ROM Multi-threadedEngine IncorporatingPixel – C64x+ TM InstructionSet Features and VertexShader Functionality • Byte-Addressable(8-/16-/32-/64-BitData)
• IndustryStandard API Support: • 8-BitOverflowProtectionOpenGLES 1.1and 2.0,OpenVG1.0 • Bit-FieldExtract,Set,Clear• FineGrained Task Switching,Load • Normalization,Saturation,Bit-CountingBalancing,and Power Management • Compact 16-BitInstructions• Programmable High QualityImage • AdditionalInstructionstoSupportAnti-Aliasing Complex Multiplies– Advanced Very-Long-Instruction-Word – ExternalMemory Interfaces:(VLIW)TMS320C64x+ TM DSP Core
• SDRAM Controller(SDRC)• EightHighlyIndependentFunctional – 16,32-bitMemory ControllerWithUnits 1G-Byte TotalAddress Space• SixALUs (32-/40-Bit);Each Supports – InterfacestoLow-Power SDRAMSingle32-bit,Dual 16-bit,or Quad 8-bit, – SDRAM Memory Scheduler(SMS) andArithmeticper Clock Cycle RotationEngine• Two MultipliersSupport Four 16 x 16-Bit
• GeneralPurpose Memory ControllerMultiplies(32-BitResults)per Clock (GPMC)Cycle or Eight8 x 8-BitMultiplies(16-Bit Results)per Clock Cycle – 16-bitWide MultiplexedAddress/Data Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2POWERVR SGX isa trademarkofImaginationTechnologiesLtd. 3OMAP isa trademarkofTexas Instruments. 4Cortex,NEON aretrademarksofARM Limited. 5ARM isa registeredtrademarkofARM Ltd. 6Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas of publicationdate. Copyright© 2010–2011,Texas InstrumentsIncorporatedProducts conform to specificationsper the terms of the Texas Instrumentsstandard warranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Bus • GluelessInterfacetoCommon Video Decoders– Up to8 Chip SelectPins With 128M-Byte Address Space per Chip • ResizeEngine SelectPin – ResizeImages From 1/4xto4x – GluelessInterfacetoNOR Flash, – SeparateHorizontal/VerticalControl NAND Flash(WithECC Hamming – System DirectMemory Access (SDMA)Code Calculation),SRAM and Controller(32LogicalChannels WithPseudo-SRAM ConfigurablePriority) – TrustZone® 0.9-Vto1.1-VAdaptiveCore Logic Voltage – Thumb ®-2Note:These aredefaultOperating Performance Point(OPP) voltagesand could – MMU Enhancements be optimizedtolowervaluesusing • In-Order,Dual-Issue,SuperscalarSmartReflexAVS. MicroprocessorCore – Commercial, Industrial,and Extended • NEON MultimediaArchitectureTemperature Grades • Over 2x Performance ofARMv6 SIMD– SerialCommunication • Supports Both Integerand FloatingPoint• 5 MultichannelBufferedSerialPorts SIMD(McBSPs) • Jazelle® RCT ExecutionEnvironment– 512 Byte Transmit/ReceiveBuffer Architecture(McBSP1/3/4/5) • Dynamic Branch PredictionwithBranch– 5K-Byte Transmit/ReceiveBuffer TargetAddress Cache, GlobalHistory(McBSP2) Buffer,and 8-EntryReturn Stack – SIDETONE Core Support (McBSP2 and • Embedded Trace Macrocell(ETM)3 Only)For Filter,Gain,and Mix Support forNon-InvasiveDebugOperations – ARM Cortex-A8Memory Architecture:– DirectInterfacetoI2Sand PCM Device • 32K-Byte InstructionCache (4-Wayand T Buses Set-Associative)– 128 Channel Transmit/ReceiveMode • 32K-Byte Data Cache (4-Way• Four Master/SlaveMultichannelSerial Set-Associative)PortInterface(McSPI)Ports • 256K-Byte L2 Cache• High-Speed/Full-Speed/Low-SpeedUSB – 32K-Byte ROMOTG Subsystem (12-/8-PinULPI Interface) – 64K-Byte Shared SRAM• High-Speed/Full-Speed/Low-Speed – Endianess:MultiportUSB Host Subsystem

• ARM Instructions-LittleEndian– 12-/8-PinULPI Interfaceor 6-/4-/3-Pin
• ARM Data – ConfigurableSerialInterface
• DSP Instructions/Data-LittleEndian• One HDQ/1-Wire Interface
• Removable Media Interfaces:• Four UARTs (One withInfraredData – Three MultimediaCard (MMC)/ Secure DigitalAssociation[IrDA]and Consumer Infrared (SD)With Secure Data I/O(SDIO)[CIR]Modes)
• TestInterfaces• Three Master/SlaveHigh-Speed Inter-IntegratedCircuit(I2C)Controllers – IEEE-1149.1(JTAG) Boundary-Scan Compatible– Camera Image SignalProcessing(ISP) – Embedded Trace Macro Interface(ETM)• CCD and CMOS Imager Interface – SerialData TransportInterface(SDTI)• Memory Data Input
• 12 32-bitGeneralPurpose Timers• BT.601/BT.656DigitalYCbCr 4:2:2 (8-/10-Bit)Interface • 2 32-bitWatchdog Timers

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011

• 1 32-bitSecure Watchdog Timer • Packages:
• 1 32-bit32-kHz Sync Timer – 515-pins-PBGA package (CBP Suffix),.5mm BallPitch(Top),.4mm BallPitch(Bottom)• Up to188 General-PurposeI/O(GPIO)Pins (MultiplexedWith Other Device Functions) – 515-pins-PBGA package (CBC Suffix),.65mm BallPitch(Top),.5mm Ball• 45-nm CMOS Technology Pitch(Bottom)• Package-On-Package (POP) Implementationfor – 423-pins-PBGA package (CUSMemory Stacking(NotAvailableinCUS Suffix),.65mm BallPitchPackage) Copyright© 2010–2011,Texas InstrumentsIncorporated DM3730, DM3725 DigitalMedia Processors 3 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com

1.2 Description

The DM37x generationofhigh-performance,digitalmedia processorsarebased on theenhanced device architectureand areintegratedon TI'sadvanced 45-nm processtechnology.Thisarchitectureisdesigned to providebestinclassARM and Graphicsperformancewhiledeliveringlow power consumption.This balanceofperformanceand power allowthedevicetosupportthefollowingexample applications:

• PortableData Terminals
• Navigation
• AutoInfotainment
• Gaming
• MedicalImaging
• Home Automation
• Human Interface
• IndustrialControl
• Testand Measurement
• SingleboardComputers The devicecan supportnumerous HLOS and RTOS solutionsincludingLinuxand Windows Embedded CE whichareavailabledirectlyfromTI.Additionally,thedeviceisfullybackward compatiblewithprevious Cortex™-A8 processorsand OMAP ™ processors. This DM3730/25 DigitalMedia Processor data manual presents the electricaland mechanical specificationsfortheDM3730/25 DigitalMedia Processor.The informationcontainedinthisdatamanual appliestothecommercial,industrial,and extendedtemperatureversionsoftheDM3730/25 DigitalMedia Processorunlessotherwiseindicated.Itconsistsofthefollowingsections:
• A descriptionof the DM3730/25 terminals:assignment,electricalcharacteristics,multiplexing,and functionaldescription
• A presentationof the electricalcharacteristicsrequirements:power domains, operatingconditions, power consumption,and dc characteristics
• The clockspecifications:inputand outputclocks,DPLL and DLL
• A descriptionofthermalcharacteristics,devicenomenclature,and mechanicaldataabouttheavailable packaging

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L2$ 256K MPU Subsystem POWERVR SGX Graphics Accelerator TM 3232 Channel System DMA 3232 Parallel TV Amp LCD Panel CVBS or S-Video Dual Output 3-Layer Display Processor (1xGraphics, 2xVideo) Temporal Dithering SDTV QCIF Support® Camera ISP Image Capture Hardware Image Pipeline Camera (Parallel) HS USB Host HS USB OTG L3 Interconnect Network-Hierarchial, Performance, and Power Driven 64KB On-Chip RAM 32KB On-Chip ROM SMS: SDRAM Memory Scheduler/ Rotation SDRC: SDRAM Memory Controller L4 Interconnect System Controls PRCM 2xSmartReflexTM Control Module External Peripherals Interfaces Peripherals: 4xUART, 3xHigh-Speed I2C, 5xMcBSP (2x with Sidetone/Audio Buffer) 4xMcSPI, 6xGPIO 3xHigh-Speed MMC/SDIO HDQ/1 Wire, 6xMailboxes 12xGPTimers, 2xWDT, 32K Sync Timer GPMC: General Purpose Memory Controller NAND/ NOR Flash, SRAM Emulation Debug: SDTI, ETM, JTAGExternal and Stacked Memories IVA 2.2 Subsystem TMS320DM64x+ DSP Imaging Video and Audio Processor 32K/32K L1$ 48K L1D RAM 64K L2$ 32K L2 RAM 16K L2 ROM Video Hardware 64 32 Async 64 32 ARM Cortex™- A8 Core TrustZone 32K/32K L1$ DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011

1.3 FunctionalBlock Diagram

The functionalblockdiagramoftheDM3730/25 DigitalMedia Processorisshown below. Figure1-1.DM3730/25 FunctionalBlock Diagram Copyright© 2010–2011,Texas InstrumentsIncorporated DM3730, DM3725 DigitalMedia Processors 5 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com RevisionHistory NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Thisdata sheetrevisionhistoryhighlightsthe technicalchanges made from the previousto the current revision. RevisionHistory SECTION ADDITIONS/CHANGES/DELETIONS Changed:

• Table2-3.BallCharacteristics(CUS Pkg.).Removed restrictionnotefromGPIO_16. Changed:
• Table3-1.AbsoluteMaximum RatingoverJunctionTemperatureRange. Added JTAG toElectricalCharacteristics VESD.
• Table3-5.DC ElectricalCharacteristics.Removed USIM ballR27. Added noteon riseand falltimesforthesetables:
• InputClockRequirements
• sys_xtalinSquarerInputClockTimingRequirements-Bypass Mode
• sys_32kInputClockTimingRequirements
• sys_altclkInputClockTimingRequirementsClockSpecifications
• sys_clkout1OutputClockSwitchingCharacteristics
• sys_clkout2OutputClockSwitchingCharacteristics Added:
• Table4-2,CrystalElectricalCharacteristics.Added entryforDL -Crystaldrivelevel

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2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 A B C D E F G H J K L M N P T R U V W Y AA AB AC 24 25 26 27 28 AD AE AF AG AH 030-001 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011

2 TERMINAL DESCRIPTION

2.1 TerminalAssignment

Figure2-1 throughFigure2-5 show the balllocationsforthe 515- and 423- ballplasticballgridarray (s-PBGA) packages.Table 2-1 throughTable 2-25 indicatethe signalnames and ballgridnumbers for bothpackages. Note:Thereareno ballspresenton thetopofthe423-balls-PBGA package. Figure2-1.DM3730/25 DigitalMedia Processor CBP s-PBGA-N515 Package (Bottom View) Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 7 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

A C D E G K L M N P T R U V W Y AB B F H J AA AC 22 21 20 18 17 16 15 13 12 10 9 8 7 6 5 4 3 2 11114 1923 030-002 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Figure2-2.DM3730/25 DigitalMedia Processor CBP s-PBGA-N515 Package (Top View)

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Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Figure2-3.DM3730/25 DigitalMedia Processor CBC s-PBGA-515 Package (Bottom View) Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 9 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

Y W V U T R P N M L K J H G F E D C B A 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Figure2-4.DM3730/25 DigitalMedia Processor CBC s-PBGA-515 Package (Top View)

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Y W V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Figure2-5.DM3730/25 DigitalMedia Processor CUS s-PBGA-N423 Package (Bottom View)

2.2 Pin Assignments

2.2.1 Pin Map (Top View)

The followingpinmaps show thetopviewsofthe515-pinsPBGA package [CBP],the515-pinsPBGA package [CBC],and the423-pinsPBGA package [CUS] pinassignmentsinfourquadrants(A,B, C, and D). Note: A pinwithan "NC" designatorindicatesNo Connection.For properdeviceoperation,thesepins must be leftunconnected. Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 11 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

A vdds_mem 765432 NC B vdds_memvss C D E F G H J K vdds_memNC vdds_memNC vss vss vdd_corevdd_core vssvss gpmc_nwegpmc_nadv _ale vdds_memvdds_mem NC gpmc_nbe0 _cle gpmc_noeNC gpmc_wait3 vdd_coregpmc_ncs1gpmc_d8gpmc_nwp vss vdd_corevssvdds_memvdds_mem vdd_mpu _ivagpmc_wait1 gpmc_a10gpmc_d9gpmc_d0 gpmc_a4 gpmc_wait2 vdd_mpu _iva gpmc_ncs0 vss L M N P vdd_mpu _ivagpmc_wait0 gpmc_a9gpmc_d2gpmc_d1 gpmc_ncs7 gpmc_a2gpmc_a8pop_k2 _m2 vss gpmc_a1gpmc_a7pop_l2 _n2 pop_u1 _n1 vssgpmc_d3gpmc_d10 vss gpmc_ncs6 vss gpmc_a3 NC NC 121 110 NC vdds_mem NCvdds_mem vssvss vssvss NCNCNCNC vssvssvdd_mpu _iva vdd_mpu _iva vdd_mpu _ivavss vdd_mpu _iva vdd_mpu _ivavss vdd_mpu _iva NC vdd_mpu _iva vdd_mpu _iva vdd_mpu _iva vss pop_y23 _m1 NC NC NC NC NC NC NC NC NC NCNC NCNCNC NCNCNC NC NC NC NC NC NC NC NC NC NC NC NC NC NCNCNC NC NC DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com A. Top Views areprovidedtoassistinhardwaredebuggingefforts. Figure2-6.CBP Pin Map [QuadrantA -Top View]

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A 20 21 22 23 24 25 cam_d5 26 27 pop_a22 _a27 Bcam_d2 cam_d10 vss C Ddss_hsync E F G H J K vdds_mem cam_vs cam_hs pop_a23 _a28 vdds_mem cam_wen cam_xclkb pop_b23 _b28 vss cam_fld cam_d3 vss cam_xclka cam_d1 1 cam_pclk vdds_mem vss vdd_core cam_d4 dss_vsync dss_pclk vdd_core dss_data6 dss_acbias dss_data20 vdds dss_data8 dss_data7 uart3_rx _irrx dss_data9 vss vdds_mem dss_data19 dss_data18 dss_data17 vdds vdd_core hdq_sio dss_data21 pop_k1 _j28 vss mcbsp1_fsx cam_d8 cam_d6vdds_ mmc1 vdd_core dss_data16 cam_strobevdd_core L M N P vss vss cam_d9 cam_d7 vdd_core mmc1 _cmd vss vdd_core mmc1 _dat2 mmc1 _dat1 mmc1 _dat0 mmc1 _clk gpio_127 gpio_126 mmc1 _dat3vdds_x vdd_core vdd_core pop_a12 _a15 NC 17 18 19 NC NC vdds_mem NC NC vdds_mem vdds_mem NC vss vdd_core vdds_mem NC vss NC NC uart3_cts _rctx uart3_rts _sd vss vss vdd_core vdda_dplls _dll vdd_core vss vss vss vss vdd_mpu _iva NC NC vdd_core vdd_core vdd_core vss i2c1_sda cap_vdd _sram_core i2c1_scl mcbsp2_dx mcbsp2 _clkx mcbsp2_fsx uart3_tx _irtx NC NC NC NC NC NC NC NC NC NC pop_b12 _b15 vdds pop_h22 _j27 pop_k22 _m26 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Figure2-7.CBP Pin Map [QuadrantB -Top View] Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 13 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

etk_d5 etk_d15 7654 mmc2 _dat1 pop_ac2 _ah2 AG mmc2 _cmd mmc2 _dat2vss AF etk_d8 AE mmc2 _dat7 AD AC AB AA Y W etk_d13vdds_memmmc2 _dat0 etk_d9etk_d14etk_d12vssvsspop_ab1 _ag1 etk_d1 1mcbsp3_dxmcbsp3 _clkx mmc2 _dat5 mmc2 _dat3 mmc2 _dat6 vdd_coremcbsp3_drmcbsp3_fsxmmc2 _clk mcbsp4 _clkx mcbsp4_dxmcbsp4_dr vdd_coremcspi1_cs1mcspi1 _cs0 mcbsp4 _fsx mcspi1_clkmcspi1 _cs3 mcspi1 _cs2 uart1_txmcspi1 _somimcspi2_clkpop_aa1 _aa1 vdd_mpu _iva mcspi2 _cs0 mcspi2 _somi mcspi2_ simogpmc_d15 vdd_mpu _ivauart1_ctsvssgpmc_d7gpmc_d14 vdds uart1_rx uart1_rts mcspi1 _simo mmc2 _dat4 etk_d10 V U T R vssgpmc_ncs2mcspi2 _cs1gpmc_d6gpmc_d5 gpmc_ncs3 cap_vdd _bb_mpu _iva gpmc_nbe1vssvdds_mem vdd_mpu _ivagpmc_clkgpmc_a5gpmc_d13gpmc_d4 vdd_mpu _ivagpmc_ncs5gpmc_a6gpmc_d12gpmc_d1 1 vdds_mem gpmc_ncs4 vss cap_vdd _sram _mpu_iva etk_d7 13121 110 i2c3_scl etk_d2pop_ac9 _ah1 1 i2c3_sdapop_ab1 1 _ag13 etk_d1pop_ab9 _ag1 1 etk_d6vssetk_d0etk_clk sys_boot2etk_d3etk_d4etk_ctl jtag_tckjtag_rtckjtag_emu1 vdd_mpu _iva vdd_mpu _iva vdd_mpu _iva vss vssvss vdda_wkup _bg_bb vss jtag_emu0 vss vdd_mpu _iva vdd_mpu _iva vdd_mpu _iva vssvdd_mpu _iva vssvdd_mpu _iva pop_aa2 _aa2 vdds vdds vdds vddspop_u2 _af2 pop_ac8 _af1 pop_ab8 _ag10 pop_ac1 1 _ah13 pop_ac13 _ah10pop_ac1 _ah1 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Figure2-8.CBP Pin Map [QuadrantC -Top View]

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cap_vddu _array vss 22 23 24 25 sys _nrespwron 26 27 pop_ac22 _ah27 AGdss_data4 sys_clkout1 vdds AFvss AEi2c4_sda AD AC AB AA Y W dss_data1 dss_data3 dss_data5 vdds dss_data0 dss_data2 sys_boot1 pop_ab23 _ag28 sys_boot6 sys_off _mode sys _nreswarm sys_boot0 sys_clkreq sys_nirq vss sys_boot5 vdds vdd_core uart2_rx i2c4_scl dss_data1 1 dss_data10 vss vss dss_ data22 dss_ data23 uart2_cts dss_data13 dss_data12 uart2_tx dss_ data15 dss_ data14 vss vssa_dac cvideo1 _out cvideo1 _rset cvideo2 _vfb cvideo2 _outvss uart2_rts sys_32ksys_clkout2 V U T R hsusb0 _data7 hsusb0 _data6 hsusb0 _data5 hsusb0 _data4 hsusb0 _data3 hsusb0 _data2 hsusb0 _data1 hsusb0_stp hsusb0_nxt hsusb0 _data0 hsusb0_clk vss gpio_128 hsusb0_dirgpio_129 vdda_dac 15 16 pop_ac14 _ah16 17 18 19 i2c2_scl cam_d1 gpio_1 15 pop_ab13 _ag15 cam_d0 vdds sys_xtalout sys_boot3 sys_boot4 i2c2_sda vdd_core vdd_coresys_xtalin jtag_tdi mcbsp1 _clkr vdd_core vdd_core mcbsp1_dx mcbsp1 _clkx vdd_core vdd_core mcbsp1_dr mcbsp_clks vss mcbsp2_dr vss cap_vddu _wkup _logic vdda_dpll _per jtag_tms _tmsc jtag_tdo vdd_core sys_ xtalgnd vdd_core vdd_mpu _iva vdd_core vss vss vdds_sram vss vdd_mpu _iva jtag_ntrst vdd_core vdd_core vdd_core vss mcbsp1_fsr NC NC cvideo1 _vfb pop_aa23 _ae28 vdds pop_h23 _af28pop_aa22 _af27 vdds pop_l1 _ah15 gpio_1 13 pop_ac23 _ah28 vss gpio_1 14 gpio_1 12 vdds DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Figure2-9.CBP Pin Map [QuadrantD -Top View] Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 15 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

A 98765432 NC B vss C D E F G H J K gpmc _a1 1 pop_a1 _a1 NC gpmc_ ncs2 vdds uart1 _rx vdd_mpu _iva mmc2 _dat7 vss L M N gpmc _d14 pop_j1 _l1 mcbsp3 _dr cap_vdd _sram _mpu_iva vdds 13121 110 vdd_mpu _ivavss vdd_mpu _iva vdda_ dplls_ dll vdd_mpu _iva gpmc_ ncs4 gpmc_ wait2 NC vss cap_ vdd_bb _mpu_iva NCsys_ boot6 i2c2_scl vss vss NC vss NC NC NC NC vss NC vdd_ core gpmc_ ncs6 gpmc_ ncs3 NC NC NC NC NC NC NC NC NC NC vdds NC NC NC NC gpmc_ wait3 gpmc_ ncs7 gpmc_ ncs5 sys_ boot2 sys_ boot1 I2C2_SDA gpmc _a9 gpmc _a10 gpmc _a7 gpmc _a8 sys_ boot3 sys_ boot4 gpmc _a5 gpmc _a6 sys_ boot0 NC vss gpmc _a4 sys_ boot5 vdds gpmc _a2 gpmc _a3 vss gpmc _nbe1 gpmc _a1 NC NC vss gpmc _nbe0 _cle NC mmc2 _dat6 gpmc _nwe gpmc _d15 mmc2 _dat5 uart1 _tx gpmc _clk gpmc _noe vss NCvdd_mpu _ivavssvdd_mpu _iva NC vss vdd_mpu _iva NC NC NC NC NC NC NC NC NC vssNC vdd_ core vdds NC NCNCNC NC NC NC vdd_mpu _iva vdd_mpu _iva NC NC vss vdd_mpu _iva DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com A. Top Views areprovidedtoassistinhardwaredebuggingefforts. Figure2-10.CBC Pin Map [QuadrantA -Top View]

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A 18 19 20 21 22 23 cam_wen 24 25 26 BNC cam_d2 C D E F G H J K pop_b16 _a20 NC NC NC NC pop_ b21_b26 NC NC NC cam_ xclka NC NC NC NC uart3_ rts_sd dss_ data20 dss_ acbias dss_ data7 hdq_sio vdd_ core L M Nvdds_ mmc1 cam_d9 NC 15 16 17 NC NC NC NC NC NC NC NC vss NC vss cap_vddu_ wkup_ logic vss vdd_ core i2c1_scl NC NC NC vdds NC NC NCNC NC vss vss NC NC NC vss cam_d3 cam_d5 cam_d4 vdds cam_fld cam_hs cam_vs vss pop_ a20_a25 pop_ a21_a26 cam_ pclk cam_d10 cam_ strobe cam_d1 1 dss_ pclk cam_ xclkb dss_ data6 uart3_ cts_ rctx uart3_ tx_ irtx vss NC uart3_ rx_ irrx dss_ data8 dss_ data9i2c1_sda pop_ h21_k26vssdss_ hsync NC vss vdds dss_ data16 dss_ data17 dss_ data19 dss_ vsync dss_ data18NC cam_d8dss_ data21 NC NC gpio_126 vdd_ core NC vss vdd_ coreNCNCNCNCNCNC NCNCvddsNCNCvddsNC NC NC mmc1_ dat2 NC cap_vdd _sram_ core vddsvssmmc1_ cmd mmc1_ dat0 mmc1_ dat1 mmc1_ dat3 mmc1_ clkNCvss DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Figure2-11.CBC Pin Map [QuadrantB -Top View] Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 17 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

etk_d14 87654321 AE AD AC AB AA Y W V U etk_d13 sys_ nres warm pop_t2 _y2 NCetk_d9gpmc _d8 vdd_mpu _iva T R P pop_n2 _t2 gpmc _d10 mcbsp4 _dx uart1 _rts mcspi1 _clkNCmcbsp3 _dx gpmc _d13 mcspi1 _simo 13121 110 gpmc_ nadv_ale jtag_ rtckNC vdd_mpu _iva sys_ nresp wron sys_off _mode vdd_mpu _iva vdd_mpu _iva vdds_ sram vss i2c3_scl pop_aa1 1 _af13 pop_y9_ _af10NC uart1 _cts vdd_ core mcspi1 _cs0 mcspi1 _somi jtag_ tdo vdd_ corevss NC vss vss mcspi1 _cs1 mcspi1 _cs2 mmc2 _cmd mmc2 _dat0 mmc2 _dat1 mcspi1 _cs3vddsmcbsp4 _fsx gpmc _d12 gpmc _d1 1 mcbsp3 _clkx mcbsp4 _dr vdd_ core mcspi2 _somi mmc2 _dat3 mmc2 _dat2 vdd_mpu _iva mmc2 _dat4 mcspi2 _cs1 mcspi2 _cs0 vdd_mpu _iva mcbsp4 _clkx mcbsp3 _fsx vss mcspi2 _clk mcspi2 _simo vdd_mpu _iva mmc2 _clk sys_ clkout2 vdd_mpu _iva vdd_mpu _iva vdd_ corevssvddsetk_d4gpmc _d9 gpmc _d1 gpmc _d0 etk_d3 etk_d8 etk_d5 etk_clk etk_ctl vss gpmc _d3 gpmc _d2 etk_d0 i2c3_sda gpmc _d7 gpmc _nwp vdds gpmc _wait1 NC vss gpmc _wait0 NC NC NCNCNCNCgpmc _ncs0 gpmc _d5etk_d1etk_d2etk_d7gpmc _ncs1 gpmc _d6 NC pop_w2 _ae2 etk_d6 etk_d10 gpmc _d4 etk_d12 vss NC etk_d15 vdds NC NC NC pop_aa10 _af12NCpop_y7_ _af8etk_d1 1pop_aa6 _af5 pop_y2 _af4NCNC DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Figure2-12.CBC Pin Map [QuadrantC -Top View]

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sys_ xtalin 20 21 22 23 sys _xtalgnd 24 25 26 AEdss_ data1 AD AC AB AA Y W V U pop_y21 _ae26 vdd_ core uart2 _cts dss_ data13 dss_ data12 cvideo1 _rset vssa_ dac cvideo2 _out cvideo2 _vfb pop_ p21_u26 T R P vdds vdds_x NC cam_d7 pop_aa12 _af14 15 16 17 cam_d1 cam_d0 gpio_1 13 mcbsp1 _clkr hsusb0 _data2 mcbsp2 _dx gpio_129gpio_128 vdda_ wkup_ bg_bb i2c4_sda jtag_tms _tmsc jtag_tdi vss vdda_ dpll_per jtag_ ntrst sys_nirq gpio_127 vss pop_aa21 _af26 sys_ clkout1 cap _vddu _array mcbsp1 _dr hsusb0 _stp mcbsp2 _clkx mcbsp1 _fsx jtag_ emu1 cam_d6 NC NCNCNCvdd_ core mcbsp1 _clkx mcbsp2 _dr mcbsp _clks vss NC NC vssNCmcbsp2 _fsx mcbsp1 _dx jtag_tck mcbsp1 _fsr hsusb0 _dir hsusb0 _data0 vdda_ dac cvideo1 _out cvideo1 _vfbvddsvsshsusb0 _data3 hsusb0 _clk hsusb0 _nxt hsusb0 _data4 sys_ clkreq jtag_ emu0 vss hsusb0 _data7 hsusb0 _data5 hsusb0 _data6 hsusb0 _data1 NC vss dss_ data14 uart2 _rtsNC NC vdds dss_ data23 dss_ data15 dss_ data10 dss_ data22vddsNCNC sys_32k vssvddsNCvssNC vdds NC vss i2c4_scl gpio_1 12 vdds vdds vdds uart2 _rts uart2 _rx uart2 _tx dss_ data4 dss_ data5 vss dss_ data1 1 pop_y20 _ae25 pop_aa20 _af25 pop_y19 _af24 pop_ aa19_af22 pop_y17 _af21 dss_ data3 dss_ data2 dss_ data0gpio_1 14gpio_1 15 pop_aa13 _af15 pop_aa14 _af16 pop_y14 _af17 pop_aa17 _af18 sys_ xtalout DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Figure2-13.CBC Pin Map [QuadrantD -Top View] Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 19 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

A 987654321 B C D E F G H J K sdrc_a0NC NC L M gpmc _d0 mcspi2 _cs1 121 110 sdrc _dqs0 sdrc _dm2 vdds_x gpmc _ncs3 gpmc _nwp gpmc _nadv _ale gpmc _noe gpmc _a10 gpmc _a8 gpmc _a9 gpmc _a6 gpmc _d2 vdd_mpu _iva vss vss vdd_mpu _iva gpmc_ nbe0_cle vdd_mpu _iva vdd_mpu _iva NC sdrc _dqs2 sdrc _clk sdrc _nclk sdrc_a4 sdrc_a3 sdrc_a1 sdrc_d3 sdrc _dm0 sdrc_d7 sdrc_d18 sdrc_d19 sdrc_d21 sdrc_d8 sdrc_d10 sdrc_d9sdrc_d20sdrc_d16sdrc_d6sdrc_d2sdrc_d1sdrc_a5gpmc _wait3 gpmc _wait0 sdrc_a2 sdrc_d0 sdrc_d4 sdrc_d5 sdrc_d22 sdrc_d17sdrc_a8sdrc_a9sdrc_a10sdrc_a6gpmc _ncs0 gpmc _ncs6 gpmc _ncs4 sdrc_a7 sdrc_a13 sdrc_a14 vdd_ core vdd_mpu _ivasdrc_a12sdrc_a1 1gpmc _ncs5 gpmc _ncs7 gpmc _nwe vdd_mpu _iva vdd_mpu _iva vdd_ core vdd_ core vssvssvdd_mpu _iva vdd_mpu _iva vdds _mem vdds _mem vdds _mem gpmc _a4 gpmc _a5 gpmc _a7 gpmc _a3 gpmc _a2 gpmc _a1 vdds _mem vdds _mem vdds _mem vss vss vdd_mpu _ivavssvssgpmc_ nbe1 gpmc _d1 gpmc _d4 mcspi2 _cs0 vdd_mpu _iva vdd_mpu _iva vdd_mpu _iva vss vss DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com A. Top Views areprovidedtoassistinhardwaredebuggingefforts. Figure2-14.CUS Pin Map [QuadrantA -Top View]

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A 16 17 18 19 20 21 22 23 24 B cam_hs C D E F G H J K dss_ data9 dss_ data19 dss_ acbias L M 13 14 15 sdrc_ dqs1 vdd_ core cam_ xclka uart3_ _cts_ rctx hdq_si0 dss_ data6 dss_ data18 i2c1_sda mmc1_ cmd vdda _dplls _dll cap_vdd _sram _core vdds_ mem cam_vs vdd_ core vss cam_ strobe cam_ pclk vss sdrc_ d14 sdrc_ dm3 sdrc_ dqs3 sdrc_ ncs0 sdrc_ nwe uart3_ _rx_ irrx uart3_ _rts_ sd cam_d5sdrc_ cke0 sdrc_ ncs1 sdrc_ d31 sdrc_ d30 sdrc_ d27 sdrc_ d15 sdrc_ d13 sdrc_ dm1 sdrc_ d12 sdrc_ d26 sdrc_ d28 sdrc_ ba0 sdrc_ ncas sdrc_ cke1 cam_ xclkb uart3_ _tx_ irtx dss_ data20 sdrc_ nras sdrc_ ba1 sdrc_ d29 sdrc_ d25 sdrc_ d1 1 sdrc_ d23 sdrc_ d24 vdds dss_ hsync dss_ data7 dss_ data8 dss_ vsynccam_d10cam_d3cam_wenvdds_ mem vdds_ mem vdd_ core vdds_ mem vdds_ mem cam_d2 cam_d4 cam_d1 1 dss_ pclk dss_ data17 cam_fldvdds_ memvssvdd_ core vss vss vss vss vdd_ core vdd_ core dss_ data16 cam_d8 cam_d7cam_d9dss_ data21i2c1_sclvdd_ core vdd_ core vdd_ corevssvss vss vdd_ core vdd_ core vss cam_d6 mmc1_ clk mmc1_ dat0 mmc1_ dat1 mmc1_ dat2vddsvddsvssvdd_ core DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Figure2-15.CUS Pin Map [QuadrantB -Top View] Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 21 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

etk_d14 87654321 AC AB AA Y W V U T R sys_ nres warm vdd_mpu _iva P N gpmc _d3 uart1 _rx 121 110 vdd_mpu _iva vss NC uart1 _rts vssmcspi2 _clk mmc2 _dat3 gpmc _d7 gpmc _d8 mcspi2 _simo mcspi1 _cs0 vdd_mpu _iva sys_ clkout1 etk_d4 gpmc _d14 gpmc _clk etk_clk sys_ clkout2 vdds jtag_tms _tmsc vdds_ sram sys_ boot0 uart1_ cts etk_d10 etk_d8 etk_d1 etk_d12 i2c3_sda etk_d0 mcbsp3 _dx mcspi1 _simo mcbsp1 _cs3 cap_vddu_ wkup_logic vdd_mpu _iva vdd_mpu _iva mcspi2 _somi vdd_mpu _iva vssvss vss vss vdd_mpu _iva vss vss vss vss vss gpmc _d1 1 gpmc _d5 gpmc _d6 vdd_mpu _iva vdd_mpu _iva mcspi1 _clk gpmc _d9 gpmc _d12 mcspi1 _somi vssvssvss vssvss cap_vdd _sram_ mpu_iva gpmc _d13 gpmc _d10 vdd_mpu _ivavddsvddsmcbsp3 _fsx gpmc _d15 mcbsp3 _dr vdd_mpu _ivavddsvddsuart1 _tx mcbsp3 _clkx mmc2 _dat2 vddsmmc2 _dat1 mmc2 _dat6 mmc2 _clk mmc2 _dat7 mmc2 _dat5 jtag_ rtck sys_ nres pwron jtag_ tdi jtag_ tdo jtag_ ntrst jtag_ tck mmc2 _cmd mmc2 _dat0 mmc2 _dat4 etk_d2 etk_d1 1etk_d6 etk_d5 etk_ctl etk_d9 etk_d3 etk_d7 etk_d13 etk_d15 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Figure2-16.CUS Pin Map [QuadrantC -Top View]

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sys_ xtalin 18 19 20 21 22 23 24 ACdss_ data3 AB AA Y W V U T R dss_ data15 dss_ data14 cvideo1 _rset P N 13 14 15 mcbsp1 _clkx vddsvss hsusb0 _stp mmc1_ dat3gpio_126 cap_vdd _bb_mpu _iva vdd_ core hsusb0 _dir hsusb0 _data0 cvideo2 _out cvideo1 _vfb sys_ clkreq dss_ data23 sys_32ksys_ boot6 vdda_ wkup _bg_bb i2c3_scl vssa_dac cam_d0 dss_ data12 sys_off _mode dss_ data10 dss_ data5 dss_ data0 cap_vddu _array sys_ xtalgnd jtag_ emu0 i2c4_scl vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vss vdds vdds vdds_ mmc1 gpio_129vss hsusb0 _clk mcbsp2 _dx vdd_ core vdd_ core hsusb0 _nxt hsusb0 _data1 hsusb0 _data7 mcbsp2 _clkx vdd_ core vdd_ core vdd_ core vdd_ core hsusb0 _data2 hsusb0 _data3 vdda_ dpll _per vdd_mpu _iva vdd_mpu _iva mcbsp2 _dr mcbsp2 _fsx dss_ data22 hsusb0 _data5 hsusb0 _data6 hsusb0 _data4 mcbsp1 _clkr sys_ nirq mcbsp1 _dx vdd_mpu _iva cvideo2 _vfb dss_ data13 mcbsp1 _dri2c4_sda mcbsp _clks mcbsp1 _fsx cvideo1 _out mcbsp1 _fsr dss_ data1 sys_ boot5 vdda_ dac i2c2_sda i2c2_scl sys_ boot1 sys_ boot4 cam_d1 dss_ data1 1 jtag_ emu1 dss_ data4 dss_ data2 sys_ boot3 sys_ boot2 sys_ xtaout DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Figure2-17.CUS Pin Map [QuadrantD -Top View] Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 23 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com

2.3 BallCharacteristics

Table2-1throughTable2-3describetheterminalcharacteristicsand thesignalsmultiplexedon each pin forthe CBP, CBC, and CUS packages, respectively.The followinglistdescribesthe tablecolumn headers. 1. BALL BOTTOM: Ballnumber(s)on thebottomsideassociatedwitheach signal(s)on thebottom. 2. PIN NAME: Names ofsignalsmultiplexedon each ball(alsonoticethatthename ofthepinisthe signalname inmode 0). Note:Table2-3does nottakeintoaccountsubsystempinmultiplexingoptions.Subsystem pin multiplexingoptionsaredescribedinSection2.5,SignalDescriptions. 3. MODE: Multiplexingmode number. (a) Mode 0 istheprimarymode; thismeans thatwhen mode 0 isset,thefunctionmapped on thepin correspondstothename ofthepin.Thereisalwaysa functionmapped on theprimarymode. Noticethatprimarymode isnotnecessarilythedefaultmode. Note:The defaultmode isthemode atthereleaseofthereset;alsosee theRESET REL. MODE column. (b) Modes 1 to7 arepossiblemodes foralternatefunctions.On each pin,some modes areeffectively used foralternatefunctions,whilesome modes arenotused and do notcorrespondtoa functional configuration. 4. TYPE: Signaldirection – I= Input – O = Output – I/O= Input/Output – D = Open drain – DS = Differential – A = Analog – PWR = Power – GND = Ground Note:Inthesafe_mode,thebufferisconfiguredinhigh-impedance. 5. BALL RESET STATE: The stateoftheterminalatthepower-onreset. – 0:The bufferdrivesVOL (pulldown/pullupresistornotactivated) 0(PD):The bufferdrivesVOL withan activepulldownresistor. – 1:The bufferdrivesVOH (pulldown/pullupresistornotactivated) 1(PU):The bufferdrivesVOH withan activepullupresistor. – Z:High-impedance – L:High-impedancewithan activepulldownresistor – H :High-impedancewithan activepullupresistor 6. BALL RESET REL. STATE: The stateoftheterminalatthereleaseoftheSystem ControlModule reset(PRCM CORE_RSTPWRON_RET resetsignal). – 0:The bufferdrivesVOL (pulldown/pullupresistornotactivated) 0(PD):The bufferdrivesVOL withan activepulldownresistor. – 1:The bufferdrivesVOH (pulldown/pullupresistornotactivated) 1(PU):The bufferdrivesVOH withan activepullupresistor. – Z:High-impedance – L:High-impedancewithan activepulldownresistor – H :High-impedancewithan activepullupresistor 7. RESET REL. MODE: The mode isautomaticallyconfiguredatthereleaseoftheSystem Control Module reset(PRCM CORE_RSTPWRON_RET resetsignal). 8. POWER: The voltagesupplythatpowers theterminal’s I/Obuffers. 9. HYS: Indicatesiftheinputbufferiswithhysteresis. 10. BUFFER STRENGTH: Drivestrengthoftheassociatedoutputbuffer.

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 11. PULL U/D -TYPE: Denotesthepresenceofan internalpulluporpulldownresistor.Pullupand pulldownresistorscan be enabledordisabledviasoftware. Note:The pullup/pulldowndrivestrengthisequaltominimum = 50μA,typical= 100 μA,maximum = 250 μA (unlessotherwisespecified),exceptforCBP ballsP27,P26,R27, and R25, and CUS balls N22 and P24,where thepulldowndrivestrengthisequalto1.8kΩ. 12. IO CELL: IO cellinformation. Note:Configuringtwo pinstothesame inputsignalisnotsupportedas itcan yieldunexpectedresults. Thiscan be easilypreventedwiththepropersoftwareconfiguration. NOTE IntheDM3730/25 device,new Far End loadSettingsregistersareadded forsome IOs.This new feature configures the IO according to the transmissionline and the application/peripheralload.For a fulldescriptionon theseregisters,see theSystem Control Module / SCM FunctionalDescription/ FunctionalRegisterDescription/ SignalIntegrity Parameter ControlRegisterswith Pad Group Assignment sectionof the AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-1.BallCharacteristics(CBP Pkg.)(3) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] NA J2 sdrc_d0 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA J1 sdrc_d1 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA G2 sdrc_d2 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA G1 sdrc_d3 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA F2 sdrc_d4 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA F1 sdrc_d5 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA D2 sdrc_d6 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA D1 sdrc_d7 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA B13 sdrc_d8 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA A13 sdrc_d9 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA B14 sdrc_d10 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA A14 sdrc_d11 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA B16 sdrc_d12 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA A16 sdrc_d13 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA B19 sdrc_d14 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA A19 sdrc_d15 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA B3 sdrc_d16 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA A3 sdrc_d17 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA B5 sdrc_d18 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA A5 sdrc_d19 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA B8 sdrc_d20 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA A8 sdrc_d21 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA B9 sdrc_d22 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA A9 sdrc_d23 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA B21 sdrc_d24 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA A21 sdrc_d25 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA D22 sdrc_d26 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA D23 sdrc_d27 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA E22 sdrc_d28 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA E23 sdrc_d29 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA G22 sdrc_d30 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA G23 sdrc_d31 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA AB21 sdrc_ba0 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA AC21 sdrc_ba1 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 25 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] NA N22 sdrc_a0 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA N23 sdrc_a1 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA P22 sdrc_a2 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA P23 sdrc_a3 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA R22 sdrc_a4 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA R23 sdrc_a5 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA T22 sdrc_a6 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA T23 sdrc_a7 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA U22 sdrc_a8 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA U23 sdrc_a9 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA V22 sdrc_a10 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA V23 sdrc_a11 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA W22 sdrc_a12 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA W23 sdrc_a13 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA Y22 sdrc_a14 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA M22 sdrc_ncs0 0 O 1 1 0 vdds_mem No 4 (12) NA LVCMOS NA M23 sdrc_ncs1 0 O 1 1 0 vdds_mem No 4 (12) NA LVCMOS NA A11 sdrc_clk 0 IO L 0 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA B11 sdrc_nclk 0 O 1 1 0 vdds_mem No 4 (12) NA LVCMOS NA J22 sdrc_cke0 0 O H 1 7 vdds_mem Yes 4 (12) PU/ PD LVCMOS safe_mode_out1(13) 7 NA J23 sdrc_cke1 0 O H 1 7 vdds_mem NA 4 (12) PU/ PD LVCMOS safe_mode_out1(13) 7 NA L23 sdrc_nras 0 O 1 1 0 vdds_mem No 4 (12) NA LVCMOS NA L22 sdrc_ncas 0 O 1 1 0 vdds_mem No 4 (12) NA LVCMOS NA K23 sdrc_nwe 0 O 1 1 0 vdds_mem No 4 (12) NA LVCMOS NA C1 sdrc_dm0 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA A17 sdrc_dm1 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA A6 sdrc_dm2 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA A20 sdrc_dm3 0 O 0 0 0 vdds_mem No 4 (12) NA LVCMOS NA C2 sdrc_dqs0 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA B17 sdrc_dqs1 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA B6 sdrc_dqs2 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS NA B20 sdrc_dqs3 0 IO L Z 0 vdds_mem Yes 4 (12) PU/ PD LVCMOS N4 AC15 gpmc_a1 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_34 4 IO safe_mode 7 M4 AB15 gpmc_a2 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_35 4 IO safe_mode 7 L4 AC16 gpmc_a3 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_36 4 IO safe_mode 7 K4 AB16 gpmc_a4 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_37 4 IO safe_mode 7 T3 AC17 gpmc_a5 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_38 4 IO safe_mode 7 R3 AB17 gpmc_a6 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_39 4 IO safe_mode 7

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] N3 AC18 gpmc_a7 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_40 4 IO safe_mode 7 M3 AB18 gpmc_a8 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_41 4 IO safe_mode 7 L3 AC19 gpmc_a9 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS sys_ndmareq2 1 I gpio_42 4 IO safe_mode 7 K3 AB19 gpmc_a10 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS sys_ndmareq3 1 I gpio_43 4 IO safe_mode 7 NA AC20 gpmc_a11 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS safe_mode 7 K1 M2 gpmc_d0 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS L1 M1 gpmc_d1 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS L2 N2 gpmc_d2 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS P2 N1 gpmc_d3 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS T1 R2 gpmc_d4 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS V1 R1 gpmc_d5 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS V2 T2 gpmc_d6 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS W2 T1 gpmc_d7 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS H2 AB3 gpmc_d8 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_44 4 IO safe_mode 7 K2 AC3 gpmc_d9 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_45 4 IO safe_mode 7 P1 AB4 gpmc_d10 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_46 4 IO safe_mode 7 R1 AC4 gpmc_d11 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_47 4 IO safe_mode 7 R2 AB6 gpmc_d12 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_48 4 IO safe_mode 7 T2 AC6 gpmc_d13 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_49 4 IO safe_mode 7 W1 AB7 gpmc_d14 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_50 4 IO safe_mode 7 Y1 AC7 gpmc_d15 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_51 4 IO safe_mode 7 G4 Y2 gpmc_ncs0 0 O 1 1 0 vdds_mem NA 8 NA LVCMOS H3 Y1 gpmc_ncs1 0 O H 1 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_52 4 IO safe_mode 7 Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 27 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] V8 NA gpmc_ncs2 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_53 4 IO safe_mode 7 U8 NA gpmc_ncs3 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS sys_ndmareq0 1 I gpio_54 4 IO safe_mode 7 T8 NA gpmc_ncs4 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS sys_ndmareq1 1 I mcbsp4_clkx 2 IO gpt_9_pwm_evt 3 IO gpio_55 4 IO safe_mode 7 R8 NA gpmc_ncs5 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS sys_ndmareq2 1 I mcbsp4_dr 2 I gpt_10_pwm_evt 3 IO gpio_56 4 IO safe_mode 7 P8 NA gpmc_ncs6 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS sys_ndmareq3 1 I mcbsp4_dx 2 IO gpt_11_pwm_evt 3 IO gpio_57 4 IO safe_mode 7 N8 NA gpmc_ncs7 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS gpmc_io_dir 1 O mcbsp4_fsx 2 IO gpt_8_pwm_evt 3 IO gpio_58 4 IO safe_mode 7 T4 W2 gpmc_clk 0 O L 0 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_59 4 IO safe_mode 7 F3 W1 gpmc_nadv_ale 0 O 0 0 0 vdds_mem NA 8 PU/ PD LVCMOS G2 V2 gpmc_noe 0 O 1 1 0 vdds_mem NA 8 PU/ PD LVCMOS F4 V1 gpmc_nwe 0 O 1 1 0 vdds_mem NA 8 PU/ PD LVCMOS G3 AC12 gpmc_nbe0_cle 0 O L 0 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_60 4 IO safe_mode 7 U3 NA gpmc_nbe1 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_61 4 IO safe_mode 7 H1 AB10 gpmc_nwp 0 O L 0 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_62 4 IO safe_mode 7 M8 AB12 gpmc_wait0 0 I H H 0 vdds_mem Yes NA PU/ PD LVCMOS L8 AC10 gpmc_wait1 0 I H H 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_63 4 IO safe_mode 7 K8 NA gpmc_wait2 0 I H H 7 vdds_mem Yes 8 PU/ PD LVCMOS uart4_tx 2 O gpio_64 4 IO safe_mode 7

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] J8 NA gpmc_wait3 0 I H H 7 vdds_mem Yes 8 PU/ PD LVCMOS sys_ndmareq1 1 I uart4_rx 2 I gpio_65 4 IO safe_mode 7 D28 NA dss_pclk 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_66 4 IO hw_dbg12 5 O safe_mode 7 D26 NA dss_hsync 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_67 4 IO hw_dbg13 5 O safe_mode 7 D27 NA dss_vsync 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_68 4 IO safe_mode 7 E27 NA dss_acbias 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_69 4 IO safe_mode 7 AG22 NA dss_data0 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart1_cts 2 I NA gpio_70 4 IO 8 safe_mode 7 8 AH22 NA dss_data1 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart1_rts 2 O 8 gpio_71 4 IO 8 safe_mode 7 8 AG23 NA dss_data2 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_72 4 IO 8 safe_mode 7 8 AH23 NA dss_data3 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_73 4 IO 8 safe_mode 7 8 AG24 NA dss_data4 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart3_rx_irrx 2 I NA gpio_74 4 IO 8 safe_mode 7 8 AH24 NA dss_data5 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart3_tx_irtx 2 O 8 gpio_75 4 IO 8 safe_mode 7 8 E26 NA dss_data6 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart1_tx 2 O gpio_76 4 IO hw_dbg14 5 O safe_mode 7 F28 NA dss_data7 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart1_rx 2 I gpio_77 4 IO hw_dbg15 5 O safe_mode 7 Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 29 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] F27 NA dss_data8 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart3_rx_irrx 2 I gpio_78 4 IO hw_dbg16 5 O safe_mode 7 G26 NA dss_data9 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart3_tx_irtx 2 O gpio_79 4 IO hw_dbg17 5 O safe_mode 7 AD28 NA dss_data10 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_80 4 IO safe_mode 7 AD27 NA dss_data11 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_81 4 IO safe_mode 7 AB28 NA dss_data12 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_82 4 IO safe_mode 7 AB27 NA dss_data13 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_83 4 IO safe_mode 7 AA28 NA dss_data14 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_84 4 IO safe_mode 7 AA27 NA dss_data15 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_85 4 IO safe_mode 7 G25 NA dss_data16 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_86 4 IO safe_mode 7 H27 NA dss_data17 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_87 4 IO safe_mode 7 H26 NA dss_data18 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_clk 2 IO dss_data0 3 IO gpio_88 4 IO safe_mode 7 H25 NA dss_data19 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_simo 2 IO dss_data1 3 IO gpio_89 4 IO safe_mode 7 E28 NA dss_data20 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_somi 2 IO dss_data2 3 IO gpio_90 4 IO safe_mode 7 J26 NA dss_data21 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_cs0 2 IO dss_data3 3 IO gpio_91 4 IO safe_mode 7

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] AC27 NA dss_data22 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_cs1 2 O dss_data4 3 IO gpio_92 4 IO safe_mode 7 AC28 NA dss_data23 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS dss_data5 3 IO gpio_93 4 IO safe_mode 7 W28 NA cvideo2_out 0 AO 0 0 0 vdda_dac NA NA (4) NA 10-bitDAC Y28 NA cvideo1_out 0 AO 0 0 0 vdda_dac NA NA (4) NA 10-bitDAC Y27 NA cvideo1_vfb 0 AO 0 NA 0 vdda_dac NA NA (10) NA 10-bitDAC W27 NA cvideo2_vfb 0 AO 0 NA 0 vdda_dac NA NA (10) NA 10-bitDAC W26 NA cvideo1_rset 0 AIO 0 NA 0 vdda_dac No NA NA 10-bitDAC A24 NA cam_hs 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_94 4 IO hw_dbg0 5 O safe_mode 7 A23 NA cam_vs 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_95 4 IO hw_dbg1 5 O safe_mode 7 C25 NA cam_xclka 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_96 4 IO safe_mode 7 C27 NA cam_pclk 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_97 4 IO hw_dbg2 5 O safe_mode 7 C23 NA cam_fld 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS cam_global_reset 2 IO gpio_98 4 IO hw_dbg3 5 O safe_mode 7 AG17 NA cam_d0 0 I L L 7 vdds Yes NA PU/PD LVCMOS gpio_99 4 I safe_mode 7 AH17 NA cam_d1 0 I L L 7 vdds Yes NA PU/PD LVCMOS gpio_100 4 I safe_mode 7 B24 NA cam_d2 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_101 4 IO hw_dbg4 5 O safe_mode 7 C24 NA cam_d3 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_102 4 IO hw_dbg5 5 O safe_mode 7 D24 NA cam_d4 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_103 4 IO hw_dbg6 5 O safe_mode 7 A25 NA cam_d5 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_104 4 IO Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 31 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] hw_dbg7 5 O safe_mode 7 K28 NA cam_d6 0 I L L 7 vdds Yes NA PU/ PD LVCMOS gpio_105 4 I safe_mode 7 L28 NA cam_d7 0 I L L 7 vdds Yes NA PU/ PD LVCMOS gpio_106 4 I safe_mode 7 K27 NA cam_d8 0 I L L 7 vdds Yes NA PU/ PD LVCMOS gpio_107 4 I safe_mode 7 L27 NA cam_d9 0 I L L 7 vdds Yes NA PU/ PD LVCMOS gpio_108 4 I safe_mode 7 B25 NA cam_d10 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_109 4 IO hw_dbg8 5 O safe_mode 7 C26 NA cam_d11 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_110 4 IO hw_dbg9 5 O safe_mode 7 B26 NA cam_xclkb 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_111 4 IO safe_mode 7 B23 NA cam_wen 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS cam_shutter 2 O gpio_167 4 IO hw_dbg10 5 O safe_mode 7 D25 NA cam_strobe 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_126 4 IO hw_dbg11 5 O safe_mode 7 AG19 NA gpio_112 4 I L L 7 vdds Yes NA PU/PD LVCMOS safe_mode 7 AH19 NA gpio_113 4 I L L 7 vdds Yes NA PU/PD LVCMOS safe_mode 7 AG18 NA gpio_114 4 I L L 7 vdds Yes NA PU/PD LVCMOS safe_mode 7 - AH18 NA gpio_115 4 I L L 7 vdds Yes NA PU/PD LVCMOS safe_mode 7 - P21 NA mcbsp2_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_116 4 IO safe_mode 7 N21 NA mcbsp2_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_117 4 IO safe_mode 7 R21 NA mcbsp2_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_118 4 IO safe_mode 7 M21 NA mcbsp2_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_119 4 IO safe_mode 7

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] N28 NA mmc1_clk 0 O L L 7 vdds_mmc1 ( Yes 1 PU/ PD (5) LVCMOS 15) gpio_120(1) 4 IO safe_mode 7 M27 NA mmc1_cmd 0 IO L L 7 vdds_mmc1 ( Yes 1 PU/ PD (5) LVCMOS 15) gpio_121(1) 4 IO safe_mode 7 N27 NA mmc1_dat0 0 IO L L 7 vdds_mmc1 ( Yes 1 PU/ PD (5) LVCMOS 15) gpio_122(1) 4 IO safe_mode 7 N26 NA mmc1_dat1 0 IO L L 7 vdds_mmc1 ( Yes 1 PU/ PD (5) LVCMOS 15) gpio_123(1) 4 IO safe_mode 7 N25 NA mmc1_dat2 0 IO L L 7 vdds_mmc1 ( Yes 1 PU/ PD (5) LVCMOS 15) gpio_124(1) 4 IO safe_mode 7 P28 NA mmc1_dat3 0 IO L L 7 vdds_mmc1 ( Yes 1 PU/ PD (5) LVCMOS 15) gpio_125(1) 4 IO safe_mode 7 P27 NA gpio_126(1) 4 IO L L 7 vdds_x Yes 1 PU/ PD (5) LVCMOS safe_mode 7 P26 NA gpio_127(1) 4 IO L L 7 vdds_x Yes 1 PU/ PD (5) LVCMOS safe_mode 7 R27 NA gpio_128 4 IO L L 7 vdds Yes 4 PU/ PD LVCMOS safe_mode 7 R25 NA gpio_129(1) 4 IO L L 7 vdds_x Yes 1 PU/ PD (5) LVCMOS safe_mode 7 AE2 NA mmc2_clk 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_clk 1 IO gpio_130 4 IO safe_mode 7 AG5 NA mmc2_cmd 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_simo 1 IO gpio_131 4 IO safe_mode 7 AH5 NA mmc2_dat0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_somi 1 IO gpio_132 4 IO safe_mode 7 AH4 NA mmc2_dat1 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_133 4 IO safe_mode 7 AG4 NA mmc2_dat2 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_cs1 1 O gpio_134 4 IO safe_mode 7 AF4 NA mmc2_dat3 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_cs0 1 IO gpio_135 4 IO safe_mode 7 AE4 NA mmc2_dat4 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 33 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] mmc2_dir_dat0 1 O mmc3_dat0 3 IO gpio_136 4 IO safe_mode 7 AH3 NA mmc2_dat5 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dir_dat1 1 O cam_global_reset 2 IO mmc3_dat1 3 IO gpio_137 4 IO mm3_rxdp 6 IO safe_mode 7 AF3 NA mmc2_dat6 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dir_cmd 1 O cam_shutter 2 O mmc3_dat2 3 IO gpio_138 4 IO safe_mode 7 AE3 NA mmc2_dat7 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_clkin 1 I mmc3_dat3 3 IO gpio_139 4 IO mm3_rxdm 6 IO safe_mode 7 AF6 NA mcbsp3_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart2_cts 1 I gpio_140 4 IO safe_mode 7 AE6 NA mcbsp3_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS uart2_rts 1 O gpio_141 4 IO safe_mode 7 AF5 NA mcbsp3_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart2_tx 1 O gpio_142 4 IO safe_mode 7 AE5 NA mcbsp3_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart2_rx 1 I gpio_143 4 IO safe_mode 7 AB26 NA uart2_cts 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS mcbsp3_dx 1 IO gpt_9_pwm_evt 2 IO gpio_144 4 IO safe_mode 7 AB25 NA uart2_rts 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS mcbsp3_dr 1 I gpt_10_pwm_evt 2 IO gpio_145 4 IO safe_mode 7 AA25 NA uart2_tx 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS mcbsp3_clkx 1 IO gpt_11_pwm_evt 2 IO gpio_146 4 IO safe_mode 7

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] AD25 NA uart2_rx 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS mcbsp3_fsx 1 IO gpt_8_pwm_evt 2 IO gpio_147 4 IO safe_mode 7 AA8 NA uart1_tx 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_148 4 IO safe_mode 7 AA9 NA uart1_rts 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_149 4 IO safe_mode 7 W8 NA uart1_cts 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_150 4 IO safe_mode 7 Y8 NA uart1_rx 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS mcbsp1_clkr 2 IO mcspi4_clk 3 IO gpio_151 4 IO safe_mode 7 AE1 NA mcbsp4_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_152 4 IO mm3_txse0 6 IO safe_mode 7 AD1 NA mcbsp4_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_153 4 IO mm3_rxrcv 6 IO safe_mode 7 AD2 NA mcbsp4_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_154 4 IO mm3_txdat 6 IO safe_mode 7 AC1 NA mcbsp4_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_155 4 IO mm3_txen_n 6 IO safe_mode 7 Y21 NA mcbsp1_clkr 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi4_clk 1 IO gpio_156 4 IO safe_mode 7 AA21 NA mcbsp1_fsr 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS cam_global_reset 2 IO gpio_157 4 IO safe_mode 7 V21 NA mcbsp1_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi4_simo 1 IO mcbsp3_dx 2 IO gpio_158 4 IO safe_mode 7 U21 NA mcbsp1_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi4_somi 1 IO mcbsp3_dr 2 I gpio_159 4 IO safe_mode 7 T21 NA mcbsp_clks 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 35 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] cam_shutter 2 O gpio_160 4 IO uart1_cts 5 I safe_mode 7 K26 NA mcbsp1_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi4_cs0 1 IO mcbsp3_fsx 2 IO gpio_161 4 IO safe_mode 7 W21 NA mcbsp1_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mcbsp3_clkx 2 IO gpio_162 4 IO safe_mode 7 H18 NA uart3_cts_rctx 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_163 4 IO safe_mode 7 H19 NA uart3_rts_sd 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_164 4 IO safe_mode 7 H20 NA uart3_rx_irrx 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_165 4 IO safe_mode 7 H21 NA uart3_tx_irtx 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_166 4 IO safe_mode 7 T28 NA hsusb0_clk 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_120 4 IO safe_mode 7 T25 NA hsusb0_stp 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_121 4 IO safe_mode 7 R28 NA hsusb0_dir 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_122 4 IO safe_mode 7 T26 NA hsusb0_nxt 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_124 4 IO safe_mode 7 T27 NA hsusb0_data0 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart3_tx_irtx 2 O gpio_125 4 IO uart2_tx 5 O safe_mode 7 U28 NA hsusb0_data1 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart3_rx_irrx 2 I gpio_130 4 IO uart2_rx 5 I safe_mode 7 U27 NA hsusb0_data2 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart3_rts_sd 2 O gpio_131 4 IO uart2_rts 5 O safe_mode 7 U26 NA hsusb0_data3 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart3_cts_rctx 2 IO

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] gpio_169 4 IO uart2_cts 5 I safe_mode 7 U25 NA hsusb0_data4 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_188 4 IO safe_mode 7 V28 NA hsusb0_data5 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_189 4 IO safe_mode 7 V27 NA hsusb0_data6 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_190 4 IO safe_mode 7 V26 NA hsusb0_data7 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_191 4 IO safe_mode 7 K21 NA i2c1_scl 0 OD H H 0 vdds NA 3 PU/ PD (6)(7) Open Drain J21 NA i2c1_sda 0 IOD H H 0 vdds Yes 3 PU/ PD (6)(7) Open Drain AF15 NA i2c2_scl 0 OD H H 7 vdds Yes 3 PU/ PD (6)(8) Open Drain gpio_168 4 IO 4 safe_mode 7 AE15 NA i2c2_sda 0 IOD H H 7 vdds Yes 3 PU/ PD (6)(8) Open Drain gpio_183 4 IO 4 safe_mode 7 AF14 NA i2c3_scl 0 OD H H 7 vdds Yes 3 PU/ PD (6)(8) Open Drain gpio_184 4 IO 4 safe_mode 7 AG14 NA i2c3_sda 0 IOD H H 7 vdds Yes 3 PU/ PD (6)(8) Open Drain gpio_185 4 IO 4 safe_mode 7 AD26 NA i2c4_scl 0 OD H H 0 vdds Yes 3 PU/ PD (6)(7) Open Drain sys_nvmode1 1 O 4 safe_mode 7 AE26 NA i2c4_sda 0 IOD H H 0 vdds Yes 3 PU/ PD (6)(7) Open Drain sys_nvmode2 1 O 4 safe_mode 7 J25 NA hdq_sio 0 IOD H H 7 vdds Yes 4 PU/ PD LVCMOS sys_altclk 1 I i2c2_sccbe 2 OD i2c3_sccbe 3 OD gpio_170 4 IO safe_mode 7 AB3 NA mcspi1_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dat4 1 IO gpio_171 4 IO safe_mode 7 AB4 NA mcspi1_simo 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dat5 1 IO gpio_172 4 IO safe_mode 7 AA4 NA mcspi1_somi 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dat6 1 IO gpio_173 4 IO safe_mode 7 AC2 NA mcspi1_cs0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 37 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] mmc2_dat7 1 IO gpio_174 4 IO safe_mode 7 AC3 NA mcspi1_cs1 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS mmc3_cmd 3 IO gpio_175 4 IO safe_mode 7 AB1 NA mcspi1_cs2 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS mmc3_clk 3 O gpio_176 4 IO safe_mode 7 AB2 NA mcspi1_cs3 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS hsusb2_ data2 3 IO gpio_177 4 IO mm2_txdat 5 IO safe_mode 7 AA3 NA mcspi2_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS hsusb2_ data7 3 IO gpio_178 4 IO safe_mode 7 Y2 NA mcspi2_simo 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpt_9_pwm_evt 1 IO hsusb2_ data4 3 IO gpio_179 4 IO safe_mode 7 Y3 NA mcspi2_somi 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpt_10_pwm_evt 1 IO hsusb2_ data5 3 IO gpio_180 4 IO safe_mode 7 Y4 NA mcspi2_cs0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS gpt_11_pwm_evt 1 IO hsusb2_ data6 3 IO gpio_181 4 IO safe_mode 7 V3 NA mcspi2_cs1 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpt_8_pwm_evt 1 IO hsusb2_ data3 3 IO gpio_182 4 IO mm2_txen_n 5 IO safe_mode 7 AE25 NA sys_32k 0 I Z Z 0 vdds Yes NA PU/ PD LVCMOS AE17 NA sys_xtalin 0 AI Z Z 0 vdds Yes NA No LVCMOS Analog AF17 NA sys_xtalout 0 AO Z 0 0 vdds NA NA NA LVCMOS Analog AF25 NA sys_clkreq 0 IO 0 See (11) 0 vdds Yes 4 PU/ PD LVCMOS gpio_1 4 IO safe_mode 7 AF26 NA sys_nirq 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_0 4 IO safe_mode 7 AH25 NA sys_nrespwron 0 I Z Z 0 vdds Yes NA No LVCMOS AF24 NA sys_nreswarm 0 IOD 0 H 0 vdds Yes 4 PU/ PD LVCMOS gpio_30 4 IO Open Drain

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] safe_mode 7 AH26 NA sys_boot0 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS dss_data18 3 IO gpio_2 4 IO safe_mode 7 AG26 NA sys_boot1 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS dss_data19 3 IO gpio_3 4 IO safe_mode 7 AE14 NA sys_boot2 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS gpio_4 4 IO safe_mode 7 AF18 NA sys_boot3 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS dss_data20 3 O gpio_5 4 IO safe_mode 7 AF19 NA sys_boot4 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS mmc2_dir_dat2 1 O dss_data21 3 O gpio_6 4 IO safe_mode 7 AE21 NA sys_boot5 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS mmc2_dir_dat3 1 O dss_data22 3 O gpio_7 4 IO safe_mode 7 AF21 NA sys_boot6 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS dss_data23 3 O gpio_8 4 IO safe_mode 7 AF22 NA sys_off_mode 0 O 0 L 7 vdds Yes 4 PU/ PD LVCMOS gpio_9 4 IO safe_mode 7 AG25 NA sys_clkout1 0 O L L 7(14) vdds Yes 4 PU/ PD LVCMOS gpio_10 4 IO safe_mode 7 AE22 NA sys_clkout2 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_186 4 IO safe_mode 7 AA17 NA jtag_ntrst 0 I L L 0 vdds Yes NA PU/ PD LVCMOS AA13 NA jtag_tck 0 I L L 0 vdds Yes NA PU/ PD LVCMOS AA12 NA jtag_rtck 0 O L 0 0 vdds NA 4 PU/ PD LVCMOS AA18 NA jtag_tms_tmsc 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS AA20 NA jtag_tdi 0 I H H 0 vdds Yes NA PU/ PD LVCMOS AA19 NA jtag_tdo 0 O L Z 0 vdds NA 4 PU/ PD LVCMOS AA11 NA jtag_emu0 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS gpio_11 4 IO safe_mode 7 AA10 NA jtag_emu1 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS gpio_31 4 IO safe_mode 7 AF10 NA etk_clk 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcbsp5_ clkx 1 IO mmc3_clk 2 O Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 39 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] hsusb1_stp 3 O gpio_12 4 IO mm1_rxdp 5 IO hw_dbg0 7 O AE10 NA etk_ctl 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mmc3_cmd 2 IO hsusb1_clk 3 O gpio_13 4 IO hw_dbg1 7 O AF11 NA etk_d0 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_simo 1 IO mmc3_dat4 2 IO hsusb1_ data0 3 IO gpio_14 4 IO mm1_rxrcv 5 IO hw_dbg2 7 O AG12 NA etk_d1 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_somi 1 IO hsusb1_ data1 3 IO gpio_15 4 IO mm1_txse0 5 IO hw_dbg3 7 O AH12 NA etk_d2 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_cs0 1 IO hsusb1_ data2 3 IO gpio_16 4 IO mm1_txdat 5 IO hw_dbg4 7 O AE13 NA etk_d3 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_clk 1 IO mmc3_dat3 2 IO hsusb1_ data7 3 IO gpio_17 4 IO hw_dbg5 7 O AE11 NA etk_d4 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mcbsp5_dr 1 I mmc3_dat0 2 IO hsusb1_ data4 3 IO gpio_18 4 IO hw_dbg6 7 O AH9 NA etk_d5 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mcbsp5_fsx 1 IO mmc3_dat1 2 IO hsusb1_ data5 3 IO gpio_19 4 IO hw_dbg7 7 O AF13 NA etk_d6 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mcbsp5_dx 1 O mmc3_dat2 2 IO hsusb1_ data6 3 IO gpio_20 4 IO hw_dbg8 7 O AH14 NA etk_d7 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_cs1 1 O

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] mmc3_dat7 2 IO hsusb1_ data3 3 IO gpio_21 4 IO mm1_txen_n 5 IO hw_dbg9 7 O AF9 NA etk_d8 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mmc3_dat6 2 IO hsusb1_dir 3 I gpio_22 4 IO hw_dbg10 7 O AG9 NA etk_d9 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mmc3_dat5 2 IO hsusb1_nxt 3 I gpio_23 4 IO mm1_rxdm 5 IO hw_dbg11 7 O AE7 NA etk_d10 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS uart1_rx 2 I hsusb2_clk 3 O gpio_24 4 IO hw_dbg12 7 O AF7 NA etk_d11 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS hsusb2_stp 3 O gpio_25 4 IO mm2_rxdp 5 IO hw_dbg13 7 O AG7 NA etk_d12 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS hsusb2_dir 3 I gpio_26 4 IO hw_dbg14 7 O AH7 NA etk_d13 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS hsusb2_nxt 3 I gpio_27 4 IO mm2_rxdm 5 IO hw_dbg15 7 O AG8 NA etk_d14 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS hsusb2_ data0 3 IO gpio_28 4 IO mm2_rxrcv 5 IO hw_dbg16 7 O AH8 NA etk_d15 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS hsusb2_ data1 3 IO gpio_29 4 IO mm2_txse0 5 IO hw_dbg17 7 O AH21 NA vss 0 GND - - - - - - - - AG16 NA vss 0 GND - - - - - - - - M28 NA vss 0 GND - - - - - - - - AH20 NA cap_vddu_array 0 PWR - - - - - - - - AG20 NA vdds 0 PWR - - - - - - - - AG21 NA vdds 0 PWR - - - - - - - - H28 NA vdds 0 PWR - - - - - - - - P25 NA vdds_x 0 PWR - - - - - - - - Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 41 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] AE9, AE18, NA vdd_core 0 PWR - - - - - - - - AE19, AE24, AC4, Y16, Y18,Y19, Y20,W18, W20, V20, U19, U20, T19,P20, N19, N20, M19, M25, L25,K18, K20,J4, J18,J19, J20,H4, E25,D8, D9, D15, D22, D23 Y9,Y10, NA vdd_mpu_iva 0 PWR - - - - - - - - Y11,Y14, Y15,W9, W11, W12, W15, U10, T9,T10,R9, R10, N10, M9, M10, L9,L10, K11,K14, K13,J9, J10,J11, J14,J15 AH6, U1, AC5, P1, vdds_mem 0 PWR - - - - - - - - R4, J1,J2, H1, F23,E1, G28, F1,F2, C23, A4,A7, D16, C16, A10,A15, C28, B5,B8, A18 B12,B18, B22,A5,A8, A12,A18, A22 AG27, AF8, NA vdds 0 PWR - - - - - - - - AF16, AF23, AE8, AE16, AE23, AD3, AD4, W4, F25,F26 W16 NA vdds_sram 0 PWR K15 NA vdda_dplls_dll 0 PWR - - - - - - - - AA16 NA vdda_dpll_per 0 PWR - - - - - - - - AA14 NA vdda_wkup_ 0 PWR - - - - - - - - bg_bb K25 NA vdds_mmc1 0 PWR - - - - - - - - V25 NA vdda_dac 0 PWR - - - - - - - - Y26 NA vssa_dac 0 GND - - - - - - - -

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] AG2, AG3, B4,B7,B10, vss 0 GND - - - - - - - - AG6, AF12, B15,B18, AF20, AE12, C22, E2, AE20, F22,H2, P2, AC25, AB5, AB14, AC26, Y12, AB20 Y13,Y25, W3, W10, W13, W14, W17, W19, W25, V9, V10,V19, U2, U9, T20, R19, R20, R26, P3,P4, P9,P10, P19,N9, M20, L19, L20,L26, K9,K10, K12,K16, K17,K19, J3,J12,J13, J16,J17, G27, E3,E4, D7, D10, D13, D19, D21, C7, C10, C13, C19, C22, B2,B27,A3, A26 AA15 NA cap_vddu_wkup_ 0 PWR - - - - - - - - logic AH10, A12,AA1, Feed-Through - - - - - - - - - - AH11, AA23, AB11, Pins(9) AH13, AB9, AC11, AH15, AC13, AH16, AC14, AC8, AG11, AC9, H23, AG13, AF1, K1,L1,U1, AF28, AE28, Y23,A1,A2, AA1, N1, A22,A23, M1, J28, AB1, AB23, A15,M2, AC1, AC2, N2, A1,A2, AC22, A27,A28, AC23, B1, AG1, AG28, B23,AA2, AH1, AH2, U2, AA22, AH27, AB8, AB13, AH28, B1, B12,H22, B28,AA2, K2,K22,L2 AF2, AF27, AG10, AG15, B15, J27,M26 Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 43 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-1.BallCharacteristics(CBP Pkg.)(3) (continued) BALLBALL BALL RESET BUFFER PULLUPBALL TOP RESET IO CELLBOTTOM PIN NAME [2] MODE [3] TYPE [4] RESET REL. MODE POWER [8] HYS [9] STRENGTH /DOWN[1] REL. [12][1] STATE [5] [7] (mA) [10] TYPE [11]STATE [6] G1, A13, AB2, AB22, No Connect(2) - - A14,A16, B2,B22 A17,B14, B16,B17, C14, C15, C17, D17, D18, H9, H10, H11, H12, H13, H14, H15, H16, H17, A4,A6,A7, A9,A10, A11,A19, A20,A21, B3,B4,B6, B7,B9,B10, B11,B13, B19,B20, B21,C1,C2, C3, C4,C5, C6, C8,C9, C11, C12, C18, C20, C21, D1, D2, D3, D4, D5,D6,D11, D12,D14, D20, E1,E2, AA26, AE27 Y17 NA sys_xtalgnd 0 GND U4 NA cap_vdd_bb_ 0 PWR mpu_iva V4 NA cap_vdd_sram 0 PWR _mpu_iva L21 NA cap_vdd_sram_core 0 PWR (1) The usage ofthisGPIO isstronglyrestricted.Formore information,see theGPIO chapteroftheAM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). (2) Pinslabeledas "No connect"must be leftunconnected.Any connectionstothesepinsmay resultinunpredictablebehavior. (3) NA inthistablestandsfor"NotApplicable". (4) The drivestrengthisfixedregardlessoftheload.The driverisdesignedtodrive75-ohm forvideoapplications. (5) PU = [50to100 kΩ]perdefaultor[10to50 kΩ]accordingtotheselectedmode. Fora fulldescriptionofthepull-updrivestrengthprogramming,see thePRG_SDMMC_PUSTRENGTH configurationregisterbitfieldin theSystem ControlModule chapteroftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). PD: 30 to150 kΩ. (6) The pullupand pulldowncan be eitherthestandardLVCMOS 100-μA drivestrengthortheI2C pullupand pulldowndescribedbelow: Nominalresistance= 1.66kΩ inhigh-speedmode witha loadrangeof5 pF to12 pF,4.5kΩ instandard/fastmode witha loadrange of5 pF to15 pF. (7) The defaultbufferconfigurationisHigh-SpeedI2C point-to-pointmode usinginternalpullup.Fora fulldescriptionofthepulldrive strengthprogramming,see prg_i2c1_pullupresx,prg_i2c1_lb1lb0,and prg_sr_pullupresx,prg_sr_lbbitsoftheCONTROL_PROG_IO1, CONTROL_PROG_IO_WKUP1 controlmodules intheSystem ControlModule /SCM Programming Model /FeatureSettingssection and theSystem ControlModule chapteroftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 )tomodifytheIO settingsifrequiredby thetargetedinterfaceapplication. (8) The defaultbufferconfigurationisstandardLVCMOS mode (non-I2C).Fora fulldescriptionofthepulldrivestrengthprogramming,see PADCONFS bitsofCONTROL_PADCONF_X controlmodules (standardLVCMOS mode),orprg_i2c2_pullupresx,prg_i2c2_lb1lb0,and prg_i2c3_pullupresx,prg_i2c3_lb1lb0bitsoftheCONTROL_PROG_IO2, CONTROL_PROG_IO3 controlmodules (I2Cmode) inthe System ControlModule chapteroftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 )to modifytheIO settingsifrequiredby thetargetedinterfaceapplication. (9) These signalsarefeed-throughballs.Formore information,see Table2-28. (10)Inbuffermode, thedrivestrengthisfixedregardlessoftheload.The driverisdesignedtodrive75Ω forvideoapplications.Inbypass mode, thedrivestrengthis0.47mA. (11)Dependingon thesys_clkreqdirectionthecorrespondingresetreleasedstatevaluecan be: – Z ifsys_clkreqisused as input – 1 ifsys_clkreqisused as output Fora fulldescriptionofthesys_clkreqcontrol,see Power,Reset,and ClockManagement chapteroftheAM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). (12)The drivestrengthoftheseIOs issetaccordingtotheprogrammableloadrange:2 pF to4 pF perdefaultor4 pF to12 pF.Fora full descriptionofthedrivestrengthprogramming,see theSystem ControlModule chapteroftheAM/DM37x MultimediaDeviceTechnical

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 ReferenceManual (literaturenumber SPRUGN4 ). (13)Inthesafe_mode_out1,thebufferisconfiguredtodrive1. (14)Mux0 ifsys_boot6ispulleddown (clockmaster). (15)IfMMC1 functionalsignalsareenabled,vdds_mmc1 forMMC1 must be suppliedby a dedicatedpower source. IfMMC1 functionalsignalsaredisabled,othermultiplexedCMOS signalsoftheinterfacecan be enabled.The interfacecan be supplied by thesame power sourceas vdds.The vdds power sourcesuppliesthevdds_mmc1 ball. IfneitherMMC1 functionalballsorCMOS signalsareenabled,theinterfaceballsareleftunconnectedwithitsassociatedpower supply (vdda/vssa)grounded. ForthecorrespondingsettingofthePBIASLITEPWRDNZ0 bit,see theSystem ControlModule /SCM Programming Model / Extended-DrainI/Osand PBIAS CellsProgramming Guide sectionoftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-2.BallCharacteristics(CBC Pkg.)(5) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] AE16 NA cam_d0 0 I L L 7 vdda Yes NA PU/ PD LVCMOS gpio_99 4 I safe_mode 7 - AE15 NA cam_d1 0 I L L 7 vdda Yes NA PU/ PD LVCMOS gpio_100 4 I safe_mode 7 - AD17 NA gpio_112 4 I L L 7 vdda Yes NA PU/ PD LVCMOS safe_mode 7 - AE18 NA gpio_114 4 I L L 7 vdda Yes NA PU/ PD LVCMOS safe_mode 7 - AD16 NA gpio_113 4 I L L 7 vdda Yes NA PU/ PD LVCMOS safe_mode 7 - gpio_115 4 I AE17 NA safe_mode 7 - L L 7 vdda Yes NA PU/ PD LVCMOS NA G20 sdrc_a0 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA K20 sdrc_a1 0 O 0 0 0 vdds NA 4(1) PU/ PD LVCMOS NA J20 sdrc_a2 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA J21 sdrc_a3 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA U21 sdrc_a4 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA R20 sdrc_a5 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA M21 sdrc_a6 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA M20 sdrc_a7 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA N20 sdrc_a8 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA K21 sdrc_a9 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA Y16 sdrc_a10 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA N21 sdrc_a11 0 O 0 0 0 vdds NA 4(1) PU/ PD LVCMOS NA R21 sdrc_a12 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA AA15 sdrc_a13 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA Y12 sdrc_a14 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA AA18 sdrc_ba0 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA V20 sdrc_ba1 0 O 0 0 0 vdds NA 4(1) PU/ PD LVCMOS NA Y15 sdrc_cke0 0 O H 1 7 vdds NA 4 (1) PU/ PD LVCMOS safe_mode_out1(6) 7 NA Y13 sdrc_cke1 0 O H 1 7 vdds NA 4 (1) PU/ PD LVCMOS safe_mode_out1(6) 7 NA A12 sdrc_clk 0 IO L 0 0 vdds Yes 4 (1) PU/ PD LVCMOS NA D1 sdrc_d0 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA G1 sdrc_d1 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA G2 sdrc_d2 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA E1 sdrc_d3 0 IO L Z 0 vdds Yes 4(1) PU/ PD LVCMOS NA D2 sdrc_d4 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA E2 sdrc_d5 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA B3 sdrc_d6 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 45 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] NA B4 sdrc_d7 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA A10 sdrc_d8 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA B11 sdrc_d9 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA A11 sdrc_d10 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA B12 sdrc_d11 0 IO L Z 0 vdds Yes 4(1) PU/ PD LVCMOS NA A16 sdrc_d12 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA A17 sdrc_d13 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA B17 sdrc_d14 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA B18 sdrc_d15 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA B7 sdrc_d16 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA A5 sdrc_d17 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA B6 sdrc_d18 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA A6 sdrc_d19 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA A8 sdrc_d20 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA B9 sdrc_d21 0 IO L Z 0 vdds Yes 4(1) PU/ PD LVCMOS NA A9 sdrc_d22 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA B10 sdrc_d23 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA C21 sdrc_d24 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA D20 sdrc_d25 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA B19 sdrc_d26 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA C20 sdrc_d27 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA D21 sdrc_d28 0 IO L Z 0 vdds Yes 4(1) PU/ PD LVCMOS NA E20 sdrc_d29 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA E21 sdrc_d30 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA G21 sdrc_d31 0 IO L Z 0 vdds Yes 4(1) PU/ PD LVCMOS NA H1 sdrc_dm0 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA A14 sdrc_dm1 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA A4 sdrc_dm2 0 O 0 0 0 vdds NA 4(1) PU/ PD LVCMOS NA A18 sdrc_dm3 0 O 0 0 0 vdds NA 4 (1) PU/ PD LVCMOS NA C2 sdrc_dqs0 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA B15 sdrc_dqs1 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA B8 sdrc_dqs2 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA A19 sdrc_dqs3 0 IO L Z 0 vdds Yes 4 (1) PU/ PD LVCMOS NA U20 sdrc_ncas 0 O 1 1 0 vdds NA 4 (1) PU/ PD LVCMOS NA B13 sdrc_nclk 0 O 1 1 0 vdds NA 4 (1) PU/ PD LVCMOS NA T21 sdrc_ncs0 0 O 1 1 0 vdds NA 4 (1) PU/ PD LVCMOS NA T20 sdrc_ncs1 0 O 1 1 0 vdds NA 4 (1) PU/ PD LVCMOS NA V21 sdrc_nras 0 O 1 1 0 vdds NA 4 (1) PU/ PD LVCMOS NA Y18 sdrc_nwe 0 O 1 1 0 vdds NA 4 (1) PU/ PD LVCMOS AE21 NA dss_data0 0 IO L L 7 vdda Yes 8 PU/ PD LVCMOS uart1_cts 2 I NA gpio_70 4 IO 8 safe_mode 7 - 8 AE22 NA dss_data1 0 IO L L 7 vdda Yes 8 PU/ PD LVCMOS uart1_rts 2 O 8 gpio_71 4 IO 8 safe_mode 7 - 8 AE23 NA dss_data2 0 IO L L 7 vdda Yes 8 PU/ PD LVCMOS gpio_72 4 IO 8 safe_mode 7 - 8 AE24 NA dss_data3 0 IO L L 7 vdda Yes 8 PU/ PD LVCMOS gpio_73 4 IO 8 safe_mode 7 - 8 AD23 NA dss_data4 0 IO L L 7 vdda Yes 8 PU/ PD LVCMOS uart3_rx_irrx 2 I NA

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] gpio_74 4 IO 8 safe_mode 7 - 8 AD24 NA dss_data5 0 IO L L 7 vdda Yes 8 PU/ PD LVCMOS uart3_tx_irtx 2 O 8 gpio_75 4 IO 8 safe_mode 7 - 8 AC26 NA dss_data10 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_80 4 IO safe_mode 7 - AD26 NA dss_data11 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_81 4 IO safe_mode 7 - AA25 NA dss_data12 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_82 4 IO safe_mode 7 - Y25 NA dss_data13 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_83 4 IO safe_mode 7 - AA26 NA dss_data14 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_84 4 IO safe_mode 7 - AB26 NA dss_data15 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_85 4 IO safe_mode 7 - F25 NA dss_data20 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_somi 2 IO dss_data2 3 IO gpio_90 4 IO safe_mode 7 - AC25 NA dss_data22 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_cs1 2 O dss_data4 3 IO gpio_92 4 IO safe_mode 7 - AB25 NA dss_data23 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS dss_data5 3 IO gpio_93 4 IO safe_mode 7 - G25 NA dss_pclk 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_66 4 IO hw_dbg12 5 O safe_mode 7 - J2 NA gpmc_a1 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_34 4 IO safe_mode 7 - H1 NA gpmc_a2 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_35 4 IO safe_mode 7 - H2 NA gpmc_a3 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_36 4 IO safe_mode 7 - G2 NA gpmc_a4 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_37 4 IO safe_mode 7 - F1 NA gpmc_a5 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 47 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] gpio_38 4 IO safe_mode 7 - F2 NA gpmc_a6 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_39 4 IO safe_mode 7 - E1 NA gpmc_a7 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_40 4 IO safe_mode 7 - E2 NA gpmc_a8 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_41 4 IO safe_mode 7 - D1 NA gpmc_a9 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS sys_ndmareq2 1 I gpio_42 4 IO safe_mode 7 - D2 NA gpmc_a10 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS sys_ndmareq3 1 I gpio_43 4 IO safe_mode 7 - N1 L1 gpmc_clk 0 O L 0 0 vdds Yes 8 PU/ PD LVCMOS gpio_59 4 IO safe_mode 7 - AA2 U2 gpmc_d0 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AA1 U1 gpmc_d1 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AC2 V2 gpmc_d2 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AC1 V1 gpmc_d3 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AE5 AA3 gpmc_d4 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AD6 AA4 gpmc_d5 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AD5 Y3 gpmc_d6 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AC5 Y4 gpmc_d7 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS V1 R1 gpmc_d8 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_44 4 IO safe_mode 7 - Y1 T1 gpmc_d9 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_45 4 IO safe_mode 7 - T1 N1 gpmc_d10 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_46 4 IO safe_mode 7 - U2 P2 gpmc_d11 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_47 4 IO safe_mode 7 - U1 P1 gpmc_d12 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_48 4 IO safe_mode 7 - P1 M1 gpmc_d13 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_49 4 IO safe_mode 7 - L2 J2 gpmc_d14 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_50 4 IO safe_mode 7 - M2 K2 gpmc_d15 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS gpio_51 4 IO safe_mode 7 - AD10 AA9 gpmc_nadv_ale 0 O 0 0 0 vdds NA 8 NA LVCMOS

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] K2 NA gpmc_nbe0_cle 0 O L 0 0 vdds Yes 8 PU/ PD LVCMOS gpio_60 4 IO safe_mode 7 - J1 NA gpmc_nbe1 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_61 4 IO safe_mode 7 - AD8 AA8 gpmc_ncs0 0 O 1 1 0 vdds NA 8 NA LVCMOS AD1 W1 gpmc_ncs1 0 O H 1 0 vdds Yes 8 PU/ PD LVCMOS gpio_52 4 IO safe_mode 7 - A3 NA gpmc_ncs2 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_53 4 IO safe_mode 7 - B6 NA gpmc_ncs3 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS sys_ndmareq0 1 I gpio_54 4 IO safe_mode 7 - B4 NA gpmc_ncs4 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS sys_ndmareq1 1 I mcbsp4_clkx 2 IO gpt_9_pwm_evt 3 IO gpio_55 4 IO safe_mode 7 - C4 NA gpmc_ncs5 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS sys_ndmareq2 1 I mcbsp4_dr 2 I gpt_10_pwm_evt 3 IO gpio_56 4 IO safe_mode 7 - B5 NA gpmc_ncs6 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS sys_ndmareq3 1 I mcbsp4_dx 2 IO gpt_11_pwm_evt 3 IO gpio_57 4 IO safe_mode 7 - C5 NA gpmc_ncs7 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpmc_io_dir 1 O mcbsp4_fsx 2 IO gpt_8_pwm_evt 3 IO gpio_58 4 IO safe_mode 7 - N2 L2 gpmc_noe 0 O 1 1 0 vdds NA 8 NA LVCMOS M1 K1 gpmc_nwe 0 O 1 1 0 vdds NA 8 NA LVCMOS AC6 Y5 gpmc_nwp 0 O L 0 0 vdds Yes 8 PU/ PD LVCMOS gpio_62 4 IO safe_mode 7 - AC11 Y10 gpmc_wait0 0 I H H 0 vdds Yes NA PU/ PD LVCMOS AC8 Y8 gpmc_wait1 0 I H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_63 4 IO safe_mode 7 - B3 NA gpmc_wait2 0 I H H 7 vdds Yes 8 PU/ PD LVCMOS uart4_tx 2 O gpio_64 4 IO safe_mode 7 - C6 NA gpmc_wait3 0 I H H 7 vdds Yes 8 PU/ PD LVCMOS Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 49 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] sys_ndmareq1 1 I uart4_rx 2 I gpio_65 4 IO safe_mode 7 - W19 NA hsusb0_clk 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_120 4 IO safe_mode 7 - V20 NA hsusb0_data0 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart3_tx_irtx 2 O gpio_125 4 IO uart2_tx 5 O safe_mode 7 - Y20 NA hsusb0_data1 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart3_rx_irrx 2 I gpio_130 4 IO uart2_rx 5 I safe_mode 7 - V18 NA hsusb0_data2 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart3_rts_sd 2 O gpio_131 4 IO uart2_rts 5 O safe_mode 7 - W20 NA hsusb0_data3 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart3_cts_rctx 2 IO gpio_169 4 IO uart2_cts 5 I safe_mode 7 - W17 NA hsusb0_data4 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_188 4 IO safe_mode 7 - Y18 NA hsusb0_data5 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_189 4 IO safe_mode 7 - Y19 NA hsusb0_data6 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_190 4 IO safe_mode 7 - Y17 NA hsusb0_data7 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_191 4 IO safe_mode 7 - V19 NA hsusb0_dir 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_122 4 IO safe_mode 7 - W18 NA hsusb0_nxt 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_124 4 IO safe_mode 7 - U20 NA hsusb0_stp 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_121 4 IO safe_mode 7 - U15 NA jtag_ntrst 0 I L L 0 vdds Yes NA PU/ PD LVCMOS W13 NA jtag_rtck 0 O L 0 0 vdds NA 4 PU/ PD LVCMOS V14 NA jtag_tck 0 I L L 0 vdds Yes NA PU/ PD LVCMOS U16 NA jtag_tdi 0 I H H 0 vdds Yes NA PU/ PD LVCMOS Y13 NA jtag_tdo 0 O L Z 0 vdds NA 4 PU/ PD LVCMOS V15 NA jtag_tms_tmsc 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] N19 NA mmc1_clk 0 O L L 7 vdds_mmc1 ( Yes 1 PU/ PD (3) LVCMOS 13) gpio_120(8) 4 IO safe_mode 7 - L18 NA mmc1_cmd 0 IO L L 7 vdds_mmc1 ( Yes 1 PU/ PD (3) LVCMOS 13) gpio_121(8) 4 IO safe_mode 7 - M19 NA mmc1_dat0 0 IO L L 7 vdds_mmc1 ( Yes 1 PU/ PD (3) LVCMOS 13) gpio_122(8) 4 IO safe_mode 7 - M18 NA mmc1_dat1 0 IO L L 7 vdds_mmc1 ( Yes 1 PU/ PD (3) LVCMOS 13) gpio_123(8) 4 IO safe_mode 7 - K18 NA mmc1_dat2 0 IO L L 7 vdds_mmc1 ( Yes 1 PU/ PD (3) LVCMOS 13) gpio_124(8) 4 IO safe_mode 7 - N20 NA mmc1_dat3 0 IO L L 7 vdds_mmc1 ( Yes 1 PU/ PD (3) LVCMOS 13) gpio_125(8) 4 IO safe_mode 7 - M20 NA gpio_126(8) 4 IO L L 7 vdds_x Yes 1 PU/PD (3) LVCMOS safe_mode 7 - P17 NA gpio_127(8) 4 IO L L 7 vdds_x Yes 1 PU/PD (3) LVCMOS safe_mode 7 - P18 NA gpio_128 4 IO L L 7 vdds Yes 4 PU/PD LVCMOS safe_mode 7 - P19 NA gpio_129(8) 4 IO L L 7 vdds_x Yes 1 PU/PD (3) LVCMOS safe_mode 7 - J25 NA i2c1_scl 0 OD H H 0 vdds NA 3 PU/ PD (9)(10) Open Drain J24 NA i2c1_sda 0 IOD H H 0 vdds Yes 3 PU/ PD (9)(10) LVCMOS Open Drain C2 NA i2c2_scl 0 OD H H 7 vdds Yes 3 PU/ PD (9)(11) LVCMOS Open Drain gpio_168 4 IO 4 safe_mode 7 - 4 C1 NA i2c2_sda 0 IOD H H 7 vdds Yes 3 PU/ PD (9)(11) LVCMOS Open Drain gpio_183 4 IO 4 safe_mode 7 - 4 AB4 NA i2c3_scl 0 OD H H 7 vdds Yes 3 PU/ PD (9)(11) LVCMOS Open Drain gpio_184 4 IO 4 safe_mode 7 - 4 AC4 NA i2c3_sda 0 IOD H H 7 vdds Yes 3 PU/ PD (9)(11) LVCMOS Open Drain gpio_185 4 IO 4 safe_mode 7 - 4 U19 NA mcbsp1_clkr 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi4_clk 1 IO gpio_156 4 IO safe_mode 7 - T17 NA mcbsp1_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mcbsp3_clkx 2 IO gpio_162 4 IO safe_mode 7 - Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 51 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] T20 NA mcbsp1_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi4_somi 1 IO mcbsp3_dr 2 I gpio_159 4 IO safe_mode 7 - U17 NA mcbsp1_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi4_simo 1 IO mcbsp3_dx 2 IO gpio_158 4 IO safe_mode 7 - V17 NA mcbsp1_fsr 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS cam_global_reset 2 IO gpio_157 4 IO safe_mode 7 - P20 NA mcbsp1_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi4_cs0 1 IO mcbsp3_fsx 2 IO gpio_161 4 IO safe_mode 7 - R18 NA mcbsp2_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_117 4 IO safe_mode 7 - T18 NA mcbsp2_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_118 4 IO safe_mode 7 - R19 NA mcbsp2_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_119 4 IO safe_mode 7 - U18 NA mcbsp2_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_116 4 IO safe_mode 7 - P9 NA mcspi1_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dat4 1 IO gpio_171 4 IO safe_mode 7 - R7 NA mcspi1_cs0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dat7 1 IO gpio_174 4 IO safe_mode 7 - R9 NA mcspi1_cs2 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS mmc3_clk 3 O gpio_176 4 IO safe_mode 7 - P8 NA mcspi1_simo 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dat5 1 IO gpio_172 4 IO safe_mode 7 - P7 NA mcspi1_somi 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dat6 1 IO gpio_173 4 IO safe_mode 7 - W7 NA mcspi2_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS hsusb2_data7 3 IO gpio_178 4 IO safe_mode 7 -

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] V8 NA mcspi2_cs0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS gpt_11_pwm_evt 1 IO hsusb2_data6 3 IO gpio_181 4 IO safe_mode 7 - W8 NA mcspi2_simo 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpt_9_pwm_evt 1 IO hsusb2_data4 3 IO gpio_179 4 IO safe_mode 7 - U8 NA mcspi2_somi 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpt_10_pwm_evt 1 IO hsusb2_data5 3 IO gpio_180 4 IO safe_mode 7 - W10 NA mmc2_clk 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_clk 1 IO gpio_130 4 IO safe_mode 7 - R10 NA mmc2_cmd 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_simo 1 IO gpio_131 4 IO safe_mode 7 - T10 NA mmc2_dat0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_somi 1 IO gpio_132 4 IO safe_mode 7 - T9 NA mmc2_dat1 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_133 4 IO safe_mode 7 - U10 NA mmc2_dat2 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_cs1 1 O gpio_134 4 IO safe_mode 7 - U9 NA mmc2_dat3 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_cs0 1 IO gpio_135 4 IO safe_mode 7 - V10 NA mmc2_dat4 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dir_dat0 1 O mmc3_dat0 3 IO gpio_136 4 IO safe_mode 7 - R2 NA uart1_rts 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_149 4 IO safe_mode 7 - H3 NA uart1_rx 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS mcbsp1_clkr 2 IO mcspi4_clk 3 IO gpio_151 4 IO safe_mode 7 - L4 NA uart1_tx 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_148 4 IO safe_mode 7 - Y24 NA uart2_cts 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 53 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] mcbsp3_dx 1 IO gpt_9_pwm_evt 2 IO gpio_144 4 IO safe_mode 7 - AA24 NA uart2_rts 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS mcbsp3_dr 1 I gpt_10_pwm_evt 2 IO gpio_145 4 IO safe_mode 7 - AD21 NA uart2_rx 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS mcbsp3_fsx 1 IO gpt_8_pwm_evt 2 IO gpio_147 4 IO safe_mode 7 - AD22 NA uart2_tx 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS mcbsp3_clkx 1 IO gpt_11_pwm_evt 2 IO gpio_146 4 IO safe_mode 7 - F23 NA uart3_cts_rctx 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_163 4 IO safe_mode 7 - F24 NA uart3_rts_sd 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_164 4 IO safe_mode 7 - H24 NA uart3_rx_irrx 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_165 4 IO safe_mode 7 - G24 NA uart3_tx_irtx 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_166 4 IO safe_mode 7 - J23 NA hdq_sio 0 IOD H H 7 vdds Yes 4 PU/ PD LVCMOS Open Drain sys_altclk 1 I i2c2_sccbe 2 OD i2c3_sccbe 3 OD gpio_170 4 IO safe_mode 7 - AD15 NA i2c4_scl 0 OD H H 0 vdds Yes 3 PU/ PD (9)(10) LVCMOS Open Drain sys_nvmode1 1 O 4 safe_mode 7 - 4 W16 NA i2c4_sda 0 IOD H H 0 vdds Yes 3 PU/ PD (9)(10) LVCMOS Open Drain sys_nvmode2 1 O 4 safe_mode 7 - 4 F3 NA sys_boot0 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS dss_data18 3 IO gpio_2 4 IO safe_mode 7 - D3 NA sys_boot1 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS dss_data19 3 IO gpio_3 4 IO safe_mode 7 - C3 NA sys_boot2 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS gpio_4 4 IO

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] safe_mode 7 - E3 NA sys_boot3 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS dss_data20 3 O gpio_5 4 IO safe_mode 7 - E4 NA sys_boot4 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS mmc2_dir_dat2 1 O dss_data21 3 O gpio_6 4 IO safe_mode 7 - G3 NA sys_boot5 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS mmc2_dir_dat3 1 O dss_data22 3 O gpio_7 4 IO safe_mode 7 - D4 NA sys_boot6 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS dss_data23 3 O gpio_8 4 IO safe_mode 7 - AE14 NA sys_clkout1 0 O L L 7(12) vdds Yes 4 PU/ PD LVCMOS gpio_10 4 IO safe_mode 7 - W11 NA sys_clkout2 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_186 4 IO safe_mode 7 - W15 NA sys_clkreq 0 IO 0 see (7) 0 vdds Yes 4 PU/ PD LVCMOS gpio_1 4 IO safe_mode 7 - V16 NA sys_nirq 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_0 4 IO safe_mode 7 - V13 NA sys_nrespwron 0 I Z Z 0 vdds Yes NA No LVCMOS AD7 AA5 sys_nreswarm 0 IOD 0 H 0 vdds Yes 4 PU/ PD LVCMOS gpio_30 4 IO Open Drain safe_mode 7 - V12 NA sys_off_mode 0 O 0 L 7 vdds Yes 4 PU/ PD LVCMOS gpio_9 4 IO safe_mode 7 - AF19 NA sys_xtalin 0 AI Z Z 0 vdds Yes NA NA LVCMOS Analog AF20 NA sys_xtalout 0 AO Z 0 0 vdds NA NA NA Analog W26 NA cvideo1_out 0 AO 0 0 0 vdda_dac NA NA NA 10-bitDAC V26 NA cvideo2_out 0 AO 0 0 0 vdda_dac NA NA NA 10-bitDAC W25 NA cvideo1_vfb 0 AO 0 NA 0 vdda_dac NA NA NA 10-bitDAC U24 NA cvideo2_vfb 0 AO 0 NA 0 vdda_dac NA NA NA 10-bitDAC V23 NA cvideo1_rset 0 AIO Z NA 0 vdda_dac No NA NA 10-bitDAC AE20 NA sys_32k 0 I Z Z 0 vdds Yes NA PU/ PD LVCMOS A24 NA cam_d2 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_101 4 IO hw_dbg4 5 O safe_mode 7 - B24 NA cam_d3 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_102 4 IO hw_dbg5 5 O safe_mode 7 - Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 55 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] D24 NA cam_d4 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_103 4 IO hw_dbg6 5 O safe_mode 7 - C24 NA cam_d5 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_104 4 IO hw_dbg7 5 O safe_mode 7 - D25 NA cam_d10 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_109 4 IO hw_dbg8 5 O safe_mode 7 - E26 NA cam_d11 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_110 4 IO hw_dbg9 5 O safe_mode 7 - B23 NA cam_fld 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS cam_global_reset 2 IO gpio_98 4 IO hw_dbg3 5 O safe_mode 7 - C23 NA cam_hs 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_94 4 IO hw_dbg0 5 O safe_mode 7 - C26 NA cam_pclk 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_97 4 IO hw_dbg2 5 O safe_mode 7 - D26 NA cam_strobe 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_126 4 IO hw_dbg11 5 O safe_mode 7 - C25 NA cam_xclka 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_96 4 IO safe_mode 7 - E25 NA cam_xclkb 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_111 4 IO safe_mode 7 - P25 NA cam_d6 0 I L L 7 vdds Yes NA PU/ PD SubLVDS gpio_105 4 I safe_mode 7 - P26 NA cam_d7 0 I L L 7 vdds Yes NA PU/ PD SubLVDS gpio_106 4 I safe_mode 7 - N25 NA cam_d8 0 I L L 7 vdds NA NA PU/ PD SubLVDS gpio_107 4 I safe_mode 7 - N26 NA cam_d9 0 I L L 7 vdds NA NA PU/ PD SubLVDS gpio_108 4 I safe_mode 7 - D23 NA cam_vs 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_95 4 IO hw_dbg1 5 O safe_mode 7 -

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] A23 NA cam_wen 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS cam_shutter 2 O gpio_167 4 IO hw_dbg10 5 O safe_mode 7 - F26 NA dss_acbias 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_69 4 IO safe_mode 7 - G26 NA dss_data6 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart1_tx 2 O gpio_76 4 IO hw_dbg14 5 O safe_mode 7 - H25 NA dss_data7 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart1_rx 2 I gpio_77 4 IO hw_dbg15 5 O safe_mode 7 - H26 NA dss_data8 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart3_rx_irrx 2 I gpio_78 4 IO hw_dbg16 5 O safe_mode 7 - J26 NA dss_data9 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart3_tx_irtx 2 O gpio_79 4 IO hw_dbg17 5 O safe_mode 7 - L25 NA dss_data16 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_86 4 IO safe_mode 7 - L26 NA dss_data17 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_87 4 IO safe_mode 7 - M24 NA dss_data18 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_clk 2 IO dss_data0 3 IO gpio_88 4 IO safe_mode 7 - M26 NA dss_data19 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_simo 2 IO dss_data1 3 IO gpio_89 4 IO safe_mode 7 - N24 NA dss_data21 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_cs0 2 IO dss_data3 3 IO gpio_91 4 IO safe_mode 7 - K24 NA dss_hsync 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_67 4 IO hw_dbg13 5 O safe_mode 7 - M25 NA dss_vsync 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_68 4 IO Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 57 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] safe_mode 7 - R8 NA mcspi1_cs1 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS mmc3_cmd 3 IO gpio_175 4 IO safe_mode 7 - T8 NA mcspi1_cs3 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS hsusb2_data2 3 IO gpio_177 4 IO mm2_txdat 5 IO safe_mode 7 - V9 NA mcspi2_cs1 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpt_8_pwm_evt 1 IO hsusb2_data3 3 IO gpio_182 4 IO mm2_txen_n 5 IO safe_mode 7 - T19 NA mcbsp_clks 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS cam_shutter 2 O gpio_160 4 IO uart1_cts 5 I safe_mode 7 - AB2 NA etk_clk 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcbsp5_clkx 1 IO mmc3_clk 2 O hsusb1_stp 3 O gpio_12 4 IO mm1_rxdp 5 IO hw_dbg0 7 O AB3 NA etk_ctl 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mmc3_cmd 2 IO hsusb1_clk 3 O gpio_13 4 IO hw_dbg1 7 O AC3 NA etk_d0 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_simo 1 IO mmc3_dat4 2 IO hsusb1_data0 3 IO gpio_14 4 IO mm1_rxrcv 5 IO hw_dbg2 7 O AD4 NA etk_d1 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_somi 1 IO hsusb1_data1 3 IO gpio_15 4 IO mm1_txse0 5 IO hw_dbg3 7 O AD3 NA etk_d2 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_cs0 1 IO hsusb1_data2 3 IO gpio_16 4 IO mm1_txdat 5 IO hw_dbg4 7 O AA3 NA etk_d3 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_clk 1 IO mmc3_dat3 2 IO

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] hsusb1_data7 3 IO gpio_17 4 IO hw_dbg5 7 O Y3 NA etk_d4 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mcbsp5_dr 1 I mmc3_dat0 2 IO hsusb1_data4 3 IO gpio_18 4 IO hw_dbg6 7 O AB1 NA etk_d5 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mcbsp5_fsx 1 IO mmc3_dat1 2 IO hsusb1_data5 3 IO gpio_19 4 IO hw_dbg7 7 O AE3 NA etk_d6 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mcbsp5_dx 1 O mmc3_dat2 2 IO hsusb1_data6 3 IO gpio_20 4 IO hw_dbg8 7 O AD2 NA etk_d7 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_cs1 1 O mmc3_dat7 2 IO hsusb1_data3 3 IO gpio_21 4 IO mm1_txen_n 5 IO hw_dbg9 7 O AA4 NA etk_d8 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mmc3_dat6 2 IO hsusb1_dir 3 I gpio_22 4 IO hw_dbg10 7 O V2 NA etk_d9 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mmc3_dat5 2 IO hsusb1_nxt 3 I gpio_23 4 IO mm1_rxdm 5 IO hw_dbg11 7 O AE4 NA etk_d10 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS uart1_rx 2 I hsusb2_clk 3 O gpio_24 4 IO hw_dbg12 7 O AF6 NA etk_d11 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS hsusb2_stp 3 O gpio_25 4 IO mm2_rxdp 5 IO hw_dbg13 7 O AE6 NA etk_d12 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS hsusb2_dir 3 I gpio_26 4 IO hw_dbg14 7 O AF7 NA etk_d13 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS hsusb2_nxt 3 I Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 59 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] gpio_27 4 IO mm2_rxdm 5 IO hw_dbg15 7 O AF9 NA etk_d14 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS hsusb2_data0 3 IO gpio_28 4 IO mm2_rxrcv 5 IO hw_dbg16 7 O AE9 NA etk_d15 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS hsusb2_data1 3 IO gpio_29 4 IO mm2_txse0 5 IO hw_dbg17 7 O Y15 NA jtag_emu0 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS gpio_11 4 IO safe_mode 7 - Y14 NA jtag_emu1 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS gpio_31 4 IO safe_mode 7 - U3 NA mcbsp3_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart2_tx 1 O gpio_142 4 IO safe_mode 7 - N3 NA mcbsp3_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS uart2_rts 1 O gpio_141 4 IO safe_mode 7 - P3 NA mcbsp3_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart2_cts 1 I gpio_140 4 IO safe_mode 7 - W3 NA mcbsp3_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart2_rx 1 I gpio_143 4 IO safe_mode 7 - V3 NA mcbsp4_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_152 4 IO mm3_txse0 6 IO safe_mode 7 - U4 NA mcbsp4_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_153 4 IO mm3_rxrcv 6 IO safe_mode 7 - R3 NA mcbsp4_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_154 4 IO mm3_txdat 6 IO safe_mode 7 - T3 NA mcbsp4_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_155 4 IO mm3_txen_n 6 IO safe_mode 7 - M3 NA mmc2_dat5 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dir_dat1 1 O cam_global_reset 2 IO mmc3_dat1 3 IO

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] gpio_137 4 IO mm3_rxdp 6 IO safe_mode 7 - L3 NA mmc2_dat6 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dir_cmd 1 O cam_shutter 2 O mmc3_dat2 3 IO gpio_138 4 IO safe_mode 7 - K3 NA mmc2_dat7 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_clkin 1 I mmc3_dat3 3 IO gpio_139 4 IO mm3_rxdm 6 IO safe_mode 7 - W2 NA uart1_cts 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_150 4 IO safe_mode 7 - AC16 NA vss 0 GND AD18 NA vdds 0 PWR L19 NA vss 0 GND AC19 NA vss 0 GND AD19 NA vdds 0 PWR L20 NA vdds 0 PWR P23 NA vdds_x 0 PWR AE19 NA cap_vddu_array 0 PWR AC21, D15, NA vdd_core 0 PWR - - - - - - - - G11, G18, H20, M7, M17, R20, T7,Y8,Y12 D13, G9, NA vdd_mpu_iva 0 PWR - - - - - - - - G12, H7, K11,L9,M9, M10, N7, N8, P10, U7, U11, U13, V7, V11,W9, Y9,Y11 A18,AC7, A3,A15,B5, vdds 0 PWR - - - - - - - - AC15, F2,F21, AC18, L20,W21 AC24, AD20, AE10, C11, D9, E24, G4, J15, J18,L7, L24,M4, T4, T24,W24, Y4,AB24 U12 NA vdds_sram 0 PWR - - - - - - - - K13 NA vdda_dplls_dll 0 PWR - - - - - - - - U14 NA vdda_dpll_per 0 PWR - - - - - - - - W14 NA vdda_wkup_bg_bb 0 PWR - - - - - - - - N23 NA vdds_mmc1 0 PWR - - - - - - - - V25 NA vdda_dac 0 PWR - - - - - - - - V24 NA vssa_dac 0 GND - - - - - - - - Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 61 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] A6,A8,A13, A7,A13, vss 0 GND - - - - - - - - AB5, AB22, B14,C1, F1, AC10, F20,H2, AD14, H20, L21, AD25, AE7, M2, P20, B2,B25, R2, W20 Y6, C12, D7, Y11,AA7, D10, D12, AA16 D14, D18, D20, E22, G1, G8, G10, G20, G23, H4, K1,K15, K25,L10, L17,L23, N4, N10, N17, R1, R4, R17, T23,U25, W1, W4, W23, Y7, Y10,Y16, Y26 K14 NA cap_vddu_wkup_log 0 PWR - - - - - - - - ic A1,L1,T2, A1,J1,N2, Feed-Through - - - - - - - - - - Y2,AE2, T2,W2, Y2, Pins(4) AF4, AF5, AA6, Y7, AF8, AF10, Y9,AA10, AF12, AF13, AA11, AF14, AF15, AA12, AF17, AF16, AA13, Y14, A20,AF21, AA14, B16, AF18, AF24, Y17,AA17, AF22, A25, Y19,AA19, AE25, AF25, A20,Y20, A26,B26, AA20, A21, K26,U26, B21,H21, AE26, AF26 P21,Y21, AA21

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-2.BallCharacteristics(CBC Pkg.)(5) (continued) BALL BALL TOP PIN NAME [2] MODE [3] TYPE [4] BALL BALL RESET RESET POWER [8] HYS [9] BUFFER PULLUP IO CELL BOTTOM [1] RESET REL. STATE REL. MODE STRENGTH /DOWN [12] [1] STATE [5] [6] [7] (mA) [10] TYPE [11] A2,AF1, A2,AA1, No Connect(2) - - - - - - - - - - B1,D5,K23, AA2,B1,B2, A5,A7,A9, B20,Y1 A10,A11, A12,A14, A15,A16, A17,A19, A21,A22, AA23, AB23, AC9, AC12, AC13, AC14, AC17, AC20, AC22, AC23, AD9, AD11, AD12, AD13, AE1, AE8, AE11, AE12, AE13, AF2, AF3, AF11, B7,B8,B9, B10,B11, B12,B13, B14,B15, B16,B17, B18,B19, B20,B21, B22,C7, C8, C9, C10, C13, C14, C15, C16, C17 C18, C19, C20, C21, C22, D8, D11, D16, D17, D19, D21, D22, E23,F4,G7, G13, G14, G15, G16, G17, G19, H8, H9, H10, H11, H12, H13, H14, H15, H16, H17, H18, H19, H23, J3,J4, J7,J8,J9, J10,J11, J12,J13, J14,J16, J17,J19, J20,K4,K7, K8,K9,K10, K12,K16, K17,K19, L8,M8, M23, N18, P2,P4,P24, R23, R24, R25, R26, T25,T26, U23, V4, W12, Y23 AF23 NA sys_xtalgnd 0 GND A4 NA gpmc_a11 0 O L L 7 vdds Yes 8 PU/PD LVCMOS safe_mode 7 D6 NA cap_vdd_bb_mpu_i 0 PWR va N9 NA cap_vdd_sram_mpu 0 PWR _iva K20 NA cap_vdd_sram_core 0 PWR Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 63 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) The drivestrengthoftheseIOs issetaccordingtotheprogrammableloadrange:2 pF to4 pF perdefaultor4 pF to12 pF.Fora full descriptionofthedrivestrengthprogramming,see theSystem ControlModule chapteroftheAM/DM37x MultimediaDeviceTechnical ReferenceManual (literaturenumber SPRUGN4 ). (2) Pinslabeledas "No connect"must be leftunconnected.Any connectionstothesepinsmay resultinunpredictablebehavior. (3) PU = [50to100 kΩ]perdefaultor[10to50 kΩ]accordingtotheselectedmode. Fora fulldescriptionofthepull-updrivestrengthprogramming,see thePRG_SDMMC_PUSTRENGTH configurationregisterbitfieldin theSystem ControlModule chapteroftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). PD: 30 to150 kΩ. (4) These signalsarefeed-throughballs.Formore information,see Table2-27. (5) NA inthistablestandsfor"NotApplicable". (6) Inthesafe_mode_out1,thebufferisconfiguredtodrive1. (7) Dependingon thesys_clkreqdirectionthecorrespondingresetreleasedstatevaluecan be: – Z ifsys_clkreqisused as input – 1 ifsys_clkreqisused as output Fora fulldescriptionofthesys_clkreqcontrol,see Power,Reset,and ClockManagement chapteroftheAM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). (8) The usage ofthisGPIO isstronglyrestricted.Formore information,see theGeneral-PurposeInterfacechapteroftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (9) The pullupand pulldowncan be eitherthestandardLVCMOS 100-μA drivestrengthortheI2C pullupand pulldowndescribedas follows:Nominalresistance= 1.66kΩ inhigh-speedmode witha loadrangeof5 pF to12 pF,4.5kΩ instandard/fastmode witha load rangeof5 pF to15 pF. (10)The defaultbufferconfigurationisHigh-SpeedI2C point-to-pointmode usinginternalpullup.Fora fulldescriptionofthepulldrive strengthprogramming,see prg_i2c1_pullupresx,prg_i2c1_lb1lb0,and prg_sr_pullupresx,prg_sr_lbbitsoftheCONTROL_PROG_IO1, CONTROL_PROG_IO_WKUP1 controlmodules intheSystem ControlModule chapteroftheAM/DM37x MultimediaDeviceTechnical ReferenceManual (literaturenumber SPRUGN4 )tomodifytheIO settingsifrequiredby thetargetedinterfaceapplication. (11)The defaultbufferconfigurationisstandardLVCMOS mode (non-I2C).Fora fulldescriptionofthepulldrivestrengthprogramming,see PADCONFS bitsofCONTROL_PADCONF_X controlmodules (standardLVCMOS mode),orprg_i2c2_pullupresx,prg_i2c2_lb1lb0,and prg_i2c3_pullupresx,prg_i2c3_lb1lb0bitsoftheCONTROL_PROG_IO2, CONTROL_PROG_IO3 controlmodules (I2Cmode) inthe System ControlModule chapteroftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 )to modifytheIO settingsifrequiredby thetargetedinterfaceapplication. (12)Mux0 ifsys_boot6ispulleddown (clockmaster). (13)IfMMC1 functionalsignalsareenabled,vdds_mmc1 forMMC1 must be suppliedby a dedicatedpower source. IfMMC1 functionalsignalsaredisabled,othermultiplexedCMOS signalsoftheinterfacecan be enabled.The interfacecan be supplied by thesame power sourceas vdds.The vdds power sourcesuppliesthevdds_mmc1 ball. IfneitherMMC1 functionalballsorCMOS signalsareenabled,theinterfaceballsareleftunconnectedwithitsassociatedpower supply (vdda/vssa)grounded. ForthecorrespondingsettingofthePBIASLITEPWRDNZ0 bit,see theSystem ControlModule /SCM Programming Model / Extended-DrainI/Osand PBIAS CellsProgramming Guide sectionoftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-3.BallCharacteristics(CUS Pkg.)(1) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] D7 sdrc_d0 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS C5 sdrc_d1 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS C6 sdrc_d2 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS B5 sdrc_d3 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS D9 sdrc_d4 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS D10 sdrc_d5 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS C7 sdrc_d6 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS B7 sdrc_d7 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS B11 sdrc_d8 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS C12 sdrc_d9 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS B12 sdrc_d10 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS D13 sdrc_d11 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS C13 sdrc_d12 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS B14 sdrc_d13 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS A14 sdrc_d14 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS B15 sdrc_d15 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS C9 sdrc_d16 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] E12 sdrc_d17 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS B8 sdrc_d18 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS B9 sdrc_d19 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS C10 sdrc_d20 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS B10 sdrc_d21 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS D12 sdrc_d22 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS E13 sdrc_d23 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS E15 sdrc_d24 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS D15 sdrc_d25 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS C15 sdrc_d26 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS B16 sdrc_d27 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS C16 sdrc_d28 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS D16 sdrc_d29 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS B17 sdrc_d30 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS B18 sdrc_d31 0 IO L Z 0 vdds_mem Yes 4 (8) PU/ PD LVCMOS C18 sdrc_ba0 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS D18 sdrc_ba1 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS A4 sdrc_a0 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS B4 sdrc_a1 0 O 0 0 0 vdds_mem NA 4 (8) PU/ PD LVCMOS D6 sdrc_a2 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS B3 sdrc_a3 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS B2 sdrc_a4 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS C3 sdrc_a5 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS E3 sdrc_a6 0 O 0 0 0 vdds_mem NA 4 (8) PU/ PD LVCMOS F6 sdrc_a7 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS E10 sdrc_a8 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS E9 sdrc_a9 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS E7 sdrc_a10 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS G6 sdrc_a11 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS G7 sdrc_a12 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS F7 sdrc_a13 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS F9 sdrc_a14 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS A19 sdrc_ncs0 0 O 1 1 0 vdds_mem NA 4(8) PU/ PD LVCMOS B19 sdrc_ncs1 0 O 1 1 0 vdds_mem NA 4(8) PU/ PD LVCMOS A10 sdrc_clk 0 IO L 0 0 vdds_mem Yes 4(8) PU/ PD LVCMOS A11 sdrc_nclk 0 O 1 1 0 vdds_mem NA 4(8) PU/ PD LVCMOS B20 sdrc_cke0 0 O H 1 7 vdds_mem NA 4(8) PU/ PD LVCMOS safe_mode_out1(9) 7 C20 sdrc_cke1 0 O H 1 7 vdds_mem NA 4(8) PU/ PD LVCMOS safe_mode_out1(9) 7 D19 sdrc_nras 0 O 1 1 0 vdds_mem NA 4(8) PU/ PD LVCMOS C19 sdrc_ncas 0 O 1 1 0 vdds_mem NA 4(8) PU/ PD LVCMOS A20 sdrc_nwe 0 O 1 1 0 vdds_mem NA 4 (8) PU/ PD LVCMOS B6 sdrc_dm0 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS B13 sdrc_dm1 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS A7 sdrc_dm2 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS A16 sdrc_dm3 0 O 0 0 0 vdds_mem NA 4(8) PU/ PD LVCMOS A5 sdrc_dqs0 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS A13 sdrc_dqs1 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS A8 sdrc_dqs2 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS A17 sdrc_dqs3 0 IO L Z 0 vdds_mem Yes 4(8) PU/ PD LVCMOS K4 gpmc_a1 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_34 4 IO safe_mode 7 K3 gpmc_a2 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 65 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] gpio_35 4 IO safe_mode 7 K2 gpmc_a3 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_36 4 IO safe_mode 7 J4 gpmc_a4 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_37 4 IO safe_mode 7 J3 gpmc_a5 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_38 4 IO safe_mode 7 J2 gpmc_a6 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_39 4 IO safe_mode 7 J1 gpmc_a7 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_40 4 IO safe_mode 7 H1 gpmc_a8 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_41 4 IO safe_mode 7 H2 gpmc_a9 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS sys_ndmareq2 1 I gpio_42 4 IO safe_mode 7 G2 gpmc_a10 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS sys_ndmareq3 1 I gpio_43 4 IO safe_mode 7 L2 gpmc_d0 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS M1 gpmc_d1 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS M2 gpmc_d2 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS N2 gpmc_d3 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS M3 gpmc_d4 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS P1 gpmc_d5 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS P2 gpmc_d6 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS R1 gpmc_d7 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS R2 gpmc_d8 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_44 4 IO safe_mode 7 T2 gpmc_d9 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_45 4 IO safe_mode 7 U1 gpmc_d10 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_46 4 IO safe_mode 7 R3 gpmc_d11 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_47 4 IO safe_mode 7 T3 gpmc_d12 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_48 4 IO safe_mode 7 U2 gpmc_d13 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_49 4 IO safe_mode 7 V1 gpmc_d14 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] gpio_50 4 IO safe_mode 7 V2 gpmc_d15 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_51 4 IO safe_mode 7 E2 gpmc_ncs0 0 O 1 1 0 vdds_mem NA 8 NA LVCMOS D2 gpmc_ncs3 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS sys_ndmareq0 1 I gpio_54 4 IO safe_mode 7 F4 gpmc_ncs4 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS sys_ndmareq1 1 I mcbsp4_ clkx 2 IO gpt_9_pwm_evt 3 IO gpio_55 4 IO safe_mode 7 G5 gpmc_ncs5 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS sys_ndmareq2 1 I mcbsp4_dr 2 I gpt_10_pwm_evt 3 IO gpio_56 4 IO safe_mode 7 F3 gpmc_ncs6 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS sys_ndmareq3 1 I mcbsp4_dx 2 IO gpt_11_pwm_evt 3 IO gpio_57 4 IO safe_mode 7 G4 gpmc_ncs7 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS gpmc_io_dir 1 O mcbsp4_fsx 2 IO gpt_8_pwm_evt 3 IO gpio_58 4 IO safe_mode 7 W2 gpmc_clk 0 O L 0 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_59 4 IO safe_mode 7 F1 gpmc_nadv_ale 0 O 0 0 0 vdds_mem NA 8 PU/ PD LVCMOS F2 gpmc_noe 0 O 1 1 0 vdds_mem NA 8 PU/ PD LVCMOS G3 gpmc_nwe 0 O 1 1 0 vdds_mem NA 8 PU/ PD LVCMOS K5 gpmc_nbe0_cle 0 O L 0 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_60 4 IO safe_mode 7 L1 gpmc_nbe1 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS gpio_61 4 IO safe_mode 7 E1 gpmc_nwp 0 O L 0 0 vdds_mem Yes 8 PU/ PD LVCMOS gpio_62 4 IO safe_mode 7 C1 gpmc_wait0 0 I H H 0 vdds_mem Yes NA PU/ PD LVCMOS C2 gpmc_wait3 0 I H H 7 vdds_mem Yes 8 PU/ PD LVCMOS sys_ndmareq1 1 I uart4_rx 2 I gpio_65 4 IO safe_mode 7 Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 67 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] G22 dss_pclk 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_66 4 IO hw_dbg12 5 O safe_mode 7 E22 dss_hsync 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_67 4 IO hw_dbg13 5 O safe_mode 7 F22 dss_vsync 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS gpio_68 4 IO safe_mode 7 J21 dss_acbias 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_69 4 IO safe_mode 7 AC19 dss_data0 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart1_cts 2 I NA gpio_70 4 IO 8 safe_mode 7 8 AB19 dss_data1 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart1_rts 2 O 8 gpio_71 4 IO 8 safe_mode 7 8 AD20 dss_data2 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_72 4 IO 8 safe_mode 7 8 AC20 dss_data3 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_73 4 IO 8 safe_mode 7 8 AD21 dss_data4 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart3_rx_irrx 2 I NA gpio_74 4 IO 8 safe_mode 7 8 AC21 dss_data5 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart3_tx_irtx 2 O 8 gpio_75 4 IO 8 safe_mode 7 8 D24 dss_data6 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart1_tx 2 O gpio_76 4 IO hw_dbg14 5 O safe_mode 7 E23 dss_data7 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart1_rx 2 I gpio_77 4 IO hw_dbg15 5 O safe_mode 7 E24 dss_data8 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart3_rx_irrx 2 I gpio_78 4 IO hw_dbg16 5 O safe_mode 7 F23 dss_data9 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS uart3_tx_irtx 2 O gpio_79 4 IO hw_dbg17 5 O

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] safe_mode 7 AC22 dss_data10 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_80 4 IO safe_mode 7 AC23 dss_data11 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_81 4 IO safe_mode 7 AB22 dss_data12 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_82 4 IO safe_mode 7 Y22 dss_data13 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_83 4 IO safe_mode 7 W22 dss_data14 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_84 4 IO safe_mode 7 V22 dss_data15 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_85 4 IO safe_mode 7 J22 dss_data16 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_86 4 IO safe_mode 7 G23 dss_data17 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_87 4 IO safe_mode 7 G24 dss_data18 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_clk 2 IO dss_data0 3 IO gpio_88 4 IO safe_mode 7 H23 dss_data19 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_simo 2 IO dss_data1 3 IO gpio_89 4 IO safe_mode 7 D23 dss_data20 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_somi 2 IO dss_data2 3 IO gpio_90 4 IO safe_mode 7 K22 dss_data21 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_cs0 2 IO dss_data3 3 IO gpio_91 4 IO safe_mode 7 V21 dss_data22 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS mcspi3_cs1 2 O dss_data4 3 IO gpio_92 4 IO safe_mode 7 W21 dss_data23 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS dss_data5 3 IO gpio_93 4 IO safe_mode 7 AA23 cvideo2_out 0 AO 0 0 0 vdda_dac NA NA (6) NA 10-bitDAC Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 69 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] AB24 cvideo1_out 0 AO 0 0 0 vdda_dac NA NA (6) NA 10-bitDAC AB23 cvideo1_vfb 0 AO 0 NA 0 vdda_dac NA NA (7) NA 10-bitDAC Y23 cvideo2_vfb 0 AO 0 NA 0 vdda_dac NA NA (7) NA 10-bitDAC Y24 cvideo1_rset 0 AIO 0 NA 0 vdda_dac No NA NA 10-bitDAC A22 cam_hs 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_94 4 IO hw_dbg0 5 O safe_mode 7 E18 cam_vs 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_95 4 IO hw_dbg1 5 O safe_mode 7 B22 cam_ xclka 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_96 4 IO safe_mode 7 J19 cam_pclk 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_97 4 IO hw_dbg2 5 O safe_mode 7 H24 cam_fld 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS cam_global_reset 2 IO hw_dbg3 5 O gpio_98 4 IO safe_mode 7 AB18 cam_d0 0 I L L 7 vdds Yes NA PU/ PD LVCMOS gpio_99 4 I safe_mode 7 AC18 cam_d1 0 I L L 7 vdds Yes NA PU/ PD LVCMOS gpio_100 4 I safe_mode 7 G19 cam_d2 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_101 4 IO hw_dbg4 5 O safe_mode 7 F19 cam_d3 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_102 4 IO hw_dbg5 5 O safe_mode 7 G20 cam_d4 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_103 4 IO hw_dbg6 5 O safe_mode 7 B21 cam_d5 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_104 4 IO hw_dbg7 5 O safe_mode 7 L24 cam_d6 0 I L L 7 vdds Yes NA PU/ PD LVCMOS gpio_105 4 I safe_mode 7 K24 cam_d7 0 I L L 7 vdds Yes NA PU/ PD LVCMOS gpio_106 4 I safe_mode 7 J23 cam_d8 0 I L L 7 vdds Yes NA PU/ PD LVCMOS gpio_107 4 I safe_mode 7

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] K23 cam_d9 0 I L L 7 vdds Yes NA PU/ PD LVCMOS gpio_108 4 I safe_mode 7 F21 cam_d10 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_109 4 IO hw_dbg8 5 O safe_mode 7 G21 cam_d11 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_110 4 IO hw_dbg9 5 O safe_mode 7 C22 cam_ xclkb 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_111 4 IO safe_mode 7 F18 cam_wen 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS cam_ shutter 2 O gpio_167 4 IO hw_dbg10 5 O safe_mode 7 J20 cam_ strobe 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_126 4 IO hw_dbg11 5 O safe_mode 7 V20 mcbsp2_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_116 4 IO safe_mode 7 T21 mcbsp2_ clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_117 4 IO safe_mode 7 V19 mcbsp2_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_118 4 IO safe_mode 7 R20 mcbsp2_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_119 4 IO safe_mode 7 M23 mmc1_clk 0 O L L 7 vdds_mmc1 (1 Yes 1 PU/ PD (4) LVCMOS gpio_120(5) 4 IO safe_mode 7 L23 mmc1_cmd 0 IO L L 7 vdds_mmc1 (1 Yes 1 PU/ PD (4) LVCMOS gpio_121(5) 4 IO safe_mode 7 M22 mmc1_dat0 0 IO L L 7 vdds_mmc1 (1 Yes 1 PU/ PD (4) LVCMOS gpio_122(5) 4 IO safe_mode 7 M21 mmc1_dat1 0 IO L L 7 vdds_mmc1 (1 Yes 1 PU/ PD (4) LVCMOS gpio_123(5) 4 IO safe_mode 7 M20 mmc1_dat2 0 IO L L 7 vdds_mmc1 (1 Yes 1 PU/ PD (4) LVCMOS gpio_124(5) 4 IO safe_mode 7 N23 mmc1_dat3 0 IO L L 7 vdds_mmc1 (1 Yes 1 PU/ PD (4) LVCMOS Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 71 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] gpio_125(5) 4 IO safe_mode 7 N22 gpio_126(5) 4 IO L L 7 vdds_x Yes 1 PU/ PD (4) LVCMOS safe_mode 7 P24 gpio_129(5) 4 IO L L 7 vdds_x Yes 1 PU/ PD (4) LVCMOS safe_mode 7 Y1 mmc2_clk 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_clk 1 IO gpio_130 4 IO safe_mode 7 AB5 mmc2_cmd 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_simo 1 IO gpio_131 4 IO safe_mode 7 AB3 mmc2_ dat0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_somi 1 IO gpio_132 4 IO safe_mode 7 Y3 mmc2_ dat1 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_133 4 IO safe_mode 7 W3 mmc2_ dat2 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_cs1 1 O gpio_134 4 IO safe_mode 7 V3 mmc2_ dat3 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS mcspi3_cs0 1 IO gpio_135 4 IO safe_mode 7 AB2 mmc2_ dat4 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dir_dat0 1 O mmc3_dat0 3 IO gpio_136 4 IO safe_mode 7 AA2 mmc2_ dat5 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dir_dat1 1 O cam_global_reset 2 IO mmc3_dat1 3 IO gpio_137 4 IO mm3_rxdp 6 IO safe_mode 7 Y2 mmc2_dat6 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dir_cmd 1 O cam_shutter 2 O mmc3_dat2 3 IO gpio_138 4 IO safe_mode 7 AA1 mmc2_dat7 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_clkin 1 I mmc3_dat3 3 IO gpio_139 4 IO mm3_rxdm 6 IO safe_mode 7 V6 mcbsp3_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart2_cts 1 I

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] gpio_140 4 IO safe_mode 7 V5 mcbsp3_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS uart2_rts 1 O gpio_141 4 IO safe_mode 7 W4 mcbsp3_ clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart2_tx 1 O gpio_142 4 IO safe_mode 7 V4 mcbsp3_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart2_rx 1 I gpio_143 4 IO safe_mode 7 W7 uart1_tx 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_148 4 IO safe_mode 7 W6 uart1_rts 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_149 4 IO safe_mode 7 AC2 uart1_cts 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_150 4 IO safe_mode 7 V7 uart1_rx 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS mcbsp1_ clkr 2 IO mcspi4_clk 3 IO gpio_151 4 IO safe_mode 7 W19 mcbsp1_ clkr 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi4_clk 1 IO gpio_156 4 IO safe_mode 7 AB20 mcbsp1_fsr 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS cam_global_reset 2 IO gpio_157 4 IO safe_mode 7 W18 mcbsp1_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi4_simo 1 IO mcbsp3_dx 2 IO gpio_158 4 IO safe_mode 7 Y18 mcbsp1_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi4_somi 1 IO mcbsp3_dr 2 I gpio_159 4 IO safe_mode 7 AA18 mcbsp_clks 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS cam_ shutter 2 O gpio_160 4 IO uart1_cts 5 I safe_mode 7 AA19 mcbsp1_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mcspi4_cs0 1 IO mcbsp3_fsx 2 IO gpio_161 4 IO Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 73 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] safe_mode 7 V18 mcbsp1_ clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mcbsp3_ clkx 2 IO gpio_162 4 IO safe_mode 7 A23 uart3_cts_rctx 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_163 4 IO safe_mode 7 B23 uart3_rts_sd 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_164 4 IO safe_mode 7 B24 uart3_rx_irrx 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_165 4 IO safe_mode 7 C23 uart3_tx_irtx 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_166 4 IO safe_mode 7 R21 hsusb0_clk 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS gpio_120 4 IO safe_mode 7 R23 hsusb0_stp 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_121 4 IO safe_mode 7 P23 hsusb0_dir 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_122 4 IO safe_mode 7 R22 hsusb0_nxt 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_124 4 IO safe_mode 7 T24 hsusb0_ data0 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart3_tx_irtx 2 O gpio_125 4 IO uart2_tx 5 O safe_mode 7 T23 hsusb0_ data1 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart3_rx_irrx 2 I gpio_130 4 IO uart2_rx 5 I safe_mode 7 U24 hsusb0_ data2 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart3_rts_sd 2 O gpio_131 4 IO uart2_rts 5 O safe_mode 7 U23 hsusb0_ data3 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS uart3_cts_rctx 2 IO gpio_169 4 IO uart2_cts 5 I safe_mode 7 W24 hsusb0_ data4 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_188 4 IO safe_mode 7 V23 hsusb0_ data5 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_189 4 IO safe_mode 7

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] W23 hsusb0_ data6 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_190 4 IO safe_mode 7 T22 hsusb0_ data7 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_191 4 IO safe_mode 7 K20 i2c1_scl 0 OD H H 0 vdds NA 3 PU/ PD (10)(11) Open Drain K21 i2c1_sda 0 IOD H H 0 vdds Yes 3 PU/ PD (10)(11) Open Drain AC15 i2c2_scl 0 OD H H 7 vdds Yes 3 PU/ PD (10)(12) Open Drain gpio_168 4 IO 4 safe_mode 7 AC14 i2c2_sda 0 IOD H H 7 vdds Yes 3 PU/ PD (10)(12) Open Drain gpio_183 4 IO 4 safe_mode 7 AC13 i2c3_scl 0 OD H H 7 vdds Yes 3 PU/ PD (10)(12) Open Drain gpio_184 4 IO 4 safe_mode 7 AC12 i2c3_sda 0 IOD H H 7 vdds Yes 3 PU/ PD (10)(12) Open Drain gpio_185 4 IO 4 safe_mode 7 Y16 i2c4_scl 0 OD H H 0 vdds Yes 3 PU/ PD (10)(11) Open Drain sys_nvmode1 1 O 4 safe_mode 7 Y15 i2c4_sda 0 IOD H H 0 vdds Yes 3 PU/ PD (10)(11) Open Drain sys_nvmode2 1 O 4 safe_mode 7 A24 hdq_sio 0 IOD H H 7 vdds Yes 4 PU/ PD LVCMOS sys_altclk 1 I i2c2_sccbe 2 OD i2c3_sccbe 3 OD gpio_170 4 IO safe_mode 7 T5 mcspi1_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dat4 1 IO gpio_171 4 IO safe_mode 7 R4 mcspi1_simo 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dat5 1 IO gpio_172 4 IO safe_mode 7 T4 mcspi1_somi 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dat6 1 IO gpio_173 4 IO safe_mode 7 T6 mcspi1_cs0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS mmc2_dat7 1 IO gpio_174 4 IO safe_mode 7 R5 mcspi1_cs3 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS hsusb2_ data2 3 IO gpio_177 4 IO mm2_txdat 5 IO safe_mode 7 N5 mcspi2_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS hsusb2_ data7 3 IO Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 75 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] gpio_178 4 IO safe_mode 7 N4 mcspi2_simo 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpt_9_pwm_evt 1 IO hsusb2_ data4 3 IO gpio_179 4 IO safe_mode 7 N3 mcspi2_somi 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS gpt_10_pwm_evt 1 IO hsusb2_ data5 3 IO gpio_180 4 IO safe_mode 7 M5 mcspi2_cs0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS gpt_11_pwm_evt 1 IO hsusb2_ data6 3 IO gpio_181 4 IO safe_mode 7 M4 mcspi2_cs1 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpt_8_pwm_evt 1 IO hsusb2_ data3 3 IO gpio_182 4 IO mm2_txen_n 5 IO safe_mode 7 AA16 sys_32k 0 I Z Z 0 vdds Yes NA PU/ PD LVCMOS AD15 sys_xtalin 0 AI Z Z 0 vdds Yes NA No Analog AD14 sys_xtalout 0 AO Z 0 0 vdds NA NA NA Analog Y13 sys_clkreq 0 IO 0 see (3) 0 vdds Yes 4 PU/ PD LVCMOS gpio_1 4 IO safe_mode 7 W16 sys_nirq 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS gpio_0 4 IO safe_mode 7 AA10 sys_nrespwron 0 I Z Z 0 vdds Yes NA No LVCMOS Y10 sys_nreswarm 0 IOD 0 H 0 vdds Yes 4 PU/ PD LVCMOS gpio_30 4 IO safe_mode 7 AB12 sys_boot0 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS dss_data18 3 IO gpio_2 4 IO safe_mode 7 AC16 sys_boot1 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS dss_data19 3 IO gpio_3 4 IO safe_mode 7 AD17 sys_boot2 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS gpio_4 4 IO safe_mode 7 AD18 sys_boot3 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS dss_data20 3 O gpio_5 4 IO safe_mode 7 AC17 sys_boot4 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS mmc2_dir_dat2 1 O dss_data21 3 O gpio_6 4 IO

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] safe_mode 7 AB16 sys_boot5 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS mmc2_dir_dat3 1 O dss_data22 3 O gpio_7 4 IO safe_mode 7 AA15 sys_boot6 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS dss_data23 3 O gpio_8 4 IO safe_mode 7 AD23 sys_off_mode 0 O 0 L 7 vdds Yes 4 PU/ PD LVCMOS gpio_9 4 IO safe_mode 7 Y7 sys_clkout1 0 O L L 7(13) vdds Yes 4 PU/ PD LVCMOS gpio_10 4 IO safe_mode 7 AA6 sys_clkout2 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS gpio_186 4 IO safe_mode 7 AB7 jtag_ntrst 0 I L L 0 vdds Yes NA PU/ PD LVCMOS AB6 jtag_tck 0 I L L 0 vdds Yes NA PU/ PD LVCMOS AA7 jtag_rtck 0 O L 0 0 vdds NA 4 PU/ PD LVCMOS AA9 jtag_tms_tmsc 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS AB10 jtag_tdi 0 I H H 0 vdds Yes NA PU/ PD LVCMOS AB9 jtag_tdo 0 O L Z 0 vdds NA 4 PU/ PD LVCMOS AC24 jtag_emu0 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS gpio_11 4 IO safe_mode 7 AD24 jtag_emu1 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS gpio_31 4 IO safe_mode 7 AC1 etk_clk 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcbsp5_ clkx 1 IO mmc3_clk 2 O hsusb1_stp 3 O gpio_12 4 IO mm1_rxdp 5 IO hw_dbg0 7 O AD3 etk_ctl 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mmc3_cmd 2 IO hsusb1_clk 3 O gpio_13 4 IO hw_dbg1 7 O AD6 etk_d0 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_simo 1 IO mmc3_dat4 2 IO hsusb1_ data0 3 IO gpio_14 4 IO mm1_rxrcv 5 IO hw_dbg2 7 O AC6 etk_d1 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_somi 1 IO hsusb1_ data1 3 IO gpio_15 4 IO mm1_txse0 5 IO Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 77 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] hw_dbg3 7 O AC7 etk_d2 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_cs0 1 IO hsusb1_ data2 3 IO gpio_16 4 IO mm1_txdat 5 IO hw_dbg4 7 O AD8 etk_d3 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_clk 1 IO mmc3_dat3 2 IO hsusb1_ data7 3 IO gpio_17 4 IO hw_dbg5 7 O AC5 etk_d4 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mcbsp5_dr 1 I mmc3_dat0 2 IO hsusb1_ data4 3 IO gpio_18 4 IO hw_dbg6 7 O AD2 etk_d5 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mcbsp5_fsx 1 IO mmc3_dat1 2 IO hsusb1_ data5 3 IO gpio_19 4 IO hw_dbg7 7 O AC8 etk_d6 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mcbsp5_dx 1 O mmc3_dat2 2 IO hsusb1_ data6 3 IO gpio_20 4 IO hw_dbg8 7 O AD9 etk_d7 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mcspi3_cs1 1 O mmc3_dat7 2 IO hsusb1_ data3 3 IO gpio_21 4 IO mm1_txen_n 5 IO hw_dbg9 7 O AC4 etk_d8 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mmc3_dat6 2 IO hsusb1_dir 3 I gpio_22 4 IO hw_dbg10 7 O AD5 etk_d9 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS mmc3_dat5 2 IO hsusb1_nxt 3 I gpio_23 4 IO mm1_rxdm 5 IO hw_dbg11 7 O AC3 etk_d10 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS uart1_rx 2 I hsusb2_clk 3 O gpio_24 4 IO hw_dbg12 7 O AC9 etk_d11 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] hsusb2_stp 3 O gpio_25 4 IO mm2_rxdp 5 IO hw_dbg13 7 O AC10 etk_d12 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS hsusb2_dir 3 I gpio_26 4 IO hw_dbg14 7 O AD11 etk_d13 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS hsusb2_nxt 3 I gpio_27 4 IO mm2_rxdm 5 IO hw_dbg15 7 O AC11 etk_d14 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS hsusb2_ data0 3 IO gpio_28 4 IO mm2_rxrcv 5 IO hw_dbg16 7 O AD12 etk_d15 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS hsusb2_ data1 3 IO gpio_29 4 IO mm2_txse0 5 IO hw_dbg17 7 O E16,F15, vdds_mem 0 PWR - - - - - - - - F16,G15, G16, H15, J6, J7,J8,K6, K7,K8 F12,F13, vdd_core 0 PWR - - - - - - - - G12, G13, H12, H13, J17,J18, K17,K18, K19,L14, L15,M14, M15, R17, R18, R19, T17,T18, T19,T20 F10,G9, vdd_mpu_iva 0 PWR - - - - - - - - G10, H9, H10, J9,J10, L11,L12,M6, M7, M8, M12, N6, N7, N8, R6, R7, R8, T7,T8,U12, U13, V12, V13,W12, W13 H8 vdds_x 0 PWR - - - - - - - - M17, M18, vdds 0 PWR - - - - - - - - M19, N17, N18, N19, U10, V9,V10, W9, W10, Y9 N24 vdds_mmc1 0 PWR - - - - - - - - Y12 cap_vddu_ 0 PWR - - - - - - - - wkup_logic U8 cap_vdd_sram_mpu_ 0 PWR - - - - - - - - iva H17 cap_vdd_sram_core 0 PWR - - - - - - - - G18 vdda_dplls_dll 0 PWR - - - - - - - - U17 vdda_dpll_per 0 PWR - - - - - - - - AA12 vdds_sram 0 PWR - - - - - - - - AA13 vdda_wkup_bg_bb 0 PWR - - - - - - - - Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 79 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-3.BallCharacteristics(CUS Pkg.)(1) (continued) BALL PIN NAME [2] MODE [3] TYPE [4] BALL RESET BALL RESET RESET REL. POWER [8] HYS [9] BUFFER PULLUP IO CELL [12] NUMBER [1] STATE [5] REL. STATE MODE [7] STRENGTH /DOWN [6] (mA) [10] TYPE [11] N21 cap_vdd_bb_mpu_iv 0 PWR - - - - - - - - a N20 cap_vddu_array 0 PWR - - - - - - - - AB15 vssa_dac 0 GND - - - - - - - - AB13 vdda_dac 0 PWR - - - - - - - - H16, J11, J12,J13,J14, J15,J16, K10,K11, K14,K15,L8, L10,L13, L17,M9, M10, M11, M13, M16, N9, N10, N11, N12, N13, N14, N15, N16, P8,P10,P11, P12,P13, P14,P15, P17,R10, R11, R14, R15, T9,T10, T11,T12, T13,T14, T15,T16,U9, U11, U14, U15, U16, V15,V16 AD1, A1,A2, No Connect(2) - - - - - - - - - - W15 sys_xtalgnd 0 GND - - - - - - - - (1) NA inthistablestandsfor"NotApplicable". (2) Pinslabeledas "No connect"must be leftunconnected.Any connectionstothesepinsmay resultinunpredictablebehavior. (3) Dependingon thesys_clkreqdirectionthecorrespondingresetreleasedstatevaluecan be: – Z ifsys_clkreqisused as input – 1 ifsys_clkreqisused as output Fora fulldescriptionofthesys_clkreqcontrol,see Power,Reset,and ClockManagement chapteroftheAM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). (4) PU = [50to100 kΩ]perdefaultor[10to50 kΩ]accordingtotheselectedmode. Fora fulldescriptionofthepull-updrivestrength programming,see thePRG_SDMMC_PUSTRENGTH configurationregisterbitfieldintheSystem ControlModule chapterofthe AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ).PD: 30 to150 kΩ. (5) The usage ofthisGPIO isstronglyrestricted.Formore information,see theGeneral-PurposeInterfacechapteroftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (6) The drivestrengthisfixedregardlessoftheload.The driverisdesignedtodrive75Ω forvideoapplications. (7) Inbuffermode, thedrivestrengthisfixedregardlessoftheload.The driverisdesignedtodrive75Ω forvideoapplications.Inbypass mode, thedrivestrengthis0.47mA. (8) The drivestrengthoftheseIOs issetaccordingtotheprogrammableloadrange:2 pF to4 pF perdefaultor4 pF to12 pF.Fora full descriptionofthedrivestrengthprogramming,see theSystem ControlModule chapteroftheAM/DM37x MultimediaDeviceTechnical ReferenceManual (literaturenumber SPRUGN4 ). (9) Inthesafe_mode_out1,thebufferisconfiguredtodrive1. (10)The pullupand pulldowncan be eitherthestandardLVCMOS 100-μA drivestrengthortheI2C pullupand pulldowndescribedbelow: Nominalresistance= 1.66kΩ inhigh-speedmode witha loadrangeof5 pF to12 pF,4.5kΩ instandard/fastmode witha loadrange of5 pF to15 pF. (11)The defaultbufferconfigurationisHigh-SpeedI2C point-to-pointmode usinginternalpullup.Fora fulldescriptionofthepulldrive strengthprogramming,see prg_i2c1_pullupresx,prg_i2c1_lb1lb0,and prg_sr_pullupresx,prg_sr_lbbitsoftheCONTROL_PROG_IO1, CONTROL_PROG_IO_WKUP1 controlmodules intheSystem ControlModule /SCM Programming Model /FeatureSettingssection and theSystem ControlModule chapteroftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 )tomodifytheIO settingsifrequiredby thetargetedinterfaceapplication. (12)The defaultbufferconfigurationisstandardLVCMOS mode (non-I2C).Fora fulldescriptionofthepulldrivestrengthprogramming,see PADCONFS bitsofCONTROL_PADCONF_X controlmodules (standardLVCMOS mode),orprg_i2c2_pullupresx,prg_i2c2_lb1lb0,and prg_i2c3_pullupresx,prg_i2c3_lb1lb0bitsoftheCONTROL_PROG_IO2, CONTROL_PROG_IO3 controlmodules (I2Cmode) inthe System ControlModule chapteroftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 )to modifytheIO settingsifrequiredby thetargetedinterfaceapplication. (13)Mux0 ifsys_boot6ispulleddown (clockmaster).

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (14)IfMMC1 functionalsignalsareenabled,vdds_mmc1 forMMC1 must be suppliedby a dedicatedpower source. IfMMC1 functionalsignalsaredisabled,othermultiplexedCMOS signalsoftheinterfacecan be enabled.The interfacecan be supplied by thesame power sourceas vdds.The vdds power sourcesuppliesthevdds_mmc1 ball. IfneitherMMC1 functionalballsorCMOS signalsareenabled,theinterfaceballsareleftunconnectedwithitsassociatedpower supply (vdda/vssa)grounded. ForthecorrespondingsettingofthePBIASLITEPWRDNZ0 bit,see theSystem ControlModule /SCM Programming Model / Extended-DrainI/Osand PBIAS CellsProgramming Guide sectionoftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 81 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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2.4 MultiplexingCharacteristics

Table2-4providesa descriptionofthemultiplexingon theCBP, CBC, and CUS packages,respectively. Note: The followingdoes not take intoaccount subsystem pin multiplexingoptions.Subsystem pin multiplexingoptionsare describedin Section2.5, SignalDescription.For more information,see the System ControlModule /System ControlModule FunctionalDescription/Pad FunctionalMultiplexingand ConfigurationsectionoftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-4.MultiplexingCharacteristics CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE Bottom Top Bottom Top NA J2 NA D1 D7 sdrc_d0 NA J1 NA G1 C5 sdrc_d1 NA G2 NA G2 C6 sdrc_d2 NA G1 NA E1 B5 sdrc_d3 NA F2 NA D2 D9 sdrc_d4 NA F1 NA E2 D10 sdrc_d5 NA D2 NA B3 C7 sdrc_d6 NA D1 NA B4 B7 sdrc_d7 NA B13 NA A10 B11 sdrc_d8 NA A13 NA B11 C12 sdrc_d9 NA B14 NA A11 B12 sdrc_d10 NA A14 NA B12 D13 sdrc_d11 NA B16 NA A16 C13 sdrc_d12 NA A16 NA A17 B14 sdrc_d13 NA B19 NA B17 A14 sdrc_d14 NA A19 NA B18 B15 sdrc_d15 NA B3 NA B7 C9 sdrc_d16 NA A3 NA A5 E12 sdrc_d17 NA B5 NA B6 B8 sdrc_d18 NA A5 NA A6 B9 sdrc_d19 NA B8 NA A8 C10 sdrc_d20 NA A8 NA B9 B10 sdrc_d21 NA B9 NA A9 D12 sdrc_d22 NA A9 NA B10 E13 sdrc_d23 NA B21 NA C21 E15 sdrc_d24 NA A21 NA D20 D15 sdrc_d25 NA D22 NA B19 C15 sdrc_d26 NA D23 NA C20 B16 sdrc_d27 NA E22 NA D21 C16 sdrc_d28 NA E23 NA E20 D16 sdrc_d29 NA G22 NA E21 B17 sdrc_d30 NA G23 NA G21 B18 sdrc_d31 NA AB21 NA AA18 C18 sdrc_ba0 NA AC21 NA V20 D18 sdrc_ba1 NA N22 NA G20 A4 sdrc_a0 NA N23 NA K20 B4 sdrc_a1 NA P22 NA J20 D6 sdrc_a2 NA P23 NA J21 B3 sdrc_a3 NA R22 NA U21 B2 sdrc_a4 NA R23 NA R20 C3 sdrc_a5 NA T22 NA M21 E3 sdrc_a6 NA T23 NA M20 F6 sdrc_a7 NA U22 NA N20 E10 sdrc_a8 NA U23 NA K21 E9 sdrc_a9

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-4.MultiplexingCharacteristics(continued) CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE Bottom Top Bottom Top NA V22 NA Y16 E7 sdrc_a10 NA V23 NA N21 G6 sdrc_a11 NA W22 NA R21 G7 sdrc_a12 NA W23 NA AA15 F7 sdrc_a13 NA Y22 NA Y12 F9 sdrc_a14 NA M22 NA T21 A19 sdrc_ncs0 NA M23 NA T20 B19 sdrc_ncs1 NA A11 NA A12 A10 sdrc_clk NA B11 NA B13 A11 sdrc_nclk NA J22 NA Y15 B20 sdrc_cke0 safe_mo de_out1 NA J23 NA Y13 C20 sdrc_cke1 safe_mo de_out1 NA L23 NA V21 D19 sdrc_nras NA L22 NA U20 C19 sdrc_ncas NA K23 NA Y18 A20 sdrc_nwe NA C1 NA H1 B6 sdrc_dm0 NA A17 NA A14 B13 sdrc_dm1 NA A6 NA A4 A7 sdrc_dm2 NA A20 NA A18 A16 sdrc_dm3 NA C2 NA C2 A5 sdrc_dqs0 NA B17 NA B15 A13 sdrc_dqs1 NA B6 NA B8 A8 sdrc_dqs2 NA B20 NA A19 A17 sdrc_dqs3 N4 AC15 J2 NA K4 gpmc_a1 gpio_34 safe_mo de M4 AB15 H1 NA K3 gpmc_a2 gpio_35 safe_mo de L4 AC16 H2 NA K2 gpmc_a3 gpio_36 safe_mo de K4 AB16 G2 NA J4 gpmc_a4 gpio_37 safe_mo de T3 AC17 F1 NA J3 gpmc_a5 gpio_38 safe_mo de R3 AB17 F2 NA J2 gpmc_a6 gpio_39 safe_mo de N3 AC18 E1 NA J1 gpmc_a7 gpio_40 safe_mo de M3 AB18 E2 NA H1 gpmc_a8 gpio_41 safe_mo de L3 AC19 D1 NA H2 gpmc_a9 sys_ndmareq gpio_42 safe_mo 2 de K3 AB19 D2 NA G2 gpmc_a10 sys_ndmareq gpio_43 safe_mo 3 de NA AC20 A4 NA NA gpmc_a11 safe_mo de K1 M2 AA2 U2 L2 gpmc_d0 L1 M1 AA1 U1 M1 gpmc_d1 L2 N2 AC2 V2 M2 gpmc_d2 P2 N1 AC1 V1 N2 gpmc_d3 T1 R2 AE5 AA3 M3 gpmc_d4 V1 R1 AD6 AA4 P1 gpmc_d5 V2 T2 AD5 Y3 P2 gpmc_d6 W2 T1 AC5 Y4 R1 gpmc_d7 H2 AB3 V1 R1 R2 gpmc_d8 gpio_44 safe_mo de K2 AC3 Y1 T1 T2 gpmc_d9 gpio_45 safe_mo de P1 AB4 T1 N1 U1 gpmc_d10 gpio_46 safe_mo de Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 83 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-4.MultiplexingCharacteristics(continued) CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE Bottom Top Bottom Top R1 AC4 U2 P2 R3 gpmc_d11 gpio_47 safe_mo de R2 AB6 U1 P1 T3 gpmc_d12 gpio_48 safe_mo de T2 AC6 P1 M1 U2 gpmc_d13 gpio_49 safe_mo de W1 AB7 L2 J2 V1 gpmc_d14 gpio_50 safe_mo de Y1 AC7 M2 K2 V2 gpmc_d15 gpio_51 safe_mo de G4 Y2 AD8 AA8 E2 gpmc_ncs0 H3 Y1 AD1 W1 NA gpmc_ncs1 gpio_52 safe_mo de V8 NA A3 NA NA gpmc_ncs2 gpio_53 safe_mo de U8 NA B6 NA D2 gpmc_ncs3 sys_ndmareq gpio_54 safe_mo 0 de T8 NA B4 NA F4 gpmc_ncs4 sys_ndmareq mcbsp4_clkx gpt_9_pwm gpio_55 safe_mo 1 _evt de R8 NA C4 NA G5 gpmc_ncs5 sys_ndmareq mcbsp4_dr gpt_10_pw gpio_56 safe_mo 2 m_evt de P8 NA B5 NA F3 gpmc_ncs6 sys_ndmareq mcbsp4_dx gpt_11_pw gpio_57 safe_mo 3 m_evt de N8 NA C5 NA G4 gpmc_ncs7 gpmc_io_dir mcbsp4_fsx gpt_8_pwm gpio_58 safe_mo _evt de T4 W2 N1 L1 W2 gpmc_clk gpio_59 safe_mo de F3 W1 AD10 AA9 F1 gpmc_nadv_a le G2 V2 N2 L2 F2 gpmc_noe F4 V1 M1 K1 G3 gpmc_nwe G3 AC12 K2 NA K5 gpmc_nbe0_c gpio_60 safe_mo le de U3 NA J1 NA L1 gpmc_nbe1 gpio_61 safe_mo de H1 AB10 AC6 Y5 E1 gpmc_nwp gpio_62 safe_mo de M8 AB12 AC11 Y10 C1 gpmc_wait0 L8 AC10 AC8 Y8 NA gpmc_wait1 gpio_63 safe_mo de K8 NA B3 NA NA gpmc_wait2 uart4_tx gpio_64 safe_mo de J8 NA C6 NA C2 gpmc_wait3 sys_ndmareq uart4_rx(3) gpio_65 safe_mo 1 de D28 NA G25 NA G22 dss_pclk gpio_66 hw_dbg12 safe_mo de D26 NA K24 NA E22 dss_hsync gpio_67 hw_dbg13 safe_mo de D27 NA M25 NA F22 dss_vsync gpio_68 safe_mo de E27 NA F26 NA J21 dss_acbias gpio_69 safe_mo de AG22 NA AE21 NA AC19 dss_data0 uart1_cts gpio_70 safe_mo de AH22 NA AE22 NA AB19 dss_data1 uart1_rts gpio_71 safe_mo de AG23 NA AE23 NA AD20 dss_data2 gpio_72 safe_mo de AH23 NA AE24 NA AC20 dss_data3 gpio_73 safe_mo de AG24 NA AD23 NA AD21 dss_data4 uart3_rx_irrx gpio_74 safe_mo de AH24 NA AD24 NA AC21 dss_data5 uart3_tx_irtx gpio_75 safe_mo de E26 NA G26 NA D24 dss_data6 uart1_tx gpio_76 hw_dbg14 safe_mo de

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-4.MultiplexingCharacteristics(continued) CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE Bottom Top Bottom Top F28 NA H25 NA E23 dss_data7 uart1_rx gpio_77 hw_dbg15 safe_mo de F27 NA H26 NA E24 dss_data8 uart3_rx_irrx gpio_78 hw_dbg16 safe_mo de G26 NA J26 NA F23 dss_data9 uart3_tx_irtx gpio_79 hw_dbg17 safe_mo de AD28 NA AC26 NA AC22 dss_data10 gpio_80 safe_mo de AD27 NA AD26 NA AC23 dss_data11 gpio_81 safe_mo de AB28 NA AA25 NA AB22 dss_data12 gpio_82 safe_mo de AB27 NA Y25 NA Y22 dss_data13 gpio_83 safe_mo de AA28 NA AA26 NA W22 dss_data14 gpio_84 safe_mo de AA27 NA AB26 NA V22 dss_data15 gpio_85 safe_mo de G25 NA L25 NA J22 dss_data16 gpio_86 safe_mo de H27 NA L26 NA G23 dss_data17 gpio_87 safe_mo de H26 NA M24 NA G24 dss_data18 mcspi3_clk dss_data0 gpio_88 safe_mo de H25 NA M26 NA H23 dss_data19 mcspi3_simo dss_data1 gpio_89 safe_mo de E28 NA F25 NA D23 dss_data20 mcspi3_somi dss_data2 gpio_90 safe_mo de J26 NA N24 NA K22 dss_data21 mcspi3_cs0 dss_data3 gpio_91 safe_mo de AC27 NA AC25 NA V21 dss_data22 mcspi3_cs1 dss_data4 gpio_92 safe_mo de AC28 NA AB25 NA W21 dss_data23 dss_data5 gpio_93 safe_mo de W28 NA V26 NA AA23 cvideo2_out Y28 NA W26 NA AB24 cvideo1_out Y27 NA W25 NA AB23 cvideo1_vfb W27 NA U24 NA Y23 cvideo2_vfb W26 NA V23 NA Y24 cvideo1_rset A24 NA C23 NA A22 cam_hs gpio_94 hw_dbg0 safe_mo de A23 NA D23 NA E18 cam_vs gpio_95 hw_dbg1 safe_mo de C25 NA C25 NA B22 cam_xclka gpio_96 safe_mo de C27 NA C26 NA J19 cam_pclk gpio_97 hw_dbg2 safe_mo de C23 NA B23 NA H24 cam_fld cam_global_res gpio_98 hw_dbg3 safe_mo et de AG17 NA AE16 NA AB18 cam_d0 gpio_99(1) safe_mo de AH17 NA AE15 NA AC18 cam_d1 gpio_100(1) safe_mo de B24 NA A24 NA G19 cam_d2 gpio_101 hw_dbg4 safe_mo de C24 NA B24 NA F19 cam_d3 gpio_102 hw_dbg5 safe_mo de D24 NA D24 NA G20 cam_d4 gpio_103 hw_dbg6 safe_mo de A25 NA C24 NA B21 cam_d5 gpio_104 hw_dbg7 safe_mo de K28 NA P25 NA L24 cam_d6 gpio_105(1) safe_mo de L28 NA P26 NA K24 cam_d7 gpio_106(1) safe_mo de Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 85 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-4.MultiplexingCharacteristics(continued) CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE Bottom Top Bottom Top K27 NA N25 NA J23 cam_d8 gpio_107(1) safe_mo de L27 NA N26 NA K23 cam_d9 gpio_108(1) safe_mo de B25 NA D25 NA F21 cam_d10 gpio_109 hw_dbg8 safe_mo de C26 NA E26 NA G21 cam_d11 gpio_110 hw_dbg9 safe_mo de B26 NA E25 NA C22 cam_xclkb gpio_111 safe_mo de B23 NA A23 NA F18 cam_wen cam_shutter gpio_167 hw_dbg10 safe_mo de D25 NA D26 NA J20 cam_strobe gpio_126 hw_dbg11 safe_mo de AG19 NA AD17 NA NA gpio_112(1) safe_mo de AH19 NA AD16 NA NA gpio_113(1) safe_mo de AG18 NA AE18 NA NA gpio_114(1) safe_mo de AH18 NA AE17 NA NA gpio_115(1) safe_mo de P21 NA U18 NA V20 mcbsp2_fsx gpio_116 safe_mo de N21 NA R18 NA T21 mcbsp2_clkx gpio_117 safe_mo de R21 NA T18 NA V19 mcbsp2_dr gpio_118 safe_mo de M21 NA R19 NA R20 mcbsp2_dx gpio_119 safe_mo de N28 NA N19 NA M23 mmc1_clk gpio_120(2) safe_mo de M27 NA L18 NA L23 mmc1_cmd gpio_121(2) safe_mo de N27 NA M19 NA M22 mmc1_dat0 gpio_122(2) safe_mo de N26 NA M18 NA M21 mmc1_dat1 gpio_123(2) safe_mo de N25 NA K18 NA M20 mmc1_dat2 gpio_124(2) safe_mo de P28 NA N20 NA N23 mmc1_dat3 gpio_125(2) safe_mo de P27 NA M20 NA N22 gpio_126(2) safe_mo de P26 NA P17 NA NA gpio_127(2) safe_mo de R27 NA P18 NA NA gpio_128 safe_mo de R25 NA P19 NA P24 gpio_129(2) safe_mo de AE2 NA W10 NA Y1 mmc2_clk mcspi3_clk gpio_130 safe_mo de AG5 NA R10 NA AB5 mmc2_cmd mcspi3_simo gpio_131 safe_mo de AH5 NA T10 NA AB3 mmc2_dat0 mcspi3_somi gpio_132 safe_mo de AH4 NA T9 NA Y3 mmc2_dat1 gpio_133 safe_mo de AG4 NA U10 NA W3 mmc2_dat2 mcspi3_cs1 gpio_134 safe_mo de AF4 NA U9 NA V3 mmc2_dat3 mcspi3_cs0 gpio_135 safe_mo de AE4 NA V10 NA AB2 mmc2_dat4 mmc2_dir_dat mmc3_dat0 gpio_136 safe_mo 0 de AH3 NA M3 NA AA2 mmc2_dat5 mmc2_dir_datcam_global_resmmc3_dat1 gpio_137 mm3_rxdp safe_mo 1 et de

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-4.MultiplexingCharacteristics(continued) CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE Bottom Top Bottom Top AF3 NA L3 NA Y2 mmc2_dat6 mmc2_dir_cm cam_shutter mmc3_dat2 gpio_138 safe_mo d de AE3 NA K3 NA AA1 mmc2_dat7 mmc2_clkin mmc3_dat3 gpio_139 mm3_rxdm safe_mo de AF6 NA P3 NA V6 mcbsp3_dx uart2_cts gpio_140 safe_mo de AE6 NA N3 NA V5 mcbsp3_dr uart2_rts gpio_141 safe_mo de AF5 NA U3 NA W4 mcbsp3_clkx uart2_tx gpio_142 safe_mo de AE5 NA W3 NA V4 mcbsp3_fsx uart2_rx gpio_143 safe_mo de AB26 NA Y24 NA NA uart2_cts mcbsp3_dx gpt_9_pwm_evt gpio_144 safe_mo de AB25 NA AA24 NA NA uart2_rts mcbsp3_dr gpt_10_pwm_e gpio_145 safe_mo vt de AA25 NA AD22 NA NA uart2_tx mcbsp3_clkx gpt_11_pwm_e gpio_146 safe_mo vt de AD25 NA AD21 NA NA uart2_rx mcbsp3_fsx gpt_8_pwm_evt gpio_147 safe_mo de AA8 NA L4 NA W7 uart1_tx gpio_148 safe_mo de AA9 NA R2 NA W6 uart1_rts gpio_149 safe_mo de W8 NA W2 NA AC2 uart1_cts gpio_150 safe_mo de Y8 NA H3 NA V7 uart1_rx mcbsp1_clkr mcspi4_clk gpio_151 safe_mo de AE1 NA V3 NA NA mcbsp4_clkx gpio_152 mm3_txse0 safe_mo de AD1 NA U4 NA NA mcbsp4_dr gpio_153 mm3_rxrcv safe_mo de AD2 NA R3 NA NA mcbsp4_dx gpio_154 mm3_txdat safe_mo de AC1 NA T3 NA NA mcbsp4_fsx gpio_155 mm3_txen_ safe_mo n de Y21 NA U19 NA W19 mcbsp1_clkr mcspi4_clk gpio_156 safe_mo de AA21 NA V17 NA AB20 mcbsp1_fsr cam_global_res gpio_157 safe_mo et de V21 NA U17 NA W18 mcbsp1_dx mcspi4_simo mcbsp3_dx gpio_158 safe_mo de U21 NA T20 NA Y18 mcbsp1_dr mcspi4_somi mcbsp3_dr gpio_159 safe_mo de T21 NA T19 NA AA18 mcbsp_clks cam_shutter gpio_160 uart1_cts safe_mo de K26 NA P20 NA AA19 mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx gpio_161 safe_mo de W21 NA T17 NA V18 mcbsp1_clkx mcbsp3_clkx gpio_162 safe_mo de H18 NA F23 NA A23 uart3_cts_rctx gpio_163 safe_mo de H19 NA F24 NA B23 uart3_rts_sd gpio_164 safe_mo de H20 NA H24 NA B24 uart3_rx_irrx gpio_165 safe_mo de H21 NA G24 NA C23 uart3_tx_irtx gpio_166 safe_mo de T28 NA W19 NA R21 hsusb0_clk gpio_120 safe_mo de T25 NA U20 NA R23 hsusb0_stp gpio_121 safe_mo de R28 NA V19 NA P23 hsusb0_dir gpio_122 safe_mo de T26 NA W18 NA R22 hsusb0_nxt gpio_124 safe_mo de Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 87 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-4.MultiplexingCharacteristics(continued) CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE Bottom Top Bottom Top T27 NA V20 NA T24 hsusb0_data0 uart3_tx_irtx gpio_125 uart2_tx safe_mo de U28 NA Y20 NA T23 hsusb0_data1 uart3_rx_irrx gpio_130 uart2_rx safe_mo de U27 NA V18 NA U24 hsusb0_data2 uart3_rts_sd gpio_131 uart2_rts safe_mo de U26 NA W20 NA U23 hsusb0_data3 uart3_cts_rctx gpio_169 uart2_cts safe_mo de U25 NA W17 NA W24 hsusb0_data4 gpio_188 safe_mo de V28 NA Y18 NA V23 hsusb0_data5 gpio_189 safe_mo de V27 NA Y19 NA W23 hsusb0_data6 gpio_190 safe_mo de V26 NA Y17 NA T22 hsusb0_data7 gpio_191 safe_mo de K21 NA J25 NA K20 i2c1_scl J21 NA J24 NA K21 i2c1_sda AF15 NA C2 NA AC15 i2c2_scl gpio_168 safe_mo de AE15 NA C1 NA AC14 i2c2_sda gpio_183 safe_mo de AF14 NA AB4 NA AC13 i2c3_scl gpio_184 safe_mo de AG14 NA AC4 NA AC12 i2c3_sda gpio_185 safe_mo de AD26 NA AD15 NA Y16 i2c4_scl sys_nvmode1 safe_mo de AE26 NA W16 NA Y15 i2c4_sda sys_nvmode2 safe_mo de J25 NA J23 NA A24 hdq_sio sys_altclk i2c2_sccbe i2c3_sccbe gpio_170 safe_mo de AB3 NA P9 NA T5 mcspi1_clk mmc2_dat4 gpio_171 safe_mo de AB4 NA P8 NA R4 mcspi1_simo mmc2_dat5 gpio_172 safe_mo de AA4 NA P7 NA T4 mcspi1_somi mmc2_dat6 gpio_173 safe_mo de AC2 NA R7 NA T6 mcspi1_cs0 mmc2_dat7 gpio_174 safe_mo de AC3 NA R8 NA NA mcspi1_cs1 mmc3_cmd gpio_175 safe_mo de AB1 NA R9 NA NA mcspi1_cs2 mmc3_clk gpio_176 safe_mo de AB2 NA T8 NA R5 mcspi1_cs3 hsusb2_dat gpio_177 mm2_txdat safe_mo a2 de AA3 NA W7 NA N5 mcspi2_clk hsusb2_dat gpio_178 safe_mo a7 de Y2 NA W8 NA N4 mcspi2_simo gpt_9_pwm_e hsusb2_dat gpio_179 safe_mo vt a4 de Y3 NA U8 NA N3 mcspi2_somi gpt_10_pwm_ hsusb2_dat gpio_180 safe_mo evt a5 de Y4 NA V8 NA M5 mcspi2_cs0 gpt_11_pwm_ hsusb2_dat gpio_181 safe_mo evt a6 de V3 NA V9 NA M4 mcspi2_cs1 gpt_8_pwm_e hsusb2_dat gpio_182 mm2_txen_ safe_mo vt a3 n de AE25 NA AE20 NA AA16 sys_32k AE17 NA AF19 NA AD15 sys_xtalin AF17 NA AF20 NA AD14 sys_xtalout AF25 NA W15 NA Y13 sys_clkreq gpio_1 safe_mo de AF26 NA V16 NA W16 sys_nirq gpio_0 safe_mo de AH25 NA V13 NA AA10 sys_nrespwro n

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-4.MultiplexingCharacteristics(continued) CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE Bottom Top Bottom Top AF24 NA AD7 AA5 Y10 sys_nreswar gpio_30 safe_mo m de AH26 NA F3 NA AB12 sys_boot0 dss_data18 gpio_2 safe_mo de AG26 NA D3 NA AC16 sys_boot1 dss_data19 gpio_3 safe_mo de AE14 NA C3 NA AD17 sys_boot2 gpio_4 safe_mo de AF18 NA E3 NA AD18 sys_boot3 dss_data20 gpio_5 safe_mo de AF19 NA E4 NA AC17 sys_boot4 mmc2_dir_dat dss_data21 gpio_6 safe_mo 2 de AE21 NA G3 NA AB16 sys_boot5 mmc2_dir_dat dss_data22 gpio_7 safe_mo 3 de AF21 NA D4 NA AA15 sys_boot6 dss_data23 gpio_8 safe_mo de AF22 NA V12 NA AD23 sys_off_mode gpio_9 safe_mo de AG25 NA AE14 NA Y7 sys_clkout1 gpio_10 safe_mo de AE22 NA W11 NA AA6 sys_clkout2 gpio_186 safe_mo de AA17 NA U15 NA AB7 jtag_ntrst AA13 NA V14 NA AB6 jtag_tck AA12 NA W13 NA AA7 jtag_rtck AA18 NA V15 NA AA9 jtag_tms_tms c AA20 NA U16 NA AB10 jtag_tdi AA19 NA Y13 NA AB9 jtag_tdo AA11 NA Y15 NA AC24 jtag_emu0 gpio_11 safe_mo de AA10 NA Y14 NA AD24 jtag_emu1 gpio_31 safe_mo de AF10 NA AB2 NA AC1 etk_clk mcbsp5_clkx mmc3_clk hsusb1_stp gpio_12 mm1_rxdp hw_dbg AE10 NA AB3 NA AD3 etk_ctl mmc3_cmd hsusb1_clk gpio_13 hw_dbg AF11 NA AC3 NA AD6 etk_d0 mcspi3_simo mmc3_dat4 hsusb1_dat gpio_14 mm1_rxrcv hw_dbg a0 2 AG12 NA AD4 NA AC6 etk_d1 mcspi3_somi hsusb1_dat gpio_15 mm1_txse0 hw_dbg a1 3 AH12 NA AD3 NA AC7 etk_d2 mcspi3_cs0 hsusb1_dat gpio_16 mm1_txdat hw_dbg a2 4 AE13 NA AA3 NA AD8 etk_d3 mcspi3_clk mmc3_dat3 hsusb1_dat gpio_17 hw_dbg a7 5 AE11 NA Y3 NA AC5 etk_d4 mcbsp5_dr mmc3_dat0 hsusb1_dat gpio_18 hw_dbg a4 6 AH9 NA AB1 NA AD2 etk_d5 mcbsp5_fsx mmc3_dat1 hsusb1_dat gpio_19 hw_dbg a5 7 AF13 NA AE3 NA AC8 etk_d6 mcbsp5_dx mmc3_dat2 hsusb1_dat gpio_20 hw_dbg a6 8 AH14 NA AD2 NA AD9 etk_d7 mcspi3_cs1 mmc3_dat7 hsusb1_dat gpio_21 mm1_txen_ hw_dbg a3 n 9 AF9 NA AA4 NA AC4 etk_d8 mmc3_dat6 hsusb1_dir gpio_22 hw_dbg AG9 NA V2 NA AD5 etk_d9 mmc3_dat5 hsusb1_nxt gpio_23 mm1_rxdm hw_dbg AE7 NA AE4 NA AC3 etk_d10 uart1_rx hsusb2_clk gpio_24 hw_dbg AF7 NA AF6 NA AC9 etk_d11 hsusb2_stp gpio_25 mm2_rxdp hw_dbg AG7 NA AE6 NA AC10 etk_d12 hsusb2_dir gpio_26 hw_dbg AH7 NA AF7 NA AD11 etk_d13 hsusb2_nxt gpio_27 mm2_rxdm hw_dbg Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 89 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-4.MultiplexingCharacteristics(continued) CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE Bottom Top Bottom Top AG8 NA AF9 NA AC11 etk_d14 hsusb2_dat gpio_28 mm2_rxrcv hw_dbg a0 16 AH8 NA AE9 NA AD12 etk_d15 hsusb2_dat gpio_29 mm2_txse0 hw_dbg a1 17 AC4, J4,H4, NA AC21, D15, NA F12,F13, vdd_core D8, AE9, D9, G11, G18, G12, G13, D15, Y16, H20, M7, H12, H13, AE18, Y18, M17, R20, T7, J17,J18, W18, K18, Y8,Y12 K17,K18, J18,AE19, K19,L14, Y19,U19, L15,M14, T19,N19, M15, R17, M19, J19, R18, R19, Y20,W20, T17,T18, V20,U20, T19,T20 P20,N20, K20,J20, D22, D23, AE24, M25, L25,E25 Y9,W9, T9, NA D13, G9, NA F10,G9, G10, vdd_mpu_iva R9, M9, L9, G12, H7, K11, H9, H10, J9, J9,Y10,U10, L9,M9, M10, J10,L11,L12, T10,R10, N7, N8, P10, M6, M7, M8, N10, M10, U7, U11, U13, M12, N6, N7, L10,J10, V7,V11,W9, N8, R6, R7, Y11,W11, Y9,Y11 R8, T7,T8, K11,J11, U12, U13, W12, K13, V12,V13, Y14,K14, W12, W13 J14,Y15, W15, J15 U4 NA D6 NA N21 cap_vdd_bb_ mpu_iva AA15 NA K14 NA Y12 cap_vddu_wk up_logic K15 NA K13 NA G18 vdda_dplls_dll W16 NA U12 NA AA12 vdds_sram AD3, AD4, NA A18,AC7, A3,A15,B5,F2M17, M18, vdds W4, AF8, AC15, AC18, ,F21,L20,W21M19, N17, AE8, AF16, AC24, AD20, N18, N19, AE16, AF23, AE10, C11, U10, V9,V10, AE23, F25, D9, E24,G4, W9, W10, Y9 F26,AG27 J15,J18,L7, L24,M4, T4, T24,W24, Y4,AB24 U1, J1,F1, AC5, P1,H1, NA NA E16,F15, vdds_mem J2,F2,R4, F23,E1,C23, F16,G15, B5,A5,AH6, A4,A7,A10, G16, H15, J6, B8,A8,B12, A15,A18 J7,J8,K6, A12,D16, K7,K8 C16, B18, A18,B22, A22,G28, C28 AA16 NA U14 NA U17 vdda_dpll_per AA14 NA W14 NA AA13 vdda_wkup_b g_bb

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-4.MultiplexingCharacteristics(continued) CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE Bottom Top Bottom Top AG2, U2, B2, B4,B7,B10, A6,A8,A13, A7,A13,B14, H11, H14, vss AG3, W3, P3, B15,B18, AB5, AB22, C1, F1,F20, H16, J11, J3,E3,A3, C22, E2,F22, AC10, AD14, H2, H20, L21, J12,J13,J14, P4,E4,AG6, H2, P2,AB5, AD25, AE7, M2, P20,R2, J15,J16, D7, C7, V9, AB14, AB20 B2,B25,C12, W20 Y6,Y11, K10,K11, U9, P9,N9, D7, D10, D12, AA7, AA16 K14,K15,L8, K9,W10, D14, D18, L10,L13, V10,P10, D20, E22,G1, L17,M9, K10,D10, G8, G10, M10, M11, C10, AF12, G20, G23, M13, M16, AE12, Y12, H4, K1,K15, N9, N10, N11, K12,J12, K25,L10, N12, N13, Y13,W13, L17,L23,N4, N14, N15, J13,D13, N10, N17, R1, N16, P8,P10, C13, W14, R4, R17, T23, P11,P12, K16,J16, U25, W1, W4, P13,P14, W17, K17, W23, Y7, P15,P17, J17,W19, Y10,Y16, R10, R11, V19,R19, Y26 R14, R15, T9, P19,L19, T10,T11, K19,D19, T12,T13, C19, AF20, T14,T15, AE20, T20, T16,U9, U11, AG15, AF2, U14, U15, AF27, B15, U16, V15, J27,M2, M26, V16 N2, AA2, AG10, AC25, AC26, Y25, W25, M20, L20,L26, G27, D21, C22, B27, A26,R20, R26 V25 NA V25 NA AB13 vdda_dac Y26 NA V24 NA AB15 vssa_dac K25 NA N23 NA N24 vdds_mmc1 P25 NA P23 NA H8 vdds_x AG21 NA AD19 NA NA vdds AH20 NA AE19 NA N20 cap_vddu_arr ay AH21 NA AC19 NA NA vss AG16 NA AC16 NA NA vss AG20 NA AD18 NA NA vdds M28 NA L19 NA NA vss H28 NA L20 NA NA vdds V4 NA N9 NA U8 cap_vdd_sra m_mpu_iva L21 NA K20 NA H17 cap_vdd_sra m_core Y17 NA AF23 NA W15 sys_xtalgnd (1) ThisGPIO isonlyan input(andnotan output). (2) The usage ofthisGPIO isstronglyrestricted.Formore information,see theGeneral-PurposeInterfacechapteroftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (3) UART4 isonlyavailableon CBP and CBC packages. Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 91 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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2.5 SignalDescription

Many signalsareavailableon multiplepinsaccordingtothesoftwareconfigurationofthepinmultiplexing options. 1. SIGNAL NAME: The signalname 2. DESCRIPTION: Descriptionofthesignal 3. TYPE: Type = Balltypeforthisspecificfunction: – I= Input – O = Output – Z = High-impedance – D = Open Drain – DS = Differential – A = Analog 4. BALL BOTTOM: Associatedball(s)bottom 5. BALL TOP: Associatedball(s)top 6. SUBSYSTEM PIN MULTIPLEXING: Containsa listofthepinmultiplexingoptionsatthe module/subsystemlevel.The pinfunctionisselectedatthemodule/systemlevel. Note:The Subsystem MultiplexingSignalsarenotdescribedinthefollowingtables.Formore information,see theSystem ControlModule /System ControlModule FunctionalDescription/Pad FunctionalMultiplexingand ConfigurationsectionoftheAM/DM37x MultimediaDeviceTechnical ReferenceManual (literaturenumber SPRUGN4 ).

2.5.1 ExternalMemory Interfaces

For more information,see Memory Subsystem / General-PurposeMemory Controller/ GPMC Environmentsectionof the AM/DM37x MultimediaDevice TechnicalReference Manual (literaturenumber SPRUGN4 ). Table2-5.ExternalMemory Interfaces– GPMC SignalsDescription(1) SIGNAL NAME DESCRIPTION [2] TYPE BALL BALL BALL BOTTOM BALL TOP BALL SUBSYSTEM [1] [3] BOTTOM TOP (CBC Pkg.)[4] (CBC Pkg.)[5] BOTTOM PIN (CBP (CBP (CUS MULTIPLEXING Pkg.)[4] Pkg.)[5] Pkg.)[4] [6] gpmc_a1 GPMC outputaddressbit1 / O N4 /K1 AC15 /M2 J2 /AA2 NA /U2 K4 /L2 -/gpmc_d0 extendedmultiplexedaddress gpmc_a17 gpmc_a2 GPMC outputaddressbit2 / O M4 /L1 AB15 /M1 H1 /AA1 NA /U1 K3 /M1 -/gpmc_d1 extendedmultiplexedaddress gpmc_a18 gpmc_a3 GPMC outputaddressbit3 / O L4 /L2 AC16 /N2 H2 /AC2 NA /V2 K2 /M2 -/gpmc_d2 extendedmultiplexedaddress gpmc_a19 gpmc_a4 GPMC outputaddressbit4 / O K4 /P2 AB16 /N1 G2 /AC1 NA /V1 J4 /N2 -/gpmc_d3 extendedmultiplexedaddress gpmc_a20 gpmc_a5 GPMC outputaddressbit5 / O T3 /T1 AC17 /R2 F1 /AE5 NA /AA3 J3 /M3 -/gpmc_d4 extendedmultiplexedaddress gpmc_a21 gpmc_a6 GPMC outputaddressbit6 / O R3 /V1 AB17 /R1 F2 /AD6 NA /AA4 J2/P1 -/gpmc_d5 extendedmultiplexedaddress gpmc_a22 gpmc_a7 GPMC outputaddressbit7 / O N3 /V2 AC18 /T2 E1 /AD5 NA /Y3 J1/P2 -/gpmc_d6 extendedmultiplexedaddress gpmc_a23 gpmc_a8 GPMC outputaddressbit8 / O M3 /W2 AB18 /T1 E2 /AC5 NA /Y4 H1/ R1 -/gpmc_d7 extendedmultiplexedaddress gpmc_a24

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-5.ExternalMemory Interfaces– GPMC SignalsDescription(1)(continued) SIGNAL NAME DESCRIPTION [2] TYPE BALL BALL BALL BOTTOM BALL TOP BALL SUBSYSTEM [1] [3] BOTTOM TOP (CBC Pkg.)[4] (CBC Pkg.)[5] BOTTOM PIN (CBP (CBP (CUS MULTIPLEXING Pkg.)[4] Pkg.)[5] Pkg.)[4] [6] gpmc_a9 GPMC outputaddressbit9 / O L3 /H2 AC19 / D1 /V1 NA /R1 H2/ R2 -/gpmc_d8 extendedmultiplexedaddress AB3 gpmc_a25 gpmc_a10 GPMC outputaddressbit10 / O K3 /K2 AB19 / D2 /Y1 T1 G2/ T2 -/gpmc_d9 extendedmultiplexedaddress AC3 gpmc_a26 gpmc_a11 GPMC outputaddressbit11 / O NC /P1 AC20 / A4 /T1 -/N1 NA -/gpmc_d10 extendedmultiplexedaddress AB4 gpmc_a27 gpmc_a12 General-purposememory address O R1 AC4 U2 P2 R3 gpmc_d11 bit12 gpmc_a13 General-purposememory address O R2 AB6 U1 P1 T3 gpmc_d12 bit13 gpmc_a14 General-purposememory address O T2 AC6 P1 M1 U2 gpmc_d13 bit14 gpmc_a15 General-purposememory address O W1 AB7 L2 J2 V1 gpmc_d14 bit15 gpmc_a16 General-purposememory address O Y1 AC7 M2 K2 V2 gpmc_d15 bit16 gpmc_a17 General-purposememory address O N4 AC15 J2 NA K4 gpmc_a1 bit17 gpmc_a18 General-purposememory address O M4 AB15 H1 NA K3 gpmc_a2 bit18 gpmc_a19 General-purposememory address O L4 AC16 H2 NA K2 gpmc_a3 bit19 gpmc_a20 General-purposememory address O K4 AB16 G2 NA J4 gpmc_a4 bit20 gpmc_a21 General-purposememory address O T3 AC17 F1 NA J3 gpmc_a5 bit21 gpmc_a22 General-purposememory address O R3 AB17 F2 NA J2 gpmc_a6 bit22 gpmc_a23 General-purposememory address O N3 AC18 E1 NA J1 gpmc_a7 bit23 gpmc_a24 General-purposememory address O M3 AB18 E2 NA H1 gpmc_a8 bit24 gpmc_a25 General-purposememory address O L3 AC19 D1 NA H2 gpmc_a9 bit25 gpmc_a26 General-purposememory address O K3 AB19 D2 NA G2 gpmc_a10 bit26 gpmc_d0 GPMC databit0 /multiplexed IO K1 M2 AA2 U2 L2 gpmc_d0 addressgpmc_a1 gpmc_d1 GPMC databit1 /multiplexed IO L1 M1 AA1 U1 M1 gpmc_d1 addressgpmc_a2 gpmc_d2 GPMC databit2 /multiplexed IO L2 N2 AC2 V2 M2 gpmc_d2 addressgpmc_a3 gpmc_d3 GPMC databit3 /multiplexed IO P2 N1 AC1 V1 N2 gpmc_d3 addressgpmc_a4 gpmc_d4 GPMC databit4 /multiplexed IO T1 R2 AE5 AA3 M3 gpmc_d4 addressgpmc_a5 gpmc_d5 GPMC databit5 /multiplexed IO V1 R1 AD6 AA4 P1 gpmc_d5 addressgpmc_a6 gpmc_d6 GPMC databit6 /multiplexed IO V2 T2 AD5 Y3 P2 gpmc_d6 addressgpmc_a7 gpmc_d7 GPMC databit7 /multiplexed IO W2 T1 AC5 Y4 R1 gpmc_d7 addressgpmc_a8 gpmc_d8 GPMC databit8 /multiplexed IO H2 AB3 V1 R1 R2 gpmc_d8 addressgpmc_a9 gpmc_d9 GPMC databit9 /multiplexed IO K2 AC3 Y1 T1 T2 gpmc_d9 addressgpmc_a10 Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 93 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-5.ExternalMemory Interfaces– GPMC SignalsDescription(1)(continued) SIGNAL NAME DESCRIPTION [2] TYPE BALL BALL BALL BOTTOM BALL TOP BALL SUBSYSTEM [1] [3] BOTTOM TOP (CBC Pkg.)[4] (CBC Pkg.)[5] BOTTOM PIN (CBP (CBP (CUS MULTIPLEXING Pkg.)[4] Pkg.)[5] Pkg.)[4] [6] gpmc_d10 GPMC databit10 /multiplexed IO P1 AB4 T1 N1 U1 gpmc_d10 addressgpmc_a11 gpmc_d11 GPMC databit11 /multiplexed IO R1 AC4 U2 P2 R3 gpmc_d11 addressgpmc_a12 gpmc_d12 GPMC databit12 /multiplexed IO R2 AB6 U1 P1 T3 gpmc_d12 addressgpmc_a13 gpmc_d13 GPMC databit13 /multiplexed IO T2 AC6 P1 M1 U2 gpmc_d13 addressgpmc_a14 gpmc_d14 GPMC databit14 /multiplexed IO W1 AB7 L2 J2 V1 gpmc_d14 addressgpmc_a15 gpmc_d15 GPMC databit15 /multiplexed IO Y1 AC7 M2 K2 V2 gpmc_d15 addressgpmc_a16 gpmc_ncs0 GPMC ChipSelectbit0 O G4 Y2 AD8 AA8 E2 NA gpmc_ncs1 GPMC ChipSelectbit1 O H3 Y1 AD1 W1 NA NA gpmc_ncs2 GPMC ChipSelectbit2 O V8 NA A3 NA NA NA gpmc_ncs3 GPMC ChipSelectbit3 O U8 NA B6 NA D2 NA gpmc_ncs4 GPMC ChipSelectbit4 O T8 NA B4 NA F4 NA gpmc_ncs5 GPMC ChipSelectbit5 O R8 NA C4 NA G5 NA gpmc_ncs6 GPMC ChipSelectbit6 O P8 NA B5 NA F3 NA gpmc_ncs7 GPMC ChipSelectbit7 O N8 NA C5 NA G4 NA gpmc_io_dir GPMC IO directioncontrolforuse O N8 NA C5 NA G4 NA withexternaltransceivers gpmc_clk GPMC clock O T4 W2 N1 L1 W2 NA gpmc_nadv_ale AddressValidorAddressLatch O F3 W1 AD10 AA9 F1 NA Enable gpmc_noe OutputEnable O G2 V2 N2 L2 F2 NA gpmc_nwe WriteEnable O F4 V1 M1 K1 G3 NA gpmc_nbe0_cle Lower ByteEnable.Alsoused for O G3 AC12 K2 NA K5 NA Command LatchEnable gpmc_nbe1 Upper ByteEnable O U3 NA J1 NA L1 NA gpmc_nwp FlashWriteProtect O H1 AB10 AC6 Y5 E1 NA gpmc_wait0 Externalindicationofwait I M8 AB12 AC11 Y10 C1 NA gpmc_wait1 Externalindicationofwait I L8 AC10 AC8 Y8 NA NA gpmc_wait2 Externalindicationofwait I K8 NA B3 NA NA NA gpmc_wait3 Externalindicationofwait I J8 NA C6 NA C2 NA (1) NA intablestandsfor"NotApplicable". NOTE For more information,see Memory Subsystem / SDRAM Controller(SDRC) Subsystem / SDRC Subsystem Environmentsectionof the AM/DM37x MultimediaDevice Technical ReferenceManual (literaturenumber SPRUGN4 ).

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-6.ExternalMemory Interfaces– SDRC SignalsDescription(1) SIGNAL DESCRIPTION [2] TYPE [3] BALL BALL TOP BALL BOTTOM BALL TOP BALL BOTTOM NAME [1] BOTTOM (CBP Pkg.) (CBC Pkg.)4 (CBC Pkg.)[5] (CUS Pkg.)[4] (CBP Pkg.) [5] 4 sdrc_d0 SDRAM databit0 IO NA J2 NA D1 D7 sdrc_d1 SDRAM databit1 IO NA J1 NA G1 C5 sdrc_d2 SDRAM databit2 IO NA G2 NA G2 C6 sdrc_d3 SDRAM databit3 IO NA G1 NA E1 B5 sdrc_d4 SDRAM databit4 IO NA F2 NA D2 D9 sdrc_d5 SDRAM databit5 IO NA F1 NA E2 D10 sdrc_d6 SDRAM databit6 IO NA D2 NA B3 C7 sdrc_d7 SDRAM databit7 IO NA D1 NA B4 B7 sdrc_d8 SDRAM databit8 IO NA B13 NA A10 B11 sdrc_d9 SDRAM databit9 IO NA A13 NA B11 C12 sdrc_d10 SDRAM databit10 IO NA B14 NA A11 B12 sdrc_d11 SDRAM databit11 IO NA A14 NA B12 D13 sdrc_d12 SDRAM databit12 IO NA B16 NA A16 C13 sdrc_d13 SDRAM databit13 IO NA A16 NA A17 B14 sdrc_d14 SDRAM databit14 IO NA B19 NA B17 A14 sdrc_d15 SDRAM databit15 IO NA A19 NA B18 B15 sdrc_d16 SDRAM databit16 IO NA B3 NA B7 C9 sdrc_d17 SDRAM databit17 IO NA A3 NA A5 E12 sdrc_d18 SDRAM databit18 IO NA B5 NA B6 B8 sdrc_d19 SDRAM databit19 IO NA A5 NA A6 B9 sdrc_d20 SDRAM databit20 IO NA B8 NA A8 C10 sdrc_d21 SDRAM databit21 IO NA A8 NA B9 B10 sdrc_d22 SDRAM databit22 IO NA B9 NA A9 D12 sdrc_d23 SDRAM databit23 IO NA A9 NA B10 E13 sdrc_d24 SDRAM databit24 IO NA B21 NA C21 E15 sdrc_d25 SDRAM databit25 IO NA A21 NA D20 D15 sdrc_d26 SDRAM databit26 IO NA D22 NA B19 C15 sdrc_d27 SDRAM databit27 IO NA D23 NA C20 B16 sdrc_d28 SDRAM databit28 IO NA E22 NA D21 C16 sdrc_d29 SDRAM databit29 IO NA E23 NA E20 D16 sdrc_d30 SDRAM databit30 IO NA G22 NA E21 B17 sdrc_d31 SDRAM databit31 IO NA G23 NA G21 B18 sdrc_ba0 SDRAM bank select0 O NA AB21 NA AA18 C18 sdrc_ba1 SDRAM bank select1 O NA AC21 NA V20 D18 sdrc_a0 SDRAM addressbit0 O NA N22 NA G20 A4 sdrc_a1 SDRAM addressbit1 O NA N23 NA K20 B4 sdrc_a2 SDRAM addressbit2 O NA P22 NA J20 D6 sdrc_a3 SDRAM addressbit3 O NA P23 NA J21 B3 sdrc_a4 SDRAM addressbit4 O NA R22 NA U21 B2 sdrc_a5 SDRAM addressbit5 O NA R23 NA R20 C3 sdrc_a6 SDRAM addressbit6 O NA T22 NA M21 E3 sdrc_a7 SDRAM addressbit7 O NA T23 NA M20 F6 sdrc_a8 SDRAM addressbit8 O NA U22 NA N20 E10 sdrc_a9 SDRAM addressbit9 O NA U23 NA K21 E9 sdrc_a10 SDRAM addressbit10 O NA V22 NA Y16 E7 sdrc_a11 SDRAM addressbit11 O NA V23 NA N21 G6 sdrc_a12 SDRAM addressbit12 O NA W22 NA R21 G7 sdrc_a13 SDRAM addressbit13 O NA W23 NA AA15 F7 sdrc_a14 SDRAM addressbit14 O NA Y22 NA Y12 F9 Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 95 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-6.ExternalMemory Interfaces– SDRC SignalsDescription(1)(continued) SIGNAL DESCRIPTION [2] TYPE [3] BALL BALL TOP BALL BOTTOM BALL TOP BALL BOTTOM NAME [1] BOTTOM (CBP Pkg.) (CBC Pkg.)4 (CBC Pkg.)[5] (CUS Pkg.)[4] (CBP Pkg.) [5] 4 sdrc_ncs0 Chipselect0 O NA M22 NA T21 A19 sdrc_ncs1 Chipselect1 O NA M23 NA T20 B19 sdrc_clk Clock IO NA A11 NA A12 A10 sdrc_nclk ClockInvert O NA B11 NA B13 A11 sdrc_cke0 ClockEnable0 O NA J22 NA Y15 B20 sdrc_cke1 ClockEnable1 O NA J23 NA Y13 C20 sdrc_nras SDRAM Row Access O NA L23 NA V21 D19 sdrc_ncas SDRAM column O NA L22 NA U20 C19 addressstrobe sdrc_nwe SDRAM writeenable O NA K23 NA Y18 A20 sdrc_dm 0 Data Mask 0 O NA C1 NA H1 B6 sdrc_dm1 Data Mask 1 O NA A17 NA A14 B13 sdrc_dm2 Data Mask 2 O NA A6 NA A4 A7 sdrc_dm 3 Data Mask 3 O NA A20 NA A18 A16 sdrc_dqs0 Data Strobe0 IO NA B17 NA C2 A5 sdrc_dqs1 Data Strobe1 IO NA NA NA B15 A13 sdrc_dqs2 Data Strobe2 IO NA NA NA B8 A8 sdrc_dqs3 Data Strobe3 IO NA B20 NA A19 A17 (1) NA inthistablestandsfor"NotApplicable". (2) Fora listofpinsnotsupportedon a particularpackage,see Table2-4.

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2.5.2 Video Interfaces

Table2-7.Video Interfaces– CAM SignalsDescription SIGNAL NAME DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] cam_hs Camera HorizontalSynchronization IO A24 C23 A22 cam_vs Camera VerticalSynchronization IO A23 D23 E18 cam_xclka Camera ClockOutputa O C25 C25 B22 cam_xclkb Camera ClockOutputb O B26 E25 C22 cam_d0 Camera digitalimage databit0 I AG17 AE16 AB18 cam_d1 Camera digitalimage databit1 I AH17 AE15 AC18 cam_d2 Camera digitalimage databit2 I B24 A24 G19 cam_d3 Camera digitalimage databit3 I C24 B24 F19 cam_d4 Camera digitalimage databit4 I D24 D24 G20 cam_d5 Camera digitalimage databit5 I A25 C24 B21 cam_d6 Camera digitalimage databit6 I K28 P25 L24 cam_d7 Camera digitalimage databit7 I L28 P26 K24 cam_d8 Camera digitalimage databit8 I K27 N25 J23 cam_d9 Camera digitalimage databit9 I L27 N26 K23 cam_d10 Camera digitalimage databit10 I B25 D25 F21 cam_d11 Camera digitalimage databit11 I C26 E26 G21 cam_fld Camera fieldidentification IO C23 B23 H24 cam_pclk Camera pixelclock I C27 C26 J19 cam_wen Camera WriteEnable I B23 A23 F18 cam_strobe Flashstrobecontrolsignal O D25 D26 J20 cam_global_reset Globalresetisused strobe IO C23 /AH3 /AA21 B23/M3/V17 H24/ AA2/ AB20 synchronization cam_shutter Mechanicalshuttercontrolsignal O B23 /AF3 /T21 A23 /T19/L3 F18/Y2/AA18 NOTE For more information,see DisplaySubsystem /DisplaySubsystem Environmentsectionof the AM/DM37x Multimedia Device Technical Reference Manual (literaturenumber SPRUGN4 ). Table2-8.Video Interfaces– DSS SignalsDescription SIGNAL NAME DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] dss_pclk LCD PixelClock O D28 G25 G22 dss_hsync LCD HorizontalSynchronization O D26 K24 E22 dss_vsync LCD VerticalSynchronization O D27 M25 F22 dss_acbias AC biascontrol(STN) orpixeldataenable(TFT)output O E27 F26 J21 dss_data0 LCD PixelData bit0 O AG22 /H26 AE21 /M24 AC19 /G24 dss_data1 LCD PixelData bit1 O AH22 /H25 AE22 /M26 AB19 /H23 dss_data2 LCD PixelData bit2 O AG23 /E28 AE23 /F25 AD20 /D23 dss_data3 LCD PixelData bit3 O AH23 /J26 AE24 /N24 AC20 /K22 dss_data4 LCD PixelData bit4 O AG24 /AC27 AD23 /AC25 AD21 /V21 dss_data5 LCD PixelData bit5 O AH24 /AC28 AD24 /AB25 AC21 /W21 dss_data6 LCD PixelData bit6 O E26 G26 D24 dss_data7 LCD PixelData bit7 O F28 H25 E23 dss_data8 LCD PixelData bit8 O F27 H26 E24 dss_data9 LCD PixelData bit9 O G26 J26 F23 dss_data10 LCD PixelData bit10 O AD28 AC26 AC22 Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 97 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-8.Video Interfaces– DSS SignalsDescription(continued) SIGNAL NAME DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] dss_data11 LCD PixelData bit11 O AD27 AD26 AC23 dss_data12 LCD PixelData bit12 O AB28 AA25 AB22 dss_data13 LCD PixelData bit13 O AB27 Y25 Y22 dss_data14 LCD PixelData bit14 O AA28 AA26 W22 dss_data15 LCD PixelData bit15 O AA27 AB26 V22 dss_data16 LCD PixelData bit16 O G25 L25 J22 dss_data17 LCD PixelData bit17 O H27 L26 G23 dss_data18 LCD PixelData bit18 O H26 /AH26 M24 /F3 G24 /AB12 dss_data19 LCD PixelData bit19 O H25 /AG26 M26 /D3 H23 /AC16 dss_data20 LCD PixelData bit20 O E28 /AF18 F25 /E3 D23 /AD18 dss_data21 LCD PixelData bit21 O J26 /AF19 N24 /E4 K22 /AC17 dss_data22 LCD PixelData bit22 O AC27 /AE21 AC25 /G23 V21 /AB16 dss_data23 LCD PixelData bit23 O AC28 /AF21 AB25 /D4 W21 /AA15 Table2-9.Video Interfaces– RFBI SignalsDescription SIGNAL DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM SUBSYSTEM PIN NAME [1] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] MULTIPLEXING [6] rfbi_a0 RFBI command/data control O E27 F26 J21 dss_acbias rfbi_cs0 1stLCD chipselect O D26 K24 E22 dss_hsync rfbi_da0 RFBI databus 0 IO AG22 /H26 AE21 /M24 AC19 /G24 dss_data0 rfbi_da1 RFBI databus 1 IO AH22 /H25 AE22 /M26 AB19 /H23 dss_data1 rfbi_da2 RFBI databus 2 IO AG23 /E28 AE23 /F25 AD20 /D23 dss_data2 rfbi_da3 RFBI databus 3 IO AH23 /J26 AE24 /N24 AC20 /K22 dss_data3 rfbi_da4 RFBI databus 4 IO AG24 /AC27 AD23 /AC25 AD21 /V21 dss_data4 rfbi_da5 RFBI databus 5 IO AH24 /AC28 AD24 /AB25 AC21 /W21 dss_data5 rfbi_da6 RFBI databus 6 IO E26 G26 D24 dss_data6 rfbi_da7 RFBI databus 7 IO F28 H25 E23 dss_data7 rfbi_da8 RFBI databus 8 IO F27 H26 E24 dss_data8 rfbi_da9 RFBI databus 9 IO G26 J26 F23 dss_data9 rfbi_da10 RFBI databus 10 IO AD28 AC26 AC22 dss_data10 rfbi_da11 RFBI databus 11 IO AD27 AD26 AC23 dss_data11 rfbi_da12 RFBI databus 12 IO AB28 AA25 AB22 dss_data12 rfbi_da13 RFBI databus 13 IO AB27 Y25 Y22 dss_data13 rfbi_da14 RFBI databus 14 IO AA28 AA26 W22 dss_data14 rfbi_da15 RFBI databus 15 IO AA27 AB26 V22 dss_data15 rfbi_rd Read enableforRFBI O D28 G25 G22 dss_pclk rfbi_wr WriteEnableforRFBI O D27 M25 F22 dss_vsync rfbi_te_vsynctearingeffectremovaland Vsync input I G25 L25 J22 dss_data16 0 from1stLCD rfbi_hsync0 Hsync for1stLCD I H27 L26 G23 dss_data17 rfbi_te_vsynctearingeffectremovaland Vsync input I H26 /AH26 M24 /F3 G24 /AB12 dss_data18 1 from2nd LCD rfbi_hsync1 Hsync for2nd LCD I H25 /AG26 M26 /D3 H23 /AC16 dss_data19 rfbi_cs1 2nd LCD chipselect O E28 /AF18 F25 /E3 D23 /AD18 dss_data20

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-10.Video Interfaces– TV SignalsDescription SIGNAL NAME DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] cvideo1_out TV analogoutputComposite: AO Y28 W26 AB24 cvideo1_out cvideo2_out TV analogoutputS-VIDEO: cvideo2_out AO W28 V26 AA23 cvideo1_vfb cvideo1_vfb:Feedback throughexternal AO Y27 W25 AB23 resistortocomposite cvideo2_vfb cvideo2_vfb:Feedback throughexternal AO W27 U24 Y23 resistortoS-VIDEO cvideo1_rset cvideo1inputreferencecurrentresistor AIO W26 V23 Y24 setting Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 99 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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2.5.3 SerialCommunication Interfaces

For more information,see HDQ/1-Wire /HDQ/1-Wire EnvironmentsectionoftheAM/DM37x Multimedia DeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-11.SerialCommunication Interfaces– HDQ/1-Wire SignalsDescription SIGNAL DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM NAME [1] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] hdq_sio BidirectionalHDQ 1-Wirecontroland data IOD J25 J23 A24 Interface.Outputisopen drain. For more information,see MultimasterHigh-Speed I2C Controller/ HS I2C Environmentsectionof the AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-12.SerialCommunication Interfaces– I2C SignalsDescription SIGNAL NAME DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] INTER-INTEGRATED CIRCUIT INTERFACE (I2C1) i2c1_scl OD K21 J25 K20I2C MasterSerialclock.Outputisopen drain. i2c1_sda IOD J21 J24 K21I2C SerialBidirectionalData.Outputis open drain. INTER-INTEGRATED CIRCUIT INTERFACE (I2C3) i2c3_scl OD AF14 AB4 AC13I2C MasterSerialclock.Outputisopen drain. i2c3_sda IOD AG14 AC4 AC12I2C SerialBidirectionalData.Outputis open drain. i2c3_sccbe SerialCamera ControlBus Enable OD J25 J23 A24 INTER-INTEGRATED CIRCUIT INTERFACE (I2C2) i2c2_scl OD AF15 C2 AC15I2C MasterSerialclock.Outputisopen drain. i2c2_sda IOD AE15 C1 AC14I2C SerialBidirectionalData.Outputis open drain. i2c2_sccbe SerialCamera ControlBus Enable OD J25 J23 A24 For more information,see Power Reset and Clock Management / PRCM Introductionto Power Management / SmartReflexVoltage-ControlOverview sectionof the AM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-13.SerialCommunication Interfaces– SmartReflexSignalsDescription(1) SIGNAL NAME DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] INTER-INTEGRATED CIRCUIT INTERFACE (I2C4) i2c4_scl OD AD26 AD15 Y16I2C MasterSerialclock.Outputisopen drain. i2c4_sda IOD AE26 W16 Y15I2C SerialBidirectionalData.Outputis open drain. (1) Formore informationon SmartReflexvoltagecontrol,see thePRCM chapteroftheAM/DM37x MultimediaDeviceTechnicalReference Manual (literaturenumber SPRUGN4 ). For more information,see Multi-ChannelBufferedSerialPort / McBSP Environmentsectionof the AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-14.SerialCommunication Interfaces– McBSP LP SignalsDescription SIGNAL NAME DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] MULTICHANNEL SERIAL (McBSP LP 1)

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-14.SerialCommunication Interfaces– McBSP LP SignalsDescription(continued) SIGNAL NAME DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] mcbsp1_dr Receivedserialdata I U21 T20 Y18 mcbsp1_clkr ReceiveClock IO Y8 /Y21 U19 /H3 V7 /W19 mcbsp1_fsr Receiveframesynchronization IO AA21 V17 AB20 mcbsp1_dx Transmittedserialdata O V21 U17 W18 mcbsp1_clkx Transmitclock IO W21 T17 V18 mcbsp1_fsx Transmitframesynchronization IO K26 P20 AA19 mcbsp_clks Externalclockinput(sharedby McBSP1, 2, I T21 T19 AA18 3,4,and 5) MULTICHANNEL SERIAL (McBSP LP 2) mcbsp2_dr Receivedserialdata I R21 T18 V19 mcbsp2_dx Transmittedserialdata O M21 R19 R20 mcbsp2_clkx Combined serialclock IO N21 R18 T21 mcbsp2_fsx Combined framesynchronization IO P21 U18 V20 MULTICHANNEL SERIAL (McBSP LP 3) mcbsp3_dr Receivedserialdata I AE6 /AB25 /U21 T20 /AA24 /N3 V5 /Y18 mcbsp3_dx Transmittedserialdata O AF6 /AB26 /V21 U17 /Y24 /P3 V6 /W18 mcbsp3_clkx Combined serialclock IO AF5 /AA25 /W21 T17 /AD22 /U3 W4 /V18 mcbsp3_fsx Combined framesynchronization IO AE5 /AD25 /K26 P20 /AD21 /W3 V4 /AA19 MULTICHANNEL SERIAL (McBSP LP 4) mcbsp4_dr Receivedserialdata I R8 /AD1 C4 /U4 G5 mcbsp4_dx Transmittedserialdata O P8 /AD2 B5 /R3 F3 mcbsp4_clkx Combined serialclock IO T8 /AE1 B4 /V3 F4 mcbsp4_fsx Combined framesynchronization IO N8 /AC1 C5 /T3 G4 MULTICHANNEL SERIAL (McBSP LP 5) mcbsp5_dr Receivedserialdata I AE11 Y3 AC5 mcbsp5_dx Transmittedserialdata O AF13 AE3 AC8 mcbsp5_clkx Combined serialclock IO AF10 AB2 AC1 mcbsp5_fsx Combined framesynchronization IO AH9 AB1 AD2 For more information,see MultichannelSPI / McSPI Environmentsectionof theAM/DM37x Multimedia DeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-15.SerialCommunication Interfaces– McSPI SignalsDescription(1) SIGNAL NAME DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] MULTICHANNEL SERIAL PORT INTERFACE (McSPI1) mcspi1_clk SPI Clock IO AB3 P9 T5 mcspi1_simo Slavedatain,masterdataout IO AB4 P8 R4 mcspi1_somi Slavedataout,masterdatain IO AA4 P7 T4 mcspi1_cs0 SPI Enable0,polarityconfiguredby IO AC2 R7 T6 software mcspi1_cs1 SPI Enable1,polarityconfiguredby O AC3 R8 NA software mcspi1_cs2 SPI Enable2,polarityconfiguredby O AB1 R9 NA software mcspi1_cs3 SPI Enable3,polarityconfiguredby O AB2 T8 R5 software MULTICHANNEL SERIAL PORT INTERFACE (McSPI2) mcspi2_clk SPI Clock IO AA3 W7 N5 mcspi2_simo Slavedatain,masterdataout IO Y2 W8 N4 mcspi2_somi Slavedataout,masterdatain IO Y3 U8 N3 mcspi2_cs0 SPI Enable0,polarityconfiguredby IO Y4 V8 M5 software Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 101 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-15.SerialCommunication Interfaces– McSPI SignalsDescription(1)(continued) SIGNAL NAME DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] mcspi2_cs1 SPI Enable1,polarityconfiguredby O V3 V9 M4 software MULTICHANNEL SERIAL PORT INTERFACE (McSPI3) mcspi3_clk SPI Clock IO H26 /AE2 /AE13 W10 /M24 /AA3 G24 /Y1 /AD8 mcspi3_simo Slavedatain,masterdataout IO H25 /AG5 /AF11 R10 /M26 /AC3 H23 /AB5 /AD6 mcspi3_somi Slavedataout,masterdatain IO E28 /AH5 /AG12 F25 /T10 /AD4 D23 /AB3 /AC6 mcspi3_cs0 SPI Enable0,polarityconfiguredby IO J26 /AF4 /AH12 U9 /N24 /AD3 K22 /V3 /AC7 software mcspi3_cs1 SPI Enable1,polarityconfiguredby O AC27 /AG4 /AH14 AC25 /U10 /AD2 V21 /W3 /AD9 software MULTICHANNEL SERIAL PORT INTERFACE (McSPI4) mcspi4_clk SPI Clock IO Y8 /Y21 U19 /H3 V7 /W19 mcspi4_simo Slavedatain,masterdataout IO V21 U17 W18 mcspi4_somi Slavedataout,masterdatain IO U21 T20 Y18 mcspi4_cs0 SPI Enable0,polarityconfiguredby IO K26 P20 AA19 software (1) NA inthistablestandsfor"Notapplicable". For more information,see UART/IrDA/CIR / UART/IrDA/CIR Environmentsectionof the AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-16.SerialCommunication Interfaces– UARTs SignalsDescription SIGNAL NAME DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART1) uart1_cts UART1 ClearTo Send I AG22 /W8 /T21 AE21 /T19 /W2 AC19 /AC2 /AA18 uart1_rts UART1 RequestTo Send O AH22 /AA9 AE22 /R2 W6 /AB19 uart1_rx UART1 Receivedata I F28 /Y8 /AE7 H3 /H25 /AE4 E23 /V7 /AC3 uart1_tx UART1 Transmitdata O E26 /AA8 L4 /G26 D24 /W7 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART2) uart2_cts UART2 ClearTo Send I AF6 /AB26 /U26 Y24/P3/W20 V6/U23 uart2_rts UART2 RequestTo Send O AE6 /AB25 /U27 AA24/ N3/ V18 V5/U24 uart2_rx UART2 Receivedata I AE5 /AD25/ U28 W3/ AD21/ Y20 T23/V4 uart2_tx UART2 Transmitdata O AF5 /AA25/ T27 U3/AD22/V20 T24/W4 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART3) /IrDA uart3_cts_rctx UART3 ClearTo Send (input), IO H18 /U26 W20 /F23 A23 /U23 Remote TX (output) uart3_rts_sd UART3 RequestTo Send,IR enable O H19 /U27 V18 /F24 B23 /U24 uart3_rx_irrx UART3 Receivedata,IR and I AG24 /H20 /U28 /F27 AD23 /Y20 /H24/ H26 AD21 /B24 /T23 /E24 Remote RX uart3_tx_irtx UART3 Transmitdata,IR TX O AH24 /H21 /T27/G26 AD24 /V20 /J29 /G24 AC21 /C23 /T24/F23 UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART4) /IrDA uart4_rx UART4 Receivedata I J8 C6 NA uart4_tx UART4 Transmitdata O K8 B3 NA For more information,see High-Speed USB Host Subsystem and High-Speed USB OTG Controller/ High-Speed USB Host Subsystem / High-Speed USB Host Subsystem Environmentsectionof the AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-17.SerialCommunication Interfaces– USB SignalsDescriptionSection4.3.6 SIGNAL NAME DESCRIPTION [2] TYPE BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] [3] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] HIGH-SPEED UNIVERSAL SERIAL BUS INTERFACE (HSUSB0)

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-17.SerialCommunication Interfaces– USB SignalsDescriptionSection4.3.6(continued) SIGNAL NAME DESCRIPTION [2] TYPE BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] [3] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] hsusb0_clk Dedicatedforexternaltransceiver60-MHz clockinputtoPHY I T28 W19 R21 hsusb0_stp DedicatedforexternaltransceiverStopsignal O T25 U20 R23 hsusb0_dir DedicatedforexternaltransceiverData directioncontrolfrom I R28 V19 P23 PHY hsusb0_nxt DedicatedforexternaltransceiverNextsignalfromPHY I T26 W18 R22 hsusb0_data0 DedicatedforexternaltransceiverBidirectionaldatabus IO T27 V20 T24 hsusb0_data1 DedicatedforexternaltransceiverBidirectionaldatabus IO U28 Y20 T23 hsusb0_data2 DedicatedforexternaltransceiverBidirectionaldatabus IO U27 V18 U24 hsusb0_data3 DedicatedforexternaltransceiverBidirectionaldatabus IO U26 W20 U23 hsusb0_data4 DedicatedforexternaltransceiverBidirectionaldatabus IO U25 W17 W24 additionalsignalsfor12-pinULPI operation hsusb0_data5 DedicatedforexternaltransceiverBidirectionaldatabus IO V28 Y18 V23 additionalsignalsfor12-pinULPI operation hsusb0_data6 DedicatedforexternaltransceiverBidirectionaldatabus IO V27 Y19 W23 additionalsignalsfor12-pinULPI operation hsusb0_data7 DedicatedforexternaltransceiverBidirectionaldatabus IO V26 Y17 T22 additionalsignalsfor12-pinULPI operation MM_FSUSB3 mm3_rxdm Vminus receivedata(notused in3-or4-pinconfigurations) IO AE3 K3 NA mm3_rxdp Vplusreceivedata(notused in3-or4-pinconfigurations) IO AH3 M3 NA mm3_rxrcv Differentialreceiversignalinput(notused in3-pinmode) IO AD1 U4 NA mm3_txse0 Single-endedzero.Used as VM in4-pinVP_VM mode. IO AE1 V3 NA mm3_txdat USB data.Used as VP in4-pinVP_VM mode. IO AD2 R3 NA mm3_txen_n Transmitenable IO AC1 T3 NA MM_FSUSB2 mm2_rxdm Vminus receivedata(notused in3-or4-pinconfigurations) IO AH7 AF7 AD11 mm2_rxdp Vplusreceivedata(notused in3-or4-pinconfigurations) IO AF7 AF6 AC9 mm2_rxrcv Differentialreceiversignalinput(notused in3-pinmode) IO AG8 AF9 AC11 mm2_txse0 Single-endedzero.Used as VM in4-pinVP_VM mode. IO AH8 AE9 AD12 mm2_txdat USB data.Used as VP in4-pinVP_VM mode. IO AB2 T8 R5 mm2_txen_n Transmitenable IO V3 V9 M4 MM_FSUSB1 mm1_rxdm Vminus receivedata(notused in3-or4-pinconfigurations) IO AG9 V2 AD5 mm1_rxdp Vplusreceivedata(notused in3-or4-pinconfigurations) IO AF10 AB2 AC1 mm1_rxrcv Differentialreceiversignalinput(notused in3-pinmode) IO AF11 AC3 AD6 mm1_txse0 Single-endedzero.Used as VM in4-pinVP_VM mode. IO AG12 AD4 AC6 mm1_txdat USB data.Used as VP in4-pinVP_VM mode. IO AH12 AD3 AC7 mm1_txen_n Transmitenable IO AH14 AD2 AD9 HSUSB2 hsusb2_clk Dedicatedforexternaltransceiver60-MHz clockinputtoPHY O AE7 AE4 AC3 hsusb2_stp DedicatedforexternaltransceiverStopsignal O AF7 AF6 AC9 hsusb2_dir DedicatedforexternaltransceiverData directioncontrolfrom I AG7 AE6 AC10 PHY hsusb2_nxt DedicatedforexternaltransceiverNextsignalfromPHY I AH7 AF7 AD11 hsusb2_data0 DedicatedforexternaltransceiverBidirectionaldatabus IO AG8 AF9 AC11 hsusb2_data1 DedicatedforexternaltransceiverBidirectionaldatabus IO AH8 AE9 AD12 hsusb2_data2 DedicatedforexternaltransceiverBidirectionaldatabus IO AB2 T8 R5 hsusb2_data3 DedicatedforexternaltransceiverBidirectionaldatabus IO V3 V9 M4 hsusb2_data4 DedicatedforexternaltransceiverBidirectionaldatabus IO Y2 W8 N4 additionalsignalsfor12-pinULPI operation hsusb2_data5 DedicatedforexternaltransceiverBidirectionaldatabus IO Y3 U8 N3 additionalsignalsfor12-pinULPI operation hsusb2_data6 DedicatedforexternaltransceiverBidirectionaldatabus IO Y4 V8 M5 additionalsignalsfor12-pinULPI operation Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 103 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-17.SerialCommunication Interfaces– USB SignalsDescriptionSection4.3.6(continued) SIGNAL NAME DESCRIPTION [2] TYPE BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] [3] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] hsusb2_data7 DedicatedforexternaltransceiverBidirectionaldatabus IO AA3 W7 N5 additionalsignalsfor12-pinULPI operation HSUSB1 hsusb1_clk Dedicatedforexternaltransceiver60-MHz clockinputtoPHY O AE10 AB3 AD3 hsusb1_stp DedicatedforexternaltransceiverStopsignal O AF10 AB2 AC1 hsusb1_dir Dedicatedforexternaltransceiverdatadirectioncontrolfrom I AF9 AA4 AC4 PHY hsusb1_nxt DedicatedforexternaltransceiverNextsignalfromPHY I AG9 V2 AD5 hsusb1_data0 DedicatedforexternaltransceiverBidirectionaldatabus IO AF11 AC3 AD6 hsusb1_data1 DedicatedforexternaltransceiverBidirectionaldatabus IO AG12 AD4 AC6 hsusb1_data2 DedicatedforexternaltransceiverBidirectionaldatabus IO AH12 AD3 AC7 hsusb1_data3 DedicatedforexternaltransceiverBidirectionaldatabus IO AH14 AD2 AD9 hsusb1_data4 DedicatedforexternaltransceiverBidirectionaldatabus IO AE11 Y3 AC5 additionalsignalsfor12-pinULPI operation hsusb1_data5 DedicatedforexternaltransceiverBidirectionaldatabus IO AH9 AB1 AD2 additionalsignalsfor12-pinULPI operation hsusb1_data6 DedicatedforexternaltransceiverBidirectionaldatabus IO AF13 AE3 AC8 additionalsignalsfor12-pinULPI operation hsusb1_data7 DedicatedforexternaltransceiverBidirectionaldatabus IO AE13 AA3 AD8 additionalsignalsfor12-pinULPI operation

• NA inthistablestandsfor"Notapplicable".
• Thispinisnotsupportedon theCUS package.

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2.5.4 Removable Media Interfaces

For more information,see MMC/SDIO Card Interface/MMC/SDIO EnvironmentsectionoftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-18.Removable Media Interfaces– MMC/SDIO SignalsDescription SIGNAL NAME DESCRIPTION [2] TYPE BALL BOTTOM BALL BOTTOM BALL BOTTOM [1] [3] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] MULTIMEDIA MEMORY CARD (MMC1) /SECURE DIGITAL IO (SDIO1) mmc1_clk MMC/SD OutputClock O N28 N19 M23 mmc1_cmd MMC/SD command signal IO M27 L18 L23 mmc1_dat0 MMC/SD Card Data bit0 /SPI SerialInput IO N27 M19 M22 mmc1_dat1 MMC/SD Card Data bit1 IO N26 M18 M21 mmc1_dat2 MMC/SD Card Data bit2 IO N25 K18 M20 mmc1_dat3 MMC/SD Card Data bit3 IO P28 N20 N23 MULTIMEDIA MEMORY CARD (MMC2) /SECURE DIGITAL IO (SDIO2) mmc2_clk MMC/SD OutputClock O AE2 W10 Y1 mmc2_dir_dat0 DirectioncontrolforDAT0 signalcase an external O AE4 V10 AB2 transceiverused mmc2_dir_dat1 DirectioncontrolforDAT1 and DAT3 signalscase an O AH3 M3 AA2 externaltransceiverused mmc2_dir_dat2 DirectioncontrolforDAT2 signalcase an external O AF19 E4 AC17 transceiverused mmc2_dir_dat3 DirectioncontrolforDAT4, DAT5, DAT6, and DAT7 O AE21 G3 AB16 signalscase an externaltransceiverused mmc2_clkin MMC/SD inputClock I AE3 K3 AA1 mmc2_dat0 MMC/SD Card Data bit0 IO AH5 T10 AB3 mmc2_dat1 MMC/SD Card Data bit1 IO AH4 T9 Y3 mmc2_dat2 MMC/SD Card Data bit2 IO AG4 U10 W3 mmc2_dat3 MMC/SD Card Data bit3 IO AF4 U9 V3 mmc2_dat4 MMC/SD Card Data bit4 IO AE4 /AB3 P9 /V10 AB2 /T5 mmc2_dat5 MMC/SD Card Data bit5 IO AH3 /AB4 M3/P8 AA2 /R4 mmc2_dat6 MMC/SD Card Data bit6 IO AF3 /AA4 L3/P7 Y2 /T4 mmc2_dat7 MMC/SD Card Data bit7 IO AE3 /AC2 K3/R7 AA1 /T6 mmc2_dir_cmd DirectioncontrolforCMD signalcase an external O AF3 L3 Y2 transceiverisused mmc2_cmd MMC/SD command signal IO AG5 R10 AB5 MULTIMEDIA MEMORY CARD (MMC3) /SECURE DIGITAL IO (SDIO3) mmc3_clk MMC/SD OutputClock O AB1 /AF10 R9 /AB2 AC1 mmc3_cmd MMC/SD command signal IO AC3 /AE10 R8 /AB3 AD3 mmc3_dat0 MMC/SD Card Data bit0 /SPI SerialInput IO AE4 /AE11 V10 /Y3 AB2 /AC5 mmc3_dat1 MMC/SD Card Data bit1 IO AH3 /AH9 M3/AB1 AA2 /AD2 mmc3_dat2 MMC/SD Card Data bit2 IO AF3 /AF13 L3/AE3 Y2 /AC8 mmc3_dat3 MMC/SD Card Data bit3 IO AE3 /AE13 K3/AA3 AA1 /AD8 mmc3_dat4 MMC/SD Card Data bit4 IO AF11 AC3 AD6 mmc3_dat5 MMC/SD Card Data bit5 IO AG9 V2 AD5 mmc3_dat6 MMC/SD Card Data bit6 IO AF9 AA4 AC4 mmc3_dat7 MMC/SD Card Data bit7 IO AH14 AD2 AD9 Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 105 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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2.5.5 TestInterfaces

Table2-19.TestInterfaces– ETK SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] etk_ctl ETK tracectl O AE10 AB3 AD3 etk_clk ETK traceclock O AF10 AB2 AC1 etk_d0 ETK data0 O AF11 AC3 AD6 etk_d1 ETK data1 O AG12 AD4 AC6 etk_d2 ETK data2 O AH12 AD3 AC7 etk_d3 ETK data3 O AE13 AA3 AD8 etk_d4 ETK data4 O AE11 Y3 AC5 etk_d5 ETK data5 O AH9 AB1 AD2 etk_d6 ETK data6 O AF13 AE3 AC8 etk_d7 ETK data7 O AH14 AD2 AD9 etk_d8 ETK data8 O AF9 AA4 AC4 etk_d9 ETK data9 O AG9 V2 AD5 etk_d10 ETK data10 O AE7 AE4 AC3 etk_d11 ETK data11 O AF7 AF6 AC9 etk_d12 ETK data12 O AG7 AE6 AC10 etk_d13 ETK data13 O AH7 AF7 AD11 etk_d14 ETK data14 O AG8 AF9 AC11 etk_d15 ETK data15 O AH8 AE9 AD12 Table2-20.TestInterfaces– JTAG SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] jtag_ntrst TestReset I AA17 U15 AB7 jtag_tck TestClock I AA13 V14 AB6 jtag_rtck ARM Clock O AA12 W13 AA7 Emulation jtag_tms_tmsc TestMode Select IO AA18 V15 AA9 jtag_tdi TestData Input I AA20 U16 AB10 jtag_tdo TestData Output O AA19 Y13 AB9 jtag_emu0 Testemulation0 IO AA11 Y15 AC24 jtag_emu1 Testemulation1 IO AA10 Y14 AD24

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-21.TestInterfaces– SDTI SignalsDescription SIGNAL DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM SUBSYSTEM NAME [1] (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] SIGNAL MULTIPLEXING [6] sdti_clk Serialclockdualedge O AF7 /AA11 /AG8 AF6 /Y15 /AF9 AC9 /AC24 /AC11 etk_d11/jtag_emu0/ etk_d14 sdti_txd0 Serialdataout(SystemTrace O AG7 /AA10 /AA11 AE6 /Y14 /Y15 AC10 /AD24 / etk_d12/jtag_emu1/ messages) AC24 jtag_emu0 sdti_txd1 Serialdataout(SystemTrace O AH7 /AA10 AF7 /Y14 AD11 /AD24 etk_d13/jtag_emu1 messages) sdti_txd2 Serialdataout(SystemTrace O AG8 AF9 AC11 etk_d14 messages) sdti_txd3 Serialdataout(SystemTrace O AH8 AE9 AD12 etk_d15 messages) Table2-22.TestInterfaces– HWDBG SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] hw_dbg0 Debug signal0 O A24 /AF10 C23/AB2 AC1/A22 hw_dbg1 Debug signal1 O A23 /AE10 D23/AB3 AD3/E18 hw_dbg2 Debug signal2 O C27/ AF11 C26/AC3 AD6/J19 hw_dbg3 Debug signal3 O C23 /AG12 B23/AD4 AC6/H24 hw_dbg4 Debug signal4 O B24 /AH12 A24/AD3 AC7/G19 hw_dbg5 Debug signal5 O C24 /AE13 B24/AA3 AD8/F19 hw_dbg6 Debug signal6 O D24 /AE11 D24/Y3 AC5/G20 hw_dbg7 Debug signal7 O A25 /AH9 C24/AB1 AD2/B21 hw_dbg8 Debug signal8 O B25 /AF13 D25/AE3 AC8/F21 hw_dbg9 Debug signal9 O C26 /AH14 E26/AD2 AD9/G21 hw_dbg10 Debug signal10 O B23 /AF9 A23/AA4 AC4/F18 hw_dbg11 Debug signal11 O D25 /AG9 D26/V2 AD5/J20 hw_dbg12 Debug signal12 O D28 /AE7 G25/AE4 AC3/G22 hw_dbg13 Debug signal13 O D26 /AF7 K24/AF6 AC9/E22 hw_dbg14 Debug signal14 O E26 /AG7 G26/AE6 AC10/D24 hw_dbg15 Debug signal15 O F28 /AH7 H25/AF7 AD11/E23 hw_dbg16 Debug signal16 O F27 /AG8 H26/AF9 AC11/E24 hw_dbg17 Debug signal17 O G26 /AH8 J26/AE9 AD12/F23

2.5.6 Miscellaneous

For more information,see Timers / GP Timers / GP Timers Environmentsectionof the AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-23.Miscellaneous– GP Timer SignalsDescription SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] gpt_8_pwm_evt PWM oreventforGP IO N8 /AD25 /V3 C5 /AD21/ V9 G4/ M4 timer8 gpt_9_pwm_evt PWM oreventforGP IO T8 /AB26 /Y2 B4 /W8 /Y24 F4 /N4 timer9 gpt_10_pwm_evt PWM oreventforGP IO R8 /AB25 /Y3 C4 /U8 /AA24 G5 /N3 timer10 gpt_11_pwm_evt PWM oreventforGP IO P8 /AA25 /Y4 B5 /V8 /AD22 F3 /M5 timer11 Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 107 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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2.5.7 General-PurposeIOs

For more information,see General-PurposeInterface/General-PurposeInterfaceEnvironmentsectionof theAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-24.General-PurposeIOs SignalsDescription(1) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] gpio_0 General-purposeIO 0 IO AF26 V16 W16 gpio_1 General-purposeIO 1 IO AF25 W15 Y13 gpio_2 General-purposeIO 2 IO AH26 F3 AB12 gpio_3 General-purposeIO 3 IO AG26 D3 AC16 gpio_4 General-purposeIO 4 IO AE14 C3 AD17 gpio_5 General-purposeIO 5 IO AF18 E3 AD18 gpio_6 General-purposeIO 6 IO AF19 E4 AC17 gpio_7 General-purposeIO 7 IO AE21 G3 AB16 gpio_8 General-purposeIO 8 IO AF21 D4 AA15 gpio_9 General-purposeIO 9 IO AF22 V12 AD23 gpio_10 General-purposeIO 10 IO AG25 AE14 Y7 gpio_11 General-purposeIO 11 IO AA11 Y15 AC24 gpio_12 General-purposeIO 12 IO AF10 AB2 AC1 gpio_13 General-purposeIO 13 IO AE10 AB3 AD3 gpio_14 General-purposeIO 14 IO AF11 AC3 AD6 gpio_15 General-purposeIO 15 IO AG12 AD4 AC6 gpio_16 General-purposeIO 16 IO AH12 AD3 AC7 gpio_17 General-purposeIO 17 IO AE13 AA3 AD8 gpio_18 General-purposeIO 18 IO AE11 Y3 AC5 gpio_19 General-purposeIO 19 IO AH9 AB1 AD2 gpio_20 General-purposeIO 20 IO AF13 AE3 AC8 gpio_21 General-purposeIO 21 IO AH14 AD2 AD9 gpio_22 General-purposeIO 22 IO AF9 AA4 AC4 gpio_23 General-purposeIO 23 IO AG9 V2 AD5 gpio_24 General-purposeIO 24 IO AE7 AE4 AC3 gpio_25 General-purposeIO 25 IO AF7 AF6 AC9 gpio_26 General-purposeIO 26 IO AG7 AE6 AC10 gpio_27 General-purposeIO 27 IO AH7 AF7 AD11 gpio_28 General-purposeIO 28 IO AG8 AF9 AC11 gpio_29 General-purposeIO 29 IO AH8 AE9 AD12 gpio_30 General-purposeIO 30 IO AF24 AD7 Y10 gpio_31 General-purposeIO 31 IO AA10 Y14 AD24 gpio_34 General-purposeIO 34 IO N4 J2 K4 gpio_35 General-purposeIO 35 IO M4 H1 K3 gpio_36 General-purposeIO 36 IO L4 H2 K2 gpio_37 General-purposeIO 37 IO K4 G2 J4 gpio_38 General-purposeIO 38 IO T3 F1 J3 gpio_39 General-purposeIO 39 IO R3 F2 J2 gpio_40 General-purposeIO 40 IO N3 E1 J1 gpio_41 General-purposeIO 41 IO M3 E2 H1 gpio_42 General-purposeIO 42 IO L3 D1 H2 gpio_43 General-purposeIO 43 IO K3 D2 G2 gpio_44 General-purposeIO 44 IO H2 V1 R2 gpio_45 General-purposeIO 45 IO K2 Y1 T2 gpio_46 General-purposeIO 46 IO P1 T1 U1 gpio_47 General-purposeIO 47 IO R1 U2 R3

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-24.General-PurposeIOs SignalsDescription(1) (continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] gpio_48 General-purposeIO 48 IO R2 U1 T3 gpio_49 General-purposeIO 49 IO T2 P1 U2 gpio_50 General-purposeIO 50 IO W1 L2 V1 gpio_51 General-purposeIO 51 IO Y1 M2 V2 gpio_52 General-purposeIO 52 IO H3 AD1 NA gpio_53 General-purposeIO 53 IO V8 A3 NA gpio_54 General-purposeIO 54 IO U8 B6 D2 gpio_55 General-purposeIO 55 IO T8 B4 F4 gpio_56 General-purposeIO 56 IO R8 C4 G5 gpio_57 General-purposeIO 57 IO P8 B5 F3 gpio_58 General-purposeIO 58 IO N8 C5 G4 gpio_59 General-purposeIO 59 IO T4 N1 W2 gpio_60 General-purposeIO 60 IO G3 K2 K5 gpio_61 General-purposeIO 61 IO U3 J1 L1 gpio_62 General-purposeIO 62 IO H1 AC6 E1 gpio_63 General-purposeIO 63 IO L8 AC8 NA gpio_64 General-purposeIO 64 IO K8 B3 NA gpio_65 General-purposeIO 65 IO J8 C6 C2 gpio_66 General-purposeIO 66 IO D28 G25 G22 gpio_67 General-purposeIO 67 IO D26 K24 E22 gpio_68 General-purposeIO 68 IO D27 M25 F22 gpio_69 General-purposeIO 69 IO E27 F26 J21 gpio_70 General-purposeIO 70 IO AG22 AE21 AC19 gpio_71 General-purposeIO 71 IO AH22 AE22 AB19 gpio_72 General-purposeIO 72 IO AG23 AE23 AD20 gpio_73 General-purposeIO 73 IO AH23 AE24 AC20 gpio_74 General-purposeIO 74 IO AG24 AD23 AD21 gpio_75 General-purposeIO 75 IO AH24 AD24 AC21 gpio_76 General-purposeIO 76 IO E26 G26 D24 gpio_77 General-purposeIO 77 IO F28 H25 E23 gpio_78 General-purposeIO 78 IO F27 H26 E24 gpio_79 General-purposeIO 79 IO G26 J26 F23 gpio_80 General-purposeIO 80 IO AD28 AC26 AC22 gpio_81 General-purposeIO 81 IO AD27 AD26 AC23 gpio_82 General-purposeIO 82 IO AB28 AA25 AB22 gpio_83 General-purposeIO 83 IO AB27 Y25 Y22 gpio_84 General-purposeIO 84 IO AA28 AA26 W22 gpio_85 General-purposeIO 85 IO AA27 AB26 V22 gpio_86 General-purposeIO 86 IO G25 L25 J22 gpio_87 General-purposeIO 87 IO H27 L26 G23 gpio_88 General-purposeIO 88 IO H26 M24 G24 gpio_89 General-purposeIO 89 IO H25 M26 H23 gpio_90 General-purposeIO 90 IO E28 F25 D23 gpio_91 General-purposeIO 91 IO J26 N24 K22 gpio_92 General-purposeIO 92 IO AC27 AC25 V21 gpio_93 General-purposeIO 93 IO AC28 AB25 W21 gpio_94 General-purposeIO 94 IO A24 C23 A22 gpio_95 General-purposeIO 95 IO A23 D23 E18 gpio_96 General-purposeIO 96 IO C25 C25 B22 gpio_97 General-purposeIO 97 IO C27 C26 J19 gpio_98 General-purposeIO 98 IO C23 B23 H24 Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 109 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-24.General-PurposeIOs SignalsDescription(1) (continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] gpio_99 General-purposeIO 99 I AG17 AE16 AB18 gpio_100 General-purposeIO 100 I AH17 AE15 AC18 gpio_101 General-purposeIO 101 IO B24 A24 G19 gpio_102 General-purposeIO 102 IO C24 B24 F19 gpio_103 General-purposeIO 103 IO D24 D24 G20 gpio_104 General-purposeIO 104 IO A25 C24 B21 gpio_105 General-purposeIO 105 I K28 P25 L24 gpio_106 General-purposeIO 106 I L28 P26 K24 gpio_107 General-purposeIO 107 I K27 N25 J23 gpio_108 General-purposeIO 108 I L27 N26 K23 gpio_109 General-purposeIO 109 IO B25 D25 F21 gpio_110 General-purposeIO 110 IO C26 E26 G21 gpio_111 General-purposeIO 111 IO B26 E25 C22 gpio_112 General-purposeIO 112 I AG19 AD17 NA gpio_113 General-purposeIO 113 I AH19 AD16 NA gpio_114 General-purposeIO 114 I AG18 AE18 NA gpio_115 General-purposeIO 115 I AH18 AE17 NA gpio_116 General-purposeIO 116 IO P21 U18 V20 gpio_117 General-purposeIO 117 IO N21 R18 T21 gpio_118 General-purposeIO 118 IO R21 T18 V19 gpio_119 General-purposeIO 119 IO M21 R19 R20 gpio_120 General-purposeIO 120 IO N28 (3)/T28 W19 /N19 (3) M23 (3)/R21 gpio_121 General-purposeIO 121 IO M27 (3)/T25 U20 /L18(3) L23(3)/R23 gpio_122 General-purposeIO 122 IO N27 (3)/R28 V19 /M19 (3) M22 (3)/P23 gpio_123 General-purposeIO 123 IO N26 (3) M18 (3) M21 (3) gpio_124 General-purposeIO 124 IO N25 (3)/T26 W18 /K18(3) M20 (3)/R22 gpio_125 General-purposeIO 125 IO P28(3)/T27 V20 /N20 (3) N23 (3)/T24 gpio_126 General-purposeIO 126 IO D25 /P27(3) M20 (3)/D26 J20 /N22 (3) gpio_127 General-purposeIO 127 IO P26(3) P17(3) NA gpio_128 General-purposeIO 128 IO R27 P18 NA gpio_129 General-purposeIO 129 IO R25 (3) P19(3) P24(3) gpio_130 General-purposeIO 130 IO AE2 /U28 Y20 /W10 Y1 /T23 gpio_131 General-purposeIO 131 IO AG5 /U27 V18 /R10 AB5 /U24 gpio_132 General-purposeIO 132 IO AH5 T10 AB3 gpio_133 General-purposeIO 133 IO AH4 T9 Y3 gpio_134 General-purposeIO 134 IO AG4 U10 W3 gpio_135 General-purposeIO 135 IO AF4 U9 V3 gpio_136 General-purposeIO 136 IO AE4 V10 AB2 gpio_137 General-purposeIO 137 IO AH3 M3 AA2 gpio_138 General-purposeIO 138 IO AF3 L3 Y2 gpio_139 General-purposeIO 139 IO AE3 K3 AA1 gpio_140 General-purposeIO 140 IO AF6 P3 V6 gpio_141 General-purposeIO 141 IO AE6 N3 V5 gpio_142 General-purposeIO 142 IO AF5 U3 W4 gpio_143 General-purposeIO 143 IO AE5 W3 V4 gpio_144 General-purposeIO 144 IO AB26 Y24 NA gpio_145 General-purposeIO 145 IO AB25 AA24 NA gpio_146 General-purposeIO 146 IO AA25 AD22 NA gpio_147 General-purposeIO 147 IO AD25 AD21 NA gpio_148 General-purposeIO 148 IO AA8 L4 W7 gpio_149 General-purposeIO 149 IO AA9 R2 W6

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-24.General-PurposeIOs SignalsDescription(1) (continued) SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] BALL BOTTOM BALL BOTTOM BALL BOTTOM (CBP Pkg.)[4] (CBC Pkg.)[4] (CUS Pkg.)[4] gpio_150 General-purposeIO 150 IO W8 W2 AC2 gpio_151 General-purposeIO 151 IO Y8 H3 V7 gpio_152 General-purposeIO 152 IO AE1 V3 NA gpio_153 General-purposeIO 153 IO AD1 U4 NA gpio_154 General-purposeIO 154 IO AD2 R3 NA gpio_155 General-purposeIO 155 IO AC1 T3 NA gpio_156 General-purposeIO 156 IO Y21 U19 W19 gpio_157 General-purposeIO 157 IO AA21 V17 AB20 gpio_158 General-purposeIO 158 IO V21 U17 W18 gpio_159 General-purposeIO 159 IO U21 T20 Y18 gpio_160 General-purposeIO 160 IO T21 T19 AA18 gpio_161 General-purposeIO 161 IO K26 P20 AA19 gpio_162 General-purposeIO 162 IO W21 T17 V18 gpio_163 General-purposeIO 163 IO H18 F23 A23 gpio_164 General-purposeIO 164 IO H19 F24 B23 gpio_165 General-purposeIO 165 IO H20 H24 B24 gpio_166 General-purposeIO 166 IO H21 G24 C23 gpio_167 General-purposeIO 167 IO B23 A23 F18 gpio_168 General-purposeIO 168 IO AF15 C2 AC15 gpio_169 General-purposeIO 169 IO U26 W20 U23 gpio_170 General-purposeIO 170 IO J25 J23 A24 gpio_171 General-purposeIO 171 IO AB3 P9 T5 gpio_172 General-purposeIO 172 IO AB4 P8 R4 gpio_173 General-purposeIO 173 IO AA4 P7 T4 gpio_174 General-purposeIO 174 IO AC2 R7 T6 gpio_175 General-purposeIO 175 IO AC3 R8 NA gpio_176 General-purposeIO 176 IO AB1 R9 NA gpio_177 General-purposeIO 177 IO AB2 T8 R5 gpio_178 General-purposeIO 178 IO AA3 W7 N5 gpio_179 General-purposeIO 179 IO Y2 W8 N4 gpio_180 General-purposeIO 180 IO Y3 U8 N3 gpio_181 General-purposeIO 181 IO Y4 V8 M5 gpio_182 General-purposeIO 182 IO V3 V9 M4 gpio_183 General-purposeIO 183 IO AE15 C1 AC14 gpio_184 General-purposeIO 184 IO AF14 AB4 AC13 gpio_185 General-purposeIO 185 IO AG14 AC4 AC12 gpio_186 General-purposeIO 186 IO AE22 W11 AA6 gpio_188 General-purposeIO 188 IO U25 W17 W24 gpio_189 General-purposeIO 189 IO V28 Y18 V23 gpio_190 General-purposeIO 190 IO V27 Y19 W23 gpio_191 General-purposeIO 191 IO V26 Y17 T22 (1) NA intablestandsfor"NotApplicable". (2) The subsystempinmultiplexingoptionsarenotdescribedinTable2-1and Table2-4. (3) The usage ofthisGPIO isstronglyrestricted.Formore information,see theGeneral-PurposeInterface/General-PurposeInterface EnvironmentsectionoftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 111 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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2.5.8 Power Supplies

Note: For more information,see Power Reset and Clock Management / PRCM Environmentand the Power, Reset,and Clock Management / PRCM FunctionalDescription/ PRCM VoltageManagement FunctionalDescriptionsectionsof the AM/DM37x MultimediaDevice TechnicalReference Manual (literaturenumber SPRUGN4 ). Table2-25.Power SuppliesSignalsDescription(1) SIGNAL NAME [1] DESCRIPTION [2] BALL BOTTOM BALL TOP BALL BOTTOM BALL TOP BALL BOTTOM vdd_mpu_iva MPU/IVA power Y9 /W9 /T9 / NA H7/ N7/ U7/ V7/N8/ NA W13/ W12/ V13/ supply R9 /M9 /L9 /J9 G9/ L9/M9/ W9/ Y9/ V12/U13/ U12/ T8/ /Y10 /U10 /T10 M10/ P10/K11/U11/ T7/R8/ R7/ R6/ N8/ /R10 /N10 / V11/Y11/G12/ D13/ N7/ N6/ M12/ M8/ M10 /L10 /J10 / U13 M7/ M6/ L12/L11/ Y11 /W11 /K11 J10/J9/H10/ H9/ /J11 /W12 /K13 G10/ G9/F10 /Y14 /K14 /J14 /Y15 /W15 /J15 vdd_core Core power domain AC4 /J4 /H4 / NA M7/ T7/Y8/G11/ NA T20/T19/T18/T17/ D8 /AE9 /D9 / Y12/D15/ M17/ G18/ R19/ R18/ R17/ D15 /Y16 / H20/ R20/ AC21 M15/ M14/ L15/ AE18 /Y18 / L14/K19/K18/K17/ W18 /K18 /J18 / J18/J17/H13/ H12/ AE19 /Y19 / G13/ G12/ F13/F12 U19 /T19 /N19 / M19 /J19 /Y20 / W20 /V20 /U20 /P20 /N20 /K20 /J20 /D22 /D23 /AE24 /M25 / L25 /E25 cap_vddu_wkup_ Decoupling AA15 NA K14 NA Y12 logic capacitorfor WKUP/EMU domains (logic) vdda_dplls_dll Inputpower forthe K15 NA K13 NA G18 analogpartofthe MPU, CORE DPLLs, IVA,and the DLL vdda_dac VideoDAC power V25 NA V25 NA AB13 plane vssa_dac VideoDAC ground Y26 NA V24 NA AB15 plane vdds 1.8-Vpower for AD3 /AD4 /W4 / NA G4/ M4/ T4/Y4/L7/ A3 /A15 /B5 /F2 / Y9 /W10 /W9 /V10 standardIOs AF8 /AE8 / AC7/ D9/ AE10/ C11/ F21/L20 /W21 /V9 /U10 /N19 / AF16 /AE16 / J15/AC15/ A18/J18/ N18 /N17 /M19 / AF23 /AE23 / AC18/ AD20/ E24/ M18 /M17 F25 /F26 /AG27 L24/T24/W24/ AC24 /AB24 vdds_mem Memory IO power U1 /J1 /F1 /J2 / AC5 /P1 /H1 /F23 NA NA K8 /K7 /K6 /J8 / plane F2 /R4 /B5 /A5 /E1 /C23 /A4 /A7 J7 /J6 /H15 /G16 / /AH6 /B8 /A8 / /A10 /A15 /A18 G15 /F16 /F15 / B12 /A12 /D16 / E16 C16 /B18 /A18 / B22 /A22 /G28 / C28 vdda_dpll_per Inputpower forthe AA16 NA U14 NA U17 analogpartofthe PeripheralDPLLs vdda_wkup_bg_bb Forwakeup LDO AA14 NA W14 NA AA13 and VDDA (2LDOs SRAM and BG)

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-25.Power SuppliesSignalsDescription(1) (continued) SIGNAL NAME [1] DESCRIPTION [2] BALL BOTTOM BALL TOP BALL BOTTOM BALL TOP BALL BOTTOM vss Ground AG2 /U2 /B2 / H2 /B18 /AB5 / G1/ K1/R1/ W1/ B2/ C1/ F1/H2/ M2/ R2/ V16/V15/U16/ AG3 /W3 /P3 / AB14 /AB20 /P2 / H4/ N4/ R4/ W4/ AB5/ Y6/AA7/Y11/AA16/ U15/ U14/ U11/ J3 /E3 /A3 /P4 F22 /E2 /C22 /B4 / A6/D7/ Y7/AE7/A8/ W20/P20/ L21/H20/ U9/T16/T15/T14/ /E4 /AG6 /D7 / B7 /B10 /B15 G8/ D10/ G10/ L10/ F20/B14/A13/A7 T13/T12/T11/T10/ C7 /V9 /U9 /P9 N10/ Y10/AC10/ T9/R15/ R14/ R11/ /N9 /K9 /W10 / C12/ D12/A13/D14/ R10/ P17/P15/P14/ V10 /P10 /K10 / AD14/ K15/Y16/L17/ P13/P12/P11/P10/ D10 /C10 / N17/ R17/ D18/ P8/N16/ N15/ N14/ AF12 /AE12 / D20/G20/E22/AB22/ N13/ N12/ N11/ Y12 /K12 /J12 / G23/ L23/T23/W23/ N10/ N9/ M16/ M13/ Y13 /W13 /J13 / B25/K25/U25/AD25 / M11/ M10/ M9/ L17/ D13 /C13 /W14 Y26 L13/L10/L8/K15/ /K16 /J16 /W17 K14/K11/K10/J16/ /K17 /J17 /W19 J15/J14/J13/J12/ /V19 /R19 /P19 J11/H16/H14/ H11 /L19 /K19 /D19 /C19 /AF20 / AE20 /T20 /R20 /M20 /L20 /D21 /C22 /AC25 / Y25 /W25 / AC26 /R26 /L26 /A26 /G27 /B27 vdds_sram SRAM LDOs W16 NA U12 NA AA12 vdds_mmc1 Inputpower for K25 NA N23 NA N24 MMC1 dualvoltage buffers vdds_x Power supplyfor P25 NA P23 NA H8 dualvoltageGPIOs vss Ground M28 NA L19 NA NA vdds IO power plane AG20 NA AD18 NA NA vss Ground AG16 NA AC16 NA NA vdds IO power plane H28 NA L20 NA NA cap_vdd_sram_mpu_i Decoupling V4 NA N9 NA U8 va capacitorforSRAM inprocessor domains cap_vdd_sram_core Decoupling L21 NA K20 NA H17 capacitorforCORE domain (SRAM) vdds IO power plane AG21 NA AD19 NA NA cap_vddu_array Decoupling AH20 NA AE19 NA N20 capacitorfor WKUP/EMU domains (array) vss Ground AH21 NA AC19 NA NA cap_vdd_bb_mpu_iva Decoupling U4 NA D6 NA N21 capacitorfor processordomains (bb) sys_xtalgnd Kelvinground Y17 NA AF23 NA W15 (1) NA inthistablestandsfor"Notapplicable". (2) Fora listofpinsnotsupportedon a particularpackage,see Table2-4. Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 113 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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2.5.9 System and MiscellaneousTerminals

Note:For more information,see thePower,Reset,and ClockManagement /PRCM Environmentsection oftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table2-26.System and MiscellaneousSignalsDescription(1) SIGNAL NAME DESCRIPTION [2] TYPE [3] BALL BALL TOP BALL BALL TOP BALL [1] BOTTOM (CBP Pkg.) BOTTOM (CBC Pkg.) BOTTOM (CBP Pkg.) (2)[5] (CBC Pkg.) (2)[5] (CUS Pkg.) [4] [4] [4] sys_32k 32-kHzclockinput I AE25 NA AE20 NA AA16 sys_xtalin Main inputclock.OscillatorinputorLVCMOS at AI-I AE17 NA AF19 NA AD15 19.2,13,or12 MHz. sys_xtalout Outputofoscillator AO AF17 NA AF20 NA AD14 sys_altclk AlternateclocksourceselectableforGPTIMERs I J25 NA J23 NA A24 (maximum 54 MHz), USB (48MHz), or NTSC/PAL (54MHz) sys_clkreq Requestfromdeviceforsystemclock(open IO AF25 NA W15 NA Y13 sourcetype) sys_clkout1 Configurableoutputclock1 O AG25 NA AE14 NA Y7 sys_clkout2 Configurableoutputclock2 O AE22 NA W11 NA AA6 sys_boot0 Bootconfigurationmode bit0 I AH26 NA F3 NA AB12 sys_boot1 Bootconfigurationmode bit1 I AG26 NA D3 NA AC16 sys_boot2 Bootconfigurationmode bit2 I AE14 NA C3 NA AD17 sys_boot3 Bootconfigurationmode bit3 I AF18 NA E3 NA AD18 sys_boot4 Bootconfigurationmode bit4 I AF19 NA E4 NA AC17 sys_boot5 Bootconfigurationmode bit5 I AE21 NA G3 NA AB16 sys_boot6 Bootconfigurationmode bit6 I AF21 NA D4 NA AA15 sys_nrespwron Power On Reset I AH25 NA V13 NA AA10 sys_nreswarm Warm BootReset(opendrainoutput) IOD AF24 NA AD7 AA5 Y10 sys_nirq ExternalFIQ input I AF26 NA V16 NA W16 sys_nvmode1 Indicatesthevoltagemode O AD26 NA AD15 NA Y16 sys_nvmode2 Indicatesthevoltagemode O AE26 NA W16 NA Y15 sys_off_mode Indicatesthevoltagemode O AF22 NA V12 NA AD23 sys_ndmareq0 ExternalA request0 (systemexpansion).Level I U8 NA B6 NA D2 (activelow)oredge (falling)selectable. sys_ndmareq1 ExternalA request1 (systemexpansion).Level I T8 /J8 NA B4 /C6 NA F4 /C2 (activelow)oredge (falling)selectable. sys_ndmareq2 ExternalA request2 (systemexpansion).Level I L3 /R8 NA D1 /C4 NA H2 /G5 (activelow)oredge (falling)selectable. sys_ndmareq3 ExternalA request3 (systemexpansion).Level I K3 /P8 NA D2 /B5 NA G2 /F3 (activelow)oredge (falling)selectable. (1) NA inthistablestandsfor"Notapplicable". (2) Fora listofpinsnotsupportedon a particularpackage,see Table2-4. Table2-27.CBC Package Feed-Through Balls JEDEC 14x14mm, 0.65mm, JEDEC DESCRIPTION (1) BALL TOP BALL BOTTOM FEED-THROUGH BALL 152ball NAME NC No Connect A1 A1 pop_a1_a1 d-vdd DDR Supply J1 L1 pop_j1_l1 NC No Connect AA1 AF1 NC f-vdd FlashSupply N2 T2 pop_n2_t2 f-vdd FlashSupply T2 Y2 pop_t2_y2 NC No Connect W2 AE2 pop_w2_ae2 NC No Connect Y2 AF4 pop_y2_af4 f-vdd FlashSupply AA6 AF5 pop_aa6_af5 f-vdd FlashSupply Y7 AF8 pop_y7_af8

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table2-27.CBC Package Feed-Through Balls(continued) NC, Int No Connect;Interruptwhen Y9 AF10 pop_y9_af10 usingOneNAND POP f-nbe0,cle0 No Connect/CLE AA10 AF12 pop_aa10_af12 d-vdd DDR Supply/POP FLASH AA11 AF13 pop_aa11_af13 vpp supply d-tq No Connect/DDR die AA12 AF14 pop_aa12_af14 temperaturesensor vss Shared Ground AA13 AF15 pop_aa13_af15 d-vdd DDR Supply Y14 AF17 pop_y14_af17 d-vddq DDR Supply AA14 AF16 pop_aa14_af16 d-vdd DDR Supply B16 A20 pop_b16_a20 vss Shared Ground Y17 AF21 pop_y17_af21 d-vdd DDR Supply AA17 AF18 pop_aa17_af18 vss Shared Ground Y19 AF24 pop_y19_af24 d-vddq DDR Supply AA19 AF22 pop_aa19_af22 NC No Connect A20 A25 pop_a20_a25 NC No Connect Y20 AE25 pop_y20_ae25 NC No Connect AA20 AF25 pop_aa20_af25 NC No Connect A21 A26 pop_a21_a26 NC No Connect B21 B26 pop_b21_b26 d-vdd DDR Supply H21 K26 pop_h21_k26 d-vdd DDR Supply P21 U26 pop_p21_u26 NC No Connect Y21 AE26 pop_y21_ae26 NC No Connect AA21 AF26 pop_aa21_af26 (1) Formore detailson thefeedthroughpinconnections,pleaserefertothePoP memory datasheet. Table2-28.CBP Package Feed-Through Balls JEDEC 12x12,0.5mm, JEDEC DESCRIPTION (1) BALL TOP BALL BOTTOM FEED-THROUGH BALL 168ball NAME d-vdd DDR Supply A12 A15 pop_a12_a15 d-vdd DDR Supply AA23 AE28 pop_aa23_ae28 d-vdd DDR Supply H23 AF28 pop_h23_af28 d-vdd DDR Supply K1 J28 pop_k1_j28 d-vdd DDR Supply Y23 M1 pop_y23_m1 f-vdd FlashSupply AA1 AA1 pop_aa1_aa1 f-vdd FlashSupply AC8 AF1 pop_ac8_af1 f-vdd FlashSupply AC13 AH10 pop_ac13_ah10 f-vdd FlashSupply L1 AH15 pop_l1_ah15 f-vdd FlashSupply U1 N1 pop_u1_n1 f-vpp Flashvpp supply AC11 AH13 pop_ac11_ah13 NC, int0 No Connect/PoPOneNAND AB9 AG11 pop_ab9_ag11 interrupt NC, int1 No Connect/PoPOneNAND AC9 AH11 pop_ac9_ah11 interrupt NC No Connect A1 A1 NC NC No Connect A2 A2 NC NC No Connect A22 A27 pop_a22_a27 NC No Connect A23 A28 pop_a23_a28 NC No Connect AB1 AG1 pop_ab1_ag1 NC No Connect AB23 AG28 pop_ab23_ag28 NC No Connect AC1 AH1 pop_ac1_ah1 NC No Connect AC2 AH2 pop_ac2_ah2 NC No Connect AC22 AH27 pop_ac22_ah27 NC No Connect AC23 AH28 pop_ac23_ah28 Copyright© 2010–2011,Texas InstrumentsIncorporated TERMINAL DESCRIPTION 115 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table2-28.CBP Package Feed-Through Balls(continued) NC No Connect B1 B1 NC NC No Connect B23 B28 pop_b23_b28 f-rst#,rp# Flashreset AB11 AG13 pop_ab11_ag13 d-tq DDR temperaturealert AC14 AH16 pop_ac14_ah16 vss Shared Ground AA2 AA2 pop_aa2_aa2 vss Shared Ground U2 AF2 pop_u2_af2 vss Shared Ground AA22 AF27 pop_aa22_af27 vss Shared Ground AB8 AG10 pop_ab8_ag10 vss Shared Ground AB13 AG15 pop_ab13_ag15 vss Shared Ground B12 B15 pop_b12_b15 vss Shared Ground H22 J27 pop_h22_j27 vss Shared Ground K2 M2 pop_k2_m2 vss Shared Ground K22 M26 pop_k22_m26 vss Shared Ground L2 N2 pop_l2_n2 (1) Formore detailson thefeedthroughpinconnections,pleaserefertothePoP memory datasheet.

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3 ElectricalCharacteristics

For more information,see the Power Reset and Clock Management / PRCM Environment sectionoftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ).

3.1 AbsoluteMaximum Ratings

Stressesbeyond thoselistedas absolutemaximum ratingsmay cause permanentdamage tothedevice. These are stressratingsonly,and functionaloperationof the deviceat theseor any otherconditions beyond those listedunder "Recommended OperatingConditions"isnot implied.Exposure to absolute maximum ratedconditionsforextendedperiodsmay affectdevicereliability. Table3-1.AbsoluteMaximum Ratingover JunctionTemperature Range PARAMETER MIN MAX UNIT vdd_mpu_iva SupplyvoltagerangeforMPU /IVA domain –0.5 1.5 V vdd_core Supplyvoltagerangeforcoredomain –0.5 1.5 V vdda_wkup_bg_bb Supplyvoltagerangeforwake-up domain (internal –0.5 2.1 V LDO) vdda_dplls_dll SupplyvoltageforMPU, IVA,Core DPLLs, and DLL –0.5 2.1 V vdda_dpll_per SupplyvoltageforDPLLs (peripherals) –0.5 2.1 V vdds_sram SupplyvoltageforSRAM LDOs –0.5 2.1 V vdda_dac Supplyvoltageforvideobuffersand DAC –0.5 2.1 V vdds Supplyvoltagefor1.8-VI/Omacros –0.5 2.1 V vdds_mem Supplyvoltageformemory buffers –0.5 2.1 V vdds_mmc1 Supplyvoltagerangeformmc1 dualvoltageIOs –0.5 3.8 V vdds_x SupplyvoltagerangefordualvoltageGPIOs –0.5 3.8 V JTAG (9) 200 VESD ESD stress HBM (Human CAM (6) 400 V voltage(1) Body Model)(2) GPMC (8) 500 Othersignals 1000 CDM (ChargedDeviceModel)(3) 250 IIOI Current-pulseinjectionon each IO pin(5) 200 mA Iclamp Clamp currentforan inputoroutput –20 20 mA TSTG (4) Storagetemperaturerange –65 150 °C (1) Electrostaticdischarge(ESD) tomeasure devicesensitivity/immunitytodamage caused by electrostaticdischargesintothedevice. (2) Levellistedabove isthepassinglevelperANSI/ESDA/JEDEC JS-001-2010.JEDEC document JEP155 statesthat500V HBM allows safemanufacturingwitha standardESD controlprocess,and manufacturingwithlessthan500V HBM ispossibleifnecessary precautionsaretaken.Pinslistedas 1000V may actuallyhave higherperformance. (3) Levellistedabove isthepassinglevelperEIA-JEDEC JESD22-C101E. JEDEC document JEP157 statesthat250V CDM allowssafe manufacturingwitha standardESD controlprocess.Pinslistedas 250V may actuallyhave higherperformance. (4) Fortapeand reelthestoragetemperaturerangeis[–10°C; +50°C] witha maximum relativehumidityof70%. Itisrecommended returningtoambientroom temperaturebeforeusage. (5) Each deviceistestedwithan IO pininjectionof200 mA witha stressvoltageof1.5timesthemaximum Vdd atroom temperature. (6) Correspondingsignals:cam_d0, cam_d1, cam_d6, cam_d7, cam_d8, cam_d9. RefertoMultiplexingCharacteristicstodeterminetheball informationperpackage. (7) Correspondingsignals:dss_data0,dss_data1,dss_data2,dss_data3,dss_data4,dss_data5.RefertoMultiplexingCharacteristicsto determinetheballinformationperpackage. (8) Correspondingsignals:All46 GPMC interfacesignals(vdds_mem isnotincludedtothisexceptionlist).RefertoMultiplexing Characteristicstodeterminetheballinformationperpackage. (9) Correspondingsignals:All8 JTAG interfacesignals(jtag_emu0,jtag_emu1,jtag_ntrst,jtag_rtck,jtag_tck,jtag_tdi,jtag_tdo, jtag_tms_tmsc).RefertoMultiplexingCharacteristicstodeterminetheballinformationperpackage. Copyright© 2010–2011,Texas InstrumentsIncorporated ElectricalCharacteristics 117 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table3-2summarizesthepower consumptionattheballlevel. Table3-2.Maximum CurrentRatingsatBallLevel(3) PARAMETER MAX UNIT SIGNAL DESCRIPTION vdd_mpu_iva(7) Maximum currentratingforMPU /IVA Processors DM3730/DM3725 (1G 1400(1)(4) mA domain Hz) DM3730/DM3725 (800M 1200(5) Hz) DM3730/DM3725 (600M 800(5) Hz) vdd_core(1) Maximum currentratingforcore Core DM3730 300 mA domain DM3725 230 vdds Maximum currentratingfor1.8-VI/Omacros 60 mA vdds_mem Maximum currentratingformemory buffers 35 mA vdds_mmc1 (2) Maximum currentratingformmc1 dualvoltagebuffers 20 mA vdds_x Maximum currentratingforGPIO dualvoltagebuffers 2 mA vdda_wkup_bg_b Maximum currentratingforwake-up,bandgap and VBB LDOs 5 mA b vdda_dac Maximum currentratingforvideobuffersand DAC 60 mA vdda_dplls_dll Maximum currentratingforMPU, IVA,coreDPLLs and DLL 30 mA vdda_dpll_per Maximum currentratingforDPLLs (peripherals) 10 mA vdds_sram Maximum currentratingforSRAM LDOs (common) 41 mA (1) WithSmartReflexTM enabled. (2) MMC cardand I/Ocardarenotincluded. (3) The maximum currentratingsdocumented inthistablearepreliminarydatawhicharesubjecttochange. (4) Conditionsused formaximum currentratingsareworstcase: – TJ isup to90C – Coldprocessisused – VDD1 (vdd_mpu_iva)supplies1.38V (maximum voltagesupported) Intheseconditions,thecurrentlistedas 1400mV istheadditionofthe: – Currentwhen runningDhrystoneon ARM@1GHz multipliedby a factorx1.5(totakecareofNEON activity) – Currentwhen runningH.264 on IVA@800MHz witha x1.1factor(totakecareofmore aggressiveSW thanH.264) (5) Conditionsused formaximum currentratingsareworstcase: – TJ isup to90C – Hot processisused – VDD1 (vdd_mpu_iva)nominalOPP voltage: – DM3730 (800M Hz):@1.27V – DM3730 (600M Hz):@1.14V (6) Thismaximum vdd_mpu_ivacurrentisobservedatOPP1G operatingpoint. (7) Dependingon themicroprocessorchosen,theIVA featuremay ormay notbe supported.See theFeaturessectionformore information on devicefeatures.

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3.2 Recommended OperatingConditions

The deviceis used under the recommended operatingconditionsdescribedin Table 3-4. The POH informationin Table 3-3 isprovidedsolelyforyour convenienceand does not extend or modifythe warrantyprovidedunderTI’s standardtermsand conditionsforTIsemiconductorproducts. Table3-3.ReliabilityData JUNCTION TEMP TOTAL DEVICE LIFETIME ≥OPP130 MAX TIME OPP1G MAX TIME @105C 89K POH Not available Not available @90C 100K POH 45K 25K(1) @75C >100K POH 100K POH 75K (1) IfdeviceisonlyoperatedatOPP1G, thenPOH can be extendedto35K POH. NOTE Logicfunctionsand parametervaluesare not assured out of the range specifiedin the recommended operatingconditions. Table3-4.Recommended OperatingConditions PARAMETER DESCRIPTION MIN NOM MAX UNIT vdd_mpu_iva SupplyvoltagerangeforARM /IVA domain See(1) V Maximum Noise(peak-peak) 40 mV PP vdd_core Supplyvoltagerangeforcoredomain See(1) V Maximum Noise(peak-peak) 40 mV PP vdds Supplyvoltagefor1.8-VI/Omacros 1.71 1.80 1.91 V Maximum Noise(peak-peak) OscillatorIO (Crystalor 40 mV PP Square modes) Others 90 vdds_mem Supplyvoltageformemory buffers 1.71 1.80 1.91 V Maximum Noise(peak-peak) 90 mV PP vdds_mmc1 Supplyvoltagerangeformmc1 1.8-Vmode 1.71 1.80 1.91 V Noise(peak-peak) 1.8-Vmode 90 mV PP 3.0-Vmode 150 vdds_x Supplyvoltagerangeforx dual 1.8-Vmode 1.71 1.80 1.91 V voltageIOs 3.0-Vmode 2.70 3.00 3.60 Maximum Noise(peak-peak) 1.8-Vmode 90 mV PP 3.0-Vmode 150 vdda_wkup_bg_ Supplyvoltagerangeforwake-up LDO 1.71 1.80 1.91 V bb Maximum Noise(peak-peak) 50 mV PP vdda_dac AnalogsupplyvoltageforVideoDAC 1.71 1.80 1.91 V Maximum Noise(peak-peak)fora frequencyfrom0 to100 30 mV PP kHz (Fora frequency> 100 kHz,decreases20 dB/dec) vdds_sram SupplyvoltageforSRAM LDOs 1.71 1.80 1.91 V Maximum Noise(peak-peak) 50 mV PP vdda_dplls_dll SupplyvoltageforMPU, IVA,coreDPLLs and DLL 1.71 1.80 1.91 V Maximum Noise(peak-peak) 30 mV PP Forany frequency Copyright© 2010–2011,Texas InstrumentsIncorporated ElectricalCharacteristics 119 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table3-4.Recommended OperatingConditions(continued) PARAMETER DESCRIPTION MIN NOM MAX UNIT vdda_dpll_per SupplyvoltageforDPLLs (peripherals) 1.71 1.80 1.91 V Maximum Noise(peak-peak) 50 mV PP Forany frequency vssa_dac Ground forvideobuffersand DAC 0 V vss Main ground 0 V TJ Operatingjunctiontemperature Commercial 0 90 °C range Temperature IndustrialTemperature -40 90 ExtendedTemperature -40 105 (1) See Section4.3.4,ProcessorClocks.OPP voltagevaluesmay change followingthesiliconcharacterizationresult.

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3.3 DC ElectricalCharacteristics

Table3-5summarizesthedc electricalcharacteristics. Note:The interfacesorsignalsdescribedinTable3-5correspondtotheinterfacesorsignalsavailablein multiplexingmode 0.Allinterfacesor signalsmultiplexedon theballs/pinsdescribedinTable3-5 have thesame DC electricalcharacteristics. Table3-5.DC ElectricalCharacteristics PARAMETER MIN NOM MAX UNIT SDRC Mode (CBP Balls(19):C14 /B14 /C15 /B16 /D17 /C17 /B17 /D18 /H9 /H10 /H11 /H12 /A13 /A14 /H16 /H17 /H14 /H13 / H15 /A16 /A17)(4) VIH High-levelinputvoltage 0.7*vdds_mem V VIL Low-levelinputvoltage 0.3*vdds_mem V VHYS (1) Hysteresisvoltageatan input 0.07 V VOH High-leveloutputvoltage,driverenabled, IOH = –4 mA 0.8*vdds_mem vdds_mem V pulluporpulldowndisabled VOL Low-leveloutputvoltage,driverenabled, IOL = 4 mA 0 0.2*vdds_mem V pulluporpulldowndisabled C IN Inputcapacitance 1.15 pF tTIN (2) Inputrecommended rise,tRIN,and falltime,tFIN (measured 10 ns between 20% and 80% atPAD) tROUT (2) Outputmaximum risetime(risetime,tROUT ,evaluated 1.15 ns between 20% and 80% atPAD) @ maximum load tFOUT (2) Outputmaximum falltime(falltime,tFOUT ,evaluated 1.10 ns between 20% and 80% atPAD) @ maximum load C OUT Load capacitance DS0 = 0(3) 2 4 pF DS0 = 1(3) 4 12 MMC Interface1 Mode (CBP Balls(19):N28 /M27 /N27 /N26 /N25 /P28) 1.8-VMode VIH High-levelinputvoltage 0.70*vdds_mmc1 vdds_mmc1 + 0.3 V VIL Low-levelinputvoltage –0.3 0.30*vdds_mmc1 V VOH High-leveloutputvoltagewith100-μA sinkcurrentIOH vdds_mmc1 – 0.2 V VOL Low-leveloutputvoltagewith100-μA sinkcurrentat 0.2 V vdds_mmc1 minimum VHYS (1) Hysteresisvoltageatan input 0.1 V tTIN (2) Inputtransitiontime(tRIN ortFIN evaluated Normal Mode 3 ns between 10% and 90% atPAD) (SPEEDCTRL = 1)(4) High-Speed 8 (SPEEDCTRL = 0)(4) C OUT Load capacitance 10 30 pF LOUT Lineinductance(exceptvdds_mmc1) 16 nH 3.0-VMode VIH High-levelinputvoltage 0.625*vdds_mmc1 vdds_mmc1 + 0.3 V VIL Low-levelinputvoltage –0.3 0.25*vdds_mmc1 V VOH High-leveloutputvoltagewith100-μA sinkcurrentIOH 0.75*vdds_mmc1 V VOL Low-leveloutputvoltagewith100-μA sourcecurrentat 0.125*vdds_mmc1 V vdds_mmc1 minimum VHYS (1) Hysteresisvoltageatan input 0.05 V Copyright© 2010–2011,Texas InstrumentsIncorporated ElectricalCharacteristics 121 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table3-5.DC ElectricalCharacteristics(continued) PARAMETER MIN NOM MAX UNIT tTIN(2) Inputtransitiontime(tRIN ortFIN evaluated Normal Mode 3 ns between 10% and 90% atPAD) (SPEEDCTRL = 1)(4) High-Speed 8 (SPEEDCTRL = 0)(4) C OUT Load capacitance 10 30 pF LOUT Lineinductance(exceptvdds_mmc1) 16 nH GPIO Mode (CBP Balls(19):P27 /P26 /R25) 1.8-VMode VIH High-levelinputvoltage 0.70*vdds_x vdds_x + 0.3 V VIL Low-levelinputvoltage –0.3 0.20*vdds_x V VOH High-leveloutputvoltagewith20-μA sinkcurrentIOH 0.8*vdds_x vdds_x + 0.3 V VOL Low-leveloutputvoltagewith1-mA sourcecurrentatvdds_x –0.3 0.4 V minimum VHYS (1) Hysteresisvoltageatan input 0.1 V tTIN (2) Inputtransitiontime(tRIN ortFIN evaluated Normal Mode 35 ns between 10% and 90% atPAD) (SPEEDCTRL = 1)(4) C IN Inputcapacitance 2.5 pF C OUT Load capacitance 30 pF LOUT Lineinductance(exceptvdds_x) 16 nH 3.0-VMode VIH High-levelinputvoltage 0.70*vdds_x vdds_x + 0.3 V VIL Low-levelinputvoltage –0.3 0.20*vdds_x V VOH High-leveloutputvoltagewith20-μA sinkcurrentIOH 0.7*vdds_x vdds_x + 0.3 V VOL Low-leveloutputvoltagewith1-mA sourcecurrentat –0.3 0.4 V vdds_simminimum VHYS (1) Hysteresisvoltageatan input 0.05 V tTIN (2) Inputtransitiontime(tRIN ortFIN evaluated Normal Mode 35 ns between 10% and 90% atPAD) (SPEEDCTRL = 1)(4) C IN Inputcapacitance 2.5 pF C OUT Load capacitance 30 pF LOUT Lineinductance(exceptvdds_x) 16 nH I2C Mode (CBP Balls(19):K21 /J21 /AF15 /AE15 /AF14 /AG14 /AD26 /AE26) (6) Standard Mode VIH High-levelinputvoltage 0.7*vdds vdds + 0.5 V VIL Low-levelinputvoltage –0.5 0.3*vdds V VHYS (1) Hysteresisvoltageatan input 0.15 V VOL Low-leveloutputvoltageopen-drainat3-mA sinkcurrent NA (18) NA (18) V II Inputcurrentateach I/Opinwithan inputvoltagebetween –10 10 μA 0.1*vdds to0.9*vdds C I Capacitanceforeach I/Opin 10 pF tFOUT (5) OutputfalltimefromVIHmin toVILmax witha bus capacitance 250 ns C B from10 pF to400 pF tROUT (5) Outputrisetimewitha capacitiveloadfrom10 pF to150 pF 20 + 0.1CB 250 ns withinternalpullup FastMode VIH High-levelinputvoltage 0.7*vdds vdds + 0.5 V VIL Low-levelinputvoltage –0.5 0.3*vdds V

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table3-5.DC ElectricalCharacteristics(continued) PARAMETER MIN NOM MAX UNIT VHYS (1) Hysteresisvoltageatan input 0.15 V VOL Low-leveloutputvoltageopen-drainat3-mA sinkcurrent 0 0.2*vdds V II Inputcurrentateach I/Opinwithan inputvoltagebetween –10 10 μA 0.1*vdds to0.9*vdds C I Capacitanceforeach I/Opin 10 pF tFOUT (5) OutputfalltimefromVIHmin toVILmax witha bus capacitance 20 + 0.1CB 250 ns C B from10 pF to400 pF tROUT (5) Outputrisetimewitha capacitiveloadfrom10 pF to150 pF 20 + 0.1CB 250 ns withinternalpullup High-Speed Mode VIH High-levelinputvoltage 0.7*vdds vdds + 0.5 V VIL Low-levelinputvoltage –0.5 0.3*vdds V VHYS (1) Hysteresisvoltageatan input 0.15 V VOL Low-leveloutputvoltageopen-drainat3-mA sinkcurrent 0 0.2*vdds V II Inputcurrentateach I/Opinwithan inputvoltagebetween –10 10 μA 0.1*vdds to0.9*vdds C I Capacitanceforeach I/Opin 10 pF tFOUT (5)(6) Outputfalltimewitha capacitiveloadfrom10 pF to100 pF 10 40 ns at3-mA sinkcurrent Outputfalltimewitha capacitiveloadof400 pF at3-mA 20 80 ns sinkcurrent tROUT (5) Outputrisetimewitha capacitiveloadfrom10 pF to80 pF 10 40 ns withinternalpullup Standard LVCMOS Mode VIH High-levelinputvoltage 0.7*vdds vdds V VIL Low-levelinputvoltage –0.5 0.3*vdds V VOH High-leveloutputvoltageat4-mA sinkcurrent vdds – 0.45 V VOL Low-leveloutputvoltageat4-mA sinkcurrent 0.45 V C IN Inputcapacitance 1.15 pF tTIN (2) Inputtransitiontime(tRIN ortFIN evaluatedbetween 10% and 10 ns 90% atPAD) tTOUT Outputtransitiontimeat40-pFload(tROUT ortFOUT 10 ns evaluatedbetween 10% and 90% atPAD) MIPID-PHY Interface MIPID-PHY Interface-GPI Mode (CBP Balls(19):AG19 /AH19 /AG18 /AH18 /K28 /L28 /K27 /AG17 /AH17) VIH(7) High-levelinputvoltage 0.65*vdds_x(14) vdds_x+ 0.3(14) V VIL (8) Low-levelinputvoltage –0.3 0.35*vdds_x(14) V VHYS (1) Hysteresisvoltageatan input 0.15 V C IN Inputcapacitance 1.3 pF tTIN (2) Inputtransitiontime(tRIN ortFIN evaluatedbetween 10% and 10 ns 90% atPAD) Other Balls Common to"OtherBalls" VIH High-levelinputvoltage 0.65*vdds vdds + 0.3 V VIL Low-levelinputvoltage –0.3 0.35*vdds V VHYS (1) Hysteresisvoltageatan input 0.15 V VOH High-leveloutputvoltage,driverenabled, IOH = – X(17) vdds – 0.45 V pulluporpulldowndisabled mA VOL Low-leveloutputvoltage,driverenabled, IOL = X(17)mA 0.45 V pulluporpulldowndisabled DifferencesBetween "OtherBalls" Copyright© 2010–2011,Texas InstrumentsIncorporated ElectricalCharacteristics 123 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table3-5.DC ElectricalCharacteristics(continued) PARAMETER MIN NOM MAX UNIT InputCapacitanceand InputTransitionTime sys_xtalinpin(CBP Ball(19):AE17) C IN Inputcapacitance 1.00 1.15 1.35 pF tTIN(2) Inputtransitiontime(risetime,tRIN orfalltime,tFIN 10 ns evaluatedbetween 10% and 90% atPAD) JTAG interface(CBP Balls(19):AA17 /AA13 /AA12 /AA18 /AA20 /AA19 /AA11 /AA10) C IN Inputcapacitance 2.20 pF tTIN(2) Inputtransitiontime(risetime,tRIN orfalltime,tFIN 10 ns evaluatedbetween 10% and 90% atPAD) Otherwise C IN Inputcapacitance 1.15 pF tTIN(2) Inputtransitiontime(risetime,tRIN orfalltime,tFIN 10 ns evaluatedbetween 10% and 90% atPAD) Output CapacitanceLoad and Output TransitionTime sys_32k,sys_clkreq,sys_off_mode,sys_clkout1,sys_nirq,uart3_cts_rctx,uart3_rts_sd,uart3_rx_irrx,uart3_tx_irtx,hdq_sio (CBP Balls(19):R27 /AE25 /AF25 /AF22 /AG25 /AF26 /H18 /H19 /H20 /H21 /J25) tTOUT Outputtransitiontime(risetime,tROUT or DS[1:0]= 00(3) 1(15) 15(16) ns falltime,tFOUT evaluatedbetween 10% and 90% atPAD) C TOUT Outputload 4 60 pF tTOUT Outputtransitiontime(risetime,tROUT or DS[1:0]= 10(3) 0.4(15) 5(16) ns falltime,tFOUT evaluatedbetween 10% and 90% atPAD) C TOUT Outputload 2 21 pF tTOUT Outputtransitiontime(risetime,tROUT or DS[1:0]= 01(3) 0.6(15) 7(16) ns falltime,tFOUT evaluatedbetween 10% and 90% atPAD) C TOUT Outputload 7 33 pF CAM, HSUSB0, MMC2, UART1, UART2, McBSP, McSPI, ETK Interfaces,sys_clkout2(CBP Ball(19):AE22) tTOUT Outputtransitiontime(risetime,tROUT orfalltime,tFOUT 1.5 5 ns evaluatedbetween 10% and 90% atPAD) C TOUT Outputload 2 22 pF Otherwise tTOUT Outputtransitiontime(risetime,tROUT orfalltime,tFOUT 0.6 2.4(17) ns evaluatedbetween 10% and 90% atPAD) C TOUT Outputload 2 22 pF Hysteresis sys_xtalinpin(CBP Ball(19):AE17) VHYS (1) Hysteresisvoltageatan input 0.25 V hsusb0_clk (CBP Ball(19):T28) VHYS (1) Hysteresisvoltageatan input 0.07 V Otherwise VHYS (1) Hysteresisvoltageatan input 0.15 V (1) Vhys isthemagnitudeofthedifferencebetween thepositive-goingthresholdvoltageVT+ and thenegative-goingthresholdvoltageVT–. Some receivers,butnotall,aredesignedforhysteresis.Vhys appliesonlytothosethatare. (2) The tIN (tRIN and tFIN also)valueistherecommended condition.The tIN (tRIN and tFIN also)mismatchcausesadditionaldelaytimeinside thedevicethenleadstoac timinginvalidationinthisDM. The tIN (tRIN and tFIN also)mismatchdoes notnecessarilymean functionalfailure.Thisglobalvaluemay be overriddenon a perinterface basisifanothervalueisexplicitlydefinedforthatinterfaceintheTimingRequirementsand SwitchingCharacteristicschapterofthedata manual. (3) Fora fulldescriptionoftheDS0 loadcompensationregisterconfiguration,see thedescriptionoftheCONTROL_PROG_IO1 configurationregistersinSystem ControlModule /Programming Model /FeatureSettings/SDRC I/ODriveStrengthSelectionsection oftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ).

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (4) Fora fulldescriptionoftheSPEEDCTRL speed registerconfiguration,see thedescriptionoftheCONTROL_PROG_IO1 configuration registersinSystem ControlModule /Programming Model /FeatureSettingssectionoftheAM/DM37x MultimediaDeviceTechnical ReferenceManual (literaturenumber SPRUGN4 ). (5) Riseand falltimesarespecifiedfor(0.3*vdds)to(0.7*vdds). (6) Forcapacitiveloadfrom100 pF to400 pF,falltimeshouldbe linearlyinterpolated: tFmin = (1+ (Load– 100 pF)/300 pF)*10 ns tFmax = (1+ (Load– 100 pF)/300 pF)*40 ns (7) VIH isthevoltageatwhichthereceiverisrequiredtodetecta highstateintheinputsignal. (8) VIListhevoltageatwhichthereceiverisrequiredtodetecta lowstateintheinputsignal.VILislargerthanthemaximum single-ended linevoltageduringHS transmission.Therefore,bothLP receiverswilldetectlowduringHS signaling. (9) Thisvalueincludesa grounddifferenceof50 mV between thetransmitterand thereceiver,thestatuscommon-mode leveltolerance and variationsbelow450 MHz. (10)Common mode isdefinedas theaveragevoltagelevelofDX and DY: VCM = (V(DX) + V(DY))/2.Common mode ripplemay be due to rise-falltimeand transmissionlineimpairmentsinthePCB. (11)Valuewhen drivingintodifferentialloadimpedance anywhere intherange80 to125 Ω. (12)ULPM standsforUltraLow Power Mode. (13)UI = 1 /(2*fh),where fhisthefundamentalfrequencyofHS datatransmission.Forexample,for800 Mbps fhis400 MHz. (14)vdda_x can be vdda_csiphy1orvdda_csiphy2dependingon theinterfaceused. (15)Atminimum load. (16)Atmaximum load.Caution:ThiscreatesEMI parasiticsup to1.2ns. (17)Formore informationaboutIOH /IOL values,see one ofthetablesintheBallCharacteristicssection,column “BUFFER DRIVE STRENGTH (mA) ”. (18)No VOL specificationsareapplicableinStandardmode. (19)ForassociatedCBC and CUS balls,pleaserefertotheSection2.4,MultiplexingCharacteristicstable. Copyright© 2010–2011,Texas InstrumentsIncorporated ElectricalCharacteristics 125 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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3.4 ExternalCapacitors

To improve module performance,decouplingcapacitorsare requiredto suppressthe switchingnoise generatedby highfrequencyand tostabilizethesupplyvoltage.A decouplingcapacitorismost effective when itiscloseto the device,because thisminimizesthe inductanceof the circuitboard wiringand interconnects.

3.4.1 VoltageDecoupling Capacitors

Table3-6summarizestheCore voltagedecouplingcharacteristics.

3.4.1.1 Core VoltageDecoupling Capacitors

To improve module performance,decouplingcapacitorsare requiredto suppressthe switchingnoise generatedby highfrequencyand tostabilizethesupplyvoltage.A decouplingcapacitorismost effective when itiscloseto the device,because thisminimizesthe inductanceof the circuitboard wiringand interconnects. Table3-6.Core VoltageDecoupling Characteristics PARAMETER MIN TYP MAX UNIT C vdd_core (1) 0.6 1.2 1.8 μF C vdd_mpu_iva (2) See (2) μF (1) The typicalvaluecorrespondsto2 capacitorsof470 nF,plus3 capacitorsof100 nF.Exceptforthedecouplingcapacitancevalues,the PCB rulesofthePCB DesignRequirementsforVDD_MPU_IVA Power DistributionNetworkforTIOMAP3630, AM37xx, and DM37xx Microprocessors(SPRABJ7) applicationnotecan be used. (2) Formore informationregardingthevdd_mpu_ivadecouplingcapacitancerecommendations,see thePCB DesignRequirementsfor VDD_MPU_IVA Power DistributionNetworkforTIOMAP3630, AM37xx, and DM37xx Microprocessors(SPRABJ7) applicationnote.

3.4.1.2 IO and Analog VoltageDecoupling Capacitors

Table3-7summarizesthepower supplydecouplingcapacitorcharacteristics. Table3-7.Power Supply Decoupling CapacitorCharacteristics PARAMETER MIN TYP MAX UNIT C vdds (1)(2) 200 400 600 nF C vdds_mem (1)(3) 350 700 1050 nF C vdds_mmc1 (4) 50 100 150 nF C vdds_x (4) 50 100 150 nF C vdda_dplls_dll (4) 50 100 150 nF C vdda_dpll_per (4) 50 100 150 nF C vdds_sram (4) 110 220 330 nF C vdda_wkup_bg_bb (4) 240 470 700 nF C vdda_dac (4) 50 100 150 nF (1) Inpower planconfiguration. (2) The typicalvaluecorrespondsto4 capacitorsof100 nF. (3) The typicalvaluecorrespondsto7 capacitorsof100 nF. (4) Inpower railconfiguration.

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3.4.2 Output Capacitors

The capacitorsattheoutputsare requiredtostabilizetheinternalLDO supplyvoltages.The capacitors must be placedas closeas possibletotheballs. Table3-8summarizesthepower supplydecouplingcharacteristics. Table3-8.Output CapacitorCharacteristics PARAMETER MIN TYP MAX UNIT C cap_vdd_sram_mpu_iva 0.7 1 1.3 μF C cap_vdd_sram_core 0.7 1 1.3 μF C cap_vddu_wkup_logic 0.7 1 1.3 μF C cap_vddu_array 0.7 1 1.3 μF C cap_vdd_bb_mpu_iva 0.7 1 1.3 μF Copyright© 2010–2011,Texas InstrumentsIncorporated ElectricalCharacteristics 127 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

cap_vdd_sram_mpu_iva cap_vdd_sram_core vdds_sram DPLL5 DPLL4 vdda_dpll_per MMC I/Os vdds_mmc1 vss vssa_dac Cvdds_sram Ccap_vdd_sram_mpu_iva Ccap_vdd_sram_core Cvdda_dplls_dll Cvdda_dpll_per Cvdds_mmc1 vdda_dac vdds_mmc1 vdds_sram vdda_dpll_per vdda_dplls_dll vdds_mem Cvdds_mem CORE vdd_core Cvdd_core vdd_core vdda_wkup_bg_bbvdda_wkup_bg_bb cap_vddu_wkup_logic Cvdda_wkup_bg_bb Ccap_vddu_array cap_vddu_array DLL DPLL_MPU DPLL_IVA DPLL_CORE vdda_dplls_dll WKUP_LOGIC BG SRAM_LDO1 SRAM_LDO2 Video DAC VDDS_MEM MPU vdd_mpu_iva vdd_mpu_iva Cvdd_mpu_iva vdds VDDS I/O Cvdda_dac vdds_mem Cvdds vdds BBLDO cap_vdd_bb_mpu_iva Ccap_vddu_wkup_logic OSCILLATOR Device vdda_dac Ccap_vdd_bb_mpu_iva DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Figure3-1illustratesan example oftheexternalcapacitors. Figure3-1.ExternalCapacitors

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 NOTE

• Decouplingcapacitorsmust be placedas closedas possibleofthepower ball.Choose the ground locatedclosestto the power pinforeach decouplingcapacitor.In case of interconnectingpowers,firstinsertthe decouplingcapacitorand then interconnectthe powers.
• The decouplingcapacitorvaluedepends on theboardcharacteristics.

3.5 Power-Up and Power-Down Sequences

Thissectionprovidesthetimingrequirementsforthedevicehardwaresignals. NOTE

• IftheMMC dualvoltagesinterfacesareused with1.8-Vor3.0-V,thenthepower-upand power-down sequences specifiedin the Figure3-2 and Figure3-3 must be followed carefullytoavoidany significantcurrentconsumption.
• IftheMMC dualvoltagesinterfacesareused with1.8-Vonly(3.0-Visneverused),then vdds_mmc1, vdds_xmay be connectedtothemain power supplyvdds so thattheyramp up togetherbeforevdd_core.

3.5.1 Power-Up Sequence

For more information,see the Power, Reset,and Clock Management / PRCM Functional Description/ PRCM Reset Manager FunctionalDescription/ Reset Sequences of the AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Figure3-2shows thepower-upsequence. Copyright© 2010–2011,Texas InstrumentsIncorporated ElectricalCharacteristics 129 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

vdds, vdds_mem, vdds_sram, vdda_wkup_bg_bb vdda_dplls_dll, vdda_dpll_per vdd_core vdd_mpu_iva sys_32k sys_xtalin sys_nrespwron sys_nreswarm vdds_mmc1, vdds_x, vdda_dac 1.8 V 1.1 V (1) 1.1 V (1) 1.8 V DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) 1.2V supported. (2) Ifan externalsquare clockisprovided,itcouldbe startedaftersys_nrespwronrelease,provideditisclean,i.e.no glitch,stable frequencyand dutycycle. (3) sys_32kcan be turnedon any timebetween thevdds ramp-upand thesys_nrespwronrelease. Figure3-2.Power-Up Sequence

3.5.2 Power-Down Sequence

The followingstepsgivetwo examplesofpower-down sequence supportedby theDM37x device. 1. PuttheDM37x deviceunderreset(sys_nrespwron) 2. Stopallsignalsdriventoitsballs(sys_32k,sys_xtalin) 3. Either: (a) Shutdown allpower domains atonce.Thissequence isdescribedinblackcolorinFigure3-3. (b) Or,iftheshutdownissequenced,you must followthesesteps(describedindash stylebluecolor inFigure3-3): – TurnoffallcomplexIO domains (vdds_mmc1, vdds_x) – Turnoffallthecoreand MPU domains (vdd_core,vdd_mpu_iva) – TurnoffallDPLL domains (vdda_dplls_dll,vdda_dpll_per) – Turnoffallsram LDOs (vdds_sram) – Turnoffallreferencedomains (vdda_wkup_bg_bb) – TurnoffallstandardIO domains (vdds,vdds_mem) Figure3-3shows bothpower-down sequences:one ofthem isdescribedinblackcolor,and theotherone indash styleblue.

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vdda_dplls_dll, vdda_dpll_per vdd_core vdd_mpu_iva sys_32k sys_xtalin sys_nrespwron vdds_mmc1, vdds_x, vdda_dac vdds_sram vdda_wkup_bg_bb vdds, vdds_mem DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 A. sys_32kcan be turnedoffany timebetween thesys_nrespwronassertionand thevdds shutdown. Figure3-3.Power-Down Sequence Alternatepower-down sequence :

• vdd_mpu_ivashutsdown beforevdd_core.
• vdda_sram,vdda_wkup_bg_bb,vdds and vdds_mem shutdown simultaneously.
• vdda_dplls_dlland vdda_dpll_pershutdown anytimebetween allcomplex IO domains shutdown and vdda_sram shutsdown. Copyright© 2010–2011,Texas InstrumentsIncorporated ElectricalCharacteristics 131 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

sys_32k sys_altclk sys_clkout1 Alternate clock source selectable (48-MHz, 54-MHz) To quartz (oscillator output) or unconnected From quartz (oscillator input) or square clock Clock request. To square clock source or from peripherals Oscillator is used Oscillator is bypassed Unconnected Square clock source To peripherals (from oscillator clock [sys_xtalin]): 12-,13-, 16.8-, 19.2-, 26-, or 38.4-MHz or Core_clk: up to 332 MHz (possible divider: 4, 8, 16) or DPLL 54-MHz, DPLL 96-MHz (possible divider: 1, 2, 4, 8, or 16) GPin To peripherals (from oscillator clock [sys_xtalin]): 12-,13-, 16.8-, 19.2-, 26-, or 38.4-MHz (no divider) sys_clkout2 sys_xtalout sys_xtalin sys_clkreq sys_xtalout sys_xtalin sys_clkreq sys_xtalout sys_xtalin sys_clkreq From power IC: 32 768-Hz SWPS038-006 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com

4 Clock Specifications

For more information,see thePower,Reset,and ClockManagement /PRCM Environment/ ExternalClock Signaland Power, Reset and Clock Management / PRCM Functional Description/ PRCM Clock Manager FunctionalDescriptionsectionsof the AM/DM37x MultimediaDeviceTechnicalReferenceManual (SPRUGN4 ). Figure4-1shows externalinputclocksourcesand outputclocks. Figure4-1.Clock Interface

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 The deviceoperationrequiresthefollowingthreeinputclocks:

• The sys_32k 32-kHz clockisused forlow frequencyoperation.Itsuppliesthe wake-up domain for operationinlowestpower mode (offmode).Thisclockisprovidedthroughthesys_32kpin.
• The sys_altclksystem alternativeclockcan be used (throughthesys_altclkpin)toprovidealternative 48 MHz or54 MHz.
• The sys_xtalin/ sys_xtaloutsystem inputclock(12,13, 16.8,19.2,26, or 38.4 MHz) isused to generatethemain sourceclockofthedevice.ItsuppliestheDPLLs as wellas severalothermodules. The systeminputclockcan be connectedtoeither: – A crystaloscillatorclockmanaged by sys_xtalinand sys_xtalout.In thiscase,the sys_clkreqis used as an input(GPIN). – A CMOS digitalclockthroughthesys_xtalinpin.Inthiscase,thesys_clkreqisused as an outputto requesttheexternalsystemclock. The deviceoutputsexternallytwo clocks:
• sys_clkout1can outputtheoscillatorclock(12,13,16.8,19.2,26,or38.4MHz) atany time.Itcan be controlledby softwareor externallyusingsys_clkreqcontrol.When thedeviceisintheoffstate,the sys_clkreqcan be assertedtoenabletheoscillatorand activatethesys_clkout1withoutwakingup the device.The offstatepolarityofsys_clkout1isprogrammable.
• sys_clkout2can outputtheoscillatorclock(12,13,16.8,19.2,26,or38.4MHz), core_clk(coreDPLL output),96 MHz or 54 MHz. Itcan be dividedby 2, 4, 8, or 16 and itsoffstatepolarityis programmable.Thisoutputisactiveonlywhen thecorepower domain isactive.

4.1 InputClock Specifications

4.1.1 InputClock Requirements

Table4-1illustratestherequirementstosupplya clocktothedevice. Table4-1.InputClock Requirements (4) PAD CLOCK FREQUENCY STABILITY DUTY CYCLE JITTER TRANSITION sys_32k 32.768kHz +/-200 ppm - - <10 ns sys_xtalout 12,13,16.8,or19.2MHz Crystal ±50 ppm (±5 - - - sys_xtalin ppm)(1) 12,13,16.8,19.2,26,or38.4MHz Square ±50 ppm (±5 45% to55% X% (2)* 10 ns ppm)(1) tc(xtalin)(3)- 200ps sys_altclk 48 or54 MHz +/-50ppm 49% to51% <1% 10 ns (1) ± 50 ppm istheclockfrequencystability/accuracyand ± 5 ppm takesintoaccounttheagingeffects. (2) Dependingon theinternalsystemclockdividerconfiguration(PRCM.PRM_CLKSRC_CTRL[7:6], SYSCLKDIV bitfield),thesys_xtalin inputclockcan be dividedby 2 toprovidethestandardsystemclock(SYS_CLK) frequencies. Formore information,see thePower,Reset,and ClockManagement chapteroftheAM/DM37x MultimediaDeviceTechnicalReference Manual (SPRUGN4 ).InX%, X representsthentheinternalsystemclockdividerwithfollowingpossiblevalues:X = 1 or2. (3) tc(xtalin)isthesys_xtalincycletimeoftheclockcoming tosys_xtalinball. (4) Inthistable,thetransitiontimesarecalculatedfor10%-90% ofVDDS. Formore informationon thecorrespondingVDDS power supply name, pleasesee theBallCharacteristicstablecorrespondingtoyourpackage.The POWER column definestheVDDS power supply foreach ball. Copyright© 2010–2011,Texas InstrumentsIncorporated ClockSpecifications 133 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

sys_xtalin sys_xtalgnd sys_xtalout Cf1 Cf2 Crystal DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com 4.1.2 sys_xtalin/sys_xtaloutExternalCrystal An externalcrystalisconnectedtothedevicepins.Figure4-2describesthecrystalimplementation. Figure4-2.CrystalImplementation 1. When thecrystaloscillatorisinbypassmode (crystalimplementationisunused),thesys_xtalgndball isnotconnected. The crystalmust be inthefundamentalmode ofoperationand parallelresonant.Table4-2 summarizes therequiredelectricalconstraints. Table4-2.CrystalElectricalCharacteristics(1) NAME DESCRIPTION MIN TYP MAX UNIT fp Parallelresonancecrystalfrequency(1) 12,13,16.8,or19.2 MHz C f1 C f1loadcapacitanceforcrystalparallelresonancewithC f1= C f2 12 24 pF C f2 C f2loadcapacitanceforcrystalparallelresonancewithC f1= C f2 12 24 pF ESR(C f1,Cf2)(2) Frequency12 MHz ,Negativeresistoratnominal500 Ω,Negative 100 Ω resistoratworstcase 300 Ω Frequency13 MHz, Negativeresistoratnominal400 Ω,Negative 80 Ω resistoratworstcase 240 Ω Frequency16.8MHz and 19.2MHz, Negativeresistoratnominal 60 Ω 300 Ω,Negativeresistoratworstcase 180 Ω C o Crystalshuntcapacitance 4.5 pF DL Crystaldrivelevel 0.5 mW (1) Measured withtheloadcapacitancespecifiedby thecrystalmanufacturer.Thisloadisdefinedby thefootcapacitancestiedinseries.If C L = 20 pF,thenbothfootcapacitorswillbe C f1= C f2= 40 pF.Parasiticcapacitancefrompackage and boardmust alsobe takenin account. (2) The crystalmotionalresistanceR m isrelatedtotheequivalentseriesresistance(ESR) by thefollowingformula: ESR = R m *(1+ (CO *C f1*C f2/(Cf1+ C f2)))2. When selectinga crystal,the system design must take intoaccount the temperatureand aging characteristicsofa crystalversustheuserenvironmentand expectedlifetimeofthesystem.

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table4-3detailstheswitchingcharacteristicsoftheoscillatorand therequirementsoftheinputclock. Table4-3.OscillatorSwitchingCharacteristics—CrystalMode NAME DESCRIPTION MIN TYP MAX UNIT fp Oscillationfrequency 12,13,16.8,or19.2 MHz tsX Start-uptime(1)(2) 3 ms (1) Start-uptimeisdefinedas thetimetheoscillatortakestogainsys_xtalinamplitudeenough tohave 45% to55% dutycycleatthecore inputfromthetimepower down (PWRDN) isreleased.Start-uptimeisa strongfunctionofcrystalparameters.Atpower-onreset,the timeisadjustableusingthepinitself.The resetmust be releasedwhen theoscillatororclocksourceisstable.To switchfrombypass mode tocrystalorfromcrystalmode tobypassmode, thereisa waitingtimeabout100 μs;however,ifthechipcomes frombypass mode tocrystalmode thenthecrystalwillstart-upaftertimementionedinthetsX parameter. (2) Beforetheprocessorbootsup and theoscillatorissettobypassmode, thereisa waitingtimewhen theinternaloscillatorisin applicationmode and receivesa squarewave.The switchingtimeinthiscase isabout100 μs. 4.1.3 sys_xtalinSquarer InputClock Table4-4summarizesthebase oscillatorelectricalcharacteristics. Table4-4.OscillatorElectricalCharacteristics—Bypass Mode NAME DESCRIPTION MIN TYP MAX UNIT f Frequency 12,13,16.8,19.2,26,or38.4 MHz C i InputCapacitance 1.00 1.15 1.35 pF R i InputResistance 160 216 280 Ω tsX Start-uptime(1) See(2) ms (1) To switchfrombypassmode tocrystalmode orfromcrystalmode tobypassmode, thereisa waitingtimeabout100 μs;however,ifthe chipcomes frombypassmode tocrystalmode thenthecrystalwillstart-upaftertimementionedinTable4-3,tsX parameterabove. (2) Beforetheprocessorbootsup and theoscillatorissettobypassmode, thereisa waitingtimewhen theinternaloscillatorisin applicationmode and receivesa squarewave.The switchingtimeinthiscase isabout100 μs. Copyright© 2010–2011,Texas InstrumentsIncorporated ClockSpecifications 135 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

sys_xtalin OSC0 OSC1 OSC1 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table4-5detailsthesquarerinputclocktimingrequirements. Table4-5.sys_xtalinSquarer InputClock Timing Requirements—Bypass Mode (5) NAME DESCRIPTION MIN TYP MAX UNIT OCS0 1 /tc(xtalin) Frequency,sys_xtalin 12,13,16.8,19.2,26,or38.4 MHz OCS1 tw(xtalin) Pulseduration,sys_xtalinloworhigh 0.45*tc(xtalin) 0.55*tc(xtalin) ns tJ(xtalin) Peak-to-peakjitter(1),sys_xtalin X% (2)* ps tc(xtalin)(3)- 200 tR(xtalin) Risetime,sys_xtalin 10 ns tF(xtalin) Falltime,sys_xtalin 10 ns tJ(xtalin) Frequencystability,sys_xtalin +/-50 ppm (+/-5ppm)(4) (1) – Peak-to-peakjitterismeant hereas follows: – The maximum valueisthedifferencebetween thelongestmeasured clockperiodand theexpectedclockperiod – The minimum valueisthedifferencebetween theshortestmeasured clockperiodand theexpectedclockperiodMaximum and minimum areobtainedon a statisticalpopulationof300 periodsamplesand expressedrelativetotheexpectedclockperiod (2) Dependingon theinternalsystemclockdividerconfiguration(PRCM.PRM_CLKSRC_CTRL[7:6], SYSCLKDIV bitfield),thesys_xtalin inputclockcan be dividedby 2 toprovidethestandardsystemclock(SYS_CLK) frequencies.Formore information,see thePower, Reset,and ClockManagement chapteroftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (SPRUGN4 ).InX%, X representsthentheinternalsystemclockdividerwithfollowingpossiblevalues:X = 1 or2. (3) tc(xtalin)isthesys_xtalincycletimeoftheclockcoming tosys_xtalinball. (4) ±50 ppm istheclockfrequencystability/accuracyand ±5 ppm takesintoaccounttheagingeffects. (5) Inthistable,thetransitiontimesarecalculatedfor10%-90% ofVDDS. Formore informationon thecorrespondingVDDS power supply name, pleasesee theBallCharacteristicstablecorrespondingtoyourpackage.The POWER column definestheVDDS power supply foreach ball. Figure4-3.sys_xtalinSquarer InputClock 4.1.4 sys_32k CMOS InputClock Table4-6summarizestheelectricalcharacteristicsofthesys_32kinputclock. Table4-6.sys_32k InputClock ElectricalCharacteristics NAME DESCRIPTION MIN TYP MAX UNIT f Frequency,sys_32k 32.768 kHz C i Inputcapacitance 1.6 pF R i Inputresistance 3 106 M Ω Table4-7 detailstheinputrequirementsofthesys_32kinputclock. Table4-7.sys_32k InputClock Timing Requirements(1) NAME DESCRIPTION MIN TYP MAX UNIT CK0 1 /tc(32k) Frequency,sys_32k 32.768 kHz tR(32k) Risetime,sys_32k 10 ns tF(32k) Falltime,sys_32k 10 ns tJ(32k) Frequencystability,sys_32k 200 ppm

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sys_32k CK0 CK1 CK1 SWPS038-010 sys_altclk AL T0 AL T1 AL T1 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) Inthistable,thetransitiontimesarecalculatedfor10%-90% ofVDDS. Formore informationon thecorrespondingVDDS power supply name, pleasesee theBallCharacteristicstablecorrespondingtoyourpackage.The POWER column definestheVDDS power supply foreach ball. Figure4-4.sys_32k InputClock 4.1.5 sys_altclkCMOS InputClock Table4-8summarizestheelectricalcharacteristicsofthesys_altclkinputclock. Table4-8.sys_altclkInputClock ElectricalCharacteristics NAME DESCRIPTION MIN TYP MAX UNIT f Frequency,sys_altclk 48 or54 MHz Ci Inputcapacitance 1.6 pF Ri Inputresistance 3 106 M Ω Table4-9detailstheinputrequirementsofthesys_altclkinputclock. Table4-9.sys_altclkInputClock Timing Requirements(2) NAME DESCRIPTION MIN TYP MAX UNIT ALT0 1 /tc(altclk) Frequency,sys_altclk 48 or54 MHz ALT1 tw(altclk) Pulseduration,sys_altclkloworhigh 0.49*tc(altclk) 0.51*tc(altclk) ns tJ(altclk) Peak-to-peakjitter(1),sys_altclk -1% 1% tR(altclk) Risetime,sys_altclk 10 ns tF(altclk) Falltime,sys_altclk 10 ns tJ(altclk) Frequencystability,sys_altclk 50 ppm (1) Peak-to-peakjitterismeant hereas follows: – The maximum valueisthedifferencebetween thelongestmeasured clockperiodand theexpectedclockperiod – The minimum valueisthedifferencebetween theshortestmeasured clockperiodand theexpectedclockperiodMaximum and minimum areobtainedon a statisticalpopulationof300 periodsamplesand expressedrelativetotheexpectedclockperiod (2) Inthistable,thetransitiontimesarecalculatedfor10%-90% ofVDDS. Formore informationon thecorrespondingVDDS power supply name, pleasesee theBallCharacteristicstablecorrespondingtoyourpackage.The POWER column definestheVDDS power supply foreach ball. Figure4-5.sys_altclkInputClock Copyright© 2010–2011,Texas InstrumentsIncorporated ClockSpecifications 137 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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4.2 Output Clocks Specifications

4.2.1 sys_clkout1Output Clock Table4-10summarizesthesys_clkout1ouputclockelectricalcharacteristics. Table4-10.sys_clkout1Output Clock ElectricalCharacteristics NAME DESCRIPTION MIN TYP MAX UNIT f Frequency,sys_clkout1 sys_xtalin/sys_xtaloutclockfrequency MHz SC[0:1]= 00(1) C L Load capacitance(transmissionlineload+ farend load) 4 60 pF ZT Transmissionlineimpedance 30 70 Ω LT Transmissionlinelength 2 20 cm SC[0:1]= 01(1) C L Load capacitance(transmissionlineload+ farend load) 7 33 pF ZT Transmissionlineimpedance 30 70 Ω LT Transmissionlinelength 2 8 cm SC[0:1]= 10(1) C L Load capacitance(transmissionlineload+ farend load) 2 21 pF ZT Transmissionlineimpedance 30 70 Ω LT Transmissionlinelength 1 6 cm (1) The mode isconfiguredby bitsSC0 and SC1 oftheIO cell.Formore details,see theAM/DM37x MultimediaDeviceTechnical ReferenceManual (SPRUGN4 ). Table4-11detailsthesys_clkout1ouputclockswitchingcharacteristics. Table4-11.sys_clkout1Output Clock SwitchingCharacteristics(6) NAME DESCRIPTION MIN TYP MAX UNIT CO0 1 /tc(CLKOUT1) Frequency,sys_clkout1 sys_xtalin/sys_xtaloutclockfrequency MHz SC[0:1]= 00(1) C L Load capacitance 4 60 pF tJ Peak-to-peakjitter X(5)+ 693 ps tJC2C Cycle-to-cyclejitter X(5)+ 705 ps tW(CLKOUT1) Pulseduration,sys_clkout1loworhigh 0.45*tc(CLKOUT 0.55*tc(CLKOUT 1) 1) tR(CLKOUT1) Risetime,sys_clkout1 1(2)(4) 15(3) ns tF(CLKOUT1) Falltime,sys_clkout1 1(2)(4) 15(3) ns SC[0:1]= 01(1) C L Load capacitance 7 33 pF tJ Peak-to-peakjitter X(5)+ 543 ps tJC2C Cycle-to-cyclejitter X(5)+ 555 ps tW(CLKOUT1) Pulseduration,sys_clkout1loworhigh 0.45*tc(CLKOUT 0.55*tc(CLKOUT 1) 1) tR(CLKOUT1) Risetime,sys_clkout1 0.6(2)(4) 7(3) ns tF(CLKOUT1) Falltime,sys_clkout1 0.6(2)(4) 7(3) ns SC[0:1]= 10(1) C L Load capacitance 2 21 pF tJ Peak-to-peakjitter X(5)+ 603 ps tJC2C Cycle-to-cyclejitter X(5)+ 615 ps tW(CLKOUT1) Pulseduration,sys_clkout1loworhigh 0.47*tc(CLKOUT 0.53*tc(CLKOUT 1) 1) tR(CLKOUT1) Risetime,sys_clkout1 0.4(2)(4) 5(3) ns

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sys_clkout1 CO0 CO1 CO1 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table4-11.sys_clkout1Output Clock SwitchingCharacteristics(6)(continued) NAME DESCRIPTION MIN TYP MAX UNIT tF(CLKOUT1) Falltime,sys_clkout1 0.4(2)(4) 5(3) ns (1) The mode isconfiguredby bitsSC0 and SC1 oftheIO cell.Formore details,see theAM/DM37x MultimediaDeviceTechnical ReferenceManual (SPRUGN4 ). (2) Atminimum load (3) Atmaximum load(Maximum frequency20 MHz) (4) Caution:thiscreatesEMI parasiticsup to1.2ns (5) X parametercorrespondstotheinputjittercontributionadded atsys_xtalininputpin.Formore informationregardingthesys_xtalininput jitterrequirement,see Section4.1.1. (6) Inthistable,thetransitiontimesarecalculatedfor10%-90% ofVDDS. Formore informationon thecorrespondingVDDS power supply name, pleasesee theBallCharacteristicstablecorrespondingtoyourpackage.The POWER column definestheVDDS power supply foreach ball. Figure4-6.sys_clkout1Output Clock 4.2.2 sys_clkout2Output Clock Table4-12summarizesthesys_clkout2ouputclockelectricalcharacteristics. Table4-12.sys_clkout2Output Clock ElectricalCharacteristics NAME DESCRIPTION MIN TYP MAX UNIT f Frequency,sys_clkout2 sys_xtalinclockorcore_dpllclock(1)or54 MHz MHz, 96 MHz (2) C L Load capacitance 2 22 pF ZT Transmissionlineimpedance 30 70 Ω LT Transmissionlinelength 1 6 cm (1) Possibledivider:4,8,or16. (2) Possibledivider:1,2,4,8,or16. Table4-13detailsthesys_clkout2ouputclockswitchingcharacteristics. Table4-13.sys_clkout2Output Clock SwitchingCharacteristics(8) NAME DESCRIPTION MIN TYP MAX UNIT CO0 1 /tc(CLKOUT2) Frequency,sys_clkout2 sys_xtalinclockorcore_dpllclock(3)or54 MHz MHz, 96 MHz (4) tc(xtalin) Cycletime,sys_xtalin 1 /sys_xtalin ns (MHz) tc(coredpll) Cycletime,core_dpll(DPLL3)(7) 1 /core_dpll ns (MHz) tc(54mhz) Cycletime,54MHz clock(DPLL4)(7) 18.52 ns tc(96mhz) Cycletime,96MHz clock(DPLL4)(7) 10.42 ns CO1 tw(CLKOUT2) Pulseduration,sys_clkout2loworhigh 0.49*tc(clkout 0.51*tc(clkout ns 2) 2) Copyright© 2010–2011,Texas InstrumentsIncorporated ClockSpecifications 139 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

sys_clkout2 CO0 CO1 CO1 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table4-13.sys_clkout2Output Clock SwitchingCharacteristics(8)(continued) NAME DESCRIPTION MIN TYP MAX UNIT tJ(5) Peak-to-peakjitter Sourceclock: X% (6)* ps sys_xtalin tc(xtalin)+ 200 Sourceclock: 4% * ps core_dpll tc(coredpll)+ 200 Sourceclock:54MHz 4% *tc(54mhz) ps + 200 Sourceclock:96MHz 4% *tc(96mhz) ps + 200 tR(CLKOUT2) Risetime,sys_clkout2 1.5(1) 5(2) ns tF(CLKOUT2) Falltime,sys_clkout2 1.5(1) 5(2) ns (1) Atminimum load (2) Atmaximum load(maximum frequency104 MHz) (3) Possibledivider:4,8,16 (4) Possibledivider:1,2,4,8,or16 (5) Peak-to-peakjitterismeant hereas follows: – The maximum valueisthedifferencebetween thelongestmeasured clockperiodand theexpectedclockperiod – The minimum valueisthedifferencebetween theshortestmeasured clockperiodand theexpectedclockperiod Maximum and minimum areobtainedon a statisticalpopulationof300 periodsamplesand expressedrelativetotheexpectedclock period. (6) Dependingon theinternalsystemclockdividerconfiguration(PRCM.PRM_CLKSRC_CTRL[7:6], SYSCLKDIV bitfield),thesys_xtalin inputclockcan be dividedby 2 toprovidethestandardsystemclock(SYS_CLK) frequencies.Formore information,see thePower, Reset,and ClockManagement /PRCM FunctionalDescription/PRCM ClockManager FunctionalDescription/ExternalClockI/Os/ ExternalClockInputs/High-FrequencySystem ClocksectionofAM/DM37x MultimediaDeviceTechnicalReferenceManual (literature number SPRUGN4 ). InX%, X representsthentheinternalsystemclockdividerwithfollowingpossiblevalues:X = 1 or2. (7) Thiscycletimespecifiedhereistheclockperiodoftheclockgoingoutofsys_clkout2. (8) Inthistable,thetransitiontimesarecalculatedfor10%-90% ofVDDS. Formore informationon thecorrespondingVDDS power supply name, pleasesee theBallCharacteristicstablecorrespondingtoyourpackage.The POWER column definestheVDDS power supply foreach ball. Figure4-7.sys_clkout2Output Clock

4.3 DPLL and DLL Specifications

For more information,see Power, Reset, and Clock Management / PRCM Functional Description/ PRCM Clock Manager FunctionalDescription/ InternalClock Generation/ DPLLs section of the AM/DM37x Multimedia Device Technical Reference Manual (SPRUGN4 ). The applicativesubsystemintegratessixDPLLs and a DLL. The PRM and CM drivethoselistedbelow. The main DPLLs are:

• DPLL1 (MPU)
• DPLL2 (IVA)
• DPLL3 (Core)
• DPLL4 (Peripherals)
• DPLL5 (SecondperipheralsDPLL)

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4.3.1 DPLL Characteristics

Table 4-14 summarizes the DPLL characteristicsand assumes testingover recommended operating conditions. Table4-14.DPLL1 -DPLL2 -DPLL3 -DPLL5 Characteristics NAME DESCRIPTION MIN TYP MAX UNIT COMMENTS vdda_dplls_dll SupplyvoltageforDPLLs (MPU ,IVA, 1.71 1.8 1.91 V and Core)and DLL vdda_dpll_per SupplyvoltageforDPLL 1.71 1.8 1.91 V (Peripherals) finput CLKINP Inputfrequency 0.032 52 MHz FINP finternal Internalreferencefrequency 0.032 52 MHz REFCLK fCLKINPHIF CLKINPHIF Inputfrequency 10 1000 MHz FINPHIF fCLKINPULOW CLKINPULOW Inputfrequency 0.001 800 MHz fCLKOUT CLKOUT outputfrequency 10(1) 1000(2) MHz [M /(N + 1)]*FINP *[1/ M2] fCLKOUTx2 CLKOUTx2 outputfrequency 20(1) 2000(2) MHz 2 *[M /(N + 1)]*FINP *[1 /M2] fCLKOUTHIF CLKOUTHIF outputfrequency 10(3) 1000(4) MHz FINPHIF /M3 /M3] fDCOCLKLDO DCOCLKLDO outputfrequency 20 2000 MHz 2 *[M /(N + 1)]*FINP tlock Frequencylocktime 1.9+ μs 350*REFCLK plock Phase locktime 1.9+ μs 500*REFCLK trelock-L Relocktime—Frequencylock(5)(Low 1.9+ 70*REFCLK μs DPLL inlow-powermode: power bypass) lowcurrstdby= 1 prelock-L Relocktime—Phase lock(5)(Low 1.9+ μs DPLL inlow-powermode: power bypass) 120*REFCLK lowcurrstdby= 1 trelock-F Relocktime—Frequencylock(5)(Fast 0.05+ μs DPLL innormalmode: relockbypass) 70*REFCLK lowcurrstdby= 0 prelock-F Relocktime—Phase lock(5)(Fast 0.05+ μs DPLL innormalmode: relockbypass) 120*REFCLK lowcurrstdby= 0 (1) The minimum frequencieson CLKOUT and CLKOUTX2 areassumingM2 = 1.ForM2 > 1,theminimum frequencyon theseclockswill furtherscaledown by factorofM2. (2) The maximum frequencieson CLKOUT and CLKOUTX2 areassumingM2 = 1. (3) The minimum frequencyon CLKOUTHIF isassumingM3 = 1.ForM3 > 1,theminimum frequencyon thisclockwillfurtherscaledown by factorofM3. (4) The maximum frequencyon CLKOUTHIF isassumingM3 = 1. (5) Relocktimeassumes typicaloperatingconditions,10°C maximum temperaturedrift. Table4-15.DPLL4 Characteristics NAME DESCRIPTION MIN TYP MAX UNIT COMMENTS vdda_dpll_per SupplyvoltageforDPLL (peripherals) 1.71 1.8 1.91 V finput CLKINP inputclockfrequency 0.5 60 MHz FINP finternal REFCLK internalreferencefrequency 0.5 2.5 MHz REFCLK fCLKINPULOW CLKINPULOW bypassinput 0.001 800 MHz frequency fCLKOUT CLKOUT outputclockfrequency 10(1) 2000(2) MHz [M /(N + 1)]*FINP *[1/ M2] fDCOCLKLDO Internaloscillator(DCO) outputclock 500 2000 MHz [M /(N + 1)]*FINP frequency tlock Frequencylocktime 350*REFCLK μs plock Phase locktime 500*REFCLK μs trelock-L Relocktime—Frequencylock(3)(Low 7.5+ μs DPLL inlow-powermode: power bypass) 30*REFCLKs lowcurrstdby= 1 Copyright© 2010–2011,Texas InstrumentsIncorporated ClockSpecifications 141 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table4-15.DPLL4 Characteristics(continued) NAME DESCRIPTION MIN TYP MAX UNIT COMMENTS prelock-L Relocktime—Phase lock(3)(Low 7.5+ μs DPLL inlow-powermode: power bypass) 125*REFCLKs lowcurrstdby= 1 trelock-F Relocktime—Frequencylock(3)(Fast NA μs relockbypass) prelock-F Relocktime—Phase lock(3)(Fast NA μs relockbypass) (1) The minimum frequencyon CLKOUT isassumingM2 = 1.ForM2 > 1,theminimum frequencyon thisclockwillfurtherscaledown by factorofM2. (2) The maximum frequencyon CLKOUT isassumingM2 = 1. (3) Relocktimeassumes typicaloperatingconditions,10°C maximum temperaturedrift.

4.3.2 DLL Characteristics

Table 4-16 summarizes the DLL characteristicsand assumes testingover recommended operating conditions. Table4-16.DLL Characteristics NAME DESCRIPTION MIN TYP MAX UNIT COMMENTS vdda_dplls_dll SupplyvoltageforDPLLs (MPU ,IVA,and 1.71 1.8 1.91 V Core)and DLL finput Inputclockfrequency(1) 66 120 200 MHz Eitherapplicationmode 0 and 1 tlock Lock time 500 Clocks trelock Relocktime(Mode transitionsthroughidle 500 ns IDLE toMODEMAXDELAY mode) 250 450 Clocks IDLE toAPPLICATION MODE 1 or0 1.88 3.38 μs IDLE toAPPLICATION MODE @133 MHz 1.50 2.71 μs IDLE toAPPLICATION MODE @166 MHz 1.25 2.25 μs IDLE toAPPLICATION MODE @200 MHz (1) Maximum frequencyfornominalconditions.

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DPLL_MPU DPLL_CORE DLL DPLL5 DPLL4 vdda_dplls_dll vdda_dpll_per C Noise Filter C Noise Filter 030-017 DPLL_IVA DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011

4.3.3 DPLL and DLL Noise Isolation

The noisefilters(decouplingcapacitors)are requiredtosuppresstheswitchingnoisegeneratedby high frequencyand tostabilizethesupplyvoltage. A noisefilterismost effectivewhen itisclosetothedevice,because thisminimizestheinductanceofthe circuitboardwiringand interconnects. Figure4-8illustratesan example ofa noisefilter. A. Thiscircuitisprovidedonlyas an example. B. The filtermust be locatedas closeas possibletothedevice. Figure4-8.DPLL Noise Filter Table4-17specifiesthenoisefilterrequirements. Table4-17.DPLL Noise FilterRequirements(1) NAME MIN TYP MAX UNIT Filteringcapacitor 50 100 150 nF (1) Formore information,see IO and AnalogVoltageDecouplingCapacitors.

4.3.4 Processor Clocks

Table4-18throughTable4-20show theclocksAC performancevalues. Table4-18.Processor VoltagesWithoutSmartReflexTM RETENTIO OPP50 OPP100 OPP130 (3) N MIN MIN TYP MAX MIN TYP MAX MIN TYP MAX (V) (1) Atballlevel. (2) Minimum OPP voltagevaluesdefinedinthistableincludeany voltagetransient. (3) OPP130 isnotavailableabove TJ of90C. Table4-19.Processor VoltagesWith SmartReflexTM RETENTIO OPP50 OPP100 OPP130 (4) OPP1G (4)(5)(6) N MIN MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX Copyright© 2010–2011,Texas InstrumentsIncorporated ClockSpecifications 143 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table4-19.Processor VoltagesWith SmartReflexTM (continued) RETENTIO OPP50 OPP100 OPP130 (4) OPP1G (4)(5)(6) N (3)(V) (1) Atballlevel. (2) These VDD1 (vdd_mpu_iva)valuesaretherequiredvoltagerangespriortoenablingtheSmartReflexAVS feature.Aftercalibration,the minimum voltagemay be lowerthanthisspecification. (3) Minimum OPP voltagevaluesdefinedinthistableincludeany voltagetransient. (4) OPP130 and OPP1G arenotavailableabove TJ of90C. (5) OPP1G isa highperformanceoperatingpointwhichhas followingrequirements: – ABB LDO must be settoFBB (ForwardBody Bias)mode when switchingtothisOPP. Itrequireshavinga 1μF capacitorconnected tocap_vdd_bb_mpu_iva. – AVS (AdaptiveVoltageScaling)power techniquemust be used toachieveoptimum operatingvoltage. (6) Based on DM3730 PCB constraints,thevdd_mpu_iva(VDD1) voltagevaluecalibratedbeforeenablingSmartReflex™ isrecommended Formore informationon vdd_mpu_ivapower deliverynetworkdesignrequirements,see thePCB DesignRequirementsfor VDD_MPU_IVA Power DistributionNetworkforTIOMAP3630, AM37xx, and DM37xx Microprocessors(SPRABJ7) applicationnote. Table4-20.Processor Clocks OPP50 OPP100 OPP130 OPP1G (2) Description SourceClock Max Ratio Max Ratio Max Ratio Max Ratio Freq.(MHz) Freq.(MHz) Freq.(MHz) Freq.(MHz) DPLL1 - 1200 - 1200 - 1600 - 2000 - Locked Frequency DPLL1CLKO DPLL1 300 2 *(M2 = 600 2 *(M2 = 800 2 *(M2 = 1000 2 *(M2 = Frequency DPLL2 - 1040 - 1040 - 1320 - 1600 - Locked Frequency DPLL2CLKO DPLL2 260 2 *(M2 = 520 2 *(M2 = 660 2 *(M2 = 800 2 *(M2 = Frequency ARM_FCLK DPLL1CLKO 300 1 600 1 800 1 1000 1 UT_M2 IVA_CLK DPLL2CLKO 260 1 520 1 660 1 800 1 UT_M2 (1) Thisratioisconfigurableby softwareprogramming.Formore information,see theAM/DM37x MultimediaDeviceTechnicalReference Manual (SPRUGN4 ). (2) OPP1G isa highperformanceoperatingpointwhichhas followingrequirements: – ABB LDO must be settoFBB (ForwardBody Bias)mode when switchingtothisOPP. Itrequireshavinga 1μF capacitorconnected tocap_vdd_bb_mpu_iva. – AVS (AdaptiveVoltageScaling)power techniquemust be used toachieveoptimum operatingvoltage. (3) Formore informationaboutARM_FCLK and IVA2_CLK processorclocksconfiguration,see thePower,Reset,and ClockManagement / PRCM FunctionalDescription/PRCM ClockManager FunctionalDescription/ClockConfigurations/ProcessorClockConfigurations sectionortheMPU Subsystem /MPU Subsystem Integration/MPU Subsystem Clockand ResetDistribution/ClockDistributionsection oftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (SPRUGN4 ). (4) The DPLL ratiosdocumented inthistablearerecommended ratios.Othervaluesmay apply.

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4.3.5 Device Core Clocks

Table4-21and Table4-22show thedevicecoreclocksAC performancevalues. Table4-21.Device Core Voltages RETENTION OPP50 OPP100 MIN MIN TYP MAX MIN TYP MAX (1) Atballlevel. (2) Minimum OPP voltagevaluesdefinedinthistableincludeany voltagetransient. (3) When SmartReflex™ isnotused,thesevaluesdefinetherequiredvoltagerange.When SmartReflex™ willbe used,thesevoltagesare therequiredvoltagerangepriortoenablingtheSmartReflex™ feature.Aftercalibration,theminimum voltagemay be lowerthanthis specification. Table4-22.Device Core Clocks OPP50 OPP100 DescriptiSource Max Ratio Max Ratio Max Ratio Max Ratio Max Ratio Max Ratio z) z) z) z) z) z) DPLL3 - 800 - 664 - 400 - 800 - 664 - 532 - Locked Frequenc y DPLL3C DPLL3 200 2 *(M2 = 166 2 *(M2 = 200 2 *(M2 = 400 2 *(M2 = 332 2 *(M2 = 266 2 *(M2 = M2 Frequenc y CORE_C DPLL3C 200 1 166 1 200 1 400 1 332 1 266 1 LK LKOUT_ L3_ICLK CORE_C 100 2(1) 83 2(1) 100 2(1) 200 2(1) 166 2(1) 133 2(1) LK L4_ICLK L3_ICLK 50 2(1) 41.5 2(1) 50 2(1) 100 2(1) 83 2(1) 66.5 2(1) SDRC_C L3_ICLK 100 1 83 1 100 1 200 1 166 1 133 1 LK GPMC_C L3_ICLK 50 2(1) 41.5 2(1) 50 2(1) 100 2(1) 83 2(1) 66.5 2(1) LK (1) Thisratioisconfigurableby softwareprogramming.Formore information,see theAM/DM37x MultimediaDeviceTechnicalReference Manual (SPRUGN4 ). (2) The DPLL ratiosdocumented inthistablearerecommended ratios.Othervaluesmay apply.

4.3.6 Graphic Accelerator(SGX) Clocks

Table 4-23 and Table 4-24 show the recommended VDD2 (correspondingto vdd_core,Core and SGX voltageat balllevel)voltagesranges and the standard graphicaccelerator(SGX) clocks speed characteristicsvs VDD2 . Table4-23.Graphic AcceleratorVoltages OPP 100 (2) MIN TYPICAL MAX VDD2 (1) Atballlevel. (2) SGX (GraphicAccelerator)isnotavailableintheOPP50 operatingpoint. (3) When SmartReflex™ isnotused,thesevaluesdefinetherequiredvoltagerange.When SmartReflex™ willbe used,thesevoltagesare therequiredvoltagerangepriortoenablingtheSmartReflex™ feature.Aftercalibration,theminimum voltagemay be lowerthanthis specification. (4) Minimum OPP voltagevaluesdefinedinthistableincludeany voltagetransient. Copyright© 2010–2011,Texas InstrumentsIncorporated ClockSpecifications 145 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table4-24.Graphic AcceleratorClocks(2) OPP 100(2) Max Freq Max Freq Max FreqDescription Source Clock Ratio Ratio Ratio(MHz) (MHz) (MHz) DPLL3 Locked Frequency 800 664 532 DPLL4 Locked Frequency 1728 1728 1728 1 *(M2 = 1 *(M2 = 1 *(M2 =DPLL3CLKOUTX2_M2 DPLL3 Locked Frequency 800 664 5321)(1)(3) 1)(1)(3) 1)(1)(3) 2 *(M2 = 2 *(M2 = 2 *(M2 =DPLL3CLKOUT_M2 DPLL3 Locked Frequency 400 332 2661)(1)(3) 1)(1)(3) 1)(1)(3) 1 *(M2 = 1 *(M2 = 1 *(M2 =DPLL4CLKOUT_M2 DPLL4 Locked Frequency 192 192 1929)(1)(3) 9)(1)(3) 9)(1)(3) CORE_CLK DPLL4 Locked Frequency 400 1 332 1 266 1 COREX2_CLK DPLL3CLKOUTX2_M2 800 1 664 1 532 1 SGX_192M_FCLK DPLL4CLKOUT_M2 192 1 192 1 192 1 SGX – Option1 CORE_CLK 200 2 166 2 133 2 SGX – Option2 COREX2_CLK 177.3 3 SGX – Option3 SGX_192M_FCLK 192 1 192 1 192 1 (1) Thisratioisconfigurableby softwareprogramming.Formore information,see theAM/DM37x MultimediaDeviceTechnicalReference Manual (SPRUGN4 ). (2) SGX (GraphicAccelerator)isnotavailableinOPP50 operatingpoint. (3) The DPLL ratiosdocumented inthistablearerecommended ratios.Othervaluesmay apply.

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5 Video DAC Specifications

For more informationregardingthe VideoDAC architecture,see the DisplaySubsystem / DisplaySubsystem FunctionalDescription/ Video Encoder Functionalities/ Video DAC Stage—Architectureand Control sectionof AM/DM37x TechnicalReference Manual (literaturenumber SPRUGN4 ).

5.1 TVOUT BufferMode (DAC + Buffer)

AVDAC normalmode (DAC + Buffer),highervaluesoftheDAC inputcode providedby the Video Encoder willresultinloweroutputvoltagedue to the invertingconfigurationof the TVOUT Buffer.See Figure5-4formore detailson therelationbetween thecompositevideo signallevelsand theDAC code valuesfornormalmode ofoperation. InAVDAC bypassmode (DAC only),highervaluesoftheDAC inputcode willresultinhigher outputvoltage,as theTVOUT Bufferpathisbypassed. The connectionforthisTVOUT buffermode (DAC + Buffer)normal mode of operationis shown in Figure 5-1. The defaultmode of operationis dc coupling.For more informationregardingthe recommended values of the externalcomponents, see Section5.4, ElectricalSpecificationsOver Recommended OperatingConditions. Figure5-1.Recommended Loading ConditionsforTVOUT BufferMode (1) (1) Insingle-channelconfigurationonlychannel-1isused. Copyright© 2010–2011,Texas InstrumentsIncorporated VideoDAC Specifications 147 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

= External pin VREF TVDET TVBUF I DAC AVDAC vssa_dac vdda_dac cvideo1_out cvideo1_vfb cvideo1_rset RSET RLOAD OFF OFF DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com

5.2 TVOUT Bypass Mode (DAC Only)

Inthiscase,TVOUT bypass inputishighand theTVOUT bufferisbypassed (formore information,see Section 5.5, TVOUT Bypass Mode Specifications(DAC-Only) ElectricalSpecificationsOver Recommended OperatingConditions).Figure5-2 shows theconnection.For more informationregarding the recommended valuesof the externalcomponents,see Section5.4, ElectricalSpecificationsOver Recommended OperatingConditions. Figure5-2.Recommended Loading ConditionsforTVOUT Bypass Mode (1) (1) Insingle-channelconfigurationonlychannel-1isused.

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5.3 TVOUT Bypass Mode inDual-ChannelConfiguration

Inthiscase,TVOUT bypass inputishighand theTVOUT bufferisbypassed (formore information,see Section 5.5, TVOUT Bypass Mode Specifications(DAC-Only) ElectricalSpecificationsOver Recommended OperatingConditions).Figure5-3 shows theconnection.For more informationregarding the recommended valuesof the externalcomponents,see Section5.4, ElectricalSpecificationsOver Recommended OperatingConditions. Figure5-3.Recommended Loading ConditionsforTVOUT Bypass Mode inDual-ChannelConfiguration(1) (1) Here aresome connectionsrecommendations: – An externalresistorR SET = 10 kΩ (±1%) isrecommended tobe connectedtothecvideo1_rsetsignalofChannel1. – The cvideo1_rsetsignalofChannel2 isleftunconnected. – ExternalresistorsR LOAD1LOAD2 = 1.5kΩ (±1%) isrecommended tobe connectedtocvideo1_vfborcvideo2_vfbeach channel. Copyright© 2010–2011,Texas InstrumentsIncorporated VideoDAC Specifications 149 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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5.4 ElectricalSpecificationsOver Recommended OperatingConditions

High-swingmode isthedefaultmode. The low-swingmode isnotcompliantwiththeNTSC and PAL video-standards.Itshallbe used onlyforbackwardscompatibilitytoAM/DM37x.

• TVOUT DC HighSwing Mode: – R OUT1/2 = 2.7kΩ (±1%) – R SET = 4.7kΩ (±1%) – R LOAD = 75 Ω (±5%) – ZCABLE = 75 Ω (±5%)
• TVOUT DC Low Swing Mode: – R OUT1/2 = 2.7kΩ (±1%) – R SET = 6.8kΩ (±1%) – R LOAD = 75 Ω (±5%) – ZCABLE = 75 Ω (±5%)
• TVOUT AC HighSwing Mode: – R OUT1/2 = 2.7kΩ (±1%) – R SET = 4.7kΩ (±1%) – R LOAD = 75 Ω (±5%) – ZCABLE = 75 Ω (±5%)
• TVOUT AC Low Swing Mode: – R OUT1/2 = 2.7kΩ (±1%) – R SET = 6.8kΩ (±1%) – R LOAD = 75 Ω (±5%) – ZCABLE = 75 Ω (±5%) Table5-1.DAC – StaticElectricalSpecifications(8) PARAMETER CONDITIONS/ASSUMPTIONS MIN TYP MAX UNIT R Resolution 10 Bits DC ACCURACY INL(1) IntegralNon-Linearity(INL) 50 to111 inputcode range –6 6 LSB IntegralNon-Linearity(INL) 111 to895 inputcode range –4 4 Signalvideorange IntegralNon-Linearity(INL) 783 to1007 inputcode range –5 5 Synchronizationpulse DNL (2) Differentialnonlinearity 111 to895 inputcode range –2.5 2.5 LSB ANALOG OUTPUT - Outputvoltage 0 to1023 input Low-swingmode 0.70 0.88 1.00 V code range, High-swingmode 1.2 1.3 1.5R LOAD = 75 Ω - Gain error - Low-swingmode –20 20 % FS High-swingmode –10 10 R VOUT Outputimpedance 67.5 75.0 82.5 Ω REFERENCE VREF InternalBand Gap VoltageReference 0.55 V

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table5-1.DAC – StaticElectricalSpecifications(8)(continued) PARAMETER CONDITIONS/ASSUMPTIONS MIN TYP MAX UNIT POWER CONSUMPTION Ivdda-up AnalogSupply DC mode No Averagecurrenton vdda_dac,no 4.5 6.5 8.5 mA Current(4) load load,2 channels Inputcode 50 (maximum outputAC mode No 19 28 37voltage)load Fullload75-Ω 19 28 37 load Ivdda-up(peak) Peak analogsupplycurrent Lastslessthan1 ns 60 mA Ivdd-up Digitalsupplycurrent(5) Averagecurrent,measured atfCLK 2 mA = 54 MHz, fOUT = 2 MHz sinewave,vdd = 1.1 V Ivdd-up(peak) Peak digitalsupplycurrent(6) Peak current,full-scaletransition 8 mA lastinglessthan1 ns Ivdda-down(9) Analogsupplycurrent,totalpower T = 30ºC, vdda_dac = 1.8V,no 12 μA down (9) load Ivdda-stdby (9) Analogsupplycurrent,standbymode (9) Bandgap and internalLDO areON, 90 180 270 μA allotheranalogblocksareOFF, no load,T = 30 C º Ivdd-down(pm) (9) Digitalsupplycurrent,totalpower T = 30ºC, Full Low-swingmode 2 μA down (9) orPartialPower High-swingmode 6Management Ivdd-down(nopm) Digitalsupplycurrent,totalpower down T = 30ºC, VDD = 1.1V,no Power 60 μA (nopower management) Management (1) The INL ismeasured attheoutputoftheDAC (accessibleatan externalpinduringbypassmode).The INL atcode 783 equals0. (2) The DNL ismeasured attheoutputoftheDAC (accessibleatan externalpinduringbypassmode).The INL atcode 783 equals0. (3) ReferencePSR measures theeffectofa supplydisturbanceatcvideo1_outand cvideo2_out. (4) The analogsupplycurrentIvdda isdirectlyproportionaltothefull-scaleoutputcurrentIFS and isinsensitivetofCLK . (5) The digitalsupplycurrentIVDD isdependenton thedigitalinputwaveform,theDAC updateratefCLK ,and thedigitalsupplyVDD. (6) The peak digitalsupplycurrentoccursatfull-scaletransitionfordurationlessthan1 ns. (7) See Section5.6,AnalogSupply(vdda_dac)NoiseRequirements,foractualmaximum rippleallowedon vdda_dac. (8) Formore informationon code rangedefinition,see Figure5-4. (9) Formore informationon AVDAC power-up,power-down,and standbymode configurations,see DisplaySubsystem /Display Subsystem FunctionalDescription/VideoEncoderFunctionalities/VideoDAC StagePower Management sectionofAM/DM37x TechnicalReferenceManual (literaturenumber SPRUGN4 ). NOTE High-swingmode isthedefaultmode. The low-swingmode isnotcompliantwiththeNTSC and PAL video-standards.Itisused onlyforbackwardscompatibilitytoAM/DM37x. Copyright© 2010–2011,Texas InstrumentsIncorporated VideoDAC Specifications 151 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table5-2.Video DAC – Dynamic ElectricalSpecifications(6) PARAMET CONDITIONS/ASSUMPTIONS MIN TYP MAX UNIT ER fCLK (1) Outputupdaterate Equaltoinputclockfrequency 54 60 MHz Clockjitter RMS clockjitterrequiredinorderto 40 70 ps assure10-bitaccuracy Attenuationat5.1MHz Cornerfrequencyfor DC mode 1.5 dB signal AC mode BW Signalbandwidth 3 dB DC mode 6 MHz AC mode Differentialgain(2) 111 to895 inputcode DC mode –5% 5% range AC mode –5% 5% Differentialphase(2) 111 to895 inputcode DC mode –3º 3º range AC mode –3º 3º SFDR Withinbandwidth1 kHz to fCLK = 54 MHz, fOUT = 1 DC mode 40 50 70 dB

6 MHz MHz, sinewane input, AC mode111 to895 inputcode

SNR Withinbandwidth1 kHz to fCLK = 54 MHz, fOUT = 1 DC mode 50 54 75 dB

6 MHz MHz, sinewane input, AC mode256 to768 inputcode

PSR (4) Power supplyrejection(up 100 mVpp at6 MHz, inputcode 895 6(4) dB to6 MHz) Crosstalk Between thetwo video –50 –40 dB channels C Load TVOUT (cvideo_out1and Totaldecouplingcapacityfrom 300 pF cvideo_out2)stability, cvideo_out1orcvideo_out2toground, TVOUT decoupling C Load1 capacity C TOT TVOUT stability,total Totaldecouplingcapacity:C TOT = C Load1 600 pF TVOUT decoupling + C Load2 capacity (1) Forinternalinputclockinformation,see theDSS chapterofAM/DM37x TechnicalReferenceManual (literaturenumber SPRUGN4 ). (2) The differentialgainand phase valueisfordc coupling.Note thatthereisdegradationfortheac coupling.The DifferentialGain and Phase aremeasured withrespecttothegainand phase oftheburstsignal(–20 to20 IRE) (3) The SNR valueisfordc coupling. (4) PSR measures theeffectofa supplydisturbanceatcvideo1_outand cvideo2_out. (5) The flatband measurement isdone at500 kHz forcharacterizingtheattenuationat5.1MHz. (6) Formore informationon code rangedefinition,see Figure5-4.

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7.5 -20 -40

1.3 V *pp

DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Figure5-4describesthecompositevideosignallevels. Figure5-4.Composite Video SignalLevels(1)(2) (1) The 1.3VPP (peak-to-peak)isreferringtotheoutputsignalatcvideo1_outintheDAC + Buffercomposite-videomode. Note thatthe1.3VPP must applytobothcvideo1_outand cvideo2_outinDAC + Buffers-videomode (dual-DACmode configuredforac ordc coupling). (2) InAVDAC normalmode (DAC + Buffer),highervaluesoftheDAC inputcode providedby theVideoEncoderwillresultinloweroutput voltagedue totheinvertingconfigurationoftheTVOUT Buffer.See Figure5-4formore detailson therelationbetween thecomposite videosignallevelsand theDAC code valuesfornormalmode ofoperation. InAVDAC bypassmode (DAC only),highervaluesoftheDAC inputcode willresultinhigheroutputvoltage,as theTVOUTBuffer path isbypassed.

5.5 TVOUT Bypass Mode Specifications(DAC-Only)ElectricalSpecificationsOver

Recommended OperatingConditions NOTE The electricalcharacteristicsforsingle-and dual-channelbypass modes are the same exceptthattheactivecurrentwilldoubleinthedual-channelconfiguration. Copyright© 2010–2011,Texas InstrumentsIncorporated VideoDAC Specifications 153 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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• Bypass Mode – R LOAD = 1.5kΩ (±1%) – R SET = 10 kΩ (±1%) Table5-3.DAC —StaticElectricalSpecifications—Bypass Mode (2) PARAMETER CONDITIONS/ASSUMPTIONS MIN TYP MAX UNIT R Resolution 10 Bits DC ACCURACY INL(1) Integralnonlinearity(INL) 37 to954 inputcode range,R LOAD = 1.5kΩ –1 1 LSB DNL (1) Differentialnonlinearity 37 to954 inputcode range,R LOAD = 1.5kΩ –1 1 LSB ANALOG OUTPUT - Outputvoltage R LOAD = 1.5kΩ 0.6 0.7 0.77 V - Outputcurrent R LOAD = 1.5kΩ 0.6 0.7 0.77 V - Gain error - –10 10 % FS POWER CONSUMPTION Ivdda-up Analogsupplycurrent Averagecurrenton vdda_dac,R LOAD = 1.5kΩ 0.7 1.0 1.4 mA Inputcode 1023 Ivdda-down Analogsupplycurrent,total T = 30C º,vdda_dac = 1.8V,no load 12 μA power down Ivdda-stdby Analogsupplycurrent, Bandgap and internalLDO areON, allother 90 180 270 μA standbymode analogblocksareOFF, no load,T = 30C º (1) Inbypassmode, outputnode iscvideo1_outand cvideo2_outnodes.Formore information,see Section5.2,TVOUT Bypass Mode (DAC Only)orSection5.3,TVOUT Bypass Mode inDual-ChannelConfiguration. (2) Formore informationon code rangedefinition,see Figure5-4. Table5-4.Video DAC —Dynamic ElectricalSpecifications—Bypass Mode PARAMETER CONDITIONS/ASSUMPTIONS MIN TYP MAX UNIT fCLK Outputupdaterate Equaltoinputclockfrequency 54 60 MHz Clockjitter RMS clockjitterrequiredinorderto 40 70 ps assure10-bitaccuracy BW Signalbandwidth 3dB 6 MHz SFDR Withinbandwidth1 kHz to6 MHz fCLK = 54 MHz, fOUT = 1 MHz, sine 40 50 70 dB wave input,111 to895 inputcode range SNR Withinbandwidth1 kHz to6 MHz fCLK = 54 MHz, fOUT = 1 MHz, sine 50 54 75 dB wave input,256 to768 inputcode range PSR Power supplyrejection(upto6 MHz) 100 mVpp at6 MHz, inputcode 895 6(1) dB (1) Formore informationon code rangedefinition,see Figure5-4.

5.6 Analog Supply (vdda_dac)Noise Requirements

Inordertoassure10-bitaccuracyoftheDAC analogoutput,theanalogsupplyvdda_dac has tomeet the noiserequirementsstatedinthissection. The DAC Power SupplyRejectionRatio(PSRR) isdefinedas therelativevariationofthefull-scaleoutput currentdividedby thesupplyvariation.Thus,itisexpressedinpercentageofFull-ScaleRange (FSR) per volt of supply variation as shown in the following equation:

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Dependingon frequency,thePSRR isdefinedinTable5-5. Table5-5.Video DAC – Power Supply RejectionRatio Supply Noise PSRR % FSR/V Frequency 0 to100 kHz 1 > 100 kHz The rejectiondecreases20 dB/dec. Example:at1 MHz thePSRR is10% ofFSR/V. A graphicrepresentationisshown inFigure5-5. Figure5-5.Video DAC – Power Supply RejectionRatio To ensure thatthe DAC SFDR specificationismet, the PSRR valuesand the clockjitterrequirements translatetothefollowinglimitson vdda_dac (fortheVideoDAC). The maximum peak-to-peaknoiseon vdda (ripple)isdefinedinTable5-6. Table5-6.Video DAC – Maximum Peak-to-PeakNoise on vdda_dac Tone Frequency Maximum Peak-to-PeakNoise on vdda_dac 0 to100 kHz < 30 mV PP > 100 kHz Decreases20 dB/dec. Example:at1 MHz themaximum is3 mV PP The maximum noisespectraldensity(whitenoise)isdefinedinTable5-7. Table5-7.Video DAC – Maximum Noise SpectralDensity SupplyNoiseBandwidth Maximum SupplyNoiseDensity 0 to100 kHz < 20 µV /√Hz > 100 kHz Decreases20 dB/dec. Example:at1 MHz themaximum noisedensityis2 µV /√Hz Copyright© 2010–2011,Texas InstrumentsIncorporated VideoDAC Specifications 155 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Because theDAC PSRR deterioratesata rateof20 dB/dec after100 kHz, itishighlyrecommended to have vdda_dac low pass filtered(properdecoupling)(seetheillustratedapplication:Section5.7,External Component ValueChoice).

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5.7 ExternalComponent Value Choice

The outputcurrentIDACOUT appearingattheoutputofthe10-bitDAC isa functionofboththeinputcode DAC_CODE (rangingfrom0 to1023)and IDACMAX and can be expressedas: IDACOUT = IREF *(DAC_CODE /120)(1) The maximum outputcurrentIDACMAX fromtheDAC isgivenby: IDACMAX = IREF *1023 /120 (2) The referencecurrent,IREF ,issetby a combinationofinternaland externalresistorsinseries,R REF ,and an internalreferencevoltage,VREF ,and isgivenby: IREF = VREF /R REF (3) Typically,VREF = 0.55V and R REF = 9.4kΩ inTVOUT High-Swingmode. The videosignalvoltageat cvideo_out1and cvideo_out2nodes can be writtenas (excludingthe offset voltage): VTVOUT = 35 *R LOAD *IDACMAX *(1– DAC_CODE /1023)(4) Figure5-6 shows the cvideo_out1and cvideo_out2transferfunction.Regardingthe typicalcomposite video signallevelsversus the DAC inputcode, formore informationon code range definition,see Figure5-4. RegardingthetypicalvaluesofthetypicalvaluesforR out1/2and R set resistors,as wellforC out capacitor, for differentmodes of the TV displayinterface,see the DisplaySubsystem / DisplaySubsystem Environment/TV DisplaySupportsectionofAM/DM37x TechnicalReferenceManual (literaturenumber SPRUGN4 ). Figure5-6.cvideo_out1and cvideo_ou2 TransferFunction NOTE The dc levels(Voffset)willbe shifteddue toprocessvariations. Copyright© 2010–2011,Texas InstrumentsIncorporated VideoDAC Specifications 157 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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6 Timing Requirements and SwitchingCharacteristics

6.1 Timing TestConditions

Alltimingrequirementsand switchingcharacteristicsarevalidovertherecommended operatingconditions unlessotherwisespecified.

6.2 InterfaceClock Specifications

6.2.1 InterfaceClock Terminology

The interfaceclockisused atthesystemleveltosequence thedataand/ortocontroltransfersaccordingly withtheinterfaceprotocol.

6.2.2 InterfaceClock Frequency

The two interfaceclockcharacteristicsare:

• The maximum clockfrequency
• The maximum operatingfrequency The interfaceclockfrequencydocumented in thisdocument is the maximum clockfrequency,which correspondsto the maximum frequencyprogrammable on thisoutputclock.Thisfrequencydefinesthe maximum limitsupportedby thedeviceIC and doesn’ttakeintoaccountany system consideration(PCB, Peripherals). The system designerwillhave to considerthese system considerationsand the device IC timing characteristicsas well,to defineproperlythe maximum operatingfrequency,which correspondsto the maximum frequencysupportedtotransferthedataon thisinterface.

6.2.3 Clock JitterSpecifications

Jitterisa phase noise,whichmay alterdifferentcharacteristicsofa clocksignal.The jitterspecifiedinthis document isthetimedifferencebetween thetypicalcycleperiodand theactualcycleperiodaffectedby noisesourceson theclock.The cycle(orperiod)jitterterminologywillbe used toidentifythistypeofjitter. Figure6-1.Cycle (orPeriod)Jitter NOTE Max. CycleJitter= Max (Ti) Min.CycleJitter= Min (Ti) JitterStandardDeviation(orRMS Jitter)= StandardDeviation(Ti)

6.2.4 Clock Duty Cycle Error

The maximum dutycycleerroristhe differencebetween the absolutevalueof the maximum high-level pulsedurationorthemaximum low-levelpulsedurationand thetypicalpulsedurationvalue.

• Maximum pulseduration= Typicalpulseduration+ maximum dutycycleerror
• Minimum pulseduration= Typicalpulseduration-maximum dutycycleerror

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6.3 Timing Parameters

The timingparametersymbols used inthe timingrequirementsand switchingcharacteristicstablesare createdinaccordancewithJEDEC Standard100.To shortenthesymbols,some ofpinnames and other relatedterminologieshave been abbreviatedas follows: Table6-1.Timing Parameters SUBSCRIPTS SYMBOL PARAMETER c Cycletime(period) d Delaytime dis Disabletime en Enabletime h Holdtime su Setuptime START Startbit t Transitiontime v Validtime w Pulseduration(width) X Unknown, changing,ordon’tcarelevel F Falltime H High L Low R Risetime V Valid IV Invalid AE Activeedge FE Firstedge LE Lastedge Z Highimpedance Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 159 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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6.4 ExternalMemory Interfaces

The deviceincludesthefollowingexternalmemory interfaces:

• General-purposememory controller(GPMC)
• SDRAM controller(SDRC)

6.4.1 General-PurposeMemory Controller(GPMC)

For more information,see Memory Subsystem /General-PurposeMemory Controllersection of the AM/DM37x MultimediaDevice TechnicalReference Manual (literaturenumber SPRUGN4 ). The GPMC istheunifiedmemory controllerused tointerfaceexternalmemory devicessuch as:

• AsynchronousSRAM-likememories and ASIC devices
• Asynchronouspage mode and synchronousburstNOR flash
• NAND flash

6.4.1.1 GPMC/NOR Flash—Synchronous Mode

Table 6-3 and Table 6-4 assume testingover the recommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-2throughFigure6-6). Table6-2.GPMC/NOR FlashTiming Conditions—Synchronous Mode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 1.8 ns tF Inputsignalfalltime 1.8 ns Output Conditions C LOAD Outputloadcapacitance(1) 12 pF (1) The loadsettingoftheIO buffer:LB0 = 1. Table6-3.GPMC/NOR FlashTiming Requirements—Synchronous Mode (1) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX F12 tsu(dV-clkH) Setuptime,inputdatagpmc_d[15:0]validbefore 2.3 2.3 ns outputclockgpmc_clkhigh F13 th(clkH-dV) Holdtime,inputdatagpmc_d[15:0]validafteroutput 1.5 1.5 ns clockgpmc_clkhigh F21 tsu(waitV-clkH) Setuptime,inputwaitgpmc_waitx(2)validbefore 2.3 2.3 ns outputclockgpmc_clkhigh F22 th(clkH-waitV) Holdtime,inputwaitgpmc_waitx(2)validafteroutput 1.9 1.9 ns clockgpmc_clkhigh (1) See Section4.3.4,ProcessorClocks. (2) Ingpmc_waitx,x isequalto0,1,2,or3. Table6-4.GPMC/NOR FlashSwitchingCharacteristics—Synchronous Mode (2)(18) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX F0 1 /tc(clk) Frequency(15),outputclockgpmc_clk 100 100 MHz F1 tw(clkH) Typicalpulseduration,outputclockgpmc_clkhigh 0.5P(12) 0.5P(12) ns F1 tw(clkL) Typicalpulseduration,outputclockgpmc_clklow 0.5P(12) 0.5P(12) ns

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-4.GPMC/NOR FlashSwitchingCharacteristics—Synchronous Mode (2)(18) (continued) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX tdc(clk) Dutycycleerror,outputclockgpmc_clk –500 500 –500 500 ps tJ(clk) Jitterstandarddeviation(16),outputclockgpmc_clk 33.33 33.33 ps tR(clk) Risetime,outputclockgpmc_clk 1.6 1.6 ns tF(clk) Falltime,outputclockgpmc_clk 1.6 1.6 ns tR(do) Risetime,outputdatagpmc_d[15:0] 2 2 ns tF(do) Falltime,outputdatagpmc_d[15:0] 2 2 ns F2 td(clkH-ncsV) Delaytime,outputclockgpmc_clkrisingedge to F(6)– 1.9 F(6)+ 3.3 F(6)– 1.9 F(6)+ 3.3 ns outputchipselectgpmc_ncsx(11)transition F3 td(clkH-ncsIV) Delaytime,outputclockgpmc_clkrisingedge to E(5)– 1.9 E(5)+ 3.3 E(5)– 1.9 E(5)+ 3.3 ns outputchipselectgpmc_ncsx(11)invalid F4 td(aV-clk) Delaytime,outputaddressgpmc_a[27:1]validto B(2)– 4.1 B(2)+ 2.1 B(2)– 4.1 B(2)+ 2.1 ns outputclockgpmc_clkfirstedge F5 td(clkH-aIV) Delaytime,outputclockgpmc_clkrisingedge to –2.1 –2.1 ns outputaddressgpmc_a[27:1]invalid F6 td(nbeV-clk) Delaytime,outputlowerbyteenable/command latch B(2)– 1.2 B(2)+ 2.2 B(2)– 1.2 B(2)+ 2.2 ns enablegpmc_nbe0_cle,outputupperbyteenable gpmc_nbe1 validtooutputclockgpmc_clkfirstedge F7 td(clkH-nbeIV) Delaytime,outputclockgpmc_clkrisingedge to D (4)– 2.2 D (4)+ 1.2 D (4)– 2.2 D (4)+ 1.2 ns outputlowerbyteenable/command latchenable gpmc_nbe0_cle,outputupperbyteenablegpmc_nbe1 invalid F8 td(clkH-nadv) Delaytime,outputclockgpmc_clkrisingedge to G (7)+ 0.8 G (7)+ 2.2 G (7)+ 0.8 G (7)+ 2.2 ns outputaddressvalid/addresslatchenable gpmc_nadv_aletransition F9 td(clkH-nadvIV) Delaytime,outputclockgpmc_clkrisingedge to D (4)– 1.9 D (4)+ 4.1 D (4)– 1.9 D (4)+ 4.1 ns outputaddressvalid/addresslatchenable gpmc_nadv_aleinvalid F10 td(clkH-noe) Delaytime,outputclockgpmc_clkrisingedge to H (8)– 2.1 H (8)+ 2.1 H (8)– 2.1 H (8)+ 2.1 ns outputenablegpmc_noe transition F11 td(clkH-noeIV) Delaytime,outputclockgpmc_clkrisingedge to E(5)– 2.1 E(5)+ 2.1 E(5)– 2.1 E(5)+ 2.1 ns outputenablegpmc_noe invalid F14 td(clkH-nwe) Delaytime,outputclockgpmc_clkrisingedge to I(9)– 1.9 I(9)+ 4.1 I(9)– 1.9 I(9)+ 4.1 ns outputwriteenablegpmc_nwe transition F15 td(clkH-do) Delaytime,outputclockgpmc_clkrisingedge to J(10)– J(10)+ J(10)– J(10)+ ns outputdatagpmc_d[15:0]transition 1.7 1.2 1.7 1.2 F17 td(clkH-nbe) Delaytime,outputclockgpmc_clkrisingedge to J(10)– J(10)+ J(10)– J(10)+ ns outputlowerbyteenable/command latchenable 2.2 1.2 2.2 1.2 gpmc_nbe0_cletransition F18 tw(ncsV) Pulseduration,outputchipselect Read A(1) A(1) ns gpmc_ncsx(11)low Write A(1) A(1) ns F19 tw(nbeV) Pulseduration,outputlowerbyte Read C (3) C (3) ns enable/command latchenable Write C (3) C (3) nsgpmc_nbe0_cle,outputupperbyteenable gpmc_nbe1 low F20 tw(nadvV) Pulseduration,outputaddress Read K(13) K(13) ns valid/addresslatchenablegpmc_nadv_ale Write K(13) K(13) nslow F23 td(clkH-iodir) Delaytime,outputclockgpmc_clkrisingedge to H (8)– 2.1 H (8)+ 4.1 H (8)– 2.1 H (8)+ 4.1 ns outputIO directioncontrolgpmc_io_dirhigh(IN direction) F24 td(clkH-iodirIV) Delaytime,outputclockgpmc_clkrisingedge to M (17)– M (17)+ M (17)– M (17)+ ns outputIO directioncontrolgpmc_io_dirlow(OUT 2.1 4.1 2.1 4.1 direction) Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 161 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Forsingleread:A = (CSRdOffTime – CSOnTime) *(TimeParaGranularity+ 1)*GPMC_FCLK (14) Forburstread:A = (CSRdOffTime – CSOnTime + (n– 1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (14) Forburstwrite:A = (CSWrOffTime – CSOnTime + (n– 1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (14) Withn beingthepage burstaccessnumber. (2) B = ClkActivationTime*GPMC_FCLK (14) (3) Forsingleread:C = RdCycleTime *(TimeParaGranularity+ 1)*GPMC_FCLK (14) Forburstread:C = (RdCycleTime+ (n– 1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (14) Forburstwrite:C = (WrCycleTime+ (n– 1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (14) Withn beingthepage burstaccessnumber. (4) Forsingleread:D = (RdCycleTime– AccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (14) Forburstread:D = (RdCycleTime– AccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (14) Forburstwrite:D = (WrCycleTime– AccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (14) (5) Forsingleread:E = (CSRdOffTime – AccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (14) Forburstread:E = (CSRdOffTime – AccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (14) Forburstwrite:E = (CSWrOffTime – AccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (14) (6) FornCS fallingedge (CS activated): – Case GpmcFCLKDivider = 0: – F = 0.5*CSExtraDelay*GPMC_FCLK (14) – Case GpmcFCLKDivider = 1: – F = 0.5*CSExtraDelay*GPMC_FCLK (14)if(ClkActivationTimeand CSOnTime areodd)or(ClkActivationTimeand CSOnTime areeven) – F = (1+ 0.5*CSExtraDelay)*GPMC_FCLK (14)otherwise – Case GpmcFCLKDivider = 2: – F = 0.5*CSExtraDelay*GPMC_FCLK (14)if((CSOnTime – ClkActivationTime)isa multipleof3) – F = (1+ 0.5*CSExtraDelay)*GPMC_FCLK (14)if((CSOnTime – ClkActivationTime– 1)isa multipleof3) – F = (2+ 0.5*CSExtraDelay)*GPMC_FCLK (14)if((CSOnTime – ClkActivationTime– 2)isa multipleof3) (7) ForADV fallingedge (ADV activated): – Case GpmcFCLKDivider = 0: – G = 0.5*ADVExtraDelay*GPMC_FCLK (14) – Case GpmcFCLKDivider = 1: – G = 0.5*ADVExtraDelay*GPMC_FCLK (14)if(ClkActivationTimeand ADVOnTime areodd)or(ClkActivationTimeand ADVOnTime areeven) – G = (1+ 0.5*ADVExtraDelay)*GPMC_FCLK (14)otherwise – Case GpmcFCLKDivider = 2: – G = 0.5*ADVExtraDelay*GPMC_FCLK (14)if((ADVOnTime – ClkActivationTime)isa multipleof3) – G = (1+ 0.5*ADVExtraDelay)*GPMC_FCLK (14)if((ADVOnTime – ClkActivationTime– 1)isa multipleof3) – G = (2+ 0.5*ADVExtraDelay)*GPMC_FCLK (14)if((ADVOnTime – ClkActivationTime– 2)isa multipleof3) ForADV risingedge (ADV deactivated)inReadingmode: – Case GpmcFCLKDivider = 0: – G = 0.5*ADVExtraDelay*GPMC_FCLK (14) – Case GpmcFCLKDivider = 1: – G = 0.5*ADVExtraDelay*GPMC_FCLK (14)if(ClkActivationTimeand ADVRdOffTime areodd)or(ClkActivationTimeand ADVRdOffTime areeven) – G = (1+ 0.5*ADVExtraDelay)*GPMC_FCLK (14)otherwise – Case GpmcFCLKDivider = 2: – G = 0.5*ADVExtraDelay*GPMC_FCLK (14)if((ADVRdOffTime– ClkActivationTime)isa multipleof3) – G = (1+ 0.5*ADVExtraDelay)*GPMC_FCLK (14)if((ADVRdOffTime– ClkActivationTime– 1)isa multipleof3) – G = (2+ 0.5*ADVExtraDelay)*GPMC_FCLK (14)if((ADVRdOffTime– ClkActivationTime– 2)isa multipleof3) ForADV risingedge (ADV deactivated)inWritingmode: – Case GpmcFCLKDivider = 0: – G = 0.5*ADVExtraDelay*GPMC_FCLK (14) – Case GpmcFCLKDivider = 1: – G = 0.5*ADVExtraDelay*GPMC_FCLK (14)if(ClkActivationTimeand ADVWrOffTime areodd)or(ClkActivationTimeand ADVWrOffTime areeven) – G = (1+ 0.5*ADVExtraDelay)*GPMC_FCLK (14)otherwise – Case GpmcFCLKDivider = 2: – G = 0.5*ADVExtraDelay*GPMC_FCLK (14)if((ADVWrOffTime– ClkActivationTime)isa multipleof3) – G = (1+ 0.5*ADVExtraDelay)*GPMC_FCLK (14)if((ADVWrOffTime– ClkActivationTime– 1)isa multipleof3) – G = (2+ 0.5*ADVExtraDelay)*GPMC_FCLK (14)if((ADVWrOffTime– ClkActivationTime– 2)isa multipleof3) (8) ForOE fallingedge (OE activated)/IO DIR risingedge (DataBus inputdirection): – Case GpmcFCLKDivider = 0:o H = 0.5*OEExtraDelay*GPMC_FCLK (14) – Case GpmcFCLKDivider = 1: – H = 0.5*OEExtraDelay*GPMC_FCLK (14)if(ClkActivationTimeand OEOnTime areodd)or(ClkActivationTimeand OEOnTime areeven) – H = (1+ 0.5*OEExtraDelay)*GPMC_FCLK (14)otherwise – Case GpmcFCLKDivider = 2: – H = 0.5*OEExtraDelay*GPMC_FCLK (14)if((OEOnTime – ClkActivationTime)isa multipleof3)

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 – H = (1+ 0.5*OEExtraDelay)*GPMC_FCLK (14)if((OEOnTime – ClkActivationTime– 1)isa multipleof3) – H = (2+ 0.5*OEExtraDelay)*GPMC_FCLK (14)if((OEOnTime – ClkActivationTime– 2)isa multipleof3) ForOE risingedge (OE deactivated): – Case GpmcFCLKDivider = 0: – H = 0.5*OEExtraDelay*GPMC_FCLK (14) – Case GpmcFCLKDivider = 1: – H = 0.5*OEExtraDelay*GPMC_FCLK (14)if(ClkActivationTimeand OEOffTime areodd)or(ClkActivationTimeand OEOffTime areeven) – H = (1+ 0.5*OEExtraDelay)*GPMC_FCLK (14)otherwise – Case GpmcFCLKDivider = 2: – H = 0.5*OEExtraDelay*GPMC_FCLK (14)if((OEOffTime– ClkActivationTime)isa multipleof3) – H = (1+ 0.5*OEExtraDelay)*GPMC_FCLK (14)if((OEOffTime– ClkActivationTime– 1)isa multipleof3) – H = (2+ 0.5*OEExtraDelay)*GPMC_FCLK (14)if((OEOffTime– ClkActivationTime– 2)isa multipleof3) (9) ForWE fallingedge (WE activated): – Case GpmcFCLKDivider = 0: – I= 0.5*WEExtraDelay*GPMC_FCLK (14) – Case GpmcFCLKDivider = 1: – I= 0.5*WEExtraDelay*GPMC_FCLK (14)if(ClkActivationTimeand WEOnTime areodd)or(ClkActivationTimeand WEOnTime areeven) – I= (1+ 0.5*WEExtraDelay)*GPMC_FCLK (14)otherwise – Case GpmcFCLKDivider = 2: – I= 0.5*WEExtraDelay*GPMC_FCLK (14)if((WEOnTime – ClkActivationTime)isa multipleof3) – I= (1+ 0.5*WEExtraDelay)*GPMC_FCLK (14)if((WEOnTime – ClkActivationTime– 1)isa multipleof3) – I= (2+ 0.5*WEExtraDelay)*GPMC_FCLK (14)if((WEOnTime – ClkActivationTime– 2)isa multipleof3) ForWE risingedge (WE deactivated): – Case GpmcFCLKDivider = 0: – I= 0.5*WEExtraDelay*GPMC_FCLK (14) – Case GpmcFCLKDivider = 1: – I= 0.5*WEExtraDelay*GPMC_FCLK (14)if(ClkActivationTimeand WEOffTime areodd)or(ClkActivationTimeand WEOffTime areeven) – I= (1+ 0.5*WEExtraDelay)*GPMC_FCLK (14)otherwise – Case GpmcFCLKDivider = 2: – I= 0.5*WEExtraDelay*GPMC_FCLK (14)if((WEOffTime– ClkActivationTime)isa multipleof3) – I= (1+ 0.5*WEExtraDelay)*GPMC_FCLK (14)if((WEOffTime– ClkActivationTime– 1)isa multipleof3) – I= (2+ 0.5*WEExtraDelay)*GPMC_FCLK (14)if((WEOffTime– ClkActivationTime– 2)isa multipleof3) (10)J = GPMC_FCLK (14) (11)Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. (12)P = gpmc_clkperiodinns (13)Forread:K = (ADVRdOffTime – ADVOnTime) *(TimeParaGranularity+ 1)*GPMC_FCLK (14) Forwrite:K = (ADVWrOffTime – ADVOnTime) *(TimeParaGranularity+ 1)*GPMC_FCLK (14) (14)GPMC_FCLK isgeneral-purposememory controllerinternalfunctionalclockperiodinns. (15)Relatedtothegpmc_clkoutputclockmaximum and minimum frequenciesprogrammableintheGPMC module by settingthe GPMC_CONFIG1_CSx configurationregisterbitfieldGpmcFCLKDivider. (16)The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (17)M = (RdCycleTime– AccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (14) Above M parameterexpressionisgivenas one example ofGPMC programming.IO DIR signalwillgo fromIN toOUT afterboth RdCycleTime and BusTurnAroundcompletion.BehaviorofIO directionsignaldoes depend on kindofsuccessiveRead/Writeaccesses performedtoMemory and multiplexedornonmultiplexedmemory addressingscheme, bus keepingfeatureenabledornot.IO DIR behaviourisautomaticallyhandledby GPMC controller.Fora fulldescriptionofthegpmc_io_dirfeature,see theAM/DM37x Multimedia DeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (18)See Section4.3.4,ProcessorClocks. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 163 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir Valid Address D 0 OUT IN OUT F12 F13 F11 F19 F18 F20 F10 F19 F23 F24 SWPS038-014 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7. (2) Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-2.GPMC/NOR Flash—Synchronous SingleRead —(GpmcFCLKDivider = 0)

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gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir Valid Address D 0 D 1 D 2 OUTOUT IN OUT F12 F13 F13 F12 F8 F8 F9 F10 F11 F21 F22 F23 F24 SWPS038-015 D 3 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7. (2) Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-3.GPMC/NOR Flash—Synchronous BurstRead —4x16-bit(GpmcFCLKDivider = 0) Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 165 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_d[15:0] gpmc_waitx gpmc_io_dir D 0 D 1 D 2 D 3 OUT F15 F15 F15 F8F8 F14F14 F17 F17 F17 F9F6 F17 F17 F17 Valid Address DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7. (2) Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-4.GPMC/NOR Flash—Synchronous BurstWrite—(GpmcFCLKDivider > 0)

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gpmc_clk gpmc_ncsx gpmc_nbe0_cle gpmc_nbe1 gpmc_a[27:17] (gpmc_a[11:1]) gpmc_a[16:1] (gpmc_d[15:0]) gpmc_nadv_ale gpmc_noe gpmc_waitx gpmc_io_dir Valid Valid Address (MSB) Address (LSB) D0 D1 D2 D3 OUTOUT IN OUT F8 F8 F10 F13 F12 F12 F11 F0 F1 F6 F7 F23 F24 SWPS038-017 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7. (2) Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-5.GPMC/Multiplexed NOR Flash—Synchronous BurstRead Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 167 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

gpmc_clk gpmc_ncsx gpmc_a[27:17] (gpmc_a[11:1]) gpmc_nbe1 gpmc_nbe0_cle gpmc_nadv_ale gpmc_nwe gpmc_waitx gpmc_io_dir Address (LSB) D 0 D 1 D 2 D 3 OUT F15 F15 F15 F8F8 F17 F17 F17 F6 F17 F17 F17 F18 F20 F14 F22 F21 SWPS038-018 Address (MSB) gpmc_a[16:1] (gpmc_d[15:0]) F14 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7. (2) Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-6.GPMC/Multiplexed NOR Flash—Synchronous BurstWrite

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011

6.4.1.2 GPMC/NOR Flash—Asynchronous Mode

Table 6-6 and Table 6-7 assume testingover the recommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-7throughFigure6-12). Table6-5.GPMC/NOR FlashTiming Conditions—Asynchronous Mode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 1.8 ns tF Inputsignalfalltime 1.8 ns Output Conditions C LOAD Outputloadcapacitance(1) 16 pF (1) The loadsettingoftheIO buffer:LB0 = 0. Table6-6.GPMC/NOR FlashInternalTiming Parameters—Asynchronous Mode (1)(2)(4) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX FI1 Delaytime,outputdatagpmc_d[15:0]generationfrominternal 6.6 7.0 ns functionalclockGPMC_FCLK (3) FI2 Delaytime,inputdatagpmc_d[15:0]capturefrominternalfunctional 4.4 7.0 ns clockGPMC_FCLK (3) FI3 Delaytime,outputchipselectgpmc_ncsx generationfrominternal 6.5 7.0 ns functionalclockGPMC_FCLK (3) FI4 Delaytime,outputaddressgpmc_a[27:1]generationfrominternal 7.6 7.0 ns functionalclockGPMC_FCLK (3) FI5 Delaytime,outputaddressgpmc_a[27:1]validfrominternalfunctional 7.6 7.0 ns clockGPMC_FCLK (3) FI6 Delaytime,outputlower-byteenable/command latchenable 6.5 7.0 ns gpmc_nbe0_cle,outputupper-byteenablegpmc_nbe1 generation frominternalfunctionalclockGPMC_FCLK (3) FI7 Delaytime,outputenablegpmc_noe generationfrominternal 5.8 7.0 ns functionalclockGPMC_FCLK (3) FI8 Delaytime,outputwriteenablegpmc_nwe generationfrominternal 7.0 7.0 ns functionalclockGPMC_FCLK (3) FI9 Skew, internalfunctionalclockGPMC_FCLK (3) 100 170 ps FI10 Delaytime,IO directiongenerationfrominternalfunctionalclock 6.3 7.0 ps GPMC_FCLK (3) (1) The internalparameterstablemust be used tocalculatedataaccesstimestoredinthecorrespondingCS registerbitfield. (2) InternalparametersarereferredtotheGPMC functionalinternalclockwhichisnotprovidedexternally. (3) GPMC_FCLK isgeneral-purposememory controllerinternalfunctionalclock. (4) See Section4.3.4,ProcessorClocks. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 169 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-7.GPMC/NOR FlashTiming Requirements—Asynchronous Mode (7) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX FA5 (1) tacc(d) Data accesstime H (5) H (5) ns FA20 (3) tacc1-pgmode(d) Page mode successivedataaccesstime P(4) P(4) ns FA21 (2) tacc2-pgmode(d) Page mode firstdataaccesstime H (5) H (5) ns (1) The FA5 parameterillustratestheamount oftimerequiredtointernallysample inputdata.Itisexpressedinnumber ofGPMC functional clockcycles.From startofreadcycleand afterFA5 functionalclockcycles,inputdataisinternallysampled by activefunctionalclock edge.FA5 valuemust be storedinsidetheAccessTime registerbitfield. (2) The FA21 parameterillustratesamount oftimerequiredtointernallysample firstinputpage data.Itisexpressedinnumber ofGPMC functionalclockcycles.From startofreadcycleand afterFA21 functionalclockcycles,firstinputpage dataisinternallysampled by activefunctionalclockedge.FA21 valuemust be storedinsidetheAccessTime registerbitfield. (3) The FA20 parameterillustratesamount oftimerequiredtointernallysample successiveinputpage data.Itisexpressedinnumber of GPMC functionalclockcycles.Aftereach accesstoinputpage data,nextinputpage dataisinternallysampled by activefunctionalclock edge afterFA20 functionalclockcycles.The FA20 valuemust be storedinthePageBurstAccessTimeregisterbitfield. (4) P = PageBurstAccessTime*(TimeParaGranularity+ 1)*GPMC_FCLK (6) (5) H = AccessTime *(TimeParaGranularity+ 1)*GPMC_FCLK (6) (6) GPMC_FCLK isgeneral-purposememory controllerinternalfunctionalclockperiodinns. (7) See Section4.3.4,ProcessorClocks. Table6-8.GPMC/NOR FlashSwitchingCharacteristics—Asynchronous Mode (16) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX tR(d) Risetime,outputdatagpmc_d[15:0] 2 2 ns tF(d) Falltime,outputdatagpmc_d[15:0] 2 2 ns FA0 tw(nbeV) Pulseduration,outputlower-byte Read N (12) N (12) ns enable/command latchenable Write N (12) N (12) gpmc_nbe0_cle,output upper-byteenablegpmc_nbe1 validtime FA1 tw(ncsV) Pulseduration,outputchipselect Read A(1) A(1) ns gpmc_ncsx(13)low Write A(1) A(1) FA3 td(ncsV-nadvIV) Delaytime,outputchipselect Read B(2)– 0.2 B(2)+ 2.0 B(2)– 0.2 B(2)+ 2.6 ns gpmc_ncsx(13)validtooutput Write B(2)– 0.2 B(2)+ 2.0 B(2)– 0.2 B(2)+ 2.6addressvalid/addresslatch enablegpmc_nadv_aleinvalid FA4 td(ncsV-noeIV) Delaytime,outputchipselectgpmc_ncsx(13) C (3)– 0.2 C (3)+ 2.0 C (3)– 0.2 C (3)+ 2.6 ns validtooutputenablegpmc_noe invalid (Singleread) FA9 td(aV-ncsV) Delaytime,outputaddressgpmc_a[27:1]valid J(9)– 0.2 J(9)+ 2.0 J(9)– 0.2 J(9)+ 2.6 ns tooutputchipselectgpmc_ncsx(13)valid FA10 td(nbeV-ncsV) Delaytime,outputlower-byte J(9)– 0.2 J(9)+ 2.0 J(9)– 0.2 J(9)+ 2.6 ns enable/command latchenable gpmc_nbe0_cle,outputupper-byteenable gpmc_nbe1 validtooutputchipselect gpmc_ncsx(13)valid FA12 td(ncsV-nadvV) Delaytime,outputchipselectgpmc_ncsx(13) K(10)– 0.2 K(10)+ 2.0 K(10)– 0.2 K(10)+ 2.6 ns validtooutputaddressvalid/addresslatch enablegpmc_nadv_alevalid FA13 td(ncsV-noeV) Delaytime,outputchipselectgpmc_ncsx(13) L(11)– 0.2 L(11)+ 2.0 L (11)– 0.2 L(11)+ 2.6 ns validtooutputenablegpmc_noe valid FA14 td(ncsV-iodir) Delaytime,outputchipselectgpmc_ncsx(13) L(11)– 0.2 L(11)+ 2.0 L(11)– 0.2 L(11)+ 2.6 ns validtooutputIO directioncontrolgpmc_io_dir high FA15 td(ncsV-iodir) Delaytime,outputchipselectgpmc_ncsx(13) M (14)– 0.2 M (14)+ 2.0 M (14)– 0.2 M (14)+ 2.6 ns validtooutputIO directioncontrolgpmc_io_dir low

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-8.GPMC/NOR FlashSwitchingCharacteristics—Asynchronous Mode (16) (continued) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX FA16 tw(aIV) Pulsedurationmoutputaddressgpmc_a[26:1] G (7) G (7) ns invalidbetween 2 successiveR/W accesses FA18 td(ncsV-noeIV) Delaytime,outputchipselectgpmc_ncsx(13) I(8)– 0.2 I(8)+ 2.0 I(8)– 0.2 I(8)+ 2.6 ns validtooutputenablegpmc_noe invalid(Burst read) FA20 tw(aV) Pulseduration,outputaddressgpmc_a[27:1] D (4) D (4) ns valid– 2nd,3rd,and 4thaccesses FA25 td(ncsV-nweV) Delaytime,outputchipselectgpmc_ncsx(13) E(5)– 0.2 E(5)+ 2.0 E(5)– 0.2 E(5)+ 2.6 ns validtooutputwriteenablegpmc_nwe valid FA27 td(ncsV-nweIV) Delaytime,outputchipselectgpmc_ncsx(13) F(6)– 0.2 F(6)+ 2.0 F(6)– 0.2 F(6)+ 2.6 ns validtooutputwriteenablegpmc_nwe invalid FA28 td(nweV-dV) Delaytime,outputwriteenablegpmc_ nwe 2.0 2.6 ns validtooutputdatagpmc_d[15:0]valid FA29 td(dV-ncsV) Delaytime,outputdatagpmc_d[15:0]validto J(9)– 0.2 J(9)+ 2.0 J(9)– 0.2 J(9)+ 2.6 ns outputchipselectgpmc_ncsx(13)valid FA37 td(noeV-aIV) Delaytime,outputenablegpmc_noe validto 2.0 2.6 ns outputaddressgpmc_a[16:1]_d[15:0]phase end (1) Forsingleread:A = (CSRdOffTime – CSOnTime) *(TimeParaGranularity+ 1)*GPMC_FCLK (15) Forsinglewrite:A = (CSWrOffTime – CSOnTime) *(TimeParaGranularity+ 1)*GPMC_FCLK (15) Forburstread:A = (CSRdOffTime – CSOnTime + (n– 1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (15) Forburstwrite:A = (CSWrOffTime – CSOnTime + (n– 1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (15) withn beingthepage burstaccessnumber (2) Forreading:B = ((ADVRdOffTime– CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(ADVExtraDelay– CSExtraDelay))* GPMC_FCLK (15) Forwriting:B = ((ADVWrOffTime– CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(ADVExtraDelay– CSExtraDelay))* GPMC_FCLK (15) (3) C = ((OEOffTime– CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(OEExtraDelay– CSExtraDelay))*GPMC_FCLK (15) (4) D = PageBurstAccessTime*(TimeParaGranularity+ 1)*GPMC_FCLK (15) (5) E = ((WEOnTime – CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(WEExtraDelay– CSExtraDelay))*GPMC_FCLK (15) (6) F = ((WEOffTime– CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(WEExtraDelay– CSExtraDelay))*GPMC_FCLK (15) (7) G = Cycle2CycleDelay*GPMC_FCLK (15) (8) I= ((OEOffTime+ (n– 1)*PageBurstAccessTime– CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(OEExtraDelay– CSExtraDelay))* GPMC_FCLK (15) (9) J = (CSOnTime *(TimeParaGranularity+ 1)+ 0.5*CSExtraDelay)*GPMC_FCLK (15) (10)K = ((ADVOnTime – CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(ADVExtraDelay– CSExtraDelay))*GPMC_FCLK (15) (11)L = ((OEOnTime – CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(OEExtraDelay– CSExtraDelay))*GPMC_FCLK (15) (12)Forsingleread:N = RdCycleTime *(TimeParaGranularity+ 1)*GPMC_FCLK (15) Forsinglewrite:N = WrCycleTime *(TimeParaGranularity+ 1)*GPMC_FCLK (15) Forburstread:N = (RdCycleTime+ (n– 1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (15) Forburstwrite:N = (WrCycleTime+ (n– 1)*PageBurstAccessTime)*(TimeParaGranularity+ 1)*GPMC_FCLK (15) (13)Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7. (14)M = ((RdCycleTime– CSOnTime) *(TimeParaGranularity+ 1)– 0.5*CSExtraDelay)*GPMC_FCLK (15) Above M parameterexpressionisgivenas one example ofGPMC programming.IO DIR signalwillgo fromIN toOUT afterboth RdCycleTime and BusTurnAroundcompletion.BehaviorofIO directionsignaldoes depend on kindofsuccessiveRead/Writeaccesses performedtoMemory and multiplexedornonmultiplexedmemory addressingscheme, bus keepingfeatureenabledornot.IO DIR behaviourisautomaticallyhandledby GPMC controller.Fora fulldescriptionofthegpmc_io_dirfeature,see theAM/DM37x Multimedia DeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (15)GPMC_FCLK isgeneral-purposememory controllerinternalfunctionalclockperiodinns. (16)See Section4.3.4,ProcessorClocks. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 171 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

GPMC_FCLK gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir Valid Address Valid Valid Data IN 0 Data IN 0 OUT IN OUT FA0 FA9 FA10 FA3 FA1 FA4 FA12 FA13 FA0 FA10 FA5 FA14 FA15 SWPS038-019 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. (2) FA5 parameterillustratesamount oftimerequiredtointernallysample inputdata.Itisexpressedinnumber ofGPMC functionalclock cycles.From startofreadcycleand afterFA5 functionalclockcycles,inputdatawillbe internallysampled by activefunctionalclock edge.FA5 valuemust be storedinsideAccessTime registerbitsfield. (3) GPMC_FCLK isan internalclock(GPMC functionalclock)notprovidedexternally. Figure6-7.GPMC /NOR Flash—Asynchronous Read —SingleWord

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GPMC_FCLK gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir Address 0 Address 1 Valid Valid Valid Valid Data Upper OUT IN OUT IN FA9 FA10 FA3 FA9 FA3 FA13 FA13 FA1 FA1 FA4 FA4 FA12 FA12 FA10 FA0 FA0 FA16 FA0 FA0 FA10 FA10 FA5 FA5 FA14 FA15 FA14 FA15 SWPS038-020 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. (2) FA5 parameterillustratesamount oftimerequiredtointernallysample inputdata.Itisexpressedinnumber ofGPMC functionalclock cycles.From startofreadcycleand afterFA5 functionalclockcycles,inputdatawillbe internallysampled by activefunctionalclock edge.FA5 valuemust be storedinsideAccessTime registerbitsfield. (3) GPMC_FCLK isan internalclock(GPMC functionalclock)notprovidedexternally. Figure6-8.GPMC /NOR Flash—Asynchronous Read —32-bit Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 173 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

GPMC_FCLK gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_d[15:0] gpmc_waitx gpmc_io_dir Add0 Add1 Add2 Add3 Add4 D0 D1 D2 D3 D3 OUT IN OUT FA1 FA0 FA18 FA13 FA12 FA0 FA9 FA10 FA10 FA21 FA14 FA15 SWPS038-021 FA20 FA20FA20 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. (2) FA21 parameterillustratesamount oftimerequiredtointernallysample firstinputpage data.Itisexpressedinnumber ofGPMC functionalclockcycles.From startofreadcycleand afterFA21 functionalclockcycles,firstinputpage datawillbe internallysampled by activefunctionalclockedge.FA21 calculationmust be storedinsideAccessTime registerbitsfield. (3) FA20 parameterillustratesamount oftimerequiredtointernallysample successiveinputpage data.Itisexpressedinnumber of GPMC functionalclockcycles.Aftereach access to inputpage data,next inputpage data willbe internallysampled by active functionalclockedge afterFA20 functionalclockcycles.FA20 isalsothedurationofaddressphases forsuccessiveinputpage data (excludingfirstinputpage data).FA20 valuemust be storedinPageBurstAccessTimeregisterbitsfield. (4) GPMC_FCLK isan internalclock(GPMC functionalclock)notprovidedexternally. Figure6-9.GPMC /NOR Flash—Asynchronous Read —Page Mode 4x16-bit

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gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[10:1] gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_d[15:0] gpmc_waitx gpmc_io_dir Valid Address Data OUT OUT FA0 FA1 FA10 FA3 FA25 FA29 FA9 FA12 FA27 FA0 FA10 SWPS038-022 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-10.GPMC /NOR Flash—Asynchronous Write—SingleWord Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 175 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

GPMC_FCLK gpmc_clk gpmc_ncsx gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_noe gpmc_io_dir gpmc_waitx Address (MSB) Valid Valid Address (LSB) Data IN Data IN OUT IN OUT FA0 FA9 FA10 FA3 FA13 FA29 FA1 FA37 FA12 FA4 FA10 FA0 FA5 FA14 FA15 SWPS038-023 gpmc_a[27:17] (gpmc_a[11:1]) gpmc_a[16:1] (gpmc_d[15:0]) DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. (2) FA5 parameterillustratesamount oftimerequiredtointernallysample inputdata.Itisexpressedinnumber ofGPMC functionalclock cycles.From startofreadcycleand afterFA5 functionalclockcycles,inputdatawillbe internallysampled by activefunctionalclock edge.FA5 valuemust be storedinsideAccessTime registerbitsfield. (3) GPMC_FCLK isan internalclock(GPMC functionalclock)notprovidedexternally. Figure6-11.GPMC /MultiplexedNOR Flash—Asynchronous Read —SingleWord

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gpmc_fclk gpmc_clk gpmc_ncsx gpmc_a[27:17] (gpmc_a[11:1]) gpmc_nbe0_cle gpmc_nbe1 gpmc_nadv_ale gpmc_nwe gpmc_a[16:1] (gpmc_d[15:0]) gpmc_waitx gpmc_io_dir Address (MSB) Valid Address (LSB) Data OUT OUT FA0 FA1 FA9 FA10 FA3 FA25 FA29 FA12 FA27 FA28 FA0 FA10 SWPS038-024 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-12.GPMC /MultiplexedNOR Flash—Asynchronous Write—SingleWord Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 177 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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6.4.1.3 GPMC/NAND Flash—Asynchronous Mode

Table 6-10 and Table 6-11 assume testingover the recommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-13throughFigure6-16). Table6-9.GPMC/NAND FlashTiming Conditions—Asynchronous Mode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 1.8 ns tF Inputsignalfalltime 1.8 ns Output Conditions C LOAD Outputloadcapacitance(1) 16 pF (1) The loadsettingoftheIO buffer:LB0 = 0. Table6-10.GPMC/NAND FlashInternalTiming Parameters—Asynchronous Mode (1)(2)(4) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX GNFI1 Delaytime,outputdatagpmc_d[15:0]generationfrominternal 6.5 9.1 ns functionalclockGPMC_FCLK (3) GNFI2 Delaytime,inputdatagpmc_d[15:0]capturefrominternal 4.0 5.6 ns functionalclockGPMC_FCLK (3) GNFI3 Delaytime,outputchipselectgpmc_ncsx generationfrom 6.5 9.1 ns internalfunctionalclockGPMC_FCLK (3) GNFI4 Delaytime,outputaddressvalid/addresslatchenable 6.5 9.1 ns gpmc_nadv_alegenerationfrominternalfunctionalclock GPMC_FCLK (3) GNFI5 Delaytime,outputlower-byteenable/command latchenable 6.5 9.1 ns gpmc_nbe0_clegenerationfrominternalfunctionalclock GPMC_FCLK (3) GNFI6 Delaytime,outputenablegpmc_noe generationfrominternal 6.5 9.1 ns functionalclockGPMC_FCLK (3) GNFI7 Delaytime,outputwriteenablegpmc_nwe generationfrom 6.5 9.1 ns internalfunctionalclockGPMC_FCLK (3) GNFI8 Skew, functionalclockGPMC_FCLK (3) 100 170 ps (1) Internalparameterstablemust be used tocalculatedataaccesstimestoredinthecorrespondingCS registerbitfield. (2) InternalparametersarereferredtotheGPMC functionalinternalclockwhichisnotprovidedexternally. (3) GPMC_FCLK isgeneral-purposememory controllerinternalfunctionalclock. (4) See Section4.3.4,ProcessorClocks. Table6-11.GPMC/NAND FlashTiming Requirements—Asynchronous Mode (4) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX GNF12 (1) tacc(d) Access time,inputdatagpmc_d[15:0] J(2) J(2) ns (1) The GNF12 parameterillustratestheamount oftimerequiredtointernallysample inputdata.Itisexpressedinnumber ofGPMC functionalclockcycles.From startofthereadcycleand afterGNF12 functionalclockcycles,inputdataisinternallysampled by the activefunctionalclockedge.The GNF12 valuemust be storedinsideAccessTime registerbitfield. (2) J = AccessTime *(TimeParaGranularity+ 1)*GPMC_FCLK (3) (3) GPMC_FCLK isgeneral-purposememory controllerinternalfunctionalclockperiodinns. (4) See Section4.3.4,ProcessorClocks.

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-12.GPMC/NAND FlashSwitchingCharacteristics—Asynchronous Mode (15) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX tR(d) Risetime,outputdatagpmc_d[15:0] 2 2 ns tF(d) Falltime,outputdatagpmc_d[15:0] 2 2 ns GNF0 tw(nweV) Pulseduration,outputwriteenablegpmc_nwe A(1) A(1) ns valid GNF1 td(ncsV-nweV) Delaytime,outputchipselectgpmc_ncsx(13) B(2)– 0.2 B(2)+ 2.0 B(2)– 0.2 B(2)+ 2.6 ns validtooutputwriteenablegpmc_nwe valid GNF2 tw(cleH-nweV) Delaytime,outputlower-byte C (3)– 0.2 C (3)+ 2.0 C (3)– 0.2 C (3)+ 2.6 ns enable/command latchenablegpmc_nbe0_cle hightooutputwriteenablegpmc_nwe valid GNF3 tw(nweV-dV) Delaytime,outputdatagpmc_d[15:0]validto D (4)– 0.2 D (4)+ 2.0 D (4)– 0.2 D (4)+ 2.6 ns outputwriteenablegpmc_nwe valid GNF4 tw(nweIV-dIV) Delaytime,outputwriteenablegpmc_nwe E(5)– 0.2 E(5)+ 2.0 E(5)– 0.2 E(5)+ 2.6 ns invalidtooutputdatagpmc_d[15:0]invalid GNF5 tw(nweIV-cleIV) Delaytime,outputwriteenablegpmc_nwe F(6)– 0.2 F(6)+ 2.0 F(6)– 0.2 F(6)+ 2.6 ns invalidtooutputlower-byteenable/command latchenablegpmc_nbe0_cleinvalid GNF6 tw(nweIV-ncsIV) Delaytime,outputwriteenablegpmc_nwe G (7)– 0.2 G (7)+ 2.0 G (7)– 0.2 G (7)+ 2.6 ns invalidtooutputchipselectgpmc_ncsx(13) invalid GNF7 tw(aleH-nweV) Delaytime,outputaddressvalid/addresslatch C (3)– 0.2 C (3)+ 2.0 C (3)– 0.2 C (3)+ 2.6 ns enablegpmc_nadv_alehightooutputwrite enablegpmc_nwe valid GNF8 tw(nweIV-aleIV) Delaytime,outputwriteenablegpmc_nwe F(6)– 0.2 F(6)+ 2.0 F(6)– 0.2 F(6)+ 2.6 ns invalidtooutputaddressvalid/addresslatch enablegpmc_nadv_aleinvalid GNF9 tc(nwe) Cycletime,write H (8) H (8) ns GNF10 td(ncsV-noeV) Delaytime,outputchipselectgpmc_ncsx(13) I(9)– 0.2 I(9)+ 2.0 I(9)– 0.2 I(9)+ 2.6 ns validtooutputenablegpmc_noe valid GNF13 tw(noeV) Pulseduration,outputenablegpmc_noe valid K(10) K(10) ns GNF14 tc(noe) Cycletime,read L(11) L(11) ns GNF15 tw(noeIV-ncsIV) Delaytime,outputenablegpmc_noe invalidto M (12)– 0.2 M (12)+ 2.0 M (12)– 0.2 M (12)+ 2.6 ns outputchipselectgpmc_ncsx(13)invalid (1) A = (WEOffTime – WEOnTime) *(TimeParaGranularity+ 1)*GPMC_FCLK (14) (2) B = ((WEOnTime – CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(WEExtraDelay– CSExtraDelay))*GPMC_FCLK (14) (3) C = ((WEOnTime – ADVOnTime) *(TimeParaGranularity+ 1)+ 0.5*(WEExtraDelay– ADVExtraDelay))*GPMC_FCLK (14) (4) D = (WEOnTime *(TimeParaGranularity+ 1)+ 0.5*WEExtraDelay)*GPMC_FCLK (14) (5) E = ((WrCycleTime– WEOffTime) *(TimeParaGranularity+ 1)– 0.5*WEExtraDelay)*GPMC_FCLK (14) (6) F = ((ADVWrOffTime– WEOffTime) *(TimeParaGranularity+ 1)+ 0.5*(ADVExtraDelay– WEExtraDelay))*GPMC_FCLK (14) (7) G = ((CSWrOffTime– WEOffTime) *(TimeParaGranularity+ 1)+ 0.5*(CSExtraDelay– WEExtraDelay))*GPMC_FCLK (14) (8) H = WrCycleTime *(1+ TimeParaGranularity)*GPMC_FCLK (14) (9) I= ((OEOnTime – CSOnTime) *(TimeParaGranularity+ 1)+ 0.5*(OEExtraDelay– CSExtraDelay))*GPMC_FCLK (14) (10)K = (OEOffTime– OEOnTime) *(1+ TimeParaGranularity)*GPMC_FCLK (14) (11)L = RdCycleTime *(1+ TimeParaGranularity)*GPMC_FCLK (14) (12)M = ((CSRdOffTime– OEOffTime)*(TimeParaGranularity+ 1)+ 0.5*(CSExtraDelay– OEExtraDelay))*GPMC_FCLK (14) (13)Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7. (14)GPMC_FCLK isgeneral-purposememory controllerinternalfunctionalclockperiodinns. (15)See Section4.3.4,ProcessorClocks. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 179 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

GPMC_FCLK gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_a[16:1] (gpmc_d[15:0]) Command GNF0 GNF1 GNF2 GNF3 GNF4 GNF5 GNF6 SWPS038-025 GPMC_FCLK gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_nwe gpmc_a[16:1] (gpmc_d[15:0]) Address GNF0 GNF1 GNF7 GNF3 GNF4 GNF6 GNF8 GNF9 SWPS038-026 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7. Figure6-13.GPMC /NAND Flash—Command Latch Cycle (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7. Figure6-14.GPMC /NAND Flash—Address Latch Cycle

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GPMC_FCLK gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_waitx DA T A GNF10 GNF14 GNF15 GNF12 SWPS038-027 GNF13 gpmc_a[16:1] (gpmc_d[15:0]) GPMC_FCLK gpmc_ncsx gpmc_nbe0_cle gpmc_nadv_ale gpmc_noe gpmc_nwe DA T A GNF0 GNF1 GNF4 GNF9 GNF3 GNF6 SWPS038-028 gpmc_a[16:1] (gpmc_d[15:0]) DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) GNF12 parameterillustratesamount oftimerequiredtointernallysample inputdata.Itisexpressedinnumber ofGPMC functional clockcycles.From startof read cycleand afterGNF12 functionalclockcycles,inputdata willbe internallysampled by active functionalclockedge.GNF12 valuemust be storedinsideAccessTime registerbitsfield. (2) GPMC_FCLK isan internalclock(GPMC functionalclock)notprovidedexternally. (3) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7.Ingpmc_waitx,x isequalto0,1,2,or3. Figure6-15.GPMC /NAND Flash—Data Read Cycle (1) Ingpmc_ncsx,x isequalto0,1,2,3,4,5,6,or7. Figure6-16.GPMC /NAND Flash—Data WriteCycle Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 181 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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6.4.2 SDRAM Memory Controller(SDRC)

For more information,see Memory Subsystem / SDRAM Controller(SDRC) Subsystem sectionoftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). The SDRAM controllersubsystem module providesconnectivitybetween the processorand external DRAM memory components.The module includessupportfordouble-data-rateSDRAM (mobileDDR).

6.4.2.1 LPDDR Interface

The LPDDR interfaceisballedouton thebottomsideoftheCUS package and on thetopsideofthePOP packages.The LPDDR interfaceon thetopofthePOP package has been designedforcompatibilityany POP LPDDR devicewitha matchingfootprintand compliancewiththeJEDEC LPDDR-266 specification. Thissectionprovidesthetimingspecificationforthebottom-sideLPDDR interfaceas a PCB designand manufacturingspecification.The design rulesconstrainPCB tracelength,PCB traceskew, signal integrity,cross-talk,and signaltiming.These rules,when followed,resultina reliableLPDDR memory system withouttheneed fora complex timingclosureprocess.For more informationregardingguidelines forusingthisLPDDR specification,see the UnderstandingTI'sPCB RoutingRule-BasedDDR Timing SpecificationApplicationReport(literaturenumber SPRAAV0 ). 6.4.2.1.1LPDDR InterfaceSchematic Figure6-17and Figure6-18show theLPDDR interfaceschematicsfora LPDDR memory system.The 1 x16 LPDDR system schematicisidenticalto Figure6-17 exceptthatthe highword LPDDR deviceis deleted.

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sdrc_d0 sdrc_d7 sdrc_dm0 sdrc_dqs0 sdrc_d8 sdrc_d15 sdrc_dm1 sdrc_dqs1 sdrc_d16 sdrc_d23 sdrc_dm2 sdrc_dqs2 sdrc_d24 sdrc_d31 sdrc_dm3 sdrc_dqs3 sdrc_ba0 sdrc_ba1 sdrc_a0 sdrc_a14 sdrc_ncs0 sdrc_ncs1 N/C sdrc_ncas sdrc_nras sdrc_nwe sdrc_cke0 sdrc_cke1 N/C sdrc_clk sdrc_nclk T T T T T T T T T T T T T T T T T T T DQ0 DQ7 LDM LDQS DQ8 DQ15 UDM UDQS BA0 BA1 A14 CS CAS RAS WE CKE CK CK BA0 BA1 A14 CS CAS RAS WE CKE CK CK T T T T T T T T LPDDR DQ0 DQ7 LDM LDQS DQ8 DQ15 UDM UDQS LPDDR DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Figure6-17.DM37x LPDDR High LevelSchematic (x16memories) Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 183 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

sdrc_d0 sdrc_d7 sdrc_dm0 sdrc_dqs0 sdrc_d8 sdrc_d15 sdrc_dm1 sdrc_dqs1 sdrc_d16 sdrc_d23 sdrc_dm2 sdrc_dqs2 sdrc_d24 sdrc_d31 sdrc_dm3 sdrc_dqs3 sdrc_ba0 sdrc_ba1 sdrc_a0 sdrc_a14 sdrc_ncs0 sdrc_ncas sdrc_nras sdrc_nwe sdrc_cke0 sdrc_clk sdrc_nclk T T T T T T T T T T T T T T T T T T T BA0 BA1 A14 CS CAS RAS WE CKE CK CK T T T T T T T T DQ0 DQ7 DM0 DQS0 DQ8 DQ15 DM1 DQS1 LPDDR DQ16 DQ23 DM2 DQS2 DQ24 DQ31 DM3 DQS3 N/C N/C sdrc_ncs1 sdrc_cke1 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Figure6-18.DM37x LPDDR High LevelSchematic (x32memory) 6.4.2.1.2Compatible JEDEC LPDDR Devices Table6-13 shows theparametersoftheJEDEC LPDDR devicesthatare compatiblewiththisinterface. Generally,theLPDDR interfaceiscompatiblewithx16 and x32 LPDDR266 and LPDDR333 speed grade LPDDR devices. Table6-13.Compatible JEDEC LPDDR Devices NO. PARAMETER MIN MAX UNIT NOTES JEDEC LPDDR DeviceSpeed1 LPDDR-266 See Note (1) Grade

2 JEDEC LPDDR DeviceBitWidth 16 32 Bits

3 JEDEC LPDDR DeviceCount 1 2 Devices See Note (2)

JEDEC LPDDR DeviceBall4 60 90 BallsCount

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) HigherLPDDR speed gradesaresupporteddue toinherentJEDEC LPDDR backwardscompatibility. (2) 1 x16 LPDDR deviceisused for16 bitLPDDR memory system.1x32 or2x16 LPDDR devicesareused fora 32-bitLPDDR memory system. 6.4.2.1.3PCB Stackup The minimum stackuprequiredforroutingthe DM37x is a sixlayerstackas shown in Table 6-14. Additionallayersmay be added tothePCB stackup toaccommodate othercircuitryortoreducethesize ofthePCB footprint. Table6-14.DM37x Minimum PCB Stack Up LAYER TYPE DESCRIPTION

1 Signal Top RoutingMostlyHorizontal

2 Plane Ground

3 Plane Power

4 Signal InternalRouting

5 Plane Ground

6 Signal BottomRoutingMostlyVertical

Table6-15.PCB Stack Up Specifications(4) NO. PARAMETER MIN TYP MAX UNIT NOTES

1 PCB Routing/PlaneLayers 6

2 SignalRoutingLayers 3

3 FullgroundlayersunderLPDDR routingregion 2

4 Number ofgroundplanecutsallowedwithinLPDDR routingregion 0

Number ofgroundreferenceplanesrequiredforeach LPDDR routing15 1layer Number oflayersbetween LPDDR routinglayerand referenceground06 0plane

7 PCB RoutingFeatureSize 4 Mils

8 PCB TraceWidthw 4 Mils

9 PCB BGA escape viapad size 18 Mils

10 PCB BGA escape viaholesize 8 Mils

11 DeviceBGA Pad Size See Note(1)

12 LPDDR DeviceBGA Pad Size See Note(2)

13 SingleEnded Impedance,ZO 50 75 Ω

14 Impedance Control Z-5 Z Z + 5 Ω See Note(3)

(1) See theFlipChipBallGridArrayPackage (SPRU811) referenceguidefordeviceBGA pad size. (2) See theLPDDR devicemanufacturerdocumentationfortheLPDDR deviceBGA pad size. (3) Z isthenominalsingledended impedance selectedforthePCB specifiedby item12. (4) SpecificroutingguidelinesfortheCUS package can be foundintheAM37x CUS RoutingGuidelines(SPRABD4) applicationnote.

6.4.2.2 Placement

Figure6-19 shows the requiredplacementforthe DM37x deviceas wellas the LPDDR devices.The dimensionsforFigure6-19aredefinedinTable6-16.The placementdoes notrestrictthesideofthePCB thatthe devicesare mounted on. The ultimatepurpose of the placementisto limitthe maximum trace lengthsand allowforproperroutingspace.For 1x16 and 1x32 LPDDR memory systems,the second LPDDR deviceisomittedfromtheplacement. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 185 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

X Y OFFSET Recommended□LPDDR□Device Orientation Y Y OFFSET LPDDR Device LPDDRControllerOMAP DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Figure6-19.DM37xx and LPDDR Device Placement Table6-16.Placement Specifications NO. PARAMETER MIN MAX UNIT NOTES

1 X 1440 Mils See Notes(1),(2)

2 Y 1030 Mils See Notes(1),(2)

3 Y Offset 525 Mils See Notes(1),(2),(3)

4 LPDDR KeepoutRegion See Note(4)

Clearancefromnon-LPDDR signaltoLPDDR5 4 w See Note(5) KeepoutRegion (1) See Figure6-17fordimensiondefinitions. (2) Measurements fromcenterofdevicetocenterofLPDDR device. (3) For16 bitmemory systemsitisrecommended thatY Offsetbe as smallas possible. (4) LPDDR keepoutregiontoencompass entireLPDDR routingarea. (5) Non-LPDDR signalsallowedwithinLPDDR keepoutregionprovidedtheyareseparatedfromLPDDR routinglayersby a groundplane.

6.4.2.3 LPDDR Keep Out Region

The regionof the PCB used forthe LPDDR circuitrymust be isolatedfrom othersignals.The LPDDR keep outregionisdefinedforthispurposeand isshown inFigure6-20.The sizeofthisregionvarieswith theplacementand LPDDR routing.Additionalclearancesrequiredforthekeep outregionare shown in Table6-16.

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LPDDR□Controller LPDDR□Device Region□should□encompass□all□LPDDR□circuitry□and□varies□depending on□placement.□Non-LPDDR□signals□should□not□be□routed□on□the LPDDR□signal□layers□within□the□LPDDR□keep□out□region.□Non-LPDDR signals□may□be□routed□in□the□region□provided□they□are□routed□on layers□separated□from□LPDDR□signal□layers□by□a□ground□layer.□No breaks□should□be□allowed□in□the□□reference□ground□layers□in□this region.□In□addition,□the□1.8□V□power□plane□should□cover□the□entire□keep out□region. DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Figure6-20.LPDDR Keepout Region

6.4.2.4 Net Classes

Table6-17liststheclocknetclassesfortheLPDDR interface.Table6-18liststhesignalnetclasses,and associatedclocknetclasses,forthesignalsintheLPDDR interface.These netclassesare used forthe terminationand routingrulesthatfollow. Table6-17.Clock Net Class Definitions CLOCK NET CLASS PIN NAMES CK sdrc_clk/sdrc_nclk DQS0 sdrc_dqs0 DQS1 sdrc_dqs1 DQS2 sdrc_dqs2 DQS3 sdrc_dqs3 Table6-18.SignalNet Class Definitions CLOCK NET CLASS ASSOCIATED CLOCK NET CLASS PIN NAMES sdrc_ba[1:0],sdrc_a[14:0],sdrc_ncs[1:0], ADDR_CTRL CK sdrc_ncas,sdrc_nras,sdrc_nwe, sdrc_cke[1:0] DQ0 DQS0 sdrc_d[7:0],sdrc_dm0 DQ1 DQS1 sdrc_d[15:8],sdrc_dm1 DQ2 DQS2 sdrc_d[23:16],sdrc_dm2 DQ3 DQS3 sdrc_d[31:24],sdrc_dm3

6.4.2.5 LPDDR SignalTermination

No terminationsof any kindare requiredinorderto meet signalintegrityand overshootrequirements. Serialterminatorsare permitted,ifdesired,toreduceEMI risk;however,serialterminationsare theonly typepermitted.Table6-19shows thespecificationsfortheseriesterminators. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 187 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

A T LPDDRController OMAP DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-19.LPDDR SignalTerminations NO. PARAMETER MIN TYP MAX UNIT NOTES

1 CK Net Class 0 10 Ω See Note(1)

2 ADDR_CTRL Net Class 0 22 Zo Ω See Notes(1),(2),(3)

Data ByteNet Classes3 0 22 Zo Ω See Notes(1),(2),(3) (DQS0-DQS3, DQ0-DQ3) (1) Onlyseriesterminationispermitted,parallelorSST specificallydisallowed. (2) Terminatorvalueslargerthantypicalonlyrecommended toaddressEMI issues. (3) Terminationvalueshouldbe uniformacrossnetclass.

6.4.2.6 LPDDR CK and ADDR_CTRL Routing

Figure6-21 shows thetopologyoftheroutingfortheCK and ADDR_CTRL netclasses.The routeisa balancedT as itisintendedthatthelengthofsegments B and C be equal.Inaddition,thelengthofA shouldbe maximized. Figure6-21.CK and ADDR_CTRL Routing and Topology Table6-20.CK and ADDR_CTRL Routing Specification(5) NO. PARAMETER MIN TYP MAX UNIT NOTES

1 CentertoCenterCK-CK spacing 2w

2 CK DifferentialPairSkew LengthMismatch(4) 25 Mils See Note(1)

3 CK B toC Skew LengthMismatch 25 Mils

CentertoCenterCK toother4 4w See Note(2) LPDDR tracespacing

5 CK/ADDR_CTRL nominaltracelength CACLM-50 CACLM CACLM+50 Mils See Note(3)

6 ADDR_CTRL toCK Skew LengthMismatch 100 Mils

ADDR_CTRL toADDR_CTRL7 100 MilsSkew LengthMismatch CentertoCenterADDR_CTRL toother8 4w See Note(2) LPDDR tracespacing CentertoCenterADDR_CTRL toother9 3w See Note(2) ADDR_CTRL tracespacing ADDR_CTRL A toB,ADDR_CTRL A toC10 100 Mils See Note(1) Skew LengthMismatch

11 ADDR_CTRL B toC Skew LengthMismatch 100 Mils

(1) Seriesterminator,ifused,shouldbe locatedclosesttoDM37x. (2) Centertocenterspacingisallowedtofalltominimum (w)forup to500 milsofroutedlengthtoaccommodate BGA escape and routing congestion. (3) CACLM isthelongestManhattandistanceoftheCK and ADDR_CTRL netclasses. (4) Differentialimpedance shouldbe 100 ohms. (5) SpecificroutingguidelinesfortheCUS package can be foundintheAM37x CUS RoutingGuidelines(SPRABD4) applicationnote.

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T T OMAP T LPDDRController T DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Figure6-22shows thetopologyand routingfortheDQS and DQ netclasses;theroutesarepointtopoint. Skew matchingacrossbytesisnotneeded norrecommended. Figure6-22.DQS and DQ Routing and Topology Table6-21.DQS and DQ Routing Specification(1)(6) PARAMETER MIN TYP MAX UNIT NOTES DQS E Skew LengthMismatch 25 Mils CentertoCenterDQS tootherLPDDR trace 4w See Note(2) spacing DQS/DQ nominaltracelength DQLM -50 DQLM DQLM + 50 Mils See Note(2) DQ toDQS Skew LengthMismatch 100 Mils See Note (4) DQ toDQ Skew LengthMismatch 100 Mils See Note (4) CentertoCenterDQ tootherLPDDR trace 4w See Note(5) spacing CentertoCenterDQ tootherDQ trace 3w See Note(2),(3) spacing DQ E Skew LengthMismatch 100 Mils (1) Seriesterminator,ifused,shouldbe locatedclosesttoLPDDR. (2) Centertocenterspacingisallowedtofalltominimum (w)forup to500 milsofroutedlengthtoaccommodate BGA escape and routing congestion. (3) DQLM isthelongestManhattandistanceoftheDQS and DQ netclasses. (4) Thereisno need,and itisnotrecommended, toskew match acrossdatabytes.Thisspecificationisonlyrelativewithina databyte. (5) DQs fromotherbytesareconsideredotherLPDDR traces. (6) SpecificroutingguidelinesfortheCUS package can be foundintheAM37x CUS RoutingGuidelines(SPRABD4) applicationnote. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 189 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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6.5 MultimediaInterfaces

6.5.1 Camera ISP2P Interface

For more information,see Camera ISP chapterof the AM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). The camera subsystemprovidesthesystem interfacesand theprocessingcapabilitytoconnectraw,YUV or JPEG image sensor modules to the deviceforvideo-preview,video-recordand still-image-capture applications. The camera ISP2P subsystemsupportsup totwo simultaneouspixelflowsbutonlyone ofthem can use thevideoprocessinghardware:

• Parallelcamera interface+ Serialcamera interface:one interfacedata goes throughthe video processinghardware.The otherinterfacedatagoes directlytomemory
• Serialcamera interface+ Serialcamera interface:one serialinterfacedata goes throughthe video processing hardware. The other serial interface data goes directly to memory. The camera ISP2P subsystemsupportsdifferentcamera configurations:
• 10-bitParallelinterface
• 12-bitParallelinterface
• 12-bitParallelinterface Note:For more information,see theCamera ISP /Camera ISP Environment/Camera ISP Connectivity Schemes sectionof the AM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ).

6.5.1.1 Camera Output Clocks (cam_xclkaand cam_xclkb)

Table6-22.ISP2P cam_xclka and cam_xclkb Output Clocks SwitchingCharacteristics NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX ISP15 1 /tc(xclk) Frequency(1),outputclockcam_xclkn(4) 216 216 MHz ISP16 tw(xclkH) Typicalpulseduration,outputclock 0.5P(2) 0.5P(2) ns cam_xclkn(4)high ISP16 tw(xclkL) Typicalpulseduration,outputclock 0.5P(2) 0.5P(2) ns cam_xclkn(4)low tdc(xclk) Dutycycleerror,outputclockcam_xclkn(4) 0.5*P(2)-2.083 0.5*P(2)-2.083 ps tJ(xclk) Cyclejitter(3),outputclockcam_xclkn(4) 0.044*P(2) 0.044*P(2) ps tR(xclk) Risetime,outputclockcam_xclkn(4) 0.93 0.93 ns tF(xclk) Falltime,outputclockcam_xclkn(4) 0.93 0.93 ns (1) Relatedwiththecam_xclkn(4)maximum and minimum frequenciesprogrammableintheISP module. NOTE :You must disablethecamera sensororthecamera module tochange thefrequencyconfiguration.Formore information,see the AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (2) P = cam_xclkn(4)periodinns (3) Maximum cyclejittersupportedby cam_xclkaand cam_xclkboutputclocks. (4) Incam_xclkn,n isequaltoa orb.

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6.5.1.2 ParallelCamera Interface(CPI)

The imagingsubsystemdealswiththeprocessingofthepixeldatacoming froman externalimage sensor orfromvideoand graphicsdigitizer.Itisa key component forthefollowingmultimediaapplications:video preview,camera viewfinder,videorecordand stillimage capture.ItsupportsRAW, RGB, and YUV data processing. Table 6-24 assumes testingover the recommended operatingconditionsand electricalcharacteristic conditionsbelow(seeFigure6-23and Figure6-24). Table6-23.CPI Timing Conditions—Video and Graphics Digitizer1.8-VMode TIMING CONDITION PARAMETER VALUE UNIT MIN MAX InputConditions tR Inputsignalrisetime 80 1800 ps tF Inputsignalfalltime 80 1800 ps Table6-24.CPI Timing Requirements—Video and Graphics Digitizer1.8-VMode (4)(6) NO. PARAMETER OPP100 UNIT MIN MAX ISP1 1 /tc(pclk) Frequency(1),inputpixelclockcam_pclk 148.5 MHz ISP2 tw(pclkL) Typicalpulseduration,inputpixelclockcam_pclklow 0.5P(2) ns ISP3 tw(pclkH) Typicalpulseduration,inputpixelclockcam_pclkhigh 0.5P(2) ns tdc(pclk) Dutycycleerror,inputpixelclockcam_pclk 0.5*P(2)- ns 3.247 tJ(pclk) Cyclejitter(3),inputpixelclockcam_pclk 0.06P(2) ns ISP4 tsu(vsV-pclkH) Setuptime,inputverticalsynchronizationcam_vs validbeforeinput 0.75 ns pixelclockcam_pclkrising/fallingedge ISP5 th(pclkH-vsV) Holdtime,inputverticalsynchronizationcam_vs validafterinputpixel 0.96 ns clockcam_pclkrising/fallingedge ISP6 tsu(hsV-pclkH) Setuptime,inputhorizontalsynchronizationcam_hs validbeforeinput 0.75 ns pixelclockcam_pclkrising/fallingedge ISP7 th(pclkH-hsV) Holdtime,inputhorizontalsynchronizationcam_hs validafterinput 0.96 ns pixelclockcam_pclkrising/fallingedge ISP8 tsu(dV-pclkH) Setuptime,inputdatacam_dn:0validbeforeinputpixelclock 0.75 ns cam_pclkrising/fallingedge ISP9 th(pclkH-dV) Holdtime,inputdatacam_dn:0validafterinputpixelclock 0.96 ns cam_pclkrising/fallingedge ISP10 tsu(wenV-pclkH) Setuptime,inputwriteenablecam_wen validbeforeinputpixelclock 0.75 ns cam_pclkrising/fallingedge ISP11 th(pclkH-wenV) Holdtime,inputwriteenablecam_wen validafterinputpixelclock 0.96 ns cam_pclkrising/fallingedge ISP12 tsu(fldV-pclkH) Setuptime,inputfieldidentificationcam_fldvalidbeforeinputpixel 0.75 ns clockcam_pclkrising/fallingedge ISP13 th(pclkH-fldV) Holdtime,inputfieldidentificationcam_fldvalidafterinputpixelclock 0.96 ns cam_pclkrising/fallingedge (1) Relatedwiththeinputmaximum frequencysupportedby theISP module in8-bitmode with8 to16 databitsconversionbridgeenabled. (2) P = cam_pclkperiodinns (3) Maximum cyclejittersupportedby cam_pclkinputclock (4) The timingrequirementsareassuredup tothecyclejitterand dutycycleerrorconditionsspecified. (5) n = 11 (Databus sizeislimitedto8 bits.So thebitsconfigurationiseithercam_d[7:0]orcam_d[11:4]).Linesnotconnectedmust be tiedlow. (6) See Section4.3.4,ProcessorClocks. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 191 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

D(n-2) cam_pclk cam_vs cam_hs cam_d[N:0] cam_wen cam_fld D(0) D(n-2) D(n-1) D(0) D(n-1) ISP1 ISP4 ISP5 ISP6 ISP7 ISP9 ISP8 ISP10 ISP1 1 ISP3 SWPS038-048 ISP2 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) The polarityofcam_pclk,cam_fld,cam_vs, and cam_hs aresoftwareconfigurable.Optionally,thecam_wen signalcan be used as an externalmemory write-enablesignal.For furtherdetails,see the AM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). (2) N = 11 (Databus sizeislimitedto8 bits.So thebitsconfigurationiseithercam_d[7:0]or cam_d[11:4]).When thenumber ofdata linesislessthancam_d[N:0],datalinescan be connectedtotheupper or lowerlinesofcam_d[N:0].Linesnotconnectedmust be tiedlow.For more informationabout videoportmapping, see the AM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). Figure6-23.CPI—Video and Graphics Digitizer—1.8-VProgressiveMode

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cam_pclk cam_vs cam_hs cam_d[N:0] cam_wen cam_fld D(n–1) D(0) D(n–1) D(0) D(n–1) EVEN ODD ISP1 ISP2 ISP4 ISP5 ISP6 ISP7 ISP9 ISP8 ISP10 ISP1 1 ISP3 ISP12 ISP13 SWPS038-049 D(0) D(0) D(n–1) DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) The polarityofcam_pclk,cam_fld,cam_vs, and cam_hs aresoftwareconfigurable.Optionally,thecam_wen signalcan be used as an externalmemory write-enablesignal.For furtherdetails,see the AM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). (2) N = 11 (Databus sizeislimitedto8 bits.So thebitsconfigurationiseithercam_d[7:0]or cam_d[11:4]).When thenumber ofdata linesislessthancam_d[N:0],datalinescan be connectedtotheupper or lowerlinesofcam_d[N:0].Linesnotconnectedmust be tiedlow.For more informationabout videoportmapping, see the AM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). Figure6-24.CPI—Video and Graphics Digitizer—1.8-VInterlacedMode 6.5.1.2.2CPI—12-BitSYNC Normal ProgressiveMode Table 6-26 assumes testingover the recommended operatingconditionsand electricalcharacteristic conditionsbelow(seeFigure6-25). Table6-25.CPI Timing Conditions—12-BitSYNC Normal ProgressiveMode (1) TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 2.7 ns tF Inputsignalfalltime 2.7 ns Output Condition C LOAD Outputloadcapacitance 8.6 pF (1) The loadsettingoftheIO buffer:LB0 = 1. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 193 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-26.CPI Timing Requirements—12-BitSYNC Normal ProgressiveMode (4)(5) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX ISP17 1 /tc(pclk) Frequency(1),inputpixelclockcam_pclk 75 45 MHz ISP18 tw(pclkH) Typicalpulseduration,inputpixelclockcam_pclkhigh 0.5P(2) 0.5P(2) ns ISP18 tw(pclkL) Typicalpulseduration,inputpixelclockcam_pclklow 0.5P(2) 0.5P(2) ns tdc(pclk) Dutycycleerror,inputpixelclockcam_pclk 0.5P(2)- 0.5P(2)- ns 3.465 6.93 tJ(pclk) Cyclejitter(3),inputpixelclockcam_pclk 0.0649*P 0.0649*P ns (2) (2) ISP19 tsu(dV-pclkH) Setuptime,inputdatacam_d[11:0]validbeforeinput 1.82 3.25 ns pixelclockcam_pclkrisingedge ISP20 th(pclkH-dV) Holdtime,inputdatacam_d[11:0]validafterinput 1.82 3.25 ns pixelclockcam_pclkrisingedge ISP21 tsu(dV-vsH) Setuptime,inputverticalsynchronizationcam_vs valid 1.82 3.25 ns beforeinputpixelclockcam_pclkrisingedge ISP22 th(pclkH-vsV) Holdtime,inputverticalsynchronizationcam_vs valid 1.82 3.25 ns afterinputpixelclockcam_pclkrisingedge ISP23 tsu(dV-hsH) Setuptime,inputhorizontalsynchronizationcam_hs 1.82 3.25 ns validbeforeinputpixelclockcam_pclkrisingedge ISP24 th(pclkH-hsV) Holdtime,inputhorizontalsynchronizationcam_hs 1.82 3.25 ns validafterinputpixelclockcam_pclkrisingedge ISP25 tsu(dV-hsH) Setuptime,inputwriteenablecam_wen validbefore 1.82 3.25 ns inputpixelclockcam_pclkrisingedge ISP26 th(pclkH-hsV) Holdtime,inputwriteenablecam_wen validafterinput 1.82 3.25 ns pixelclockcam_pclkrisingedge (1) Relatedwiththeinputmaximum frequencysupportedby theISP module. (2) P = cam_pclkperiodinns (3) Maximum cyclejittersupportedby cam_pclkinputclock. (4) The timingrequirementsareassuredup tothecyclejitterand dutycycleerrorconditionsspecified. (5) See Section4.3.4,ProcessorClocks.

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cam_xclki cam_pclk cam_vs cam_hs cam_d[1 1:0] cam_wen cam_fld D(0) D(n–3) D(n–2) D(n–1) D(0) D(1) ISP15 ISP16 ISP16 ISP17 ISP18 ISP19 ISP20 ISP21 ISP22 ISP24ISP23 ISP25 ISP26 ISP18 SWPS038-050 D(n–1) DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) The polarityofcam_pclk,cam_fld,cam_vs, and cam_hs are configurable.Ifthecam_hs, cam_vs, and cam_fldsignalsare output, thesignallengthcan be set. (2) The parallelcamera inSYNC mode supportsprogressiveimage sensormodules and 8-,10-,11-,or12-bitdata. (3) When theimage sensorhas fewerthan12 datalines,itmust be connectedtothelowerdatalinesand theunused linesmust be grounded. (4) However,itispossibletoshiftthedatato0,2,or4 datainternallanes. (5) The bitconfigurationsare:cam_d[11:4]orcam_d[7:0]in8-bitmode, cam_d[11:2]orcam_d[9:0]in10-bitmode, cam_d[10:0]in11-bit mode and cam_d[11:0]in12-bitmode. (6) Optionally,thedatawritetomemory can be qualifiedby theexternalcam_wen signal. (7) The cam_wen signalcan be used as an externalmemory write-enablesignal.The dataisstoredtomemory onlyifcam_hs, cam_vs, and cam_wen signalsareasserted. (8) Incam_xclki,ican be equaltoa orb.See Table6-22forISP15 and ISP16 parameters. Figure6-25.CPI—12-BitSYNC Normal ProgressiveMode 6.5.1.2.3CPI—8-BitSYNC Packed ProgressiveMode Table 6-28 assumes testingover the recommended operatingconditionsand electricalcharacteristic conditionsbelow(seeFigure6-26). Table6-27.CPI Timing Conditions—8-BitSYNC Packed ProgressiveMode (1) TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 2.5 ns tF Inputsignalfalltime 2.5 ns Output Condition C LOAD Outputloadcapacitance 8.6 pF Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 195 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) The loadsettingoftheIO buffer:LB0 = 1. Table6-28.CPI Timing Requirements—8-BitSYNC Packed ProgressiveMode (4)(5) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX ISP3 1 /tc(pclk) Frequency(1),inputpixelclockcam_pclk 130 65 MHz ISP4 tw(pclkH) Typicalpulseduration,inputpixelclock 0.5*P(2) 0.5*P(2) ns cam_pclkhigh ISP4 tw(pclkL) Typicalpulseduration,inputpixelclock 0.5*P(2) 0.5*P(2) ns cam_pclklow tdc(pclk) Dutycycleerror,inputpixelclockcam_pclk 0.5*P(2)- 0.5*P(2)- ns 3.465 6.93 tJ(pclk) Cyclejitter(3),inputpixelclockcam_pclk 0.0649*P(2) 0.0649*P(2) ns ISP5 tsu(dV-pclkH) Setuptime,inputdatacam_d[7:0]validbefore 1.08 2.27 ns inputpixelclockcam_pclkrisingedge ISP6 th(pclkH-dV) Holdtime,inputdatacam_d[7:0]validafterinput 1.08 2.27 ns pixelclockcam_pclkrisingedge ISP7 tsu(dV-vsH) Setuptime,inputverticalsynchronization 1.08 2.27 ns cam_vs validbeforeinputpixelclockcam_pclk risingedge ISP8 th(pclkH-vsV) Holdtime,inputverticalsynchronizationcam_vs 1.08 2.27 ns validafterinputpixelclockcam_pclkrisingedge ISP9 tsu(dV-hsH) Setuptime,inputhorizontalsynchronization 1.08 2.27 ns cam_hs validbeforeinputpixelclockcam_pclk risingedge ISP10 th(pclkH-hsV) Holdtime,inputhorizontalsynchronization 1.08 2.27 ns cam_hs validafterinputpixelclockcam_pclk risingedge ISP11 tsu(dV-hsH) Setuptime,inputwriteenablecam_wen valid 1.08 2.27 ns beforeinputpixelclockcam_pclkrisingedge ISP12 th(pclkH-hsV) Holdtime,inputwriteenablecam_wen valid 1.08 2.27 ns afterinputpixelclockcam_pclkrisingedge (1) Relatedwiththeinputmaximum frequencysupportedby theISP module. (2) P = cam_pclkperiodinns (3) Maximum cyclejittersupportedby cam_pclkinputclock. (4) The timingrequirementsareassuredup tothecyclejitterand dutycycleerrorconditionsspecified. (5) See Section4.3.4,ProcessorClocks.

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cam_xclki cam_pclk cam_vs cam_hs cam_d[7:0] cam_wen cam_fld D(0) D(n-3) D(n-2) D(n-1) D(0) D(1) D(n-1) ISP15 ISP16 ISP16 ISP3 ISP4 ISP5 ISP6 ISP7 ISP8 ISP10 ISP4 ISP9 ISP1 1 ISP12 SWPS038-051 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) The polarityofcam_pclk,cam_fld,cam_vs,and cam_hs areconfigurable. (2) The image sensorisconnectedtothelowerdatalinesand theunused linesaregrounded.However,itispossibletoshiftthedatato 0,2,or4 datainternallanes.The bitconfigurationsare:cam_d[11:4]orcam_d[7:0]in8-bitpacked mode. (3) Optionally,the data writeto memory can be qualifiedby the externalcam_wen signal.The cam_wen signalcan be used as a externalmemory write-enablesignal.The dataisstoredtomemory onlyifcam_hs, cam_vs, and cam_wen signalsareasserted.The polarityofcam_fldisprogrammable. (4) The camera module can pack 8-bitdatainto16 bits.Itdoublesthemaximum pixelclock.Thismode can be particularlyusefulto transferan YCbCr datastreamorcompressed streamtomemory atveryhighspeed. (5) Incam_xclki,ican be equaltoa orb.See Table6-22forISP15 and ISP16 parameters. Figure6-26.CPI—8-BitSYNC Packed ProgressiveMode 6.5.1.2.4CPI—12-BitSYNC Normal InterlacedMode Table 6-30 assumes testingover the recommended operatingconditionsand electricalcharacteristic conditionsbelow(seeFigure6-27). Table6-29.CPI Timing Conditions—12-BitSYNC Normal InterlacedMode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 2.7 ns tF Inputsignalfalltime 2.7 ns Output Condition C LOAD Outputloadcapacitance(1) 8.6 pF (1) The loadsettingoftheIO buffer:LB0 = 1. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 197 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-30.CPI Timing Requirements—12-BitSYNC Normal InterlacedMode (4)(5) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX ISP17 1 /tc(pclk) Frequency(1),inputpixelclockcam_pclk 75 45 MHz ISP18 tw(pclkH) Typicalpulseduration,inputpixelclockcam_pclkhigh 0.5P(2) 0.5P(2) ns ISP18 tw(pclkL) Typicalpulseduration,inputpixelclockcam_pclklow 0.5P(2) 0.5P(2) ns tdc(pclk) Dutycycleerror,inputpixelclockcam_pclk 0.5*P(2)- 0.5*P(2)- ns 3.465 6.93 tJ(pclk) Cyclejitter(3),inputpixelclockcam_pclk 0.0649*P 0.0649*P ns (2) (2) ISP19 tsu(dV-pclkH) Setuptime,inputdatacam_d[11:0]validbeforeinput 1.82 3.25 ns pixelclockcam_pclkrisingedge ISP20 th(pclkH-dV) Holdtime,inputdatacam_d[11:0]validafterinput 1.82 3.25 ns pixelclockcam_pclkrisingedge ISP21 tsu(dV-vsH) Setuptime,inputverticalsynchronizationcam_vs valid 1.82 3.25 ns beforeinputpixelclockcam_pclkrisingedge ISP22 th(pclkH-vsV) Holdtime,inputverticalsynchronizationcam_vs valid 1.82 3.25 ns afterinputpixelclockcam_pclkrisingedge ISP23 tsu(dV-hsH) Setuptime,inputhorizontalsynchronizationcam_hs 1.82 3.25 ns validbeforeinputpixelclockcam_pclkrisingedge ISP24 th(pclkH-hsV) Holdtime,inputhorizontalsynchronizationcam_hs 1.82 3.25 ns validafterinputpixelclockcam_pclkrisingedge ISP25 tsu(dV-hsH) Setuptime,inputwriteenablecam_wen validbefore 1.82 3.25 ns inputpixelclockcam_pclkrisingedge ISP26 th(pclkH-hsV) Holdtime,inputwriteenablecam_wen validafterinput 1.82 3.25 ns pixelclockcam_pclkrisingedge ISP27 tsu(dV-fldH) Setuptime,inputfieldidentificationcam_fldvalid 1.82 3.25 ns beforeinputpixelclockcam_pclkrisingedge ISP28 th(pclkH-fldV) Holdtime,inputfieldidentificationcam_fldvalidafter 1.82 3.25 ns inputpixelclockcam_pclkrisingedge (1) Relatedwiththeinputmaximum frequencysupportedby theISP module. (2) P = cam_pclkperiodinns (3) Maximum cyclejittersupportedby cam_pclkinputclock. (4) The timingrequirementsareassuredup tothecyclejitterand dutycycleerrorconditionsspecified. (5) See Section4.3.4,ProcessorClocks.

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cam_xclki cam_pclk cam_vs cam_hs cam_d[1 1:0] cam_wen cam_fld FRAME(0) L(0) L(0) D(0) D(n-3) D(n-2) D(n-1) D(0) D(1) D(2) D(n-1) P AIR IMP AIR ISP16 ISP16 ISP17 ISP18 ISP27 ISP19 ISP21 ISP22 ISP23 ISP20 ISP28 ISP25 ISP26 SWPS038-052 FRAME(0) L(n-1) ISP18 ISP15 ISP24 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) The polarityofcam_pclk,cam_fld,cam_vs, and cam_hs are configurable.Ifthecam_hs, cam_vs, and cam_fldsignalsare output, thesignallengthcan be set. (2) The parallelcamera inSYNC mode supportsinterlacedimage sensormodules and 8-,10-,11-,or12-bitdata. (3) When theimage sensorhas fewerthan12 datalines,itisconnectedtothelowerdatalinesand theunused linesaregrounded. (4) Itispossibletoshiftthedatato0,2,or4 datainternallanes. (5) The bitconfigurationsare:cam_d[11:4]orcam_d[7:0]in8-bitmode, cam_d[11:2]orcam_d[9:0]in10-bitmode, cam_d[10:0]in11-bit mode and cam_d[11:0]in12-bitmode. (6) Optionally,thedatawritetomemory can be qualifiedby theexternalcam_wen signal. (7) The cam_wen signalcan be used as an externalmemory write-enablesignal.The dataisstoredtomemory onlyifcam_hs, cam_vs, and cam_wen signalsareasserted. (8) Incam_xclki,ican be equaltoa orb.See Table6-22forISP15 and ISP16 parameters. Figure6-27.CPI—12-bitSYNC Normal InterlacedMode Section5.3 Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 199 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com 6.5.1.2.5CPI—8-BitSYNC Packed InterlacedMode Table 6-32 assumes testingover the recommended operatingconditionsand electricalcharacteristic conditionsbelow(seeFigure6-28). Table6-31.CPI Timing Conditions—8-BitSYNC Packed InterlacedMode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 2.5 ns tF Inputsignalfalltime 2.5 ns Output Condition C LOAD Outputloadcapacitance(1) 8.6 pF (1) The loadsettingoftheIO buffer:LB0 = 1. Table6-32.CPI Timing Requirements—8-BitSYNC Packed InterlacedMode (4)(5) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX ISP3 1 /tc(pclk) Frequency(1),inputpixelclockcam_pclk 130 65 MHz ISP4 tw(pclkH) Typicalpulseduration,inputpixelclockcam_pclkhigh 0.5P(2) 0.5P(2) ns ISP4 tw(pclkL) Typicalpulseduration,inputpixelclockcam_pclklow 0.5P(2) 0.5P(2) ns tdc(pclk) Dutycycleerror,inputpixelclockcam_pclk 0.5*P(2)- 0.5*P(2)- ns 3.465 6.93 tJ(pclk) Cyclejitter(3),inputpixelclockcam_pclk 0.0649*P 0.0649*P ns (2) (2) ISP5 tsu(dV-pclkH) Setuptime,inputdatacam_d[8:0]validbeforeinput 1.08 2.27 ns pixelclockcam_pclkrisingedge ISP6 th(pclkH-dV) Holdtime,inputdatacam_d[8:0]validafterinputpixel 1.08 2.27 ns clockcam_pclkrisingedge ISP7 tsu(dV-vsH) Setuptime,inputverticalsynchronizationcam_vs valid 1.08 2.27 ns beforeinputpixelclockcam_pclkrisingedge ISP8 th(pclkH-vsV) Holdtime,inputverticalsynchronizationcam_vs valid 1.08 2.27 ns afterinputpixelclockcam_pclkrisingedge ISP9 tsu(dV-hsH) Setuptime,inputhorizontalsynchronizationcam_hs 1.08 2.27 ns validbeforeinputpixelclockcam_pclkrisingedge ISP10 th(pclkH-hsV) Holdtime,inputhorizontalsynchronizationcam_hs 1.08 2.27 ns validafterinputpixelclockcam_pclkrisingedge ISP11 tsu(dV-hsH) Setuptime,inputwriteenablecam_wen validbefore 1.08 2.27 ns inputpixelclockcam_pclkrisingedge ISP12 th(pclkH-hsV) Holdtime,inputwriteenablecam_wen validafterinput 1.08 2.27 ns pixelclockcam_pclkrisingedge ISP13 tsu(dV-fldH) Setuptime,inputfieldidentificationcam_fldvalid 1.08 2.27 ns beforeinputpixelclockcam_pclkrisingedge ISP14 th(pclkH-fldV) Holdtime,inputfieldidentificationcam_fldvalidafter 1.08 2.27 ns inputpixelclockcam_pclkrisingedge (1) Relatedwiththeinputmaximum frequencysupportedby theISP module. (2) P = cam_pclkperiodinns (3) Maximum cyclejittersupportedby cam_pclkinputclock. (4) The timingrequirementsareassuredup tothecyclejitterand dutycycleerrorconditionsspecified. (5) See Section4.3.4,ProcessorClocks.

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cam_xclki cam_pclk cam_vs cam_hs cam_d[7:0] cam_wen cam_fld FRAME(0) FRAME(0) L(0) L(0) D(0) D(n-3) D(n-2) D(0) D(1) D(2) D(n-1) P AIR IMP AIR ISP15 ISP16 ISP16 ISP3 ISP4 ISP4 ISP13 ISP5 ISP7 ISP8 ISP9 ISP6 ISP14 ISP1 1 ISP12 SWPS038-053 D(n-1) L(n-1) ISP10 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) The polarityofcam_pclk,cam_fld,cam_vs,and cam_hs areconfigurable. (2) The image sensorisconnectedtothelowerdatalinesand theunused linesaregrounded.However,itispossibletoshiftthedatato 0,2,or4 datainternallanes.The bitconfigurationsare:cam_d[11:4]orcam_d[7:0]in8-bitpacked mode . (3) Optionally,the data writeto memory can be qualifiedby the externalcam_wen signal.The cam_wen signalcan be used as an externalmemory write-enablesignal.The dataisstoredtomemory onlyifcam_hs, cam_vs,and cam_wen signalsareasserted. (4) The camera module can pack 8-bitdatainto16 bits.Itdoublesthemaximum pixelclock.Thismode can be particularlyusefulto transfera YCbCr datastreamorcompressed streamtomemory atveryhighspeed. (5) Incam_xclki,ican be equaltoa orb.See Table6-22forISP15 and ISP16 parameters. Figure6-28.CPI—8-BitSYNC Packed InterlacedMode 6.5.1.2.6CPI—ITU Mode Table 6-34 assumes testingover the recommended operatingconditionsand electricalcharacteristic conditionsbelow(seeFigure6-29). Table6-33.CPI Timing Conditions—ITU Mode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 2.7 ns tF Inputsignalfalltime 2.7 ns Output Condition C LOAD Outputloadcapacitance(1) 8.6 pF (1) The loadsettingoftheIO buffer:LB0 = 1. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 201 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

cam_xclki cam_pclk cam_d[9:0] SOF D(0) D(n-1) EOF SOF D(0) D(n-1) EOF ISP16 ISP16 ISP17 ISP23 ISP24 ISP18 ISP18 ISP15 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-34.CPI Timing Requirements—ITU Mode (4)(5) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX ISP17 1 /tc(pclk) Frequency(1),inputpixelclockcam_pclk 75 45 MHz ISP18 tw(pclkH) Typicalpulseduration,inputpixelclockcam_pclkhigh 0.5P(2) 0.5P(2) ns ISP18 tw(pclkL) Typicalpulseduration,inputpixelclockcam_pclklow 0.5P(2) 0.5P(2) ns tdc(pclk) Dutycycleerror,inputpixelclockcam_pclk 0.5*P(2)- 0.5*P(2)- ns 3.465 6.93 tJ(pclk) Cyclejitter(3),inputpixelclockcam_pclk 0.0649*P 0.0649*P ns (2) (2) ISP23 tsu(dV-pclkH) Setuptime,inputdatacam_d[9:0]validbeforeinput 1.82 3.25 ns pixelclockcam_pclkrisingedge ISP24 th(pclkH-dV) Holdtime,inputdatacam_d[9:0]validafterinputpixel 1.82 3.25 ns clockcam_pclkrisingedge (1) Relatedwiththeinputmaximum frequencysupportedby theISP module. (2) P = cam_pclkperiodinns (3) Maximum cyclejittersupportedby cam_pclkinputclock. (4) The timingrequirementsareassuredup tothecyclejitterand dutycycleerrorconditionsspecified. (5) See Section4.3.4,ProcessorClocks. (1) The unused linesaregroundedand thedatabus isconnectedtothelowerdatalines.However,itispossibletoshiftthedatato0,2, or4 datainternallanes.The differentconfigurationsare:cam_d[11:4]orcam_d[7:0]in8-bitmode and cam_d[11:2]orcam_d[9:0]in 10-bitmode. (2) The parallelcamera inITU mode supportsprogressivecamera modules. (3) Incam_xclki,ican be equaltoa orb.See Table6-22forISP15 and ISP16 parameters. Figure6-29.CPI—ITU Mode

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6.5.2 DisplaySubsystem (DSS)

For more information,see DisplaySubsystem chapteroftheAM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). The displaysubsystem (DSS) providesthe logicto displaythe videoframe from external(SDRAM) or internal(SRAM) memory on an LCD panelor a TV set.The displaysubsystem integratesthefollowing elements:

• Displaycontroller(DISPC)module
• Remote framebufferinterface(RFBI)module
• NTSC/PAL videoencoder
• LCD displaywith: – ParallelInterface The two displaysupportscan be activeatthesame time.

6.5.2.1 DSS —ParallelInterface

Inparallelinterface,thepathsofthedisplaysubsystemmodules arethedisplaycontrollerand theRFBI. The displaycontrollerhas two I/Opad modes and couldbe inthefollowingconfiguration:

• Bypass mode (RFBIdisabled),whichimplementstheMIPIDPI protocol
• RFBI mode (RFBIenabled),whichimplementsMIPIDBI 2.0typeB protocol For more informationabout MIPI DPI and MIPI DBI protocols,see the DSS chapterinthe AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). 6.5.2.1.1DSS —ParallelInterface—Bypass Mode Two typesofLCD panelaresupported:
• Thinfilmtransistor(TFT)oractivematrixtechnology
• Supertwistednematic(STN) orpassivematrixtechnology Bothconfigurationsarediscussedinthefollowingparagraphs. 6.5.2.1.2DSS —ParallelInterface—Bypass Mode —TFT Mode Table 6-36 assumes testingover the recommended operatingconditionsand electricalcharacteristic conditionsbelow(seeFigure6-30). Table6-35.DSS Timing Conditions—TFT Mode TIMING CONDITION PARAMETER VALUE UNIT MIN MAX Output Condition C LOAD Outputloadcapacitance(1) 10 pF (1) Bufferstrengthconfiguration:LB0 = 1 Table6-36.DSS SwitchingCharacteristics—TFT Mode (4) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX DL0 td(pclkA-hsync) Delaytime,outputpixelclockdss_pclkactiveedge to –4.215 4.215 –4.658 4.658 ns outputhorizontalsynchronizationdss_hsynctransition DL1 td(pclkA-vsync) Delaytime,outputpixelclockdss_pclkactiveedge to –4.215 4.215 –4.658 4.658 ns outputverticalsynchronizationdss_vsynctransition Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 203 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

dss_pclk dss_vsync dss_hsync dss_acbias dss_data[23:0] DL4 DL5 DL3 DL0 DL2 DL1 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-36.DSS SwitchingCharacteristics—TFT Mode (4) (continued) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX DL2 td(pclkA-acbiasA) Delaytime,outputpixelclockdss_pclkactiveedge to –4.215 4.215 –4.658 4.658 ns outputdataenabledss_acbiasactivelevel DL3 td(pclkA-dV) Delaytime,outputpixelclockdss_pclkactiveedge to –4.215 4.215 –4.658 4.658 ns outputdatadss_data[23:0]valid DL4 1 /tc(pclk) Frequency(2),outputpixelclockdss_pclk 74.3(3) 66(3) MHz DL5 tw(pclk) Pulseduration,outputpixelclockdss_pclkloworhigh 0.45P(1) 0.55P(1) 0.45P(1) 0.55P(1) ns (5) (5) (1) P = dss_pclkperiodinns (2) The pixelclockfrequencyissoftwareprogrammableviathepixelclockdividerconfigurationfrom1 to255 divisionrangeinthe DISPC_DIVISOR register. (3) FortheDSS (TFT mode) inHD-TV application,torunatfullspeed (74.3MHz) itisrecommended touse thedss_data[5:0]signalson thedss_data[23:18]balls(H26,H25, E28,J26,AC27, AC28).Inthatcase,thedss_data[23:18]signalsareavailableon thesys_boot0, sys_boot1,sys_boot3,sys_boot4,sys_boot5,and sys_boot6balls(AH26,AG26, AF18, AF19, AE21, AF21) torunatfullspeed (74.3 MHz). Ifthedss_data[5:0]signalsareused on thedss_data[5:0]balls(AG22,AH22, AG23, AH23, AG24, AH24),OPP100 DSS (TFT mode) arelimitedat66 MHz. The valuesmay change followingthesiliconcharacterizationresult. (4) See Section4.3.4,ProcessorClocks. (5) tW(pclk)= 0.66.Pwhen DISPC_DIVISOR[6:0]PCD = 3. (1) The pixeldatabus depends on theuse of8-,9-,12-,16-,18-,or24-bitperpixeldataoutputpins. (2) The pixelclockfrequencyisprogrammable. (3) Alltimingsnotillustratedinthewaveform areprogammable by software,and controlsignalpolarityand drivenedge ofdss_pclktoo. (4) For more information,see the DSS chapterinthe AM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). Figure6-30.DSS —TFT Mode 6.5.2.1.3DSS —ParallelInterface—Bypass Mode —STN Mode Table 6-38 assumes testingover the recommended operatingconditionsand electricalcharacteristic conditionsbelow(seeFigure6-31). Table6-37.DSS Timing Conditions—STN Mode TIMING CONDITION PARAMETER VALUE UNIT MIN MAX Output Condition C LOAD Outputloadcapacitance(1) 40 pF

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dss_pclk dss_vsync dss_hsync dss_acbias dss_data[23:0] DL4 DL5 DL3 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) Bufferstrengthconfiguration:LB0 = 1 Table6-38.DSS SwitchingCharacteristics—STN Mode (3)(4) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX DL3 td(pclkA-dV) Delaytime,outputpixelclockdss_pclkactive –6.868 6.868 –6.868 6.868 ns edge tooutputdatadss_data[7:0]valid DL4 1 /tc(pclk) Frequency(2),outputpixelclockdss_pclk 44 44 MHz DL5 tw(pclk) Pulseduration,outputpixelclockdss_pclklow 0.45P(1) 0.55P(1)(5) 0.45P(1) 0.55P(1)(5) ns orhigh (1) P = dss_pclkperiodinns (2) The pixelclockfrequencyissoftwareprogrammableviathepixelclockdividerconfigurationfrom1 to255 divisionrangeinthe DISPC_DIVISOR register. (3) The DSS inSTN mode isused with4 or8 pinsonly;unused pixeldatabitsalwaysremainlow. (4) See Section4.3.4,ProcessorClocks. (5) tW(pclk)= 0.66Pwhen DISPC_DIVISOR[6:0]PCD = 3. (1) The pixeldatabus depends on theuse of4-,8-,12-,16-,18-,or24-bitperpixeldataoutputpins. (2) Alltimingsnotillustratedinthewaveform areprogammable by software,and controlsignalpolarityand drivenedge ofdss_pclktoo. (3) dss_vsyncwidthmust be programmed tobe as smallas possible. (4) The pixelclockfrequencyisprogrammable. (5) For more information,see the DSS chapterinthe AM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). Figure6-31.DSS —STN Mode

6.5.2.2 DSS —ParallelInterface— RFBI Mode — Applications

The Remote Frame BufferInterface(RFBI) module providesthe necessarycontrolsignalsand data (MIPI® DBI 2.0typeB protocol)tointerfacetotheLCD driveroftheLCD panel. Table 6-40 and Table 6-41 assume testingover the recommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-32throughFigure6-34). Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 205 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-39.DSS Timing Conditions—RFBI Mode —MIPIDBI 2.0-LCD Panel(2) TIMING CONDITION PARAMETER VALUE UNIT MIN MAX InputConditions tR Inputsignalrisetime 15 ns tF Inputsignalfalltime 15 ns Output Condition C LOAD Outputloadcapacitance(1) 30 pF (1) Bufferstrengthconfiguration:LB0 = 1. (2) Forany informationregardingtheRFBI registersconfiguration,see DisplaySubsystem /theDisplaySubsystem Environment/LCD Support/ParallelInterface/ParallelInterfaceinRFBI Mode (MIPIDBI Protocol)/TransactionTimingDiagramssectionofthe AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table6-40.DSS Timing Requirements—RFBI Mode —MIPIDBI 2.0-LCD Panel NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX DR0 tsu(dV-rdH) Setuptime,inputdatarfbi_da[15:0]validtooutput 7.3 6.3 ns readenablerfbi_rdhigh DR1 th(rdH-dIV) Holdtime,outputreadenablerfbi_rdhightoinputdata 10.6 9.6 ns rfbi_da[15:0]invalid td(Datasampled) Inputdatarfbi_da[15:0]sampled attheend ofthe N (1) N (1) ns accesstime (1) N = (AccessTime)*(TimeParaGranularity+ 1)*L4CLK Table6-41.DSS SwitchingCharacteristics— RFBI Mode — MIPIDBI 2.0-LCD Panel PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX tw(wrH) Pulseduration,outputwriteenablerfbi_wrhigh A(1) A(1) ns tw(wrL) Pulseduration,outputwriteenablerfbi_wrlow B(2) B(2) ns td(a0-wrL) Delaytime,outputcommand/data controlrfbi_a0transitionto C (3) C (3) ns outputwriteenablerfbi_wrlow td(wrH-a0) Delaytime,outputwriteenablerfbi_wrhightooutput D (4) D (4) ns command/data controlrfbi_a0transition td(csx-wrL) Delaytime,outputchipselectrfbi_csx(14)lowtooutputwrite E(5) E(5) ns enablerfbi_wrlow td(wrH-csxH) Delaytime,outputwriteenablerfbi_wrhightooutputchipselect F(6) F(6) ns rfbi_csx(14)high td(dV) Outputdatarfbi_da[15:0]valid G (7) G (7) ns td(a0H-rdL) Delaytime,outputcommand/data controlrfbi_a0hightooutput H (8) H (8) ns readenablerfbi_rdlow td(rdlH-a0) Delaytime,outputreadenablerfbi_rdhightooutput I(9) I(9) ns command/data controlrfbi_a0transition tw(rdH) Pulseduration,outputreadenablerfbi_rdhigh J(10) J(10) ns tw(rdL) Pulseduration,outputreadenablerfbi_rdlow K(11) K(11) ns td(rdL-csxL) Delaytime,outputreadenablerfbi_rdlowtooutputchipselect L(12) L(12) ns rfbi_csx(14)low td(rdH-csxH) Delaytime,outputreadenablerfbi_rdhightooutputchipselect M (13) M (13) ns rfbi_csx(14)high tR(wr) Risetime,outputwriteenablerfbi_wr 10 10 ns tF(wr) Falltime,outputwriteenablerfbi_wr 10 10 ns tR(a0) Risetime,outputcommand/data controlrfbi_a0 10 10 ns tF(a0) Falltime,outputcommand/data controlrfbi_a0 10 10 ns tR(csx) Risetime,outputchipselectrfbi_csx(14) 10 10 ns

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rfbi_a0 rfbi_csx rfbi_wr rfbi_da[n:0] rfbi_rd rfbi_te_vsync[1:0] rfbi_hsync[1:0] DA T A0 DA T A1 CsOnTime CsOffTime WeOnTime WeOffTime CsOnTime CsOffTime WeOnTime WeOffTime CsPulseWidth WeCycleTime WeCycleTime SWPS038-057 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-41.DSS SwitchingCharacteristics— RFBI Mode — MIPIDBI 2.0-LCD Panel (continued) PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX tF(csx) Falltime,outputchipselectrfbi_csx(14) 10 10 ns tR(d) Risetime,outputdatarfbi_da[15:0] 10 10 ns tF(d) Falltime,outputdatarfbi_da[15:0] 10 10 ns tR(rd) Risetime,outputreadenablerfbi_rd 10 10 ns tF(rd) Falltime,outputreadenablerfbi_rd 10 10 ns (1) A = (WECycleTime – WEOffTime) *(TimeParaGranularity+ 1)*L4CLK (2) B = (WEOffTime – WEOntime) *(TimeParaGranularity+ 1)*L4CLK (3) C = WEOnTime *(TimeParaGranularity+ 1)*L4CLK (4) D = (WECycleTime + CSPulseWidth– WEOffTime) *(TimeParaGranularity+ 1)*L4CLK ifmode WritetoRead orRead toWriteis enabled (5) E = (WEOnTime – CSOnTime) *(TimeParaGranularity+ 1)*L4CLK (6) F = (CSOffTime– WEOffTime) *(TimeParaGranularity+ 1)*L4CLK (7) G = WECycleTime *(TimeParaGranularity+ 1)*L4CLK (8) H = REOnTime *(TimeParaGranularity+ 1)*L4CLK (9) I= (RECycleTime+ CSPulseWidth– REOffTime)*(TimeParaGranularity+ 1)*L4CLK ifmode WritetoRead orRead toWriteis enabled (10)J = (RECycleTime– REOffTime)*(TimeParaGranularity+ 1)*L4CLK (11)K = (REOffTime– REOntime) *(TimeParaGranularity+ 1)*L4CLK (12)L = (REOnTime – CSOnTime) *(TimeParaGranularity+ 1)*L4CLK (13)M = (CSOffTime– REOffTime)*(TimeParaGranularity+ 1)*L4CLK (14)Inrfbi_csx,x isequalto0 or1. (1) Inrfbi_csx,x isequalto0 or1. (2) rfbi_data[n:0],n up to15 (3) For more information,see the DSS chapterinthe AM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). Figure6-32.DSS —RFBI Mode —MIPIDBI 2.0—LCD Panel—Command /Data Write Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 207 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

rfbi_a0 rfbi_csx rfbi_rd rfbi_da[n:0] rfbi_wr rfbi_te_vsync[1:0] rfbi_hsync[1:0] DA T A0 DA T A1 CsOnTime ReOffTime CsPulseWidth AccessTime CsOnTime CsOffTime ReOnTime ReOffTime AccessTime ReCycleTime DR1 SWPS038-058 ReCycleTime CsOffTime ReOnTime DR0 rfbi_a0 rfbi_csx rfbi_wr rfbi_rd rfbi_da[n:0] rfbi_te_vsync[1:0] rfbi_hsync[1:0] WRITE READ WRITE CsOnTime CsOffTime WEOffTime WECycleTime CsPulseWidth ReCycleTime AccessTime CsOnTime CsOffTime ReOffTime CsPulseWidth CsOnTime WEOffTime CsOffTime WECycleTime SWPS038-059 WEOnTime ReOnTime WEOnTime DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Inrfbi_csx,x isequalto0 or1. (2) rfbi_data[n:0],n up to15 (3) For more information,see the DSS chapterinthe AM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). Figure6-33.DSS —RFBI Mode —MIPIDBI 2.0—LCD Panel—Command /Data Read (1) Inrfbi_csx,x isequalto0 or1. (2) rfbi_data[n:0],n up to15 (3) For more information,see the DSS chapterinthe AM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). Figure6-34.DSS —RFBI Mode —MIPIDBI 2.0— LCD Panel—Command /Data WritetoRead and Read to WriteModes

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 6.5.2.2.2DSS —ParallelInterface—RFBI Mode —Pico DLP The Remote Frame BufferInterface(RFBI)module can providealsothe necessarycontrolsignalsand data to interfaceto the Pico DLP driverof the Pico DLP panel.Table 6-42 assumes testingover the recommended operatingconditionsand electricalcharacteristicconditionsbelow(seeFigure6-35). Table6-42.DSS Timing Conditions—RFBI Mode —Pico DLP TIMING CONDITION PARAMETER VALUE UNIT MIN MAX Output Condition C LOAD Outputloadcapacitance(1) 5 pF (1) Bufferstrengthconfiguration:LB0 = 0 To use PicoDLP application,RFBI registermust be configuredas shown inTable6-43: Table6-43.DSS RegisterConfiguration—RFBI Mode —Pico DLP DESCRIPTION REGISTER AND BIT FIELD(1) BIT VALUES Selectionparallelmode RFBI_CONFIGi and [1:0] 0b11:16-bitparalleloutputinterface ParallelMode selected Time Granularity(multipliessignaltiming RFBI_CONFIGi [4] 0b0:x2 latencydisable latenciesby 2). andTimeGranularity CS signalassertiontimefromStartAccess RFBI_ONOFF_TIMEi and [3:0] 0b0000 Time CSOnTime CS signalde-assertiontimefromStartAccess RFBI_ONOFF_TIMEi and [9:4] 0b000100:4 cycles Time CSOffTime WE signalassertiontimefromStartAccess RFBI_ONOFF_TIMEi and [13:10] 0b0000 Time WEOnTime WE signalde-assertiontimefromStartAccess RFBI_ONOFF_TIMEi and [19:14] 0b000010:2 cycles Time WEOffTime RE signalassertiontimefromStartAccess RFBI_ONOFF_TIMEi and [23:20] 0b0000 Time REOnTime RE signalde-assertiontimefromStartAccess RFBI_ONOFF_TIMEi and [29:24] 0b000000 Time REOffTime Writecycletime RFBI_CYCLE_TIMEi and [5:0] 0b000100:4 cycles WECycleTime Read cycletime RFBI_CYCLE_TIMEi and [11:6] 0b000000 ReCycleTime CS pulsewidth RFBI_CYCLE_TIMEi and [17:12] 0b000000 CSPulseWidth Read toWriteCS pulsewidthenable RFBI_CYCLE_TIMEi and [18] 0b0 RWEnable Read toRead CS pulsewidthenable RFBI_CYCLE_TIMEi and [19] 0b0 RREnable WritetoWriteCS pulsewidthenable RFBI_CYCLE_TIMEi and [20] 0b0 WWEnable WritetoRead CS pulsewidthenable RFBI_CYCLE_TIMEi and [21] 0b0 WREnable From StartAccess Time toCLK risingedge RFBI_CYCLE_TIMEi and [27:22] 0b000000 used forthefirstdatacapture AccessTime (1) iisequalto0 or1.Formore information,see theDSS chapterintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 209 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-44.DSS SwitchingCharacteristics—RFBI Mode —Pico DLP (15)(17)(18) PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX tw(wrH) Pulseduration,outputwriteenablerfbi_wrhigh A(1) A(1) ns tw(wrL) Pulseduration,outputwriteenablerfbi_wrlow B(2) B(2) ns td(a0-wrL) Delaytime,outputcommand/data controlrfbi_a0 C (3) C (3) ns transitiontooutputwriteenablerfbi_wrlow td(wrH-a0) Delaytime,outputwriteenablerfbi_wrhightooutput D (4) D (4) ns command/data controlrfbi_a0transition td(csx-wrL) Delaytime,outputchipselectrfbi_csx(14)lowtooutput E(5) E(5) ns writeenablerfbi_wrlow td(wrH-csxH) Delaytime,outputwriteenablerfbi_wrhightooutput F(6) F(6) ns chipselectrfbi_csx(14)high td(dataV) Outputdatarfbi_da15:0valid G (7) G (7) ns td(Skew) Skew between outputwriteenablefallingrfbi_wrand 15.5 15.5 ns outputdatarfbi_da15:0highorlow td(a0H-rdL) Delaytime,outputcommand/data controlrfbi_a0highto H (8) H (8) ns outputreadenablerfbi_rdlow td(rdlH-a0) Delaytime,outputreadenablerfbi_rdhightooutput I(9) I(9) ns command/data controlrfbi_a0transition tw(rdH) Pulseduration,outputreadenablerfbi_rdhigh J(10) J(10) ns tw(rdL) Pulseduration,outputreadenablerfbi_rdlow K(11) K(11) ns td(rdL-csxL) Delaytime,outputreadenablerfbi_rdlowtooutputchip L(12) L(12) ns selectrfbi_csx(14)low td(rdL-csxH) Delaytime,outputreadenablerfbi_rdlowtooutputchip M (13) M (13) ns selectrfbi_csx(14)high tR(wr) Risetime,outputwriteenablerfbi_wr 7 7 ns tF(wr) Falltime,outputwriteenablerfbi_wr 7 7 ns tR(a0) Risetime,outputcommand/data controlrfbi_a0 7 7 ns tF(a0) Falltime,outputcommand/data controlrfbi_a0 7 7 ns tR(csx) Risetime,outputchipselectrfbi_csx(14) 7 7 ns tF(csx) Falltime,outputchipselectrfbi_csx(14) 7 7 ns tR(d) Risetime,outputdatarfbi_da15:0 7 7 ns tF(d) Falltime,outputdatarfbi_da15:0 7 7 ns tR(rd) Risetime,outputreadenablerfbi_rd 7 7 ns tF(rd) Falltime,outputreadenablerfbi_rd 7 7 ns CsOnTime CS signalassertiontimefromStartAccess Time - 0(19) ns RFBI_ONOFF_TIMEi Register CsOffTime CS signalde-assertiontimefromStartAccess Time - 40(19) ns RFBI_ONOFF_TIMEi Register WeOnTime WE signalassertiontimefromStartAccess Time - 0(19) ns RFBI_ONOFF_TIMEi Register WeOffTime WE signalde-assertiontimefromStartAccess Time - 20(19) ns RFBI_ONOFF_TIMEi Register ReOnTime RE signalassertiontimefromStartAccess Time - - ns RFBI_ONOFF_TIMEi Register ReOffTime RE signalde-assertiontimefromStartAccess Time - - ns RFBI_ONOFF_TIMEi Register WeCycleTime Writecycletime-RFBI_CYCLE_TIMEi Register 40(19) ns ReCycleTime Read cycletime-RFBI_CYCLE_TIMEi Register - ns CsPulseWidth CS pulsewidth-RFBI_CYCLE_TIMEi Register 0(19) ns

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rfbi_hsync[1:0] rfbi_a0 rfbi_csx rfbi_wr rfbi_da[n:0] rfbi_rd rfbi_te_vsync[1:0] DA T A0 DA T A1 CsOnTime CsOffTime WeOffTime CsOnTime CsOffTime WeOnTime WeOffTime CsPulseWidth WeCycleTime WeOnTime WeCycleTime DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) A = (WECycleTime – WEOffTime) *(TimeParaGranularity+ 1)*L4CLK (2) B = (WEOffTime – WEOntime) *(TimeParaGranularity+ 1)*L4CLK (3) C = WEOnTime *(TimeParaGranularity+ 1)*L4CLK (4) D = (WECycleTime + CSPulseWidth– WEOffTime) *(TimeParaGranularity+ 1)*L4CLK ifmode WritetoRead orRead toWriteis enabled. (5) E = (WEOnTime – CSOnTime) *(TimeParaGranularity+ 1)*L4CLK (6) F = (CSOffTime– WEOffTime) *(TimeParaGranularity+ 1)*L4CLK (7) G = WECycleTime *(TimeParaGranularity+ 1)*L4CLK (8) H = REOnTime *(TimeParaGranularity+ 1)*L4CLK (9) I= (RECycleTime+ CSPulseWidth– REOffTime)*(TimeParaGranularity+ 1)*L4CLK ifmode WritetoRead orRead toWriteis enabled. (10)J = (RECycleTime– REOffTime)*(TimeParaGranularity+ 1)*L4CLK (11)K = (REOffTime– REOntime) *(TimeParaGranularity+ 1)*L4CLK (12)L = (REOnTime – CSOnTime) *(TimeParaGranularity+ 1)*L4CLK (13)M = (CSOffTime– REOffTime)*(TimeParaGranularity+ 1)*L4CLK (14)Inrfbi_csx,x isequalto0 or1. (15)See Section4.3.4,ProcessorClocks. (16)16-bitparalleloutputinterfaceisselectedinDSS register. (17)AtOPP100, L4 clockis100 MHz and atOPP50, L4 clockis50 MHz. (18)rfbi_wrmust be at25 MHz. (19)These valuesarecalculatedby thefollowingformula:RFBI Register(Value)*L4 Clock(ns). Figure6-35.DSS —RFBI Mode —Pico DLP —Command /Data Write(1)(2) (1) Inrfbi_csx,x isequalto0 or1. (2) rfbi_da[n:0],n up to15 Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 211 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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6.6 SerialCommunications Interfaces

6.6.1 MultichannelBufferedSerialPort(McBSP)

For more information,see Multi-ChannelBufferedSerialPort chapterof the AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). The MultichannelBufferedSerialPort(McBSP) providesa fullduplexdirectserialinterfacebetween the chipand otherdevicesina system such as otherapplicationchips,codecs.Itcan accommodate a wide rangeofperipheralsand clockedframeorientedprotocols(I2S,PCM, T )due toitshighlevelofversatility. McBSP may supporttwo typesofdatatransferatthesystemlevel:

• The fullcyclemode, forwhich one clockperiodisused totransferthedata,generatedon one edge and capturedon thesame edge (oneclockperiodlater).
• The halfcyclemode, forwhich one halfclockperiodisused totransferthedata,generatedon one edge and capturedon the oppositeedge (one halfclockperiodlater).Note thata new data is generatedonlyeveryclockperiod,whichsecurestherequiredholdtime. The interfaceclock(clkx/clkr)activationedge (data/framesync captureand generation)has to be configuredaccordinglywiththe externalperipheral(activationedge capability)and the type of data transferrequiredatthesystemlevel. Dependingon thenumber ofpins,McBSP supportseither:
• 6-pinmode: dx and dras datapins;clkx,clkr,fsx,and fsras controlpins
• 4-pinmode: dx and dr as data pins;clkxand fsxpinsas controlpins.The clkxand fsxpinsare internallyloopedback,viasoftwareconfiguration,respectivelyto the clkrand fsrinternalsignalsfor datareceive. McBSP1 supportsthe6-pinmode. McBSP2, 3,4,and 5 supportonlythe4-pinmode. The followingsectionsdescribethetimingcharacteristicsforapplicationsinnormalmode (thatis,McBSPx connectedtoone peripheral)and T applicationsinmultipointmode.

6.6.1.1 McBSP Timing Conditions—Normal Mode

Table6-46throughTable6-70assume testingovertherecommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-36throughFigure6-43). Table6-45.McBSP Timing Conditions—Normal Mode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 2 ns tF Inputsignalfalltime 2 ns Output Condition C LOAD Outputloadcapacitance(1) 10 pF (1) Bufferstrengthconfiguration: – McBSP4 -Set#1:LB0 = 1. – Otherwise:LB0 = 0.

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-46.McBSP Output Clock Characteristics—Normal Mode (4) PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX McBSP1 tc(CLK) Cycletime,mcbsp1_clkx(multiplexingmode 0)/ 48 24 MHz mcbsp1_clkr(multiplexingmode 0 & 2) McBSP2 tc(CLK) Cycletime,mcbsp2_clkx(multiplexingmode 0) 48 24 MHz McBSP3 tc(CLK) Cycletime,mcbsp3_clkx IO set1 32 16 MHz (multiplexing mode 0) IO set2 48 24 (multiplexing mode 1) IO set3 48 24 (multiplexing mode 2) McBSP4 tc(CLK) Cycletime,mcbsp4_clkx IO set1 48 16 MHz (multiplexing mode 0) IO set3 32 16 (multiplexing mode 2) McBSP5 tc(CLK) Cycletime,mcbsp5_clkx IO set2 32 16 MHz (multiplexing mode 1) tW(CLKH) Typicalpulseduration,mcbsp1_clkr/mcbspx_clkxhigh(2) 0.5*P(1) 0.5*P(1) ns tW(CLKL) Typicalpulseduration,mcbsp1_clkr/mcbspx_clkxlow(2) 0.5*P(1) 0.5*P(1) ns tdc(CLK) Dutycycleerror,mcbsp1_clkr/mcbspx_clkx(2) –0.75 0.75 –0.75 0.75 ns Jitter,mcbsp1_clkr/mcbspx_clkx(3)/mcbsp_clks -0.40 0.40 -0.40 0.40 ns (1) P = mcbspy_clkx(2)ormcbsp1_clkroutputclockperiodinns (2) Inmcbspy,y isequalto1,2,3,4,or5. (3) Inmcbspx,x identifiestheMcBSP number:1,2,3,4,or5. (4) See Section4.3.4,ProcessorClocks. 6.6.1.1.1RisingEdge as ActivationMode Table6-47.McBSP1, 2,and 3 (Sets#2 and #3)Timing Requirements—RisingEdge and Receive Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKAE) Setuptime,mcbspx_dr validbefore Master 4.36 8.63 ns mcbsp1_clkr/mcbspx_clkxactiveedge Slave 3.67 7.94 ns B4 th(CLKAE-DRV) Holdtime,mcbspx_dr validafter Master 1.01 1.01 ns mcbsp1_clkr/mcbspx_clkxactiveedge Slave 0.4 0.4 ns B5 tsu(FSV-CLKAE) Setuptime,mcbsp1_fsr/mcbspx_fsxvalidbefore 3.67 7.94 ns mcbsp1_clkr/mcbspx_clkxactiveedge B6 th(CLKAE-FSV) Holdtime,mcbsp1_fsr/mcbspx_fsxvalidafter 0.5 0.5 ns mcbsp1_clkr/mcbspx_clkxactiveedge Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 213 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Inmcbspx,x identifiestheMcBSP number:1,2,or3.Note thatfortheMcBSP3, thesetimingsconcernonlySet#2 (multiplexingmode on UART pins)and Set#3 (multiplexingmode on McBSP1 pins). (2) See Section4.3.4,ProcessorClocks. Table6-48.McBSP1, 2,and 3 (Sets#2 and #3)SwitchingCharacteristics—RisingEdge and Receive Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKAE-FSV) Delaytime,mcbsp1_clkr/mcbspx_clkxactiveedge to 0.7 14.79 0.7 29.58 ns mcbsp1_fsr/mcbspx_fsxvalid (1) Inmcbspx,x identifiestheMcBSP number:1,2,or3.Note thatfortheMcBSP3, thesetimingsconcernonlySet#2 (multiplexingmode on UART pins)and Set#3 (multiplexingmode on McBSP1 pins). (2) See Section4.3.4,ProcessorClocks. Table6-49.McBSP4 (Set#1)Timing Requirements—RisingEdge and Receive Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKXAE) Setuptime,mcbspx_dr validbefore Master 2.87 8.63 ns mcbspx_clkxactiveedge Slave 3.67 7.94 ns B4 th(CLKXAE-DRV) Holdtime,mcbspx_dr validafter Master 1.01 1.01 ns mcbspx_clkxactiveedge Slave 0.4 0.4 ns B5 tsu(FSXV-CLKXAE) Setuptime,mcbspx_fsxvalidbeforemcbspx_clkx 3.67 7.94 ns activeedge B6 th(CLKXAE-FSXV) Holdtime,mcbspx_fsxvalidaftermcbspx_clkxactive 0.5 0.5 ns edge (1) Inmcbspx,x identifiestheMcBSP number:4.Note thatfortheMcBSP4, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP4 isalsomultiplexedon GPMC pins(Set#2):thecorrespondingtimingsarespecifiedinTable6-51and Table6-52. (2) See Section4.3.4,ProcessorClocks. Table6-50.McBSP4 (Set#1)SwitchingCharacteristics—RisingEdge and Receive Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delaytime,mcbspx_clkxactiveedge tomcbspx_fsx 0.7 16.56 0.7 33.12 ns valid (1) Inmcbspx,x identifiestheMcBSP number:4.Note thatfortheMcBSP4, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP4 isalsomultiplexedon GPMC pins(Set#2):thecorrespondingtimingsarespecifiedinTable6-51and Table6-52. (2) See Section4.3.4,ProcessorClocks. Table6-51.McBSP3 (Set#1),4 (Set#2),and 5 Timing Requirements—RisingEdge and Receive Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKXAE) Setuptime,mcbspx_dr validbefore Master 6.49 12.90 ns mcbspx_clkxactiveedge Slave 5.80 12.21 ns B4 th(CLKXAE-DRV) Holdtime,mcbspx_dr validafter Master 1.01 1.01 ns mcbspx_clkxactiveedge Slave 0.4 0.4 ns B5 tsu(FSXV-CLKXAE) Setuptime,mcbspx_fsxvalidbeforemcbspx_clkx 5.81 12.21 ns activeedge B6 th(CLKXAE-FSXV) Holdtime,mcbspx_fsxvalidaftermcbspx_clkxactive 0.5 0.5 ns edge

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mcbspx_clkr mcbspx_fsr mcbspx_dr D7 D6 D5 B2 B2 B3 B4 SWPS038-063 mcbspx_clkr mcbspx_fsr mcbspx_dr D7 D6 D5 B3 B4 B5 B6 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) Inmcbspx,x identifiestheMcBSP number:3,4,or5.Note thatfortheMcBSP3, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP3 isalsomultiplexedon UART pins(Set#2)and on McBSP1 pins(Set#3):thecorrespondingtimingsare specifiedinTable6-47and Table6-48. FortheMcBSP4, thesetimingsconcernonlySet#2 (multiplexingmode on GPMC pins). (2) See Section4.3.4,ProcessorClocks. Table6-52.McBSP3 (Set#1),4 (Set#2),and 5 SwitchingCharacteristics—RisingEdge and Receive Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delaytime,mcbspx_clkxactiveedge tomcbspx_fsx 0.7 22.18 0.7 44.37 ns valid (1) Inmcbspx,x identifiestheMcBSP number:3,4,or5.Note thatfortheMcBSP3, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP3 isalsomultiplexedon UART pins(Set#2)and on McBSP1 pins(Set#3):thecorrespondingtimingsare specifiedinTable6-47and Table6-48. FortheMcBSP4, thesetimingsconcernonlySet#2 (multiplexingmode on GPMC pins) (2) See Section4.3.4,ProcessorClocks. (1) Inmcbspx,x identifiestheMcBSP number:1,2,3,4,or5. Figure6-36.McBSP RisingEdge Receive Timing inMaster Mode (1) Inmcbspx,x identifiestheMcBSP number:1,2,3,4,or5. Figure6-37.McBSP RisingEdge Receive Timing inSlaveMode Table6-53.McBSP1, 2,and 3 (Sets#2 and #3)Timing Requirements—RisingEdge and TransmitMode (1) (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B5 tsu(FSXV-CLKXAE) Setuptime,mcbspx_fsxvalidbeforemcbspx_clkx 3.67 7.94 ns activeedge B6 th(CLKXAE-FSXV) Holdtime,mcbspx_fsxvalidaftermcbspx_clkxactive 0.5 0.5 ns edge Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 215 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Inmcbspx,x identifiestheMcBSP number:1,2,or3.Note thatfortheMcBSP3, thesetimingsconcernonlySet#2 (multiplexingmode on UART pins)and Set#3 (multiplexingmode on McBSP1 pins). (2) See Section4.3.4,ProcessorClocks. Table6-54.McBSP1, 2,and 3 (Sets#2 and #3)SwitchingCharacteristics—RisingEdge and Transmit Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delaytime,mcbspx_clkxactiveedge tomcbspx_fsx 0.7 14.79 0.7 29.58 ns valid B8 td(CLKXAE-DXV) Delaytime,mcbspx_clkxactiveedge to Master 0.6 14.79 0.6 29.58 ns mcbspx_dx valid Slave 0.6 13.89 0.6 28.68 ns (1) Inmcbspx,x identifiestheMcBSP number:1,2,or3.Note thatfortheMcBSP3, thesetimingsconcernonlySet#2 (multiplexingmode on UART pins)and Set#3 (multiplexingmode on McBSP1 pins). (2) See Section4.3.4,ProcessorClocks. Table6-55.McBSP4 (Set#1)Timing Requirements—RisingEdge and TransmitMode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B5 tsu(FSXV-CLKXAE) Setuptime,mcbspx_fsxvalidbeforemcbspx_clkx 3.67 7.94 ns activeedge B6 th(CLKXAE-FSXV) Holdtime,mcbspx_fsxvalidaftermcbspx_clkxactive 0.5 0.5 ns edge (1) Inmcbspx,x identifiestheMcBSP number:4.Note thatfortheMcBSP4, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP4 isalsomultiplexedon GPMC pins(Set#2):thecorrespondingtimingsarespecifiedinTable6-57and Table6-58. (2) See Section4.3.4,ProcessorClocks. Table6-56.McBSP4 (Set#1)SwitchingCharacteristics—RisingEdge and TransmitMode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delaytime,mcbspx_clkxactiveedge tomcbspx_fsx 0.7 16.56 0.7 33.12 ns valid B8 td(CLKXAE-DXV) Delaytime,mcbspx_clkxactiveedge to Master 0.6 16.56 0.6 33.12 ns mcbspx_dx valid Slave 0.6 17.15 0.6 32.22 ns (1) Inmcbspx,x identifiestheMcBSP number:4.Note thatfortheMcBSP4, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP4 isalsomultiplexedon GPMC pins(Set#2):thecorrespondingtimingsarespecifiedinTable6-57and Table6-58. (2) See Section4.3.4,ProcessorClocks. Table6-57.McBSP3 (Set#1),4 (Set#2),and 5 Timing Requirements—RisingEdge and TransmitMode (1) (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B5 tsu(FSXV-CLKXAE) Setuptime,mcbspx_fsxvalidbeforemcbspx_clkx 5.81 12.21 ns activeedge B6 th(CLKXAE-FSXV) Holdtime,mcbspx_fsxvalidaftermcbspx_clkxactive 0.5 0.5 ns edge (1) Inmcbspx,x identifiestheMcBSP number:3,4,or5.Note thatfortheMcBSP3, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP3 isalsomultiplexedon UART pins(Set#2)and on McBSP1 pins(Set#3):thecorrespondingtimingsare specifiedinTable6-53and Table6-54. FortheMcBSP4, thesetimingsconcernonlySet#2 (multiplexingmode on GPMC pins). (2) See Section4.3.4,ProcessorClocks.

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mcbspx_clkx mcbspx_fsx mcbspx_dx D7 D6 D5 B2 B2 SWPS038-065 mcbspx_clkx mcbspx_fsx mcbspx_dx D7 D6 D5 B5 B6 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-58.McBSP3 (Set#1),4 (Set#2),and 5 SwitchingCharacteristics—RisingEdge and Transmit Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delaytime,mcbspx_clkxactiveedge tomcbspx_fsx 0.7 22.18 0.7 44.37 ns valid B8 td(CLKXAE-DXV) Delaytime,mcbspx_clkxactiveedge to Master 0.6 21.28 0.6 43.47 ns mcbspx_dx valid Slave 0.6 21.28 0.6 43.47 ns (1) Inmcbspx,x identifiestheMcBSP number:3,4,or5.Note thatfortheMcBSP3, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP3 isalsomultiplexedon UART pins(Set#2)and on McBSP1 pins(Set#3):thecorrespondingtimingsare specifiedinTable6-53and Table6-54. FortheMcBSP4, thesetimingsconcernonlySet#2 (multiplexingmode on GPMC pins). (2) See Section4.3.4,ProcessorClocks. (1) Inmcbspx,x identifiestheMcBSP number:1,2,3,4,or5. Figure6-38.McBSP RisingEdge TransmitTiming inMaster Mode (1) Inmcbspx,x identifiestheMcBSP number:1,2,3,4,or5. Figure6-39.McBSP RisingEdge TransmitTiming inSlaveMode 6.6.1.1.2FallingEdge as ActivationEdge Table6-59.McBSP1, 2,3 (Sets#2 and #3)Timing Requirements—FallingEdge and Receive Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKAE) Setuptime,mcbspx_dr validbefore Master 4.36 8.63 ns mcbsp1_clkr/mcbspx_clkxactiveedge Slave 3.67 7.94 ns B4 th(CLKAE-DRV) Holdtime,mcbspx_dr validafter Master 1.01 1.01 ns mcbsp1_clkr/mcbspx_clkxactiveedge Slave 0.4 0.4 ns B5 tsu(FSV-CLKAE) Setuptime,mcbsp1_fsr/mcbspx_fsxvalidbefore 3.7 7.94 ns mcbsp1_clkr/mcbspx_clkxactiveedge B6 th(CLKAE-FSV) Holdtime,mcbsp1_fsr/mcbspx_fsxvalidafter 0.5 0.5 ns mcbsp1_clkr/mcbspx_clkxactiveedge Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 217 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Inmcbspx,x identifiestheMcBSP number:1,2,or3.Note thatfortheMcBSP3, thesetimingsconcernonlySet#2 (multiplexingmode on UART pins)and Set#3 (multiplexingmode on McBSP1 pins). (2) See Section4.3.4,ProcessorClocks. Table6-60.McBSP1, 2,and 3 (Sets#2 and #3)SwitchingCharacteristics—FallingEdge and Receive Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKAE-FSV) Delaytime,mcbsp1_clkr/mcbspx_clkxactiveedge to 0.7 14.79 0.7 29.58 ns mcbsp1_fsr/mcbspx_fsxvalid (1) Inmcbspx,x identifiestheMcBSP number:1,2,or3.Note thatfortheMcBSP3, thesetimingsconcernonlySet#2 (multiplexingmode on UART pins)and Set#3 (multiplexingmode on McBSP1 pins). (2) See Section4.3.4,ProcessorClocks. Table6-61.McBSP4 (Set#1)Timing Requirements—FallingEdge and Receive Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKXAE) Setuptime,mcbspx_dr validbefore Master 2.87 8.63 ns mcbspx_clkxactiveedge Slave 3.67 7.94 ns B4 th(CLKXAE-DRV) Holdtime,mcbspx_dr validafter Master 1.01 1.01 ns mcbspx_clkxactiveedge Slave 0.4 0.4 ns B5 tsu(FSXV-CLKXAE) Setuptime,mcbspx_fsxvalidbeforemcbspx_clkx 3.67 7.94 ns activeedge B6 th(CLKXAE-FSXV) Holdtime,mcbspx_fsxvalidaftermcbspx_clkxactive 0.5 0.5 ns edge (1) Inmcbspx,x identifiestheMcBSP number:4.Note thatfortheMcBSP4, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP4 isalsomultiplexedon GPMC pins(Set#2):thecorrespondingtimingsarespecifiedinTable6-63and Table6-64. (2) See Section4.3.4,ProcessorClocks. Table6-62.McBSP4 (Set#1)SwitchingCharacteristics—FallingEdge and Receive Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delaytime,mcbspx_clkxactiveedge tomcbspx_fsx 0.7 16.56 0.7 33.12 ns valid (1) Inmcbspx,x identifiestheMcBSP number:4.Note thatfortheMcBSP4, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP4 isalsomultiplexedon GPMC pins(Set#2):thecorrespondingtimingsarespecifiedinTable6-63and Table6-64. (2) See Section4.3.4,ProcessorClocks. Table6-63.McBSP3 (Set#1),4 (Set#2),and 5 Timing Requirements—FallingEdge and Receive Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B3 tsu(DRV-CLKXAE) Setuptime,mcbspx_dr validbefore Master 6.5 12.9 ns mcbspx_clkxactiveedge Slave 5.81 12.21 ns B4 th(CLKXAE-DRV) Holdtime,mcbspx_dr validafter Master 1.01 1.01 ns mcbspx_clkxactiveedge Slave 0.4 0.4 ns B5 tsu(FSXV-CLKXAE) Setuptime,mcbspx_fsxvalidbeforemcbspx_clkx 5.81 12.21 ns activeedge B6 th(CLKXAE-FSXV) Holdtime,mcbspx_fsxvalidaftermcbspx_clkxactive 0.5 0.5 ns edge

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mcbspx_clkr mcbspx_fsr mcbspx_dr D7 D6 D5 B2 B2 B3 B4 SWPS038-067 mcbspx_clkr mcbspx_fsr mcbspx_dr D7 D6 D5 B3 B4 B5 B6 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) Inmcbspx,x identifiestheMcBSP number:3,4,or5.Note thatfortheMcBSP3, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP3 isalsomultiplexedon UART pins(Set#2)and on McBSP1 pins(Set#3):thecorrespondingtimingsare specifiedinTable6-59and Table6-60. FortheMcBSP4, thesetimingsconcernonlySet#2 (multiplexingmode on GPMC pins). (2) See Section4.3.4,ProcessorClocks. Table6-64.McBSP3 (Set#1),4 (Set#2),and 5 SwitchingCharacteristics—FallingEdge and Receive Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delaytime,mcbspx_clkxactiveedge tomcbspx_fsx 0.7 22.19 0.7 44.37 ns valid (1) Inmcbspx,x identifiestheMcBSP number:3,4,or5.Note thatfortheMcBSP3, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP3 isalsomultiplexedon UART pins(Set#2)and on McBSP1 pins(Set#3):thecorrespondingtimingsare specifiedinTable6-59and Table6-60. (2) See Section4.3.4,ProcessorClocks. (1) Inmcbspx,x identifiestheMcBSP number:1,2,3,4,or5. Figure6-40.McBSP FallingEdge Receive Timing inMaster Mode (1) Inmcbspx,x identifiestheMcBSP number:1,2,3,4,or5. Figure6-41.McBSP FallingEdge Receive Timing inSlaveMode Table6-65.McBSP1, 2,and 3 (Sets#2 and #3)Timing Requirements—FallingEdge and Transmit Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B5 tsu(FSXV-CLKXAE) Setuptime,mcbspx_fsxvalidbeforemcbspx_clkx 3.67 7.94 ns activeedge B6 th(CLKXAE-FSXV) Holdtime,mcbspx_fsxvalidaftermcbspx_clkxactive 0.5 0.5 ns edge Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 219 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Inmcbspx,x identifiestheMcBSP number:1,2,or3.Note thatfortheMcBSP3, thesetimingsconcernonlySet#2 (multiplexingmode on UART pins)and Set#3 (multiplexingmode on McBSP1 pins). (2) See Section4.3.4,ProcessorClocks. Table6-66.McBSP1, 2,and 3 (Sets#2 and #3)SwitchingCharacteristics—FallingEdge and Transmit Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delaytime,mcbspx_clkxactiveedge tomcbspx_fsx 0.7 14.79 0.7 29.58 ns valid B8 td(CLKXAE-DXV) Delaytime,mcbspx_clkxactiveedge to Master 0.6 14.79 0.6 29.58 ns mcbspx_dx valid Slave 0.6 13.89 0.6 28.68 ns (1) Inmcbspx,x identifiestheMcBSP number:1,2,or3.Note thatfortheMcBSP3, thesetimingsconcernonlySet#2 (multiplexingmode on UART pins)and Set#3 (multiplexingmode on McBSP1 pins). (2) See Section4.3.4,ProcessorClocks. Table6-67.McBSP4 (Set#1)Timing Requirements—FallingEdge and TransmitMode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B5 tsu(FSXV-CLKXAE) Setuptime,mcbspx_fsxvalidbeforemcbspx_clkx 3.67 7.94 ns activeedge B6 th(CLKXAE-FSXV) Holdtime,mcbspx_fsxvalidaftermcbspx_clkxactive 0.5 0.5 ns edge (1) Inmcbspx,x identifiestheMcBSP number:4.Note thatfortheMcBSP4, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP4 isalsomultiplexedon GPMC pins(Set#2):thecorrespondingtimingsarespecifiedinTable6-69and Table6-70. (2) See Section4.3.4,ProcessorClocks. Table6-68.McBSP4 (Set#1)SwitchingCharacteristics—FallingEdge and TransmitMode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delaytime,mcbspx_clkxactiveedge tomcbspx_fsx 0.7 16.56 0.7 33.12 ns valid B8 td(CLKXAE-DXV) Delaytime,mcbspx_clkxactiveedge to Master 0.6 16.56 0.6 33.12 ns mcbspx_dx valid Slave 0.6 17.15 0.6 32.22 ns (1) Inmcbspx,x identifiestheMcBSP number:4.Note thatfortheMcBSP4, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP4 isalsomultiplexedon GPMC pins(Set#2):thecorrespondingtimingsarespecifiedinTable6-69and Table6-70. (2) See Section4.3.4,ProcessorClocks. Table6-69.McBSP3 (Set#1),4 (Set#2),and 5 Timing Requirements—FallingEdge and TransmitMode (1) (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B5 tsu(FSXV-CLKXAE) Setuptime,mcbspx_fsxvalidbeforemcbspx_clkx 5.81 12.21 ns activeedge B6 th(CLKXAE-FSXV) Holdtime,mcbspx_fsxvalidaftermcbspx_clkxactive 0.5 0.5 ns edge (1) Inmcbspx,x identifiestheMcBSP number:3,4,or5.Note thatfortheMcBSP3, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP3 isalsomultiplexedon UART pins(Set#2)and on McBSP1 pins(Set#3):thecorrespondingtimingsare specifiedinTable6-66and Table6-67. FortheMcBSP4, thesetimingsconcernonlySet#2 (multiplexingmode on GPMC pins). (2) See Section4.3.4,ProcessorClocks.

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mcbspx_clkx mcbspx_fsx mcbspx_dx D7 D6 D5 B2 B2 SWPS038-069 mcbspx_clkx mcbspx_fsx mcbspx_dx D7 D6 D5 B5 B6 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-70.McBSP3 (Set#1),4 (Set#2),and 5 SwitchingCharacteristics—FallingEdge and Transmit Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B2 td(CLKXAE-FSXV) Delaytime,mcbspx_clkxactiveedge tomcbspx_fsx 0.7 22.18 0.7 44.37 ns valid B8 td(CLKXAE-DXV) Delaytime,mcbspx_clkxactiveedge to Master 0.6 21.28 0.6 43.47 ns mcbspx_dx valid Slave 0.6 21.28 0.6 43.47 ns (1) Inmcbspx,x identifiestheMcBSP number:3,4,or5.Note thatfortheMcBSP3, thesetimingsconcernonlySet#1:multiplexingmode by default.The McBSP3 isalsomultiplexedon UART pins(Set#2)and on McBSP1 pins(Set#3):thecorrespondingtimingsare specifiedinTable6-66and Table6-67. FortheMcBSP4, thesetimingsconcernonlySet#2 (multiplexingmode on GPMC pins). (2) See Section4.3.4,ProcessorClocks. (1) Inmcbspx,x identifiestheMcBSP number:1,2,3,4,or5. Figure6-42.McBSP FallingEdge TransmitTiming inMaster Mode (1) Inmcbspx,x identifiestheMcBSP number:1,2,3,4,or5. Figure6-43.McBSP FallingEdge TransmitTiming inSlaveMode

6.6.1.2 McBSP inTDM —MultipointMode (McBSP3)

For T applicationinmultipointmode, theprocessorisconsideredas a slave.Table6-72 and Table6-73 assume testingovertheoperatingconditionsand electricalcharacteristicconditionsdescribedbelow. Table6-71.McBSP3 (Set#3)Timing Conditions—T MultipointMode (1) TIMING CONDITION PARAMETER VALUE UNIT MIN MAX InputConditions tR Inputsignalrisetime 1.0 8.5 ns tF Inputsignalfalltime 1.0 8.5 ns Output Condition C LOAD Outputloadcapacitance(2) 40 pF (1) ForMcBSP3, thesetimingsconcernonlySet#3 (multiplexingmode inMcBSP1 pins) (2) The loadsettingoftheIO buffer:LB0 = 0. Table6-72.McBSP3 (Set#3)Timing Requirements—T MultipointMode (4) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX 1 /tc(clkxH) Frequency,inputclockmcbsp3_clkx 6 6 MHz Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 221 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-72.McBSP3 (Set#3)Timing Requirements—T MultipointMode (4) (continued) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX tw(clkxH) Pulseduration,inputclockmcbsp3_clkxhigh 0.5P(1) 0.5P(1) ns tw(clkxL) Pulseduration,inputclockmcbsp3_clkxlow 0.5P(1) 0.5P(1) ns tdc(clkx) Dutycycleerror,inputclockmcbsp3_clkx –8.14 8.14 –8.14 8.14 ns B3(3) tsu(drV-clkxAE) Setuptime,inputdatamcbsp3_dr validbeforeinput 9 9 ns clockmcbsp3_clkxactiveedge B4(3) th(clkxAE-drV) Holdtime,inputdatamcbsp3_dr validafterinputclock 2.4 2.4 ns mcbsp3_clkxactiveedge B5(3) tsu(fsxV-clkxAE) Setuptime,inputframesynchronizationmcbsp3_fsx 9 9 ns validbeforeinputclockmcbsp3_clkxactiveedge B6(3) th(clkxAE-fsxV) Holdtime,inputframesynchronizationmcbsp3_fsx 2.4 2.4 ns validafterinputclockmcbsp3_clkxactiveedge (1) P = inputclockmcbsp3_clkxperiodinns (2) ForMcBSP3, thesetimingsconcernonlySet#3 (multiplexingmode inMcBSP1 pins). (3) See Section6.6.1.1forcorrespondingfigures. (4) See Section4.3.4,ProcessorClocks. Table6-73.McBSP3 (Set#3)SwitchingCharacteristics—T MultipointMode (1) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX B8(2) td(clkxAE-dxV) Delaytime,mcbsp3_clkxactiveedge tooutputdata 0.6 15.89 0.6 28.68 ns mcbsp3_dx valid (1) ForMcBSP3, thesetimingsconcernonlySet#3 (multiplexingmode inMcBSP1 pins). (2) See Section6.6.1.1forcorrespondingfigures.

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6.6.2 MultichannelSerialPortInterface(McSPI)

For more information,see MultichannelSPI chapterof the AM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). McSPI allowsa duplex,synchronous,serialcommunicationbetween a localhost and SPI compliant externaldevices.The followingtimingsare applicableto the differentconfigurationsof McSPI in master/slavemode forany McSPI and any channel(n).

6.6.2.1 McSPI —SlaveMode

In slavemode, McSPI initiatesdata transferon the data lines(mcspix_somi,mcspix_simo)when it receivesan SPI clock(mcspix_clk)fromtheexternalSPI masterdevice. Table 6-75 and Table 6-76 assume testingover the recommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-44and Figure6-45). Table6-74.McSPI Timing Conditions—SlaveMode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 4 ns tF Inputsignalfalltime 4 ns Output Condition C LOAD Outputloadcapacitance(1) 20 pF (1) The loadsettingoftheIO buffer:LB0 = 1. Table6-75.McSPI Timing Requirements—SlaveMode (1)(3) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX SS0 1/tc(CLK) Frequency,mcspix_clk 24 12 MHz SS1 tw(CLK) Pulseduration,mcspix_clkhighorlow 0.45*P(2) 0.55*P(2) 0.45*P(2) 0.55*P(2) ns SS2 tsu(SIMOV-CLKAE) Setuptime,mcspix_simovalidbeforemcspix_clk 4.2 9.5 ns activeedge SS3 th(SIMOV-CLKAE) Holdtime,mcspix_simovalidaftermcspix_clkactive 4.6 9.9 ns edge SS4 tsu(CS0V-CLKFE) Setuptime,mcspix_cs0validbeforemcspix_clkfirst 13.8 28.6 ns edge SS5 th(CS0I-CLKLE) Holdtime,mcspix_cs0invalidaftermcspix_clklast 13.8 28.6 ns edge (1) Inmcspix,x isequalto1,2,3,or4. (2) P = mcspix_clkclockperiod (3) See Section4.3.4,ProcessorClocks. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 223 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

mcspi_cs(IN) mcspi_clk(IN) mcspi_clk(IN) mcspi_somi(OUT) mcspi_cs(IN) mcspi_clk(IN) mcspi_clk(IN) mcspi_somi(OUT) Bit n–1 Bit n–2 Bit n–3 Bit n–4 Bit 0 Bit n–1 Bit n–2 Bit n–3 Bit 1 Bit 0 PHA=0 EPOL=1 POL=0 POL=1 POL=0 POL=1 PHA=1 EPOL=1 SS6 SS1 SS0 SS1 SS0 SS1 SS0 SS1 SS0 SS6 SS6 SS4 SS5 SS7 SS4 SS1 SS1 SS1 SS1 SS6 SS6SS6 SS5 SWPS038-070 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-76.McSPI SwitchingCharacteristics—SlaveMode (1)(3)(4) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX SS6 td(CLKAE-SOMIV) Delaytime,mcspix_clkactiveedge tomcspix_somi 1.8 15.9 3.2 31.7 ns shifted SS7 td(CS0AE-SOMIV) Delaytime,mcspix_cs0activeedge to Modes 0 15.9 31.7 ns mcspix_somishifted and 2(2) (1) Inmcspix,x isequalto1,2,3,or4. (2) The polarityofmcspix_clkand theactiveedge (risingorfalling)on whichmcspix_simoisdrivenand mcspix_somiislatchedisall softwareconfigurable: – mcspix_clk(1)phase programmablewiththebitPHA ofMCSPI_CH(i)CONF register:PHA = 0 (Modes 0 and 2) Formore information,see theMcSPI environmentchapter,Data FormatConfigurationssectionoftheAM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 )formodes and phase correspondencedescription. (3) Thistimingappliestoallconfigurationsregardlessofmcspix_clkpolarityand whichclockedges areused todriveoutputdataand captureinputdata. (4) See Section4.3.4,ProcessorClocks. (1) The activeclockedge selectionof mcspi_clk(risingor falling)on which mcspi_simo isdrivenand mcspi_somi data islatchedis softwareconfigurablewiththebitMCSPI_CH(i)CONF[1] = POL and thebitMCSPI_CH(i)CONF[0] = PHA. (2) The polarityofmcspi_csissoftwareconfigurablewiththebitMCSPI_CH(i)CONF[6] = EPOL. Figure6-44.McSPI —SlaveMode —Transmit

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mcspi_cs(IN) mcspi_clk(IN) mcspi_clk(IN) mcspi_simo(IN) mcspi_cs(IN) mcspi_clk(IN) mcspi_clk(IN) mcspi_simo(IN) Bit n–1 Bit n–2 Bit n–3 Bit n–4 Bit 0 Bit n–1 Bit n–2 Bit n–3 Bit 1 Bit 0 PHA=0 EPOL=1 POL=0 POL=1 POL=0 POL=1 PHA=1 EPOL=1 SS1 SS1 SS1 SS1 SS4 SS5 SS4 SS5 SS1 SS1 SS1 SS1 SS2 SS3 SS3 SS2 SS2 SS3 SS2 SS3 SWPS038-071 SS0 SS0 SS0 SS0 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) The activeclockedge selectionof mcspi_clk(risingor falling)on which mcspi_simo isdrivenand mcspi_somi data islatchedis softwareconfigurablewiththebitMCSPI_CH(i)CONF[1] = POL and thebitMCSPI_CH(i)CONF[0] = PHA. (2) The polarityofmcspi_csissoftwareconfiguablewiththebitMCSPI_CH(i)CONF[6] = EPOL. Figure6-45.McSPI —SlaveMode —Receive Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 225 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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6.6.2.2 McSPI —Master Mode

Inmastermode, McSPI supportsmultichannelcommunication.McSPI initiatesa datatransferon thedata lines(SPIDAT [1:0])and generatesclock(SPICLK) and controlsignals(SPIEN) to a singleSPI slave deviceata time. Table 6-78 and Table 6-81 assume testingover the recommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-46and Figure6-47). Table6-77.McSPI Timing Conditions—Master Mode (1) TIMING CONDITION PARAMETER VALUE UNIT MIN MAX InputConditions tR Inputsignalrisetime 4 ns tF Inputsignalfalltime 4 ns Output Conditions McSPI1, McSPI2, McSPI3, and McSPI4 C LOAD Outputloadcapacitanceforspix_csnsignals 20 pF McSPI2 and McSPI3 C LOAD Outputloadcapacitanceforspix_clkand spix_simo 30 pF McSPI1 and McSPI4 C LOAD Outputloadcapacitanceforspix_clkand spix_simo 20 pF (1) Bufferstrengthconfiguration:LB0 = 1. Table6-78.McSPI1, 2,and 4 Timing Requirements—Master Mode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX SM2 tsu(SOMIV-CLKAE) Setuptime,mcspix_somivalidbeforemcspix_clk 1.1 1.5 ns activeedge SM3 th(SOMIV-CLKAE) Holdtime,mcspix_somivalidaftermcspix_clkactive 1.9 2.8 ns edge (1) Inmcspix,x isequalto1,2,or4.Inmcspix_csn,n isequalto0,1,2,or3 forx equalto1,n isequalto0 or1 forx equalto2 and 4. (2) See Section4.3.4,ProcessorClocks. Table6-79.McSPI1, 2,and 4 SwitchingCharacteristics—Master Mode (1)(6) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX SM0 1/tc(CLK) Frequency,mcspix_clk 48 24 MHz SM1 tw(CLK) Pulseduration,mcspix_clkhighorlow 0.45*P(3) 0.55*P(3) 0.45*P(3) 0.55*P(3) ns tR(clk) Risetime,outputclockmcspi1_clkand mcspi4_clk 5.72 5.68 ns Risetime,outputclockmcspi2_clk 7.33 7.31 tF(clk) Falltime,outputclockmcspi1_clkand mcspi4_clk 5.22 5.21 ns Falltime,outputclockmcspi2_clk 6.77 6.71 SM4 td(CLKAE-SIMOV) Delaytime,mcspix_clkactiveedge tomcspix_simo –2.1 5.0 –2.1 11.3 ns shifted SM5 td(CSnA-CLKFE) Delaytime,mcspix_csiactiveto Modes 1 and 3(2) A(4)– 3.2 A(4)– 4.4 ns mcspix_clkfirstedge Modes 0 and 2(2) B(5)– 3.2 B(5)– 4.4 ns SM6 td(CLKLE-CSnI) Delaytime,mcspix_clklast Modes 1 and 3(2) B(5)– 3.2 B(5)– 4.4 ns edge tomcspix_csiinactive Modes 0 and 2(2) A(4)– 3.2 A(4)– 4.4 ns SM7 td(CSnAE-SIMOV) Delaytime,mcspix_csiactiveedge tomcspix_simo 5.0 11.3 ns shifted

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) Inmcspix,x isequalto1,2,or4.Inmcspix_csn,n isequalto0,1,2,or3 forx equalto1,n isequalto0 or1 forx equalto2 and 4. (2) The polarityofmcspix_clkand theactiveedge (risingorfalling)on whichmcspix_simoisdrivenand mcspix_somiislatchedisall softwareconfigurable: – mcspix_clk(1)phase programmablewiththebitPHA ofMCSPI_CH(i)CONF register:PHA = 1 (Modes 1 and 3). – mcspix_clk(1)phase programmablewiththebitPHA ofMCSPI_CH(i)CONF register:PHA = 0 (Modes 0 and 2). Formore information,see theMcSPI environmentchapter,Data FormatConfigurationssectionoftheAM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 )formodes and phase correspondencedescription. (3) P = mcspix_clkclockperiod (4) Case P = 20.8ns,A = (TCS+0.5)*P(3)(TCS isa bitfieldofMSPI_CHCONFx[26:25] register). Case P > 20.8ns,A = TCS*P (3)(TCS isa bitfieldofMSPI_CHCONFx[26:25] register).Formore information,see theMcSPI chapterof theAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (5) B = TCS*P (3)(TCS isa bitfieldofMSPI_CHCONFx[26:25] register).Formore information,see theMcSPI chapteroftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (6) See Section4.3.4,ProcessorClocks. Table6-80.McSPI3 Timing Requirements—Master Mode (1) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX SM2 tsu(SOMIV-CLKAE) Setuptime,mcspi3_somivalidbeforemcspi3_clk 1.5 4.3 ns activeedge SM3 th(SOMIV-CLKAE) Holdtime,mcspi3_somivalidaftermcspi3_clkactive 2.8 5.9 ns edge (1) See Section4.3.4,ProcessorClocks. Table6-81.McSPI3 SwitchingCharacteristics—Master Mode (1)(2)(6) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX SM0 1/tc(CLK) Frequency,mcspi3_clk 24 12 MHz SM1 tw(CLKH) Pulseduration,mcspi3_clkhighorlow 0.45*P(3) 0.55*P(3) 0.45*P(3) 0.55*P(3) ns tR(clk) Risetime,outputclockmcspi3_clk CBP 7.33 7.31 ns Balls: AE2 / AE13 CBP 4.31 4.30 Ball:H26 tF(clk) Falltime,outputclockmcspi3_clk CBP 6.77 6.71 ns Balls: AE2 / AE13 CBP 4.0 4.0 Ball:H26 SM4 td(CLK-SIMO) Delaytime,mcspi3_clkactiveedge tomcspi3_simo –2.1 11.3 –5.3 23.6 ns shifted SM5 td(CSn-CLK) Delaytime,mcspi3_csiactiveto Modes 1 A(4)– 4.4 A(4)– ns mcspi3_clkfirstedge and 3 10.1 Modes 0 B(5)– 4.4 B(5)– ns and 2 10.1 SM6 td(CLK-CSn) Delaytime,mcspi3_clklastedge to Modes 1 B(5)– 4.4 B(5)– ns mcspi3_csiinactive and 3 10.1 Modes 0 A(4)– 4.4 A(4)– ns and 2 10.1 SM7 td(csn-simo) Delaytime,mcspi3_csiactiveedge to Modes 0 11.3 23.6 ns mcspi3_simoshifted and 2 Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 227 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

mcspi_cs(OUT) mcspi_clk(OUT) mcspi_clk(OUT) mcspi_simo(OUT) mcspi_cs(OUT) mcspi_clk(OUT) mcspi_clk(OUT) mcspi_simo(OUT) Bit n–1 Bit n–2 Bit n–3 Bit n–4 Bit 0 Bit n–1 Bit n–2 Bit n–3 Bit 1 Bit 0 PHA=0 EPOL=1 POL=0 POL=1 PHA=1 EPOL=1 POL=0 POL=1 SM5 SM6 SM4 SM1 SM0 SM1 SM0 SM5 SM6SM1 SM0 SM1 SM0 SM4 SM7 SM4 SM1 SM1 SM1 SM1 SM4 SM4 SM4 SWPS038-072 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Inmcspi3_csn,n isequalto0 or1.The polarityofmcspi3_clkand theactiveedge (risingorfalling)on whichmcspi3_simoisdrivenand mcspi3_somiislatchedisallsoftwareconfigurable. – mcspi3_clkphase programmablewiththebitPHA ofMCSPI_CH(i)CONF register:PHA = 1 (Modes 1 and 3). – mcspi3_clkphase programmablewiththebitPHA ofMCSPI_CH(i)CONF register:PHA = 0 (Modes 0 and 2). Formore information,see theMcSPI environmentchapter,Data FormatConfigurationssectionoftheAM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 )formodes and phase correspondencedescription. (2) ThistimingappliestoallconfigurationsregardlessofMcSPI3_CLK polarityand whichclockedges areused todriveoutputdataand captureinputdata. (3) P = mcspi3_clkclockperiod (4) Case P = 20.8ns,A = (TCS + 0.5)*P(3)(TCS isa bitfieldofMSPI_CHCONFx[26:25] register). Case P > 20.8ns,A = TCS*P (3)(TCS isa bitfieldofMSPI_CHCONFx[26:25] register).Formore information,see theMcSPI chapterof AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (5) B = TCS*P (3)(TCS isa bitfieldofMSPI_CHCONFx[26:25] register).Formore information,see theMcSPI chapterofAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (6) See Section4.3.4,ProcessorClocks. (1) The activeclockedge selectionof mcspi_clk(risingor falling)on which mcspi_simo isdrivenand mcspi_somi data islatchedis softwareconfigurablewiththebitMCSPI_CH(i)CONF[1] = POL and thebitMCSPI_CH(i)CONF[0] = PHA. (2) The polarityofmcspi_ncsissoftwareconfiguablewiththebitMCSPI_CH(i)CONF[6] = EPOL. Figure6-46.McSPI —Master Mode —Transmit

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mcspi_cs(OUT) mcspi_clk(OUT) mcspi_clk(OUT) mcspi_somi(IN) mcspi_cs(OUT) mcspi_clk(OUT) mcspi_clk(OUT) mcspi_somi(IN) Bit n–1 Bit n–2 Bit n–3 Bit n-4 Bit 0 Bit n–1 Bit n–2 Bit n–3 Bit 1 Bit 0 PHA=0 EPOL=1 PHA=1 EPOL=1 POL=0 POL=1 POL=0 POL=1 SM5 SM6 SM1 SM0 SM1 SM0 SM5 SM6SM1 SM0 SM1 SM0 SM1 SM1 SM1 SM1 SM3 SM3 SM3 SM3 SM2 SM2 SM2 SM2 SWPS038-073 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) The activeclockedge selectionof mcspi_clk(risingor falling)on which mcspi_simo isdrivenand mcspi_somi data islatchedis softwareconfigurablewiththebitMCSPI_CH(i)CONF[1] = POL and thebitMCSPI_CH(i)CONF[0] = PHA. (2) The polarityofmcspi_ncsissoftwareconfiguablewiththebitMCSPI_CH(i)CONF[6] = EPOL. Figure6-47.McSPI —Master Mode —Receive

6.6.3 MultiportFull-SpeedUniversalSerialBus (FS-USB)

For more information,see High-Speed USB Host Subsystem and High-Speed USB OTG Controller/High-SpeedUSB Host Subsystem sectionoftheAM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ). The processorprovidesthreeUSB portsworkinginfull-and low-speeddatatransactions(upto12Mbit/s). When connectedtoeithera seriallinkcontrollerora serialPHY (PHY interfacemodes) itsupports:

• 6-pin(Tx:Dat/Se0orTx:Dp/ )unidirectionalmode
• 4-pinbidirectionalmode
• 3-pinbidirectional Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 229 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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6.6.3.1 FS-USB —UnidirectionalStandard 6-pinMode

Table 6-83 and Table 6-84 assume testingover the recommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-48). Table6-82.LS- /FS-USB Timing Conditions—UnidirectionalStandard 6-PinMode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 2 ns tF Inputsignalfalltime 2 ns Output Condition C LOAD Outputloadcapacitance(1) 15 pF (1) Bufferstrengthconfiguration:LB0 = 1. Table6-83.LS- /FS-USB Timing Requirements—UnidirectionalStandard 6-PinMode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX FSU1 td(vp,vm) Time duration,mmx_rxdp and mmx_rx lowtogether 14 14 ns duringtransition FSU2 td(vp,vm) Time duration,mmx_rxdp and mmx_rx hightogether 8 8 ns duringtransition FSU3 td(rcvU0) Time duration,mmx_rrxcv undefineduringa single 14 14 ns end 0 (mmx_rxdp and mmx_rx lowtogether) FSU4 td(rcvU1) Time duration,mmx_rxrcv undefineduringa single 8 8 ns end 1 (mmx_rxdp and mmx_rx hightogether) (1) Inmmx, x isequalto0,1,or2. (2) See Section4.3.4,ProcessorClocks. Table6-84.LS- /FS-USB SwitchingCharacteristics—UnidirectionalStandard 6-PinMode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX FSU5 td(txenL-dV) Delaytime,mmx_txen_n lowtommx_txdat valid 81.8 84.8 81.8 84.8 ns FSU6 td(txenL-se0V) Delaytime,mmx_txen_n lowtommx_txse0 valid 81.8 84.8 81.8 84.8 ns FSU7 ts(d-se0) Skew between mmx_txdat and mmx_txse0 transition 1.5 1.5 ns FSU8 td(dI-txenH) Delaytime,mmx_txdat invalidtommx_txen_n high 81.8 81.8 ns FSU9 td(se0I-txenH) Delaytime,mmx_txse0 invalidtommx_txen_n high 81.8 81.8 ns (1) Inmmx, x isequalto0,1,or2. (2) See Section4.3.4,ProcessorClocks.

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mmx_txen_n mmx_txdat mmx_txse0 mmx_rxdp mmx_rxdm mmx_rxrcv FSU5 FSU6 FSU7 FSU1 FSU1 FSU2 FSU2 FSU3 FSU4 FSU8 FSU9 Transmit Receive SWPS038-074 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) Inmmx, x isequalto0,1,or2. Figure6-48.LS- /FS-USB —UnidirectionalStandard 6-PinMode

6.6.3.2 FS-USB —BidirectionalStandard 4-pinMode

Table 6-86 and Table 6-87 assume testingover the recommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-49). Table6-85.LS- /FS-USB Timing Conditions—BidirectionalStandard 4-PinMode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 2 ns tF Inputsignalfalltime 2 ns Output Condition C LOAD Outputloadcapacitance(1) 15 pF (1) Bufferstrengthconfiguration:LB0 = 1. Table6-86.LS- /FS-USB Timing Requirements—BidirectionalStandard 4-PinMode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX FSU10 td(d,se0) Time duration,mmx_txdat and mmx_txse0 low 14 14 ns togetherduringtransition FSU11 td(d,se0) Time duration,mmx_txdat and mmx_txse0 high 8 8 ns togetherduringtransition FSU12 td(rcvU0) Time duration,mmx_rrxcv undefineduringa single 14 14 ns end 0 (mmx_txdatand mmx_txse0 lowtogether) FSU13 td(rcvU1) Time duration,mmx_rxrcv undefineduringa single 8 8 ns end 1 (mmx_txdatand mmx_txse0 hightogether) (1) Inmmx, x isequalto0,1,or2. (2) See Section4.3.4,ProcessorClocks. Table6-87.LS- /FS-USB SwitchingCharacteristics—BidirectionalStandard 4-PinMode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX FSU14 td(txenL-dV) Delaytime,mmx_txen_n lowtommx_txdat valid 81.8 84.8 81.8 84.8 ns FSU15 td(txenL-se0V) Delaytime,mmx_txen_n lowtommx_txse0 valid 81.8 84.8 81.8 84.8 ns FSU16 ts(d-se0) Skew between mmx_txdat and mmx_txse0 transition 1.5 1.5 ns FSU17 td(dV-txenH) Delaytime,mmx_txdat invalidbeforemmx_txen_n 81.8 81.8 ns high Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 231 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

mmx_txen_n mmx_txdat mmx_txse0 mmx_rxrcv FSU16 FSU14 FSU15 FSU10 FSU10 FSU1 1 FSU1 1 FSU12 FSU13 FSU17 FSU18 Transmit Receive SWPS038-075 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-87.LS- /FS-USB SwitchingCharacteristics—BidirectionalStandard 4-PinMode (1)(2) (continued) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX FSU18 td(se0V-txenH) Delaytime,mmx_txse0 invalidbeforemmx_txen_n 81.8 81.8 ns high (1) Inmmx, x isequalto0,1,or2. (2) See Section4.3.4,ProcessorClocks. (1) Inmmx, x isequalto0,1,or2. Figure6-49.LS- /FS-USB —BidirectionalStandard 4-PinMode

6.6.3.3 FS-USB —BidirectionalStandard 3-pinMode

Table 6-89 and Table 6-90 assume testingover the recommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-50). Table6-88.LS- /FS-USB Timing Conditions—BidirectionalStandard 3-PinMode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 2 ns tF Inputsignalfalltime 2 ns Output Condition C LOAD Outputloadcapacitance(1) 15 pF (1) Bufferstrengthconfiguration:LB0 = 1. Table6-89.LS- /FS-USB Timing Requirements—BidirectionalStandard 3-PinMode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX FSU19 td(d,se0) Time duration,mmx_txdat and mmx_txse0 low 14 14 ns togetherduringtransition FSU20 td(d,se0) Time duration,mmx_tsdat and mmx_txse0 high 8 8 ns togetherduringtransition (1) Inmmx, x isequalto0,1,or2. (2) See Section4.3.4,ProcessorClocks.

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mmx_txen_n mmx_txdat mmx_txse0 FSU23 FSU21 FSU22 FSU19 FSU19 FSU20 FSU20 FSU24 FSU25 ReceiveTransmit DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-90.LS- /FS-USB SwitchingCharacteristics—BidirectionalStandard 3-PinMode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX FSU21 td(txenL-dV) Delaytime,mmx_txen_n lowtommx_txdat valid 81.8 84.8 81.8 84.8 ns FSU22 td(txenL-se0V) Delaytime,mmx_txen_n lowtommx_txse0 valid 81.8 84.8 81.8 84.8 ns FSU23 ts(d-se0) Skew between mmx_txdat and mmx_txse0 transition 1.5 1.5 ns FSU24 td(dI-txenH) Delaytime,mmx_txdat invalidtommx_txen_n high 81.8 81.8 ns FSU25 td(se0I-txenH) Delaytime,mmx_txse0 invalidtommx_txen_n high 81.8 81.8 ns (1) Inmmx, x isequalto0,1,or2. (2) See Section4.3.4,ProcessorClocks. Figure6-50.LS- /FS-USB —BidirectionalStandard 3-PinMode (1) (1) Inmmx, x isequalto0,1,or2. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 233 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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6.6.4 MultiportHigh-Speed UniversalSerialBus (HS-USB)

For more information,see High-Speed USB Host Subsystem and High-Speed USB OTG Controller/ High-Speed USB OTG Controllerand High-Speed USB Host Subsystem and High-Speed USB OTG Controller/ High-Speed USB Host Subsystem sectionsof the AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Inadditiontothefull-speed(FS)USB controller,a high-speed(HS) USB OTG controllerisincorporatedin thedevice.Itallowshigh-speedtransactions(upto480 Mbit/s)on theUSB ports0,1,2,and 3 described below:

• Port0: – 12-bitslavemode (SDR)
• Ports1 and 2: – 12-bitmastermode (SDR)
• Port3:

6.6.4.1 HSUSB0 —Port0—12-bitSlaveMode

Table 6-92 and Table 6-93 assume testingover the recommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-51). Table6-91.HSUSB0 Timing Conditions—12-bitSlaveMode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 2 ns tF Inputsignalfalltime 2 ns Output Condition C LOAD Outputloadcapacitance(1) 3.5 pF (1) Bufferstrengthconfiguration:LB0 = 0. Table6-92.HSUSB0 Timing Requirements—12-bitSlaveMode (3)(4) NO. PARAMETER OPP100 UNIT MIN MAX HSU0 fp(CLK) hsusb0_clkclockfrequency(1) 60.03 MHz tJ(CLK) Cyclejitter(2),hsusb0_clk 500 ps HSU3 ts(DIRV-CLKH) Setuptime,hsusb0_dirvalidbeforehsusb0_clkrisingedge 6.68 ns ts(NXTV-CLKH) Setuptime,hsusb0_nxtvalidbeforehsusb0_clkrisingedge 6.68 ns HSU4 th(CLKH-DIRIV) Holdtime,hsusb0_dirvalidafterhsusb0_clkrisingedge 0 ns th(CLKH-NXT/IV) Holdtime,hsusb0_nxtvalidafterhsusb0_clkrisingedge 0 ns HSU5 ts(DATAV-CLKH) Setuptime,hsusb0_data[0:7]validbeforehsusb0_clkrisingedge 6.68 ns HSU6 th(CLKH-DATIV) Holdtime,hsusb0_data[0:7]validafterhsusb0_clkrisingedge 0 ns (1) Relatedwiththeinputmaximum frequencysupportedby theUSB module. (2) Maximum cyclejittersupportedby hsusb0_clkinputclock (3) The timingrequirementsareassuredup tothecyclejittererrorconditionspecified. (4) See Section4.3.4,ProcessorClocks.

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hsusb0_clk hsusb0_stp hsusb0_dir and hsusb0_nxt hsusb0_data[7:0] Data_OUT Data_IN HSU1 HSU0 HSU1 HSU4 HSU2 HSU2 HSU6 HSU3 HSU5 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-93.HSUSB0 SwitchingCharacteristics—12-bitSlaveMode (1) NO. PARAMETER OPP100 UNIT MIN MAX HSU1 td(clkL-STPV) Delaytime,hsusb0_clkhightooutputusb0_stpvalid 8.6 ns td(clkL-STPIV) Delaytime,hsusb0_clkhightooutputusb0_stpinvalid 0 ns HSU2 td(clkL-DV) Delaytime,hsusb0_clkhightooutputhsusb0_data[0:7]valid 8.6 ns td(clkL-DIV) Delaytime,hsusb0_clkhightooutputhsusb0_data[0:7]invalid 0 ns (1) See Section4.3.4,ProcessorClocks. Figure6-51.HSUSB0 —12-bitSlaveMode

6.6.4.2 HSUSB1 and HSUSB2 —Ports1 and 2—12-bitSlaveMode

Table 6-95 and Table 6-96 assume testingover the recommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-52). Table6-94.HSUSB1 and HSUSB2 Timing Conditions—12-bitMaster Mode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 3 ns tF Inputsignalfalltime 2 ns Output Condition C LOAD Outputloadcapacitance(1) 5 pF (1) Bufferstrengthconfiguration:LB0 = 0. Table6-95.HSUSB1 and HSUSB2 Timing Requirements—12-bitMaster Mode (1)(2) NO. PARAMETER OPP100 UNIT MIN MAX HSU3 tsu(dirV-clkH) Setuptime,inputdirectioncontrolhsusbx_dirvalidbeforeoutputclock 9.3 ns hsusbx_clkrisingedge tsu(nxtV-clkH) Setuptime,inputnextsignalhsusbx_nxtvalidbeforeoutputclock 9.3 ns hsusbx_clkrisingedge HSU4 th(clkH-dirIV) Holdtime,inputdirectioncontrolhsusbx_dirvalidafteroutputclock –0.52 ns hsusbx_clkrisingedge th(clkH-nxtIV) Holdtime,inputnextsignalhsusbx_nxtvalidafteroutputclock –0.52 ns hsusbx_clkrisingedge HSU5 tsu(dV-clkH) Setuptime,inputdatahsusbx_data[7:0]validbeforeoutputclock 9.3 ns hsusbx_clkrisingedge Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 235 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

hsusbx_clk hsusbx_stp hsusbx_dir and hsusbx_nxt hsusbx_data[7:0] Data_OUT Data_IN HSU1 HSU0 HSU1 HSU4 HSU2 HSU2 HSU6 HSU3 HSU5 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-95.HSUSB1 and HSUSB2 Timing Requirements—12-bitMaster Mode (1)(2) (continued) NO. PARAMETER OPP100 UNIT MIN MAX HSU6 th(clkH-dV) Holdtime,inputdatahsusbx_data[7:0]validafteroutputclock –0.52 ns hsusbx_clkrisingedge (1) Inhsusbx,x isequalto1 or2. (2) See Section4.3.4,ProcessorClocks. Table6-96.HSUSB1 and HSUSB2 SwitchingCharacteristics—12-bitMaster Mode (1)(3) NO. PARAMETER OPP100 UNIT MIN MAX HSU0 fp(clk) Frequency,outputclockhsusbx_clk 60 MHz tJ(clk) Jitterstandarddeviation(2),outputclockhsusbx_clk 400 ps HSU1 td(clkH-stpV) Delaytime,outputclockhsusbx_clkrisingedge tooutputstopsignal 12.81 ns hsusbx_stpvalid td(clkH-stpIV) Delaytime,outputclockhsusbx_clkrisingedge tooutputstopsignal 1.95 ns hsusbx_stpinvalid HSU2 td(clkH-dV) Delaytime,outputclockhsusbx_clkrisingedge tooutputdata 12.81 ns hsusbx_data[7:0]valid td(clkH-dIV) Delaytime,outputclockhsusbx_clkrisingedge tooutputdata 1.95 ns hsusbx_data[7:0]invalid tR(d) Risetime,outputdatahsusbx_data[7:0] 0 ns tF(d) Falltime,outputdatahsusbx_data[7:0] 0 ns (1) Inhsusbx,x isequalto1 or2. (2) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (3) See Section4.3.4,ProcessorClocks. (1) Inhsusbx,x isequalto1 or2. Figure6-52.HSUSB1 and HSUSB2 —12-bitMaster Mode

6.6.5 Inter-IntegratedCircuitInterface(I2C)

For more information,see MultimasterHigh-SpeedI2C ControllerchapteroftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). The multi-masterI2C peripheralprovidesan interfacebetween two ormore devicesviaan I2C serialbus.

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 The I2C controllersupportsthe multi-mastermode which allowsmore than one device capable of controllingthe bus to be connectedto it.Each I2C deviceisrecognizedby a uniqueaddressand can operatesas eithertransmitteror receiver,accordingtothefunctionofthedevice.Inadditiontobeinga transmitterorreceiver,a deviceconnectedtotheI2C bus can alsobe consideredas masterorslavewhen performingdatatransfers.Thisdatatransferiscarriedoutviatwo serialbidirectionalwires:

• An SDA dataline
• An SCL clockline InFigure6-53thedatatransferisinmasterorslaveconfigurationwith7-bitaddressingformat. The I2C interfaceiscompliantwithPhilipsI2C specificationversion2.1.Itsupportsstandardmode (upto 100K bits/s),fastmode (upto400K bits/s)and high-speedmode (upto3.4Mb/s).

6.6.5.1 I2C —Standard and FastModes

Table6-97.I2C —Standard and FastModes NO. PARAMETER STANDARD MODE FAST MODE UNIT MIN MAX MIN MAX fscl Frequency,clocki2cx_scl(4) 100 400 kHz I1 tw(sclH) Pulseduration,clocki2cx_scl(4)high 4.0 0.6 μs I2 tw(sclL) Pulseduration,clocki2cx_scl(4)low 4.7 1.3 μs I3 tsu(sdaV-sclH) Setuptime,datai2cx_sda(4)validbeforeclock 250 100(1) ns i2cx_scl(4)activelevel I4 th(sclH-sdaV) Holdtime,datai2cx_sda(4)validafterclock 0(2) 3.45(3) 0(2) 0.9(3) μs i2cx_scl(4)activelevel I5 tsu(sdaL-sclH) Setuptime,clocki2cx_scl(4)highafterdata 4.7 0.6 μs i2cx_sda(4)low(fora START (5)conditionora repeatedSTART condition) I6 th(sclH-sdaH) Holdtime,datai2cx_sdalowlevelafterclock 4.0 0.6 μs i2cx_scl(4)highlevel(STOP condition) I7 th(sclH-RSTART) Holdtime,datai2cx_sda(4)lowlevelafter 4.0 0.6 μs clocki2cx_scl(4)highlevel(fora repeated START condition) I8 tw(sdaH) Pulseduration,datai2cx_sda(4)highbetween 4.7(4) 1.3 μs STOP and START conditions tR(scl) Risetime,clocki2cx_scl(4) 1000 20 + 300 ns 0.1CB tF(scl) Falltime,clocki2cx_scl(4) 300 20 + 300 ns 0.1CB tR(sda) Risetime,datai2cx_sda(4) 1000 20 + 300 ns 0.1CB tF(sda) Falltime,datai2cx_sda(4) 300 20 + 300 ns 0.1CB C B Capacitiveloadforeach bus line 400 400 pF (1) A fast-modeI2C-bus devicecan be used ina standard-modeI2C-bus system,buttherequirementtsu(SDAV-SCLH) ≥ 250 ns must thenbe met.Thisisautomaticallythecase ifthedevicedoes notstretchthelowperiodofthei2cx_scl(4).Ifsuch a devicedoes stretchthelow periodofthei2cx_scl(4),itmust outputthenextdatabittothei2cx_sda(4)linetr(SDA)max + tsu(SDAV-SCLH) = 1000 + 250 = 1250 ns (accordingtothestandard-modeI2C-bus specification)beforethei2cx_scl(4)lineisreleased. (2) The deviceprovides(viatheI2C bus)a minimum holdtime(=I2C_FCLK periodx (PSC+1) x 4)forthei2cx_sda(4)signal(seethefall and risetimesofi2cx_scl(4))tobridgetheundefinedregionofthefallingedge ofi2cx_scl(4). (3) The maximum th(SCLH-SDA) has onlytobe met ifthedevicedoes notstretchthelowperiodofthei2cx_scl(4)signal. (4) Ini2cx,x isequalto1,2,3,or4.Note thatI2C4 ismastertransmitteronly. (5) Afterthistime,thefirstclockisgenerated. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 237 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

i2cX_sda i2cX_scl ST ART REPEA T STOP ST ART ST ART I1 I2 I3 I4 I6I6 I7 SWPS038-085 i2cX_sda i2cX_scl STOPST ART REPEA T IH1 IH2 IH3 IH4IH6IH5 IH7 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Ini2cX,X isequalto1,2,3,or4. Figure6-53.I2C —Standard and FastModes

6.6.5.2 I2C —High-Speed Mode

Table6-98.I2C —High-Speed Mode NO. PARAMETER MIN MAX UNIT fscl Frequency,clocki2cx_scl(3) 3.4(5) MHz I1 tw(sclH) Pulseduration,clocki2cx_scl(3)high 60(1) ns I2 tw(sclL) Pulseduration,clocki2cx_scl(3)low 160(1) ns I3 tsu(sdaV-sclH) Setuptime,datai2cx_sda(3)validbeforeclocki2cx_scl(3)activelevel 10 ns I4 th(sclH-sdaV) Holdtime,datai2cx_sda(3)validafterclocki2cx_scl(3)activelevel 0(4) 70 ns I5 tsu(sdaL-sclH) Setuptime,clocki2cx_scl(3)highafterdatai2cx_sda(3)low(fora 160 ns START (2)conditionora repeatedSTART condition) I6 th(sclH-sdaH) Holdtime,datai2cx_sda(3)lowlevelafterclocki2cx_scl(3)highlevel 160 ns (STOP condition) I7 th(sclH-RSTART) Holdtime,datai2cx_sda(3)lowlevelafterclocki2cx_scl(3)highlevel 160 ns (fora repeatedSTART condition) tR(scl) Risetime,clocki2cx_scl(3) 10 40 ns tR(scl) Risetime,clocki2cx_scl(3)aftera repeatedSTART conditionand after 10 80 ns a bitacknowledge tF(scl) Falltime,clocki2cx_scl(3) 10 40 ns tR(sda) Risetime,datai2cx_sda(3) 10 80 ns tF(sda) Falltime,datai2cx_sda(3) 10 80 ns C B Capacitiveloadforeach bus line 100 pF (1) HS-mode masterdevicesgeneratea serialclocksignalwitha hightolowratioof1 to2.tw(sclL)> 2 *tw(sclH). (2) Afterthistime,thefirstclockisgenerated. (3) Ini2cx,x isequalto1,2,3,or4.Note thatI2C4 ismastertransmitteronly. (4) The deviceprovides(viatheI2C bus)a minimum holdtime(=I2C_FCLK periodx 4)forthei2cx_sda(3)signal(seethefalland risetimes ofi2cx_scl(3))tobridgetheundefinedregionofthefallingedge ofi2cx_scl(3). (5) The I2C4 clockfrequencyinhigh-speedmode isequaltothesys_xtalininputclockfrequencydividedby 15. (1) Ini2cX,X isequalto1,2,3,or4. Figure6-54.I2C —High-Speed Mode

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-99.I2C Correspondence Standard vs Data Manual Timing References TI STANDARD-I 2C Standard/FastModes High-Speed Mode fscl FSCL FSCLH I1 tw(sclH) THIGH THIGH I2 tw(sclL) TLOW TLOW I3 tsu(sdaV-sclH) TSU;DAT TSU;DAT I4 th(sclH-sdaV) TSU;DAT TSU;DAT I5 tsu(sdaL-sclH) TSU;STA TSU;STA I6 th(sclH-sdaH) THD;STA THD;STA I7 th(sclH-RSTART) TSU;STO TSU;STO I8 tw(sdaH) TBUF

6.6.6 HDQ /1-WireInterface(HDQ/1-Wire)

For more information,see HDQ/1-Wire /HDQ/1-Wire chapteroftheAM/DM37x Multimedia DeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). The module isintendedtowork withbothHDQ and 1-Wireprotocols.The protocolsuse a singlewireto communicate between the master and the slave.The protocolsemploy an asynchronousreturnto one mechanism where,afterany command, thelineispulledhigh.

6.6.6.1 HDQ/1-Wire—HDQ Mode

Table6-100 and Table6-102 assume testingovertherecommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-55throughFigure6-59). Table6-100.HDQ InterfaceRead Timing PARAMETER DESCRIPTION MIN TYP MAX UNIT tCYCH Read bitwindow timing 190 250 μs tHW1 Read one datavalidafterHDQ low 32(2) 66(2) μs tHW0 Read zerodataholdafterHDQ low 70(2) 145(2) μs tRSPS Response timefromHDQ slavedevice(1) 190 320 μs (1) Definedby software (2) IftheHDQ slavedevicedrivesa logic-lowstateaftertHW0 max, itcan be interpretedas a breakpulse.Formore informationsee Table6-101and theHDQ/1-Wire chapteroftheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). Table6-101.HDQ Sampling Cases (1) CASES FIRST SAMPLING (at68 µs) SECOND SAMPLING (at180 µs)

1 L (logic-lowstate) L (logic-lowstate)

2 L (logic-lowstate) H (logic-highstate)

3 H (logic-highstate) L (logic-lowstate)

4 H (logic-highstate) H (logic-highstate)

(1) The differentcasescan be interpretedas follows: – Case 1:Ifa logic-lowstateispresentatthefirstsamplingtimeand alsoatthesecond samplingtime,thereceivedatacan be interpretedas a breakpulse. – Case 2:Ifa logic-lowstateispresentatthefirstsamplingtimeand a logic-highstateispresentatthesecond samplingtime,the receivedataon thelineisa zero(data). – Case 3:Undefined. – Case 4:Ifa logic-highstateispresentatthefirstsamplingtimeand alsoatthesecond samplingtime,thereceivedataon thelineis a one (data). Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 239 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

First sampling time Second sampling timetHW1 tHW0 tB tBR SWPS038-122 SWPS038-087 HDQ tHW1 tHW0 tCYCH SWPS038-088 HDQ tDW1 tDW0 tCYCD SWPS038-089 HDQ Break 0_(LSB) 1 6 7_(MSB) tRSPS 1 Command_byte_written Data_byte_received 0_(LSB) DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-102.HDQ WriteSwitchingCharacteristics PARAMETER DESCRIPTION MIN TYP MAX UNIT tB Breaktiming 190 μs tBR Breakrecoverytime 40 μs tCYCD Writebitwindows timing 190 μs tDW1 Writeone datavalidafterHDQ low 0.5 50 μs tDW0 WritezerodataholdafterHDQ low 86 145 μs Figure6-55.HDQ Break and Break Recovery Timing— HDQ InterfaceWritingtoSlave Figure6-56.HDQ Break Detection— HDQ InterfaceReading Slave Figure6-57.HDQ InterfaceBitRead Timing (Data) Figure6-58.HDQ InterfaceBitWriteTiming (Command/Address or Data) Figure6-59.HDQ —Communication

6.6.6.2 HDQ/1-Wire—1-WireMode

Table6-103 and Table6-104 assume testingovertherecommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-60throughFigure6-63).

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-103.HDQ/1-Wire Timing Requirements—1-WireMode PARAMETER DESCRIPTION MIN TYP MAX UNIT tPDH Presencepulsedelayhigh 15 60 μs tPDL Presencepulsedelaylow 60 240 μs tRDV Read datavalidtime tLOWR 15 μs tREL Read datareleasetime 0 45 μs Table6-104.HDQ/1-Wire SwitchingCharacteristics—1-WireMode PARAMETER DESCRIPTION MIN TYP MAX UNIT tRSTL Resettimelow 480 960 μs tRSTH Resettimehigh 480 μs tSLOT Bitcycletime 60 120 μs tLOW1 Writebit-onetime 1 15 μs tLOW0 Writebit-zerotime(2) 60 120 μs tREC Recoverytime 1 μs tLOWR Read bitstrobetime(1) 1 15 μs (1) tLOWR (lowpulsesentby themaster)must be shortas possibletomaximizethemastersamplingwindow. (2) tLOW0 must be lessthantSLOT . Figure6-60.1-WireReset Timing Figure6-61.1-WireRead BitTiming (Data) Figure6-62.1-WireWriteBit-OneTiming (Command /Address or Data) Figure6-63.1-WireWriteBit-ZeroTiming (Command/Address or Data) Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 241 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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6.6.7 UniversalAsynchronous ReceiverTransmitter(UART)

For more information,see UART/IrDA/CIR chapterof the AM/DM37x MultimediaDevice TechnicalReferenceManual (literaturenumber SPRUGN4 ).

6.6.7.1 UART

Table6-105.UART SwitchingCharacteristics(2) SIGNAL NAME MUX MODE DESCRIPTION MIN MAX UNIT UniversalAsynchronous Receiver/Transmitter(UART1) UART1 (uart1_tx):AA8 0 tR ,Risetime 1.5 5.5 ns tF,Falltime C L,Outputload 2 22 pF UART1 (uart1_rts):AA9 0 tR ,Risetime 1.5 5.5 ns tF,Falltime C L,Outputload 2 22 pF UART1 (uart1_tx):E26 2 tR ,Risetime 0.6 2.4 ns tF,Falltime C L,Outputload 2 22 pF UART1 (uart1_rts):AH22 2 tR ,Risetime SC0, SC1 = 00(1) 1 15 ns tF,Falltime C L,Outputload 4 60 pF tR ,Risetime SC0, SC1 = 00(1) 0.4 5 ns tF,Falltime C L,Outputload 2 21 pF tR ,Risetime SC0, SC1 = 00(1) 0.6 7 ns tF,Falltime C L,Outputload 7 33 pF UniversalAsynchronous Receiver/Transmitter(UART2) UART2 (uart2_tx):AA25 0 tR ,Risetime 1.5 5.5 ns tF,Falltime C L,Outputload 2 22 pF UART2 (uart2_rts):AB25 0 tR ,Risetime 1.5 5.5 ns tF,Falltime C L,Outputload 2 22 pF UART2 (uart2_tx):AF5 1 tR ,Risetime 1.5 5.5 ns tF,Falltime C L,Outputload 2 22 pF UART2 (uart2_rts):AE6 1 tR ,Risetime 1.5 5.5 ns tF,Falltime C L,Outputload 2 22 pF UART2 (uart2_tx):T27 5 tR ,Risetime 1.5 5.5 ns tF,Falltime C L,Outputload 2 22 pF UART2 (uart2_rts):U27 5 tR ,Risetime 1.5 5.5 ns tF,Falltime C L,Outputload 2 22 pF UniversalAsynchronous Receiver/Transmitter(UART3)

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-105.UART SwitchingCharacteristics(2)(continued) SIGNAL NAME MUX MODE DESCRIPTION MIN MAX UNIT UART3 (uart3_cts_rctx):H18 0 tR ,Risetime SC0, SC1 = 00(1) 1 15 ns tF,Falltime C L,Outputload 4 60 pF tR ,Risetime SC0, SC1 = 00(1) 0.4 5 ns tF,Falltime C L,Outputload 2 21 pF tR ,Risetime SC0, SC1 = 00(1) 0.6 7 ns tF,Falltime C L,Outputload 7 33 pF UART3 (uart3_rts_sd):H19 0 tR ,Risetime SC0, SC1 = 00(1) 1 15 ns tF,Falltime C L,Outputload 4 60 pF tR ,Risetime SC0, SC1 = 00(1) 0.4 5 ns tF,Falltime C L,Outputload 2 21 pF tR ,Risetime SC0, SC1 = 00(1) 0.6 7 ns tF,Falltime C L,Outputload 7 33 pF UART3 (uart3_tx_irtx):H21 0 tR ,Risetime SC0, SC1 = 00(1) 1 15 ns tF,Falltime C L,Outputload 4 60 pF tR ,Risetime SC0, SC1 = 00(1) 0.4 5 ns tF,Falltime C L,Outputload 2 21 pF tR ,Risetime SC0, SC1 = 00(1) 0.6 7 ns tF,Falltime C L,Outputload 7 33 pF UART3 (uart3_cts_rctx):U26 2 tR ,Risetime 1.5 5.5 ns tF,Falltime C L,Outputload 2 22 pF UART3 (uart3_rts_sd):U27 2 tR ,Risetime 1.5 5.5 ns tF,Falltime C L,Outputload 2 22 pF UART3 (uart3_tx_irtx):AH24 2 tR ,Risetime SC0, SC1 = 00(1) 1 15 ns tF,Falltime C L,Outputload 4 60 pF tR ,Risetime SC0, SC1 = 00(1) 0.4 5 ns tF,Falltime C L,Outputload 2 21 pF tR ,Risetime SC0, SC1 = 00(1) 0.6 7 ns tF,Falltime C L,Outputload 7 33 pF UART3 (uart3_tx_irtx):G26 2 tR ,Risetime 0.6 2.4 ns tF,Falltime C L,Outputload 2 22 pF Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 243 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

90% 90% 50%50% 10% 10% tr tf DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-105.UART SwitchingCharacteristics(2)(continued) SIGNAL NAME MUX MODE DESCRIPTION MIN MAX UNIT UART3 (uart3_tx_irtx):T27 2 tR ,Risetime 1.5 5.5 ns tF,Falltime C L,Outputload 2 22 pF UniversalAsynchronous Receiver/Transmitter(UART4) UART4 (uart4_tx):K8 2 tR ,Risetime 0.6 2.4 ns tF,Falltime C L,Outputload 2 22 pF (1) The mode isconfiguredby bitsSC0 and SC1 oftheIO cell.Formore details,see theAM/DM37x MultimediaDeviceTechnical ReferenceManual (literaturenumber SPRUGN4 ). (2) Caution:Up toa risetimeora falltimeof1.2ns,thiscan createEMI parasitics.

6.6.7.2 UART3 IrDA

The IrDAmodule can operateinthreedifferentmodes:

• Slow infrared(SIR)(≤ 115.2Kbits/s)
• Medium infrared(MIR)(0.576Mbits/sand 1.152Mbits/s)
• Fastinfrared(FIR)(4Mbits/s) Figure6-64.UART IrDA Pulse Parameters 6.6.7.2.1UART3 IrDA—Receive Mode Table6-106.UART3 IrDA SignalingRate and Pulse Duration—Receive Mode SIGNALING RATE ELECTRICAL PULSE DURATION UNIT MIN TYP MAX SIR 2.4Kbit/s 52.17 78.13 208.33 μs 9.6Kbit/s 13.10 19.53 52.08 μs 19.2Kbit/s 6.59 9.77 26.04 μs 38.4Kbit/s 3.34 4.88 13.02 μs 57.6Kbit/s 2.25 3.26 8.68 μs 115.2Kbit/s 1.17 1.63 4.34 μs MIR 0.576Mbit/s 300.55 416.67 867.86 ns

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-106.UART3 IrDA SignalingRate and Pulse Duration—Receive Mode (continued) SIGNALING RATE ELECTRICAL PULSE DURATION UNIT MIN TYP MAX 1.152Mbit/s 192.04 208.33 433.83 ns FIR 4.0Mbit/s(Singlepulse) 62.70 125.00 170.63 ns 4.0Mbit/s(Doublepulse) 208.53 250.00 291.47 ns Table6-107.UART3 IrDA Rise and FallTimes—Receive Mode PARAMETER MIN TYP MAX UNIT tR Risetime,inputdatauart3_rx_irrx 200 ns tF Falltime,inputdatauart3_rx_irrx 200 ns 6.6.7.2.2UART3 IrDA—TransmitMode Table6-108.UART3 IrDA SignalingRate and Pulse Duration—TransmitMode SIGNALING RATE ELECTRICAL PULSE DURATION UNIT MIN TYP MAX SIR 2.4Kbit/s 78.1 78.1 78.1 μs 9.6Kbit/s 19.5 19.5 19.5 μs 19.2Kbit/s 9.75 9.75 9.75 μs 38.4Kbit/s 4.87 4.87 4.87 μs 57.6Kbit/s 3.25 3.25 3.25 μs 115.2Kbit/s 1.62 1.62 1.62 μs MIR 0.576Mbit/s 414 416 419 ns 1.152Mbit/s 206 208 211 ns FIR 4.0Mbit/s(Singlepulse) 123 125 128 ns 4.0Mbit/s(Doublepulse) 248 250 253 ns

6.6.8 Removable Media Interfaces

6.6.8.1 MultimediaMemory Card and Secure DigitalIO Card (MMC)

For more information,see MMC/SD/SDIO Card Interfacechapter of the AM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). The MMC hostcontrollerprovidesan interfacetohigh-speedand standardMMC, SD memory cards,or SDIO cards.The applicationinterfaceisresponsibleformanaging transactionsemantics.The MMC/SDIO hostcontrollerdealswithMMC/SDIO protocolattransmissionlevel,packingdata,addingCRC, start/end bit,and checkingforsyntacticalcorrectness. TherearethreeMMC interfaceson thedevice:

• MMC1: – 1.8-V/3-V support – 4-bitinStandardMMC, High-SpeedMMC, StandardSD, and High-SpeedSD modes Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 245 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

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• MMC2: – 1.8-Vsupport – 8-bitwithoutexternaltransceiver – 4-bitwithexternaltransceiverallowingsupporting3-V peripherals.Transceiverdirectioncontrol signalsaremultiplexedwiththeupperfourdatabits.
• MMC3: – 1.8-Vsupport – 8-bitwithoutexternaltransceiver 6.6.8.1.1MMC1 Interface—SD IdentificationModes Table6-110 and Table6-111 assume testingovertherecommended operatingconditionsand electrical characteristicconditionsbelow. Table6-109.MMC1 InterfaceTiming Conditions—SD IdentificationModes TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 10 ns tF Inputsignalfalltime 10 ns Output Condition C LOAD Outputloadcapacitance(1) 40 pF (1) Bufferstrengthconfiguration:LB0 = 0. Table6-110.MMC1 InterfaceTiming Requirements—SD IdentificationModes (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC1 Interface(1.8-VIO) SD3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk rising 1198.4 1198.4 ns clockedge SD4 th(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk rising 1249.2 1249.2 ns clockedge MMC1 Interface(3.0-VIO) SD3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk rising 1198.4 1198.4 ns clockedge SD4 th(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk rising 1249.2 1249.2 ns clockedge (1) Correspondingfiguresshowingtimingparametersarecommon withotherinterfacemodes. (See SD ,HS SD modes). (2) See Section4.3.4,ProcessorClocks. Table6-111.MMC1 InterfaceSwitchingCharacteristics—SD IdentificationModes (4)(7) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX SD IdentificationMode SD1 tc(clk) Frequency(1),outputclockperiod 0.4 0.4 MHz SD2 tW(clkH) Typicalpulseduration,outputclockhigh X(5)*PO (2) X(5)*PO (2) ns SD2 tW(clkL) Typicalpulseduration,outputclocklow Y(6)*PO (2) Y(6)*PO (2) ns tdc(clk) Dutycycleerror,outputclock 125 125 ns tJ(clk) Jitterstandarddeviation(3),outputclock 200 200 ps MMC1 Interface(1.8-VIO) tR(clk) Risetime,outputclock 10 10 ns tF(clk) Falltime,outputclock 10 10 ns

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-111.MMC1 InterfaceSwitchingCharacteristics—SD IdentificationModes (4)(7) (continued) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX tR(data) Risetime,outputdata 10 10 ns tF(data) Falltime,outputdata 10 10 ns SD5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd 6.3 2492.7 6.3 2492.7 ns transition MMC1 Interface(3.0-VIO) tR(clk) Risetime,outputclock 10 10 ns tF(clk) Falltime,outputclock 10 10 ns tR(data) Risetime,outputdata 10 10 ns tF(data) Falltime,outputdata 10 10 ns SD5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd 6.3 2492.7 6.3 2492.7 ns transition (1) Relatedwiththeoutputclockmaximum and minimum frequenciesprogrammableinmmc module. (2) PO = outputclockperiodinns (3) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (4) Correspondingfiguresshowingtimingparametersarecommon withotherinterfacemodes. (See SD, HS SD modes). (5) The X parameterisdefinedas follows: CLKD X 1 orEven 0.5 Odd (trunk[CLKD/2]+1)/CLKD AllrequireddetailsaboutclockdivisionfactorCLKD can be foundintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (6) The Y parameterisdefinedas follows: CLKD Y 1 orEven 0.5 Odd (trunk[CLKD/2])/CLKD AllrequireddetailsaboutclockdivisionfactorCLKD can be foundintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (7) See Section4.3.4,ProcessorClocks. 6.6.8.1.2MMC1 Interface—High-Speed SD Mode Table6-113 and Table6-114 assume testingovertherecommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-65and Figure6-66). Table6-112.MMC1 InterfaceTiming Conditions—High-Speed SD Mode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 3 ns tF Inputsignalfalltime 3 ns Output Condition C LOAD Outputloadcapacitance(1) 40 pF (1) Bufferstrengthconfiguration:SPEEDCTRL = 1. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 247 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-113.MMC1 InterfaceTiming Requirements—High-Speed SD Mode (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC1 Interface(1.8-VIO) HSSD3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk rising 5.6 26 ns clockedge HSSD4 th(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk rising 2.3 1.9 ns clockedge HSSD7 tsu(DATxV-CLKIH) Setuptime,mmc1_datn:0validbeforemmc1_clk 5.6 26 ns risingclockedge HSSD8 th(CLKIH-DATxIV) Holdtime,mmc1_datn:0validaftermmc1_clk 2.3 1.9 ns risingclockedge MMC1 Interface(3.0-VIO) HSSD3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk rising 5.6 26 ns clockedge HSSD4 th(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk rising 2.3 1.9 ns clockedge HSSD7 tsu(DATxV-CLKIH) Setuptime,mmc1_datn:0validbeforemmc1_clk 5.6 26 ns risingclockedge HSSD8 th(CLKIH-DATxIV) Holdtime,mmc1_datn:0validaftermmc1_clk 2.3 1.9 ns risingclockedge (1) Inmmc1_dat[n:0],n isequalto3. (2) See Section4.3.4,ProcessorClocks.

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-114.MMC1 InterfaceSwitchingCharacteristics—High-Speed SD Mode (7) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX High-Speed SD Mode HSSD1 tc(clk) Frequency(1),outputclockperiod 48 24 MHz HSSD2 tW(clkH) Typicalpulseduration,outputclockhigh X(4)*PO (2) X(4)*PO (2) ns HSSD2 tW(clkL) Typicalpulseduration,outputclocklow Y(5)*PO (2) Y(5)*PO (2) ns tdc(clk) Dutycycleerror,outputclock 1041.67 2083.33 ps tJ(clk) Jitterstandarddeviation(3),outputclock 200 200 ps MMC1 Interface(1.8-VIO) tR(clk) Risetime,outputclock 3 3 ns tF(clk) Falltime,outputclock 3 3 ns tR(data) Risetime,outputdata 3 3 ns tF(data) Falltime,outputdata 3 3 ns HSSD5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd 3.72 14.11 4.13 34.53 ns transition HSSD6 td(CLKOH-DATx) Delaytime,mmc1_clk risingclockedge to 3.72 14.11 4.13 34.53 ns mmc1_datn:0transition MMC1 Interface(3.0-VIO) tR(clk) Risetime,outputclock 3 3 ns tF(clk) Falltime,outputclock 3 3 ns tR(data) Risetime,outputdata 3 3 ns tF(data) Falltime,outputdata 3 3 ns HSSD5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd 3.72 14.11 4.13 34.53 ns transition HSSD6 td(CLKOH-DATx) Delaytime,mmc1_clk risingclockedge to 3.72 14.11 4.13 34.53 ns mmc1_datn:0transition (1) Relatedwiththeoutputclockmaximum and minimum frequenciesprogrammableinMMC module. (2) PO = outputclockperiodinns (3) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (4) The X parameterisdefinedas follows: CLKD X 1 orEven 0.5 Odd (trunk[CLKD/2]+1)/CLKD AllrequireddetailsaboutclockdivisionfactorCLKD can be foundintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (5) The Y parameterisdefinedas follows: CLKD Y 1 orEven 0.5 Odd (trunk[CLKD/2])/CLKD AllrequireddetailsaboutclockdivisionfactorCLKD can be foundintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (6) Inmmc1_dat[n:0],n isequalto3. (7) See Section4.3.4,ProcessorClocks. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 249 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

mmc1_clk mmc1_cmd mmc1_dat[3:0] HSSD3 HSSD7 HSSD4 HSSD8 HSSD1 HSSD2 SWPS038-095 mmc1_clk mmc1_cmd mmc1_dat[3:0] HSSD5 HSSD5 HSSD6 HSSD6 HSSD1 HSSD2 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Figure6-65.MMC1 Interface—High-Speed SD Mode —Data/Command Receive Figure6-66.MMC1 Interface—High-Speed SD Mode —Data/Command Transmit 6.6.8.1.3MMC1 Interface—Standard SD Mode Table6-116 and Table6-117 assume testingovertherecommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-67and Figure6-68). Table6-115.MMC1 InterfaceTiming Conditions—Standard SD Mode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 10 ns tF Inputsignalfalltime 10 ns Output Condition C LOAD Outputloadcapacitance(1) 40 pF (1) Bufferstrengthconfiguration:SPEEDCTRL = 1. Table6-116.MMC1 InterfaceTiming Requirements—Standard SD Mode (1)(2)(4) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC1 Interface(1.8-VIO) SD3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk rising 3.3 21.9 ns clockedge SD4 th(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk rising 18.1 36.7 ns clockedge SD7 tsu(DATxV-CLKIH) Setuptime,mmc1_datn:0validbeforemmc1_clk 3.3 21.9 ns risingclockedge SD8 th(CLKIH-DATxIV) Holdtime,mmc1_datn:0validaftermmc1_clk 18.1 36.7 ns risingclockedge MMC1 Interface(3.0-VIO) SD3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk rising 3.3 21.9 ns clockedge

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-116.MMC1 InterfaceTiming Requirements—Standard SD Mode (1)(2)(4) (continued) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX SD4 th(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk rising 18.1 36.7 ns clockedge SD7 tsu(DATxV-CLKIH) Setuptime,mmc1_datn:0validbeforemmc1_clk 3.3 21.9 ns risingclockedge SD8 th(CLKIH-DATxIV) Holdtime,mmc1_datn:0validaftermmc1_clk 18.1 36.7 ns risingclockedge (1) TimingparametersarereferredtooutputclockspecifiedinTable6-117. (2) The timingrequirementsareassuredforthecyclejitterand dutycycleerrorconditionsspecifiedinTable6-117. (3) Inmmc1_dat[n:0],n isequalto3. (4) See Section4.3.4,ProcessorClocks. Table6-117.MMC1 InterfaceSwitchingCharacteristics—Standard SD Mode (7) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX Standard SD Mode SD1 tc(clk) Frequency(1),outputclockperiod 24 12 MHz SD2 tW(clkH) Typicalpulseduration,outputclockhigh X(4)*PO (2) X(4)*PO (2) ns SD2 tW(clkL) Typicalpulseduration,outputclocklow Y(5)*PO (2) Y(5)*PO (2) ns tdc(clk) Dutycycleerror,outputclock 2083.33 4166.67 ps tJ(clk) Jitterstandarddeviation(3),outputclock 200 200 ps MMC1 Interface(1.8-V) tR(clk) Risetime,outputclock 10 10 ns tF(clk) Falltime,outputclock 10 10 ns tR(data) Risetime,outputdata 10 10 ns tF(data) Falltime,outputdata 10 10 ns SD5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd 6.13 35.53 6.3 77.03 ns transition SD6 td(CLKOH-DATx) Delaytime,mmc1_clk risingclockedge to 6.13 35.53 6.3 77.03 ns mmc1_datn:0transition MMC1 Interface(3.0-V) tR(clk) Risetime,outputclock 10 10 ns tF(clk) Falltime,outputclock 10 10 ns tR(data) Risetime,outputdata 10 10 ns tF(data) Falltime,outputdata 10 10 ns SD5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd 6.13 35.53 6.3 77.03 ns transition SD6 td(CLKOH-DATx) Delaytime,mmc1_clk risingclockedge to 6.13 35.53 6.3 77.03 ns mmc1_datn:0transition (1) Relatedwiththeoutputclockmaximum and minimum frequenciesprogrammableinMMC module. (2) PO = outputclockperiodinns (3) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (4) The X parameterisdefinedas follows: CLKD X 1 orEven 0.5 Odd (trunk[CLKD/2]+1)/CLKD Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 251 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

mmc1_clk mmc1_cmd mmc1_dat[n:0] SD3 SD7 SD4 SD8 SD1 SD2 SWPS038-099 mmc1_clk mmc1_cmd mmc1_dat[n:0] SD1 SD2 SD5 SD6 SD5 SD6 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com AllrequireddetailsaboutclockdivisionfactorCLKD can be foundintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (5) The Y parameterisdefinedas follows: CLKD Y 1 orEven 0.5 Odd (trunk[CLKD/2])/CLKD AllrequireddetailsaboutclockdivisionfactorCLKD can be foundintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (6) Inmmc1_dat[n:0],n isequalto3. (7) See Section4.3.4,ProcessorClocks. Figure6-67.MMC1 Interface—Standard SD Mode —Data/Command Receive Figure6-68.MMC1 Interface—Standard SD Mode —Data/Command Transmit 6.6.8.1.4MMC1 Interface—Standard MMC and MMC IdentificationModes Table6-119 and Table6-120 assume testingovertherecommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-69and Figure6-70).

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-118.MMC1 InterfaceTiming Conditions—Standard MMC and MMC IdentificationModes TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 3 ns tF Inputsignalfalltime 3 ns Output Conditions C LOAD Outputloadcapacitance(1) 30 pF (1) Bufferstrengthconfiguration:SPEEDCTRL = 1. Table6-119.MMC1 InterfaceTiming Requirements—Standard MMC and MMC IdentificationModes (2)(3)(4) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC1 Interface(1.8-VIO) MMC3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk rising 13.6 55.1 ns clockedge MMC4 th(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk rising 7.7 7.5 ns clockedge MMC7 tsu(DATxV-CLKIH) Setuptime,mmc1_datn:0validbeforemmc1_clk 13.6 55.1 ns risingclockedge MMC8 th(CLKIH-DATxIV) Holdtime,mmc1_datn:0validaftermmc1_clk 7.7 7.5 ns risingclockedge MMC1 Interface(3.0-VIO) MMC3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk rising 13.6 55.1 ns clockedge MMC4 th(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk rising 7.7 7.5 ns clockedge MMC7 tsu(DATxV-CLKIH) Setuptime,mmc1_datn:0validbeforemmc1_clk 13.6 55.1 ns risingclockedge MMC8 th(CLKIH-DATxIV) Holdtime,mmc1_datn:0validaftermmc1_clk 7.7 7.5 ns risingclockedge (1) Inmmc1_dat[n:0],n isequalto3. (2) TimingparametersarereferredtooutputclockspecifiedinTable6-120. (3) The timingrequirementsareassuredforthecyclejitterand dutycycleerrorconditionsspecifiedinTable6-120. (4) See Section4.3.4,ProcessorClocks. Table6-120.MMC1 InterfaceSwitchingCharacteristics—Standard MMC and MMC IdentificationModes (7) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC IdentificationMode MMC1 1/tc(clk) Frequency(1),outputclkperiod 0.4 0.4 MHz MMC2 tW(clkH) Typicalpulseduration,outputclkhigh X(5)*PO (2) X(5)*PO (2) ns MMC2 tW(clkL) Typicalpulseduration,outputclklow Y(6)*PO (2) Y(6)*PO (2) ns tdc(clk) Dutycycleerror,outputclk 125 125 ns tJ(clk) Jitterstandarddeviation(3),outputclk 200 200 ps Standard MMC IdentificationMode MMC1 tc(clk) Frequency(1),outputclkperiod 24 12 MHz MMC2 tW(clkH) Typicalpulseduration,outputclkhigh X(5)*PO (2) X(5)*PO (2) ns MMC2 tW(clkL) Typicalpulseduration,outputclklow Y(6)*PO (2) Y(6)*PO (2) ns tdc(clk) Dutycycleerror,outputclk 2083.3 4166.7 ps tJ(clk) Jitterstandarddeviation(3),outputclk 200 200 ps MMC1 Interface(1.8-VIO) tR(clk) Risetime,outputclk 10 10 ns Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 253 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

mmc1_clk mmc1_cmd mmc1_dat[3:0] MMC3 MMC7 MMC4 MMC8 MMC1 MMC2 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-120.MMC1 InterfaceSwitchingCharacteristics—Standard MMC and MMC IdentificationModes (7) (continued) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX tF(clk) Falltime,outputclk 10 10 ns tR(data) Risetime,outputdata 10 10 ns tF(data) Falltime,outputdata 10 10 ns MMC5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd 4.1 37.6 4.3 79 ns transition MMC6 td(CLKOH-DATx) Delaytime,mmc1_clk risingclockedge to 4.1 37.6 4.3 79 ns mmc1_datn:0transition MMC1 Interface(3.0-VIO) tR(clk) Risetime,outputclk 10 10 ns tF(clk) Falltime,outputclk 10 10 ns tR(data) Risetime,outputdata 10 10 ns tF(data) Falltime,outputdata 10 10 ns MMC5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd 4.1 37.6 4.3 79 ns transition MMC6 td(CLKOH-DATx) Delaytime,mmc1_clk risingclockedge to 4.1 37.6 4.3 79 ns mmc1_datn:0transition (1) Relatedwiththeoutputclockmaximum and minimum frequenciesprogrammableinMMC module. (2) PO = outputclockperiodinns (3) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (4) Inmmc1_dat[n:0],n isequalto3. (5) The X parameterisdefinedas follows: CLKD X 1 orEven 0.5 Odd (trunk[CLKD/2]+1)/CLKD AllrequireddetailsaboutclockdivisionfactorCLKD can be foundintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (6) The Y parameterisdefinedas follows: CLKD Y 1 orEven 0.5 Odd (trunk[CLKD/2])/CLKD AllrequireddetailsaboutclockdivisionfactorCLKD can be foundintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (7) See Section4.3.4,ProcessorClocks. Figure6-69.MMC1 Interface—Standard MMC and MMC IdentificationModes —Data/Command Receive

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mmc1_clk mmc1_cmd mmc1_dat[3:0] MMC5 MMC5 MMC6 MMC6 MMC1 MMC2 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Figure6-70.MMC1 Interface—Standard MMC and MMC IdentificationModes —Data/Command Transmit 6.6.8.1.5MMC1 Interface—High-Speed MMC Mode Table6-122 and Table6-123 assume testingovertherecommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-71and Figure6-72). Table6-121.MMC1 InterfaceTiming Conditions—High-Speed MMC Mode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 3 ns tF Inputsignalfalltime 3 ns Output Conditions C LOAD Outputloadcapacitance(1) 30 pF (1) The loadsettingoftheIO buffer:SPEEDCTRL = 1. Table6-122.MMC1 InterfaceTiming Requirements—High-Speed MMC Mode (2)(3)(4)(5) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC1 Interface(1.8-VIO) MMC3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk rising 5.6 26.0 ns clockedge MMC4 th(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk rising 2.3 1.9 ns clockedge MMC7 tsu(DATxV-CLKIH) Setuptime,mmc1_datn:0validbeforemmc1_clk 5.6 26.0 ns risingclockedge MMC8 th(CLKIH-DATxIV) Holdtime,mmc1_datn:0validaftermmc1_clk 2.3 1.9 ns risingclockedge MMC1 Interface(3.0-VIO) MMC3 tsu(CMDV-CLKIH) Setuptime,mmc1_cmd validbeforemmc1_clk rising 5.6 26.0 ns clockedge MMC4 th(CLKIH-CMDIV) Holdtime,mmc1_cmd validaftermmc1_clk rising 2.3 1.9 ns clockedge MMC7 tsu(DATxV-CLKIH) Setuptime,mmc1_datn:0validbeforemmc1_clk 5.6 26.0 ns risingclockedge MMC8 th(CLKIH-DATxIV) Holdtime,mmc1_datn:0validaftermmc1_clk 2.3 1.9 ns risingclockedge (1) Inmmc1_dat[n:0],n isequalto3. (2) TimingparametersarereferredtooutputclockspecifiedinTable6-123. (3) The timingrequirementsareassuredforthecyclejitterand dutycycleerrorconditionsspecifiedinTable6-123. (4) Correspondingfiguresshowingtimingparametersarecommon withtheStandardMMC mode figures. (5) See Section4.3.4,ProcessorClocks. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 255 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-123.MMC1 InterfaceSwitchingCharacteristics—High-Speed MMC Mode (4)(8) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC1 tc(clk) Frequency(1),outputclkperiod 48 24 MHz MMC2 tW(clkH) Typicalpulseduration,outputclkhigh X(6)*PO (2) X(6)*PO (2) ns MMC2 tW(clkL) Typicalpulseduration,outputclklow Y(7)*PO (2) Y(7)*PO (2) ns tdc(clk) Dutycycleerror,outputclk 1041.7 2083.3 ps tJ(clk) Jitterstandarddeviation(3),outputclk 200 200 ps MMC1 Interface(1.8-VIO) tR(clk) Risetime,outputclk 3 3 ns tF(clk) Falltime,outputclk 3 3 ns tR(data) Risetime,outputdata 3 3 ns tF(data) Falltime,outputdata 3 3 ns MMC5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd 3.7 14.1 4.1 34.5 ns transition MMC6 td(CLKOH-DATx) Delaytime,mmc1_clk risingclockedge to 3.7 14.1 4.1 34.5 ns mmc1_datn:0transition MMC1 Interface(3.0-VIO) tR(clk) Risetime,outputclk 3 3 ns tF(clk) Falltime,outputclk 3 3 ns tR(data) Risetime,outputdata 3 3 ns tF(clk) Falltime,outputdata 3 3 ns MMC5 td(CLKOH-CMD) Delaytime,mmc1_clk risingclockedge tommc1_cmd 3.7 14.1 4.1 34.5 ns transition MMC6 td(CLKOH-DATx) Delaytime,mmc1_clk risingclockedge to 3.7 14.1 4.1 34.5 ns mmc1_datn:0transition (1) Relatedwiththeoutputclockmaximum and minimum frequenciesprogrammableinMMC module. (2) PO = outputclockperiodinns (3) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (4) Correspondingfiguresshowingtimingparametersarecommon withtheStandardMMC mode figures. (5) InMMC1_dat[n:0],n isequalto3. (6) The X parameterisdefinedas follows: CLKD X 1 orEven 0.5 Odd (trunk[CLKD/2]+1)/CLKD AllrequireddetailsaboutclockdivisionfactorCLKD can be foundintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (7) The Y parameterisdefinedas follows: CLKD Y 1 orEven 0.5 Odd (trunk[CLKD/2])/CLKD AllrequireddetailsaboutclockdivisionfactorCLKD can be foundintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (8) See Section4.3.4,ProcessorClocks.

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mmc1_clk mmc1_cmd mmc1_dat[3:0] MMC3 MMC7 MMC4 MMC8 MMC1 MMC2 SWPS038-101 mmc1_clk mmc1_cmd mmc1_dat[3:0] MMC5 MMC5 MMC6 MMC6 MMC1 MMC2 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Figure6-71.MMC1 Interface—High-Speed MMC Mode —Data/Command Receive Figure6-72.MMC1 Interface—High-Speed MMC Mode —Data/Command Transmit 6.6.8.1.6MMC2 and MMC3 Interfaces—SDIO IdentificationMode Table6-125 and Table6-126 assume testingovertherecommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-73and Figure6-74). Table6-124.MMC2 and MMC3 InterfacesTiming Conditions—SDIO IdentificationMode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 10 ns tF Inputsignalfalltime 10 ns Output Condition C LOAD Outputloadcapacitance(1) 5 pF (1) Bufferstrengthconfiguration:LB0 = 0 Table6-125.MMC2 and MMC3 InterfacesTiming Requirements—SDIO IdentificationMode (1)(2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC2 and MMC3 Interface(1.8-VIO) SD3 tsu(CMDV-CLKIH) Setuptime,mmcx_cmd validbefore 1198.4 1198.4 ns mmcx_clk risingclockedge SD4 th(CLKIH-CMDIV) Holdtime,mmcx_cmd validaftermmcx_clk 1249.2 1249.2 ns risingclockedge (1) See Section4.3.4,ProcessorClocks. (2) Inmmcx, x isequalto2 or3. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 257 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Table6-126.MMC2 and MMC3 InterfacesSwitchingCharacteristics—SDIO IdentificationMode (4)(7)(7) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX Standard SDIO Mode SD1 tc(clk) Frequency(1),outputclockperiod 0.4 0.4 MHz SD2 tW(clkH) Typicalpulseduration,outputclockhigh X(5)* X(5)* ns PO (2) PO (2) SD2 tW(clkL) Typicalpulseduration,outputclocklow Y(6)* Y(6)* ns PO (2) PO (2) tdc(clk) Dutycycleerror,outputclock 125 125 ns tJ(clk) Jitterstandarddeviation(3),outputclock 200 200 ps tR(clk) Risetime,outputclock 10 10 ns tF(clk) Falltime,outputclock 10 10 ns tR(data) Risetime,outputdata 10 10 ns tF(data) Falltime,outputdata 10 10 ns SD5 td(CLKOH-CMD) Delaytime,mmcx_clk risingclockedge to 6.3 2492.7 6.3 77.03 ns mmcx_cmd transition (1) Relatedtotheoutputmmcx_clk maximum and minimum frequency. (2) P = outputmmcx_clk periodinns (3) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (4) Correspondingfiguresshowingtimingparametersarecommon withotherinterfacemodes (seeSDIO, HS SDIO modes). (5) The X parameterisdefinedas follows: CLKD X 1 orEven 0.5 Odd (trunk[CLKD/2]+1)/CLKD AllrequireddetailsaboutclockdivisionfactorCLKD can be foundintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (6) The Y parameterisdefinedas follows: CLKD Y 1 orEven 0.5 Odd (trunk[CLKD/2])/CLKD AllrequireddetailsaboutclockdivisionfactorCLKD can be foundintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (7) Inmmcx, x isequalto2 or3. 6.6.8.1.7MMC2 and MMC3 Interfaces—High-Speed SDIO Mode Table6-128 and Table6-129 assume testingovertherecommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-73and Figure6-74). Table6-127.MMC2 and MMC3 InterfacesTiming Conditions—High-Speed SDIO Mode TIMING CONDITION PARAMETER VALUE UNIT MIN MAX InputConditions tR Inputsignalrisetime 0.18 5.69 ns tF Inputsignalfalltime 0.19 5.70 ns Output Condition C LOAD Outputloadcapacitance(1) 5 pF

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mmcx_clk mmcx_cmd mmcx_dat[n:0] HSSD4 HSSD8 HSSD3 HSSD7 HSSD1 HSSD2HSSD2 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) BufferstrengthconfigurationforMMC2 and MMC3: LB0 = 0. Table6-128.MMC2 and MMC3 InterfacesTiming Requirements—High-Speed SDIO Mode (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX HSSD3 tsu(dV-clkH) Setuptime,mmcx_cmd validbeforemmcx_clk rising 3.4 23.8 ns clockedge HSSD4 th(clkH-dV) Holdtime,mmcx_cmd validaftermmcx_clk rising 1.7 1.3 ns clockedge HSSD7 tsu(dV-clkH) Setuptime,mmcx_datn:0validbeforemmcx_clk 3.4 23.8 ns risingclockedge HSSD8 th(clkH-dV) Holdtime,mmcx_datn:0validaftermmcx_clk rising 1.7 1.3 ns clockedge (1) Inmmcx_dat[n:0],n isequalto3 formmc2 and 7 formmc3. (2) See Section4.3.4,ProcessorClocks. Table6-129.MMC2 and MMC3 InterfacesSwitchingCharacteristics—High-Speed SDIO Mode (2)(5) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX HSSD1 tc(clk) Frequency(1),outputmmcx_clk period 48 24 MHz HSSD2 tW(clkH) Typicalpulseduration,outputmmcx_clk high 0.5*P(3) 0.5*P(3) ns HSSD2 tW(clkL) Typicalpulseduration,outputmmcx_clk low 0.5*P(3) 0.5*P(3) ns tdc(clk) Dutycycleerror,outputmmcx_clk –1042 1042 –2083 2083 ps tJ(clk) Jitterstandarddeviation(4),outputmmcx_clk –65 65 –65 65 ps HSSD5 td(clkL-doV) Delaytime,mmcx_clk risingclockedge tommcx_cmd 2.6 13.8 3 34.3 ns transition HSSD6 td(clkL-doV) Delaytime,mmcx_clk risingclockedge to 2.6 13.8 3 34.3 ns mmcx_datn:0transition (1) Relatedwiththeoutputmmcx_clk maximum and minimum frequency. (2) Inmmcx, x = 2 or3.Inmmcx_dat[n:0],n isequalto3 formmc2 and 7 formmc3. (3) P = outputmmcx_clk periodinns. (4) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (5) See Section4.3.4,ProcessorClocks. Figure6-73.MMC2 and MMC3 Interfaces—High-Speed SDIO Mode —Data/Command Receive(1) (1) Inmmcx, x = 2 or3.Inmmcx_dat[n:0],n isequalto3 formmc2 and 7 formmc3. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 259 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

mmcx_clk mmcx_cmd mmcx_dat[n:0] HSSD5 HSSD5 HSSD6 HSSD6 HSSD1 HSSD2HSSD2 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Figure6-74.MMC2 and MMC3 Interfaces—High-Speed SDIO Mode —Data/Command Transmit(1) (1) Inmmcx, x = 2 or3.Inmmcx_dat[n:0],n isequalto3 formmc2 and 7 formmc3. 6.6.8.1.8MMC2 and MMC3 Interfaces—Standard SDIO Mode Table6-131 and Table6-132 assume testingovertherecommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure5-89and Figure5-90). Table6-130.MMC2 and MMC3 InterfacesTiming Conditions—Standard SDIO Mode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 10 ns tF Inputsignalfalltime 10 ns Output Condition C LOAD Outputloadcapacitance(1) 5 pF (1) Bufferstrengthconfiguration:SPEEDCTRL = 1 Table6-131.MMC2 and MMC3 InterfacesTiming Requirements—Standard SDIO Mode (2)(3) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC2 and MMC3 Interface(1.8-VIO) SD3 tsu(CMDV-CLKIH) Setuptime,mmcx_cmd validbefore 3.3 21.9 ns mmcx_clk risingclockedge SD4 th(CLKIH-CMDIV) Holdtime,mmcx_cmd validaftermmcx_clk 18.1 36.7 ns risingclockedge SD7 tsu(DATxV-CLKIH) Setuptime,mmcx_datn:0validbefore 3.3 21.9 ns mmcx_clk risingclockedge SD8 th(CLKIH-DATxIV) Holdtime,mmcx_datn:0validafter 18.1 36.7 ns mmcx_clk risingclockedge (1) Inmmcx_dat[n:0],n isequalto3 forMMC2 and 7 forMMC3. (2) See Section4.3.4,ProcessorClocks. (3) Inmmcx, x isequalto2 or3. Table6-132.MMC2 and MMC3 InterfacesSwitchingCharacteristics—Standard SDIO Mode (6)(7) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX Standard SDIO Mode SD1 tc(clk) Frequency(1),outputclockperiod 24 12 MHz SD2 tW(clkH) Typicalpulseduration,outputclockhigh X(4)* X(4)* ns PO (2) PO (2) SD2 tW(clkL) Typicalpulseduration,outputclocklow Y(5)* Y(5)* ns PO (2) PO (2) tdc(clk) Dutycycleerror,outputclock 2083.33 4166.67 ps

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mmc1_clk mmc1_cmd mmc1_dat[n:0] SD3 SD7 SD4 SD8 SD1 SD2 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-132.MMC2 and MMC3 InterfacesSwitchingCharacteristics—Standard SDIO Mode (6)(7)(continued) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX tJ(clk) Jitterstandarddeviation(3),outputclock 200 200 ps tR(clk) Risetime,outputclock 10 10 ns tF(clk) Falltime,outputclock 10 10 ns tR(data) Risetime,outputdata 10 10 ns tF(data) Falltime,outputdata 10 10 ns SD5 td(CLKOH-CMD) Delaytime,mmcx_clk risingclockedge to 6.13 35.53 6.3 77.03 ns mmcx_cmd transition SD6 td(CLKOH-DATx) Delaytime,mmcx_clk risingclockedge to 6.13 35.53 6.3 77.03 ns mmcx_datn:0transition (1) Relatedtotheoutputmmcx_clk maximum and minimum frequency. (2) P = outputmmcx_clk periodinns (3) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (4) The X parameterisdefinedas follows: CLKD X 1 orEven 0.5 Odd (trunk[CLKD/2]+1)/CLKD AllrequireddetailsaboutclockdivisionfactorCLKD can be foundintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (5) The Y parameterisdefinedas follows: CLKD Y 1 orEven 0.5 Odd (trunk[CLKD/2])/CLKD AllrequireddetailsaboutclockdivisionfactorCLKD can be foundintheAM/DM37x MultimediaDeviceTechnicalReferenceManual (literaturenumber SPRUGN4 ). (6) Inmmcx, x isequalto2 or3.Inmmcx_dat[n :0]isequalto3 formmc2 and 7 formmc3. (7) See Section4.3.4,ProcessorClocks. Figure6-75.MMC2 and MMC3 Interfaces—Standard SDIO Mode —Data/Command Receive(1) (1) Inmmcx, x isequalto2 or3.Inmmcx_dat[n:0]isequalto3 forMMC2 and 7 forMMC3. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 261 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

mmc1_clk mmc1_cmd mmc1_dat[n:0] SD1 SD2 SD5 SD6 SD5 SD6 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com Figure6-76.MMC2 and MMC3 Interfaces—Standard SDIO Mode —Data/Command Transmit(1) (1) Inmmcx, x isequalto2 or3.Inmmcx_dat[n:0]isequalto3 forMMC2 and 7 forMMC3. 6.6.8.1.9MMC2 and MMC3 Interfaces—Embedded Media Interface(eMMC) —High-Speed JC64 Mode Table6-134 and Table6-135 assume testingovertherecommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-77throughFigure6-78). Table6-133.MMC2 and MMC3 InterfacesTiming Conditions—High-Speed JC64 Mode TIMING CONDITION PARAMETER VALUE UNIT MIN MAX InputConditions tR Inputsignalrisetime 0.38 3.82 ns tF Inputsignalfalltime 0.39 3.68 ns Output Condition C LOAD Outputloadcapacitance(1) 14 pF (1) BufferstrengthconfigurationforMMC3: LB0 = 1. Table6-134.MMC2 and MMC3 InterfacesTiming Requirements—High-Speed JC64 Mode (1) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC3 tsu(cmdV-clkH) Setuptime,inputcommand mmcx_cmd validbefore 5.1 25.5 ns outputclockmmcx_clk risingedge MMC4 th(clkH-cmdIV) Holdtime,inputcommand mmcx_cmd validafter 1.3 0.9 ns outputclockmmcx_clk risingedge MMC7 tsu(dV-clkH) Setuptime,inputdatammcx_dat[n:0]validbefore 5.1 25.5 ns outputclockmmcx_clk risingedge MMC8 th(clkH-dIV) Holdtime,inputdatammcx_dat[n:0]validafteroutput 1.3 0.9 ns clockmmcx_clk risingedge (1) Inmmx_dat[n:0],x isequalto2 or3 and n isequalto7. (2) Inmmx_cmd, x isequalto2 or3. (3) Inmmx_clk,x isequalto2 or3. Table6-135.MMC2 and MMC3 InterfacesSwitchingCharacteristics—High-Speed JC64 Mode (5)(6)(7) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC1 1/tc(clk) Frequency(1),outputmmcx_clk period 48 24 MHz MMC2 tW(clkH) Typicalpulseduration,outputmmcx_clk high 0.5*P(2) 0.5*P(2) ns MMC2 tW(clkL) Typicalpulseduration,outputmmcx_clk low 0.5*P(2) 0.5*P(2) ns tdc(clk) Dutycycleerror,outputmmcx_clk –1042 1042 –2083 2083 ps tJ(clk) Jitterstandarddeviation(3),outputmmcx_clk –65 65 –65 65 ps tR(clk) Risingtime,outputmmcx_clk 2263 2263 ps tF(clk) Fallingtime,outputmmcx_clk 2136 2136 ps

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mmcx_clk mmcx_cmd mmcx_dat[n:0] MMC5 MMC5 MMC6 MMC6 MMC1 MMC2MMC2 SWPS038-105 mmcx_clk mmcx_cmd mmcx_dat[n:0] MMC4 MMC8 MMC3 MMC7 MMC1 MMC2MMC2 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-135.MMC2 and MMC3 InterfacesSwitchingCharacteristics—High-Speed JC64 Mode (5) (6)(7)(continued) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX MMC5 td(clkL-doV) Delaytime,mmcx_clk risingclockedge tommcx_cmd 3.6 16.8 4 37.2 ns transition tR(do) Risingtime,outputmmcx_cmd 2263 2263 ps tF(do) Fallingtime,outputmmcx_cmd 2136 2136 ps MMC6 td(clkL-doV) Delaytime,mmcx_clk risingclockedge tommcx_daty 3.6 16.8 4 37.2 ns transition tR(do) Risingtime,outputmmcx_datn:0 2263 2263 ps tF(do) Fallingtime,outputmmcx_datn:0 2136 2136 ps (1) Relatedwiththeoutputclockmaximum and minimum frequenciesprogrammableinMMC module. (2) PO = outputclockperiodinns (3) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (4) Inmmx_dat[n:0],x isequalto2 or3 and n isequalto7. (5) See Section4.3.4,ProcessorClocks. (6) Inmmx_cmd, x isequalto2 or3. (7) Inmmx_clk,x isequalto2 or3. Figure6-77.MMC2 and MMC3 Interfaces—High-Speed JC64 TransmiterMode (1)(2)(3) (1) Inmmx_dat[n:0],x isequalto2 or3 and n isequalto7. (2) Inmmx_cmd, x isequalto2 or3. (3) Inmmx_clk,x isequalto2 or3. Figure6-78.MMC2 and MMC3 Interfaces—High-Speed JC64 ReceiverMode (1)(2)(3) (1) Inmmx_dat[n:0],x isequalto2 or3 and n isequalto7. (2) Inmmx_cmd, x isequalto2 or3. (3) Inmmx_clk,x isequalto2 or3. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 263 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

etk_clk etk_ctl etk_d[15:0] TPIU1 TPIU2 TPIU3 TPIU4 TPIU5 TPIU5 TPIU4 SWPS038-106 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com

6.6.9 TestInterfaces

6.6.9.1 Embedded Trace Macro Interface(ETM)

Table 6-137 assumes testingover the recommended operatingconditionsand electricalcharacteristic conditionsbelow(seeFigure6-79). Table6-136.ETM Timing Conditions—TransmitMode TIMING CONDITION PARAMETER VALUE UNIT MIN MAX Output Condition C LOAD Outputloadcapacitance(1) 10 pF (1) Bufferstrengthconfiguration:LB0 = 1. Table6-137.ETM SwitchingCharacteristics—TransmitMode (4) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX TPIU1 1 /tc(clk) Frequency(3),outputclocketk_clk 166 166 MHz TPIU2 tw(clkH) Pulseduration,outputclocketk_clkhigh 0.5P(1) 0.5P(1) ns TPIU3 tw(clkL) Pulseduration,outputclocketk_clklow 0.5P(1) 0.5P(1) ns tdc(clk) Dutycycleerror,outputclocketk_clk –301 301 –301 301 ps tJ(clk) Jitterstandarddeviation(2),outputclocketk_clk 65 65 ps tR(clk) Risetime,outputclocketk_clk 1.2 1.2 ns tF(clk) Falltime,outputclocketk_clk 1.2 1.2 ns TPIU4 td(clk-ctl) Delaytime,outputclocketk_clklow/hightooutput 0.839 0.839 ns controletk_ctltransition TPIU5 td(clkH-d) Delaytime,outputclocketk_clklow/hightooutput 0.839 0.839 ns dataetk_d[15:0]transition tR(d/ctl) Risetime,outputdataetk_d[15:0]and outputcontrol 1.2 1.2 ns etk_ctl tF(d/ctl) Falltime,outputdataetk_d[15:0]and outputcontrol 1.2 1.2 ns etk_ctl (1) P = etk_clkperiodinns (2) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (3) Relatedwiththeetm_clkmaximum frequency. (4) See Section4.3.4,ProcessorClocks. Figure6-79.ETM —TransmitMode

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sdti_clk sdti_txd[3:0] Header Header Ad[7:4] Ad[3:0] Da[15:12] Da[1 1:8] Da[7:4] Da[3:0] SD1 SD2 SD3 SD3 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011

6.6.9.2 System Debug Trace Interface(SDTI)

The System Debug TraceInterface(SDTI)module providesreal-timesoftwaretracingfunctionalitytothe device.The traceinterfacehas fourtracedatapinsand a traceclockpin. Thisinterfaceisa dual-edgeinterface:

• The dataareavailableon risingand fallingedge ofsdti_clk.
• But can be also configuredin single-edgemode where data are availableon the fallingedge of sdti_clk. Serialinterfaceoperatesinclockstopregime:serialclockisnotfree-running;when thereisno tracedata, thereisno traceclock. 6.6.9.2.1SDTI—Dual-Edge Mode Table 6-139 assumes testingover the recommended operatingconditionsand electricalcharacteristic conditionsbelow(seeFigure6-80). Table6-138.SDTI Timing Conditions—Dual-Edge Mode TIMING CONDITION PARAMETER VALUE UNIT Output Condition C LOAD Outputloadcapacitance(1) 25 pF (1) Bufferstrengthconfiguration:LB0 = 1. Table6-139.SDTI SwitchingCharacteristics—Dual-Edge Mode (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX SD1 1 /tc(clk) Frequency,outputclocksdti_clk 34.5 34.5 MHz SD2 tw(clk) Pulseduration,outputclocksdti_clkhighorlow 0.5P(1)– 0.5P(1)+ 0.5P(1)– 0.5P(1)+ ns 1.2 1.2 1.2 1.2 SD3 td(clk-txd) Delaytime,outputclocksdti_clk Multiplexingmode on 2.3 10.9 2.3 10.9 ns transitiontooutputdata etkpins sdti_txd[3:0]transition Multiplexingmode on 2.3 13.9 2.3 13.9 jtag_emupins (1) P = sdti_clkclockperiodinns (2) See Section4.3.4,ProcessorClocks. Figure6-80.SDTI—Dual-Edge Mode Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 265 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

sdti_clk sdti_txd[3:0] Header Header Ad[7:4] Ad[3:0] Da[15:12] Da[1 1:8] Da[7:4] Da[3:0] SD1 SD2 SD3 SD3 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com 6.6.9.2.2SDTI—Single-EdgeMode Table 6-141 assumes testingover the recommended operatingconditionsand electricalcharacteristic conditionsbelow(seeFigure6-81). Table6-140.SDTI Timing Conditions—Single-EdgeMode TIMING CONDITION PARAMETER VALUE UNIT Output Condition C LOAD Outputloadcapacitance(1) 25 pF (1) Bufferstrengthconfiguration:LB0 = 1. Table6-141.SDTI SwitchingCharacteristics—Single-EdgeMode (2) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX SD1 1 /tc(clk) Frequency,outputclocksdti_clk 34.5 34.5 MHz SD2 tw(clk) Pulseduration,outputclocksdti_clkhighorlow 0.5P(1)– 0.5P(1)+ 0.5P(1)– 0.5P(1)+ ns 1.2 1.2 1.2 1.2 SD3 td(clk-txd) Delaytime,outputclocksdti_clk Multiplexingmode on 2.3 26.5 2.3 26.5 ns transitiontooutputdata etkpins sdti_txd[3:0]transition Multiplexingmode on 2.3 33.2 2.3 33.2 jtag_emupins (1) P = sdti_clkclockperiodinns (2) See Section4.3.4,ProcessorClocks. Figure6-81.SDTI—Single-EdgeMode

6.6.9.3 JTAG Interface(JTAG)

The JTAG TAP controllerhandlesstandardIEEE JTAG interfaces.The followingsectiondefinesthe timingrequirementsforseveraltoolsused totestthedeviceas:

• Free-runningclocktool,likeXDS560 and XDS510 tools
• Adaptiveclocktool,likeRealView® ICE tooland LauterbachTM tool 6.6.9.3.1JTAG —Free-RunningClock Mode Table6-143 and Table6-144 assume testingovertherecommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-82). Table6-142.JTAG Timing Conditions—Free-RunningClock Mode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 5 ns tF Inputsignalfalltime 5 ns Output Condition C LOAD Outputloadcapacitance 30 pF

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DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Table6-143.JTAG Timing Requirements—Free-RunningClock Mode (5)(6) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX JT4 1 /tc(tck) Frequency(1),inputclockjtag_tck 50 50 MHz JT5 tw(tckL) Pulseduration,inputclockjtag_tcklow 0.5P(2) 0.5P(2) ns JT6 tw(tckH) Pulseduration,inputclockjtag_tckhigh 0.5P(2) 0.5P(2) ns tdc(tck) Dutycycleerror,inputclockjtag_tck –1250 1250 –1667 1667 ps tJ(tck) Cyclejitter(3),inputclockjtag_tck –1250 1250 –1667 1667 ps JT7 tsu(tdiV-rtckH) Setuptime,inputdatajtag_tdivalidbeforeoutput 1.6 1.6 ns clockjtag_rtckhigh JT8 th(tdiV-rtckH) Holdtime,inputdatajtag_tdivalidafteroutputclock 0.7 1.0 ns jtag_rtckhigh JT9 tsu(tmsV-rtckH) Setuptime,inputmode selectjtag_tms_tmscvalid 1.6 1.6 ns beforeoutputclockjtag_rtckhigh JT10 th(tmsV-rtckH) Holdtime,inputmode selectjtag_tms_tmscvalidafter 0.7 1.0 ns outputclockjtag_rtckhigh JT12 tsu(emuxV-rtckH) Setuptime,inputemulationjtag_emux(4)validbefore 14.4 19.6 ns outputclockjtag_rtckhigh JT13 th(emuxV-rtckH) Holdtime,inputemulationjtag_emux(4)validafter 2.0 2.7 ns outputclockjtag_rtckhigh (1) Relatedwiththeinputmaximum frequencysupportedby theJTAG module. (2) P = inputclockjtag_tckperiodinns (3) Maximum cyclejittersupportedby inputclockjtag_tck. (4) Injtag_emux,x isequalto0 or1. (5) The timingrequirementsareassuredforthecyclejitterand dutycycleerrorconditionsspecified. (6) See Section4.3.4,ProcessorClocks. Table6-144.JTAG SwitchingCharacteristics—Free-RunningClock Mode (5) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX JT1 1 /tc(rtck) Frequency(1),outputclockjtag_rtck 50 50 MHz JT2 tw(rtckL) Pulseduration,outputclockjtag_rtcklow 0.5P(2) 0.5P(2) ns JT3 tw(rtckH) Pulseduration,outputclockjtag_rtckhigh 0.5P(2) 0.5P(2) ns tdc(rtck) Dutycycleerror,outputclockjtag_rtck –1250 1250 –1667 1667 ps tJ(rtck) Jitterstandarddeviation(3),outputclockjtag_rtck 33.3 33.3 ps tR(rtck) Risetime,outputclockjtag_rtck 0 0 ns tF(rtck) Falltime,outputclockjtag_rtck 0 0 ns JT11 td(rtckL-tdoV) Delaytime,outputclockjtag_rtcklowtooutputdata –5.8 5.8 –7.9 7.9 ns jtag_tdovalid tR(tdo) Risetime,outputdatajtag_tdo 0 0 ns tF(tdo) Falltime,outputdatajtag_tdo 0 0 ns JT14 td(rtckH-emuxV) Delaytime,outputclockjtag_rtckhightooutput 2.7 15.1 2.7 20.4 ns emulation,jtag_emux(4)valid (1) Relatedwiththejtag_rtckmaximum frequency. (2) P = outputclockjtag_rtckperiodinns (3) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (4) Injtag_emux,x isequalto0 or1. (5) See Section4.3.4,ProcessorClocks. Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 267 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

jtag_tck jtag_rtck jtag_tdi jtag_tms_tmsc jtag_emux(IN) jtag_tdo jtag_emux(OUT) JT7 JT1 1 JT1 JT2 JT3 JT8 JT10JT9 JT4 JT5 JT6 JT12 JT13 JT14 SWPS038-109 DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com (1) Injtag_emux,x isequalto0 or1. Figure6-82.JTAG —Free-RunningClock Mode 6.6.9.3.2JTAG —AdaptativeClock Mode Table6-146 and Table6-147 assume testingovertherecommended operatingconditionsand electrical characteristicconditionsbelow(seeFigure6-83). Table6-145.JTAG Timing Conditions—AdaptativeClock Mode TIMING CONDITION PARAMETER VALUE UNIT InputConditions tR Inputsignalrisetime 5 ns tF Inputsignalfalltime 5 ns Output Condition C LOAD Outputloadcapacitance 30 pF Table6-146.JTAG Timing Requirements—AdaptativeClock Mode (4)(5) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX JA4 1 /tc(tck) Frequency(1),inputclockjtag_tck 50 50 MHz JA5 tw(tckL) Pulseduration,inputclockjtag_tcklow 0.5P(2) 0.5P(2) ns JA6 tw(tckH) Pulseduration,inputclockjtag_tckhigh 0.5P(2) 0.5P(2) ns tdc(lclk) Dutycycleerror,inputclockjtag_tck –2500 2500 –2500 2500 ps tJ(lclk) Cyclejitter(3),inputclockjtag_tck –1500 1500 –1500 1500 ps JA7 tsu(tdiV-tckH) Setuptime,inputdatajtag_tdivalidbeforeinputclock 13.8 13.8 ns jtag_tckhigh JA8 th(tdiV-tckH) Holdtime,inputdatajtag_tdivalidafterinputclock 13.8 13.8 ns jtag_tckhigh JA9 tsu(tmsV-tckH) Setuptime,inputmode selectjtag_tms_tmscvalid 13.8 13.8 ns beforeinputclockjtag_tckhigh JA10 th(tmsV-tckH) Holdtime,inputmode selectjtag_tms_tmscvalidafter 13.8 13.8 ns inputclockjtag_tckhigh

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jtag_tck jtag_tdi jtag_tms jtag_rtck jtag_tdo JA1 JA2 JA3 JA4 JA5 JA6 JA7 JA8 JA10JA9 JA1 1 SWPS038-1 10 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 (1) Relatedwiththeinputmaximum frequencysupportedby theJTAG module (2) P = inputclockjtag_tckperiodinns (3) Maximum cyclejittersupportedby inputclockjtag_tck. (4) The timingrequirementsareassuredforthecyclejitterand dutycycleerrorconditionsspecified. (5) See Section4.3.4,ProcessorClocks. Table6-147.JTAG SwitchingCharacteristics—AdaptativeClock Mode (4) NO. PARAMETER OPP100 OPP50 UNIT MIN MAX MIN MAX JA1 1 /tc(rtck) Frequency(1),outputclockjtag_rtck 50 50 MHz JA2 tw(rtckL) Pulseduration,outputclockjtag_rtcklow 0.5P(2) 0.5P(2) ns JA3 tw(rtckH) Pulseduration,outputclockjtag_rtckhigh 0.5P(2) 0.5P(2) ns tdc(rtck) Dutycycleerror,outputclockjtag_rtck –2500 2500 –2500 2500 ps tJ(rtck) Jitterstandarddeviation(3),outputclockjtag_rtck 33.3 33.3 ps tR(rtck) Risetime,outputclockjtag_rtck 0 0 ns tF(rtck) Falltime,outputclockjtag_rtck 0 0 ns JA11 td(rtckL-tdoV) Delaytime,outputclockjtag_rtcklowtooutputdata –14.6 14.6 –14.6 14.6 ns jtag_tdovalid (1) Relatedtothejtag_rtckmaximum frequencyprogrammable. (2) P = outputclockjtag_rtckperiodinns (3) The jitterprobabilitydensitycan be approximatedby a Gaussianfunction. (4) See Section4.3.4,ProcessorClocks. Figure6-83.JTAG —AdaptativeClock Mode Copyright© 2010–2011,Texas InstrumentsIncorporated TimingRequirementsand SwitchingCharacteristics 269 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com

7 Package Characteristics

7.1 Package Thermal Characteristics

Table 7-1 and Table 7-2 providethe thermalresistancecharacteristicsforthe packages used on this device. Note:Thistableprovidessimulationdataand may notrepresentactualuse-casevalues. Table7-1.Thermal ResistanceCharacteristics800MHz ARM Operation-4GbDDR + Flash PACKAGE Power (W)(5) θJA (°C/W)(2) θJB (°C/W)(3) θJC (°C/W)(4) BOARD TYPE (1) The boardtypesaredefinedby JEDEC (referenceJEDEC standardJESD51-9,TestBoard forArraySurfaceMount Package Thermal Measurements). (2) θJA (Theta-JA)= ThermalResistanceJunction-to-Ambient,°C/W (3) θJB (Theta-JB)= ThermalResistanceJunction-to-Board,°C/W (4) θJC (Theta-JC)= ThermalResistanceJunction-to-Board,°C/W (5) These power numbers arebased on simulationresultsforDM37x. Power numbers forCBP and CBC packagesincludetheDM37x deviceand POP memory. CUS package isDM37x only. (6) Not applicablesincethesepackageshave memory package mounted on top. Table7-2.Thermal ResistanceCharacteristics1GHz ARM Operation-8GbDDR PACKAGE Power (W)(5) θJA (°C/W)(2) θJB (°C/W)(3) θJC (°C/W)(4) BOARD TYPE (1) The boardtypesaredefinedby JEDEC (referenceJEDEC standardJESD51-9,TestBoard forArraySurfaceMount Package Thermal Measurements). (2) θJA (Theta-JA)= ThermalResistanceJunction-to-Ambient,°C/W (3) θJB (Theta-JB)= ThermalResistanceJunction-to-Board,°C/W (4) θJC (Theta-JC)= ThermalResistanceJunction-to-Board,°C/W (5) These power numbers arebased on simulationresultsforDM37x. Power numbers forCBP and CBC packagesincludetheDM37x deviceand POP memory. CUS package isDM37x only. (6) Not applicablesincethesepackageshave memory package mounted on top.

7.2 Device Support

7.2.1 Device and Development-Support Tool Nomenclature

To designatethestagesintheproductdevelopmentcycle,TI assignsprefixestothepartnumbers ofall DM37x processorsand supporttools.Each devicehas one of threeprefixes:X, P, or null(no prefix). Texas Instrumentsrecommends two ofthreepossibleprefixdesignatorsforitssupporttools:TMDX and TMDS. These prefixesrepresentevolutionarystagesofproductdevelopmentfromengineeringprototypes (TMDX) throughfullyqualifiedproductiondevices/tools(TMDS). Devicedevelopmentevolutionaryflow: X Experimentaldevicethatis not necessarilyrepresentativeof the finaldeviceselectrical specificationsand may notuse productionassemblyflow.(TMX definition) P Prototypedevicethatisnot necessarilythe finalsilicondieand may not necessarilymeet finalelectricalspecifications.(TMP definition) null Productionversionofthesilicondiethatisfullyqualified.(TMS definition) SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

X DM3730 ( ) X = Experimental Device P = Prototype Device blank = Production Device DEVICE PACKAGE TYPE CBP = 515-pin sPBGA CBC = 515-pin sPBGA CUS = 423-pin sPBGA SILICON REVISION CBP ( ) blank = commercial temperature A = extended temperature D = industrial temperature ( ) blank = tray R = tape and reel ( ) blank = 800 MHz Cortex-A8 100 = 1GHz Cortex-A8 DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011 Supporttooldevelopmentevolutionaryflow: TMDX Development supportproductthathas not yet completed Texas Instrumentsinternal qualificationtesting. TMDS Fullyqualifieddevelopmentsupportproduct. TMX and TMP devices and TMDX development-supporttoolsare shipped againstthe following disclaimer: Developmentalproductisintendedforinternalevaluationpurposes. Productiondevicesand TMDS development-supporttoolshave been characterizedfully,and thequality and reliabilityofthedevicehave been demonstratedfully.TIsstandardwarrantyapplies. Predictionsshow thatprototypedevices(X orP),have a greaterfailureratethanthestandardproduction devices.Texas Instrumentsrecommends thatthese devicesnot be used in any productionsystem because theirexpectedend-usefailureratestillisundefined.Only qualifiedproductiondevicesaretobe used. Foradditionaldescriptionofthedevicenomenclaturemarkings,see theProcessorSiliconErrata. Figure7-1.Device Nomenclature

7.2.2 Documentation Support

7.2.2.1 RelatedDocumentation from Texas Instruments

The followingdocuments describetheDM3730/25 DigitalMedia Processor.Copies ofthesedocuments areavailableon theInternetatwww.ti.com.Tip:Entertheliteraturenumber inthesearchbox providedat www.ti.com. The currentdocumentationthatdescribesthe DM3730/25 DigitalMedia Processor,relatedperipherals, and othertechnicalcollateral,isavailableintheproductfolderat:www.ti.com. SPRUGN4 . Collectionof documents providingdetailedinformationon the SitaraTM architecture includingpower, reset,and clock control,interrupts,memory map, and switchfabric interconnect.Detailedinformationon the microprocessorunit(MPU) subsystem as wella functionaldescriptionoftheperipheralssupportedon DM3730/25devicesisalsoincluded. 7.2.2.1.1Community Resources The followinglinksconnectto TI community resources.Linkedcontentsare provided"AS IS"by the respectivecontributors.They do notconstituteTI specificationsand do notnecessarilyreflectTI'sviews; see TI'sTerms ofUse. TIE2E Community TI's Engineer-to-Engineer(E2E) Community. Created to fostercollaboration among engineers.Ate2e.ti.com,you can ask questions,shareknowledge,exploreideasand helpsolveproblemswithfellowengineers. Copyright© 2010–2011,Texas InstrumentsIncorporated Package Characteristics 271 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 SPRS685D –AUGUST 2010–REVISED JULY 2011 www.ti.com TIEmbedded Processors Wiki Texas InstrumentsEmbedded Processors Wiki.Establishedto help developersget startedwithEmbedded Processorsfrom Texas Instrumentsand to foster innovationand growthofgeneralknowledge aboutthehardwareand softwaresurrounding thesedevices.

7.2.2.2 RelatedDocumentation from Other Sources

The followingdocuments arerelatedtotheDM3730, DM3725 DigitalMedia Processors.Copiesofthese documents can be obtaineddirectlyfromtheinternetorfromyourTexas Instrumentsrepresentative. Cortex-A8 Technical Reference Manual. This is the technicalreferencemanual forthe Cortex-A8 processor.A copy ofthisdocument can be obtainedviatheinternetathttp://infocenter.arm.com.Please see the DM3730, DM3725 DigitalMedia ProcessorsSiliconErrata(literaturenumber SPRZ319 ) to determinetherevisionoftheCortex-A8coreused on yourdevice. ARM Core CortexTM -A8 (AT400/AT401) ErrataNotice.Providesa listof advisoriesforthe different revisionsoftheCortex-A8processor.ContactyourTIrepresentativefora copy ofthisdocument.Please see the DM3730, DM3725 DigitalMedia ProcessorsSiliconErrata(literaturenumber SPRZ319 ) to determinetherevisionoftheCortex-A8coreused on yourdevice. SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

DM3730,DM3725 www.ti.com SPRS685D –AUGUST 2010–REVISED JULY 2011

7.3 MechanicalData

Copyright© 2010–2011,Texas InstrumentsIncorporated Package Characteristics 273 SubmitDocumentationFeedback ProductFolderLink(s):DM3730 DM3725

www.ti.com 12-Feb-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DM3725CBC ACTIVE POP-FCBGA CBC 515 119 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 DM3725CBC DM3725CBC100 ACTIVE POP-FCBGA CBC 515 119 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 DM3725CBC100 DM3725CBCA ACTIVE POP-FCBGA CBC 515 119 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 DM3725CBCA DM3725CBP ACTIVE POP-FCBGA CBP 515 168 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 DM3725CBP DM3725CBP-AS3 DM3725CBP100 ACTIVE POP-FCBGA CBP 515 168 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 DM3725CBP100 DM3725CBP100-AS3 DM3725CBPA ACTIVE POP-FCBGA CBP 515 168 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 DM3725CBPA DM3725CBPD100 ACTIVE POP-FCBGA CBP 515 168 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 90 DM3725CBPD100 DM3725CBPD100-AS3 DM3725CBPDR100 ACTIVE POP-FCBGA CBP 515 1000 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 90 DM3725CBPD100 DM3725CUS ACTIVE FCBGA CUS 423 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 DM3725CUS DM3725CUS100 ACTIVE FCBGA CUS 423 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 DM3725CUS100 DM3725CUSA ACTIVE FCBGA CUS 423 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 DM3725CUSA DM3725CUSD100 ACTIVE FCBGA CUS 423 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 90 DM3725CUSD100 DM3730CBC ACTIVE POP-FCBGA CBC 515 119 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 DM3730CBC DM3730CBC100 ACTIVE POP-FCBGA CBC 515 119 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 DM3730CBC100 DM3730CBCA ACTIVE POP-FCBGA CBC 515 119 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 DM3730CBCA DM3730CBCD100 ACTIVE POP-FCBGA CBC 515 119 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 90 DM3730CBCD100 DM3730CBP ACTIVE POP-FCBGA CBP 515 168 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 DM3730CBP DM3730CBP-AS3

www.ti.com 12-Feb-2017 Addendum-Page 2 Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples DM3730CBP100 ACTIVE POP-FCBGA CBP 515 168 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 DM3730CBP100 DM3730CBP100-AS3 DM3730CBPA ACTIVE POP-FCBGA CBP 515 168 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 DM3730CBPA DM3730CBPD100 ACTIVE POP-FCBGA CBP 515 168 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 90 DM3730CBPD100 DM3730CBPD100-AS3 DM3730CUS ACTIVE FCBGA CUS 423 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 DM3730CUS DM3730CUS100 ACTIVE FCBGA CUS 423 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 DM3730CUS100 DM3730CUS100NEP ACTIVE FCBGA CUS 423 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR 0 to 90 DM3730CUS100 DM3730CUSA ACTIVE FCBGA CUS 423 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 105 DM3730CUSA DM3730CUSD100 ACTIVE FCBGA CUS 423 90 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 90 DM3730CUSD100 XDM3730CBP OBSOLETE POP-FCBGA CBP 515 TBD Call TI Call TI 0 to 90 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

www.ti.com 12-Feb-2017 Addendum-Page 3 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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