VCA8500IRGCT

VCA8500_0803 TI | Alldatasheet

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(1)Attenuation (46dB) Clamping Circuit LPF (T wo- pole) CW□Switch□Matrix (8□in 10□out)/c180Logic OUT CW OUT OUT Gain Control LNA IN SDI VCA8500 (1□of□8□Channels) NOTE□(1):□20dB,□25dB,□27dB,□or□30dB□gain□setting. VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 www.ti.com 8-Channel, Ultralow-Power, Variable Gain Amplifier with Low-Noise Pre-Amp Medical Imaging, Ultrasound Systems Ultralow Power: 65mW/Channel Portable Systems Low Noise: 0.8nV/ Hz Low- and Mid-Range Systems Low-Noise Pre-Amp (LNP): 20dB Fixed Gain 250mV PP Linear Input Range The VCA8500 is an 8-channel variable gain amplifier Variable Gain Amplifier: consisting of a low-noise pre-amplifier (LNP) and a Gain Control Range: 46dB variable-gain amplifier (VGA). This combination, along with the device features, makes it ideal for a Selectable PGA Gain: variety of ultrasound systems. 20dB, 25dB, 27dB, 30dB Fast Overload Recovery The LNP gain is fixed at 20dB, and has excellent noise and signal handling characteristics. The gain of Output Clamping Control the voltage-controlled attenuator can vary over a Integrated Low-Pass Filter: 46dB range with a to 1.2V control voltage Second-Order, Linear Phase common to all channels of the VCA8500. Bandwidth: 10MHz, 15MHz The post-gain amplifier (PGA) can be programmed High Accuracy: for four gain settings: 20dB, 25dB, 27dB, or 30dB gain. As a means to improve system overload Low Gain Error: 0.5dB recovery time, the VCA8500 provides an internal Excellent Channel Matching: 0.25dB clamping function. The PGA settings as well the Distortion, HD2: 50dBc at 5MHz clamp levels are controlled through the serial interface. Integrated CW Switch Matrix: Easy Current Summing The VCA8500 is built on TI s BiCOM process and is available in a small QFN-64 PowerPAD package. Serial Control Interface Small Package: QFN-64, 9mm Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PowerPAD is a trademark of Texas Instruments. Infineon is a registered trademark of Infineon Technologies. SPI is a trademark of Motorola. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION (1) SPECIFIED PACKAGE- PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT MEDIA, ECO PRODUCT LEAD DESIGNATOR RANGE MARKING NUMBER QUANTITY STATUS (2) VCA8500IRGCT Tape and Reel, 250 Pb-Free, VCA8500 QFN-64 RGC C to +85 C VCA8500 Green VCA8500IRGCR Tape and Reel, 2000 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com (2) Eco-Status information: Additional details including specific material content can be accessed at www.ti.com/leadfree GREEN: Ti defines Green to mean Lead (Pb)-Free and in addition, uses less package materials that do not contain halogens, including bromine (Br), or antimony (Sb) above 0.1% of total product weight. N/A: Not yet available Lead (Pb)-Free; for estimated conversion dates, go to www.ti.com/leadfree Pb-FREE: Ti defines Lead (Pb)-Free to mean RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and, if designed to be soldered, suitable for use in specified lead-free soldering processes. NOTE These packages conform to Lead-Free and Green Manufacturing Specifications. Over operating free-air temperature range, unless otherwise noted. PARAMETER VCA8500 UNIT Supply voltage range, AVDD1 0.3 to +3.9 V Supply voltage range, AVDD2 0.3 to V Supply voltage range, DVDD 0.3 to +3.9 V Voltage at analog inputs 0.3 to (AVDD1 +0.3) V Voltage at digital inputs 0.3 to (DVDD to +0.3) V Soldering temperature (lead, 5s) (3) +260 C Maximum junction temperature J any condition (2) +150 C Maximum junction temperature J continuous operation, long-term +125 C reliability (2) Storage temperature range, T stg to +150 C Operating temperature range, T A to +85 C Human body model (HBM) 2000 V ESD rating Charged device model (CDM) 1000 V Machine model (MM) 200 V (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the ground terminal, which is the exposed thermal pad of the package. (3) Both the part being reworked and the board must be baked out before rework to reduce the risk of delamination. Refer to Application Note SLUA271 (available for download at www.ti.com for recommended rework techniques. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com ELECTRICAL CHARACTERISTICS VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 All specifications at T A +25 AVDD2 5.0V, AVDD1 DVDD 3.3V; single-ended, ac-coupled µ input configuration to the preamp (LNA), f IN 5MHz, V CNTL 1.0V, PG 30dB, clamp disabled (CL 1), LPF 15MHz, and R LOAD Ω on each output to ground, unless otherwise noted. VCA8500 TEST PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL (1) PREAMPLIFIER (LNA) LNA gain Single-ended input to differential output dB C Input voltage Linear operation (THD 40dBc) 250 mV PP C Input voltage noise At f 2MHz 0.70 nV/ Hz B Input current noise At f 2MHz 3.0 pA/ Hz B Input bias voltage BL Internally generated +2.4 V B Bandwidth Small-signal, 3dB MHz C Input resistance (2) At f 4MHz k Ω C Input capacitance (2) Including internal ESD and clamping diodes pF C TGC SIGNAL PATH (LNA, VCA, PGA) PGA 30dB, R S Ω f 2MHz 0.81 nV/ Hz B Input voltage noise PGA 20dB, R S Ω f 2MHz 0.95 nV/ Hz B Noise figure R S 200 Ω f 1MHz to 10MHz 1.1 dB C Group delay variation 1MHz to 10MHz ns B To within of PP output Overload recovery time ns B CNTL 0.54V), PGA 20dB Output voltage OUT Differential, non-clipped V PP B Output common-mode voltage CM +1.65 V B DC to 10MHz, single-ended, Output impedance Ω C either output Output current R L Ω into V CM mA B Second-harmonic distortion f IN 5MHz, PGA 20dB, V OUT PP dBc A f IN 5MHz, PGA 30dB, V OUT PP dBc A Third-harmonic distortion f IN 5MHz, PGA 20dB, V OUT PP dBc A f IN 5MHz, PGA 30dB, V OUT PP dBc A f 4.99MHz, f 5.01MHz, Two-tone intermodulation dBc B V CNTL 1V; V OUT PP Worst case; PGA 20dB, V CNTRL 0.6V, dBc B V OUT PP Crosstalk, channel-to-channel PGA 30dB, V OUT PP dBc B FILTER Low-pass filter (second-order) 3dB point 10, MHz B Tolerance B High-pass filter (first-order, due to 3dB point, V CNTL 1.2V 150 kHz C internal ac coupling) (1) Test levels: (A) 100% tested at +25 Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation, not production tested. (C) Typical value only for information. (2) See Figure of the Typical Characteristics. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS (continued) All specifications at T A +25 AVDD2 5.0V, AVDD1 DVDD 3.3V; single-ended, ac-coupled µ input configuration to the preamp (LNA), f IN 5MHz, V CNTL 1.0V, PG 30dB, clamp disabled (CL 1), LPF 15MHz, and R LOAD Ω on each output to ground, unless otherwise noted. VCA8500 TEST PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL (1) ACCURACY 20, 25, Gain (PGA) Selectable through SPI dB A 27, Total gain, maximum LNA PGA gain, V CNTL 1.2V 49.5 dB A Gain range V CNTL to 1.2V dB A Gain range V CNTL 0.1V to 1.0V dB A Gain slope V CNTL 0.1V to 1.0V 44.4 dB/V A Gain error, absolute V CNTL 0.1V 0.5 dB A 0.1V V CNTL 1.0V 1.5 0.5 +1.5 dB A 1.0V V CNTL 1.2V 0.5 dB A Gain matching Channel-to-channel 0.25 0.5 dB A Output offset voltage Differential +25 mV A Single-ended (3) +50 mV A Clamp level OUT CL 1.7 V PP A CL (clamp disabled) 2.8 V PP B GAIN CONTROL INTERFACE Input voltage range CNTL Gain range 46dB to 1.2 V A Input resistance k Ω C V CNTL to 1.2V step; Response time 0.5 µ s B to 90% signal level, V OUT PP Gain control bandwidth 1.5 MHz C CW SIGNAL PATH Output transconductance (V/I) At V IN 100mV PP 16.4 mA/V A At V IN 200mV PP 14.5 mA/V B Dynamic CW output current, max 2.9 mA PP B Static CW output current (sink) 0.9 mA B Output common-mode voltage CM0 Supplied externally +2.5 V B Output compliance range Symmetric around V CMO 0.5 V B Output capacitance pF C Output impedance k Ω C Input voltage noise, CW mode At f 2MHz 1.15 nV/ Hz B Signal-dependent noise (RTO) At 2kHz offset from 2MHz CW carrier dB B At 2kHz offset from 5MHz CW carrier dB B Summing of eight channels (all modes) Output noise correlation factor 0.6 dB B [compared to ideal 0dB] (3) Deviation from ideal common-mode voltage CM 1.65V). Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 ELECTRICAL CHARACTERISTICS (continued) All specifications at T A +25 AVDD2 5.0V, AVDD1 DVDD 3.3V; single-ended, ac-coupled µ input configuration to the preamp (LNA), f IN 5MHz, V CNTL 1.0V, PG 30dB, clamp disabled (CL 1), LPF 15MHz, and R LOAD Ω on each output to ground, unless otherwise noted. VCA8500 TEST PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL (1) DIGITAL INPUTS (SDI) (PD, DIN, DOUT, CLK, RST) V IH high-level input voltage 2.0 V D V B V IL low-level input voltage 0.8 V B Input current µ A A Clock frequency CLK 10k 20M Hz B Input resistance M Ω C Input capacitance pF C POWER SUPPLY Supply Voltages AVDD1, DVDD Operating 3.15 3.3 3.6 V B AVDD2 Operating 4.75 5.25 V B Supply Currents (4) IAVDD1 TGC mode (D5 145 156 mA A CW mode (D5 mA A IDVDD TGC, CW mode 1.5 mA A IAVDD2 TGC mode mA A CW mode mA A Power dissipation, total All channels, TGC mode, no signal 522 570 mW A All channels, CW mode, no signal 533 575 mW A POWER-DOWN MODES Standby Mode PD (pin 49) high IAVDD1 mA A IDVDD 1.5 mA A IAVDD2 mA A Power dissipation 104 130 mW A Power-down response time 0.2 µ s C Power-up response time (5) PD to valid output (90% level) µ s C Shut-Down Mode (PWR) high IAVDD1 1.5 mA A IDVDD 1.5 mA A IAVDD2 mA A Power dissipation mW A THERMAL CHARACTERISTICS Temperature range Ambient, operating +85 C Thermal resistance, θ JA 22.5 C/W Soldered pad; four-layer PCB with thermal vias Thermal resistance, θ JC 17.0 C/W (4) Clamp enabled (D4 0). (5) See Figure of the Typical Characteristics. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com DEVICE INFORMATION VBL5 IN5 AVDD1 IN6 VBL6 VBL7 IN7 VBL8 IN8 AVDD2 VB2 VB6 VB4 VREFH VREFL AVDD1 VBL1 IN1 AVDD1 IN2 VBL2 VBL3 IN3 VBL4 IN4 VCNTL AVDD2 VB3 VB1 VB5 VCM OUT4OUT4OUT3OUT3OUT2OUT2OUT1OUT1OUT5OUT5OUT6OUT6OUT7OUT7OUT8OUT8 64 63 62 61 60 59 58 57 56 55 54 17 18 19 20 21 22 23 24 25 26 27 53 52 51 50 49 28 29 30 31 32 VCA8500 (GND) PowerPAD TM AVDD1 PDCW0CW1CW2CW3CW4D_INCLKD_OUTRSTDVDDCW5CW6CW7CW8CW9 VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 RGC PACKAGE QFN-64 (TOP VIEW) Table TERMINAL FUNCTIONS TERMINAL PIN NO. NAME I/O (+2.4V); bypass with 0.1 µ F capacitor (min) IN1 I LNA input channel AVDD1 +3.3V analog supply IN2 I LNA input channel VBL2 LNA bias voltage (+2.4V); bypass with 0.1 µ F capacitor (min) VBL3 LNA bias voltage (+2.4V); bypass with 0.1 µ F capacitor (min) IN3 I LNA input channel VBL4 LNA bias voltage (+2.4V); bypass with 0.1 µ F capacitor (min) IN4 LNA input channel V CNTL I Attenuator control voltage input (all channels) AVDD2 +5V analog supply (VCA, CW) VB3 Internal bias voltage (+4.2V); bypass with 0.1 µ F capacitor (min) VB1 Internal bias voltage (+2.4V); bypass with 2.2 µ F capacitor (1.0 µ F min) VB5 Internal bias voltage (+2.4V); bypass with 0.1 µ F capacitor (min) V CM Internal common-mode voltage (+1.65V); bypass with 0.1 µ F capacitor (min) AVDD1 +3.3V analog supply OUT4 O PGA output channel (inverted) OUT4 O PGA output channel Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 Table TERMINAL FUNCTIONS (continued) TERMINAL PIN NO. NAME I/O O PGA output channel (inverted) OUT3 O PGA output channel OUT2 O PGA output channel (inverted) OUT2 O PGA output channel OUT1 O PGA output channel (inverted) OUT1 O PGA output channel OUT5 O PGA output channel (inverted) OUT5 O PGA output channel OUT6 O PGA output channel (inverted) OUT6 O PGA output channel OUT7 O PGA output channel (inverted) OUT7 O PGA output channel OUT8 O PGA output channel (inverted) OUT8 O PGA output channel AVDD1 +3.3V analog supply V REFL Clamp reference level low, 2.0V; bypass with 0.1 µ F capacitor (min) V REFH Clamp reference level high, 2.7V; bypass with 0.1 µ F capacitor (min) VB4 Internal bias voltage (+2.4V); bypass with 0.1 µ F capacitor (min) VB6 Internal bias voltage (+2.9V); bypass with 0.1 µ F capacitor (min) VB2 Internal bias voltage (+2.7V); bypass with 0.1 µ F capacitor (min) AVDD2 +5V analog supply (VCA, CW) IN8 I LNA input channel VBL8 LNA bias voltage (+2.4V); bypass with 0.1 µ F capacitor (min) IN7 I LNA input channel VBL7 LNA bias voltage (+2.4V); bypass with 0.1 µ F capacitor (min) VBL6 I LNA bias voltage (+2.4V); bypass with 0.1 µ F capacitor (min) IN6 LNA input channel AVDD1 +3.3V analog supply IN5 I LNA input channel VBL5 LNA bias voltage (+2.4V); bypass with 0.1 µ F capacitor (min) PD I Power-down pin for standby mode; normal operation, power down CW0 O CW channel current output CW1 O CW channel current output CW2 O CW channel current output CW3 O CW channel current output CW4 O CW channel current output D_IN I Serial data input CLK I Clock input for serial interface D_OUT O Serial data output RST I Reset input; rising edge resets register to default values. DVDD +3.3V digital supply; connect to a low-noise analog supply plane (AVDD1) CW5 CW channel current output CW6 CW channel current output CW7 CW channel current output CW8 CW channel current output CW9 CW channel current output PowerPAD must be connected to the analog ground of the printed circuit board; use this ground for GND bypass capacitor return ground. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com FUNCTIONAL BLOCK DIAGRAM LNA CW□Switch□Matrix (8□in□x□10□out) VCA Clamp LPF V/I OUT1 CW9 CW8 CW7 CW6 CW5 CW4 CW3 CW2 CW1 CW0 PD CLK RST D_OUT D_IN Serial□Digital□Interface□(SDI) and□Logic OUT1 IN1 VBL1 LNA VCA Clamp LPF OUT2 OUT2 IN2 VBL2 LNA VCA Clamp LPF OUT3 OUT3 IN3 VBL3 VCNTL GNDAVDD2AVDD1DVDD VCMVREFH VREFLVB1 LNA VCA Clamp LPF OUT4 OUT4 IN4 VBL4 LNA VCA Clamp LPF OUT5 OUT5 IN5 VBL5 LNA VCA Clamp LPF OUT6 OUT6 IN6 VBL6 LNA VCA Clamp LPF OUT7 OUT7 IN7 VBL7 LNA VB2 VB3 VB4 VB5 VB6 VCA Reference Clamp LPF OUT8 PGA PGA PGA PGA PGA PGA PGA PGA OUT8 IN8 VBL8 VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com INPUT REGISTER BIT MAPS VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 Register Map BYTE BYTE BYTE BYTE BYTE D0:D7 D8:D11 D12:D15 D16:D19 D20:D23 D24:D27 D28:D31 D32:D35 D36:D39 Control CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 Table Default Register Configuration Table Byte Control Byte Register Map BIT NAME (LSB) Start bit; must be a (high); 40-bit countdown starts with first falling clock edge. W Write, Read; read prevents latching of new data/bits. Control register remains latched with previously loaded data. PWR Power-down mode enabled (shutdown). BW Low-pass filter bandwidth setting (see Table CL Clamp level setting (see Table Mode TGC mode, CW doppler mode (TGC powered down) PG0 LSB of PGA gain control (see Table (MSB) PG1 MSB of PGA gain control Table Byte First Data Byte BIT NAME (LSB) DB1:1 Channel LSB of matrix control DB1:2 Channel matrix control D10 DB1:3 Channel matrix control D11 DB1:4 Channel MSB of matrix control D12 DB2:1 Channel LSB of matrix control D13 DB2:2 Channel matrix control D14 DB2:3 Channel matrix control D15 (MSB) DB2:4 Channel MSB of matrix control Table Byte Second Data Byte BIT NAME (LSB) DB3:1 Channel LSB of matrix control D17 DB3:2 Channel matrix control D18 DB3:3 Channel matrix control D19 DB3:4 Channel MSB of matrix control D20 DB4:1 Channel LSB of matrix control D21 DB4:2 Channel matrix control D22 DB4:3 Channel matrix control D23 (MSB) DB4:4 Channel MSB of matrix control Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 Table Byte Third Data Byte BIT NAME (LSB) DB5:1 Channel LSB of matrix control D25 DB5:2 Channel matrix control D26 DB5:3 Channel matrix control D27 DB5:4 Channel MSB of matrix control D28 DB6:1 Channel LSB of matrix control D29 DB6:2 Channel matrix control D30 DB6:3 Channel matrix control D31 (MSB) DB6:4 Channel MSB of matrix control Table Byte Fourth Data Byte BIT NAME (LSB) DB7:1 Channel LSB of matrix control D33 DB7:2 Channel matrix control D34 DB7:3 Channel matrix control D35 DB7:4 Channel MSB of matrix control D36 DB8:1 Channel LSB of matrix control D37 DB8:2 Channel matrix control D38 DB8:3 Channel matrix control D39 (MSB) DB8:4 Channel MSB of matrix control Table Clamp Level and LPF Bandwidth Setting NAME SETTING FUNCTION Bandwidth set to 15MHz (default) BW Bandwidth set to 10MHz Clamps the output signal at 1.7V PP on each PGA output channel (default) CL Clamp transparent (disabled) Table PGA Gain Setting PG1 PG0 FUNCTION Set PGA gain to 20dB (default) Set PGA gain to 25dB Set PGA gain to 27dB Set PGA gain to 30dB Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com Channel□1 Input V/I Converter DIN CW0 CW1 CW2 CW3 CW4 CW5 CW6 CW7 CW8 CW9 AVDD2 DOUT CLK Decode Logic (T o□Other□Channels) VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 Table 10. CW Switch Matrix Control for Each Channel DBn:4 DBn:1 (MSB) DBn:3 DBn:2 (LSB) LNA Input Channel Directed To: Output CW0 Output CW1 Output CW2 Output CW3 Output CW4 Output CW5 Output CW6 Output CW7 Output CW8 Output CW9 Connected to AVDD2; channel disabled Connected to AVDD2; channel disabled Connected to AVDD2; channel disabled Connected to AVDD2; channel disabled Connected to AVDD2; channel disabled Connected to AVDD2; channel disabled Figure Basic CW Cross-Point Switch Matrix Configuration Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com SERIAL DIGITAL INTERFACE (SDI) TIMING INFORMATION RST□(Low) CLK DIN D0□(LSB) D1 D2 D3 D4 D5 D6 D7□(MSB) t5 t4 SERIAL PORT TIMING TABLE VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 All writes and reads are five bytes at a time. Each byte consists of bits, for a total instruction set of bits. Data are latched on the falling edge of CLK. Separate write (DIN) and read data (DOUT) lines. Reads follow the same bitstream pattern seen in the write cycle. Reads extract data from the FIFO buffer, not the latched register. DOUT data are continuously available and do not need to be enabled with a read cycle. Selecting a read cycle in the control register only prevents latching of data. The control register remains latched. The Reset pin (RST) must be low in order to allow the register to update with new data. RST can be held low permanently. To initiate a reset cycle, pull the RST pin high for at least 100ns. NOTE: This figure shows timing example for one data byte. A full register update cycle requires all five bytes (that is, bits). PARAMETER t Serial CLK period 100 ns t Serial CLK HIGH time ns t Serial CLK LOW time ns t Data hold time ns t Data setup time ns RST Reset pulse H 100 ns Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com TYPICAL CHARACTERISTICS /c45 /c45 1.2 Gain□(dB) V (V)CNTRL 20dB 25dB 27dB 30dB 0.50 0.25 0.25 0.50 /c45 /c45 1.2 Gain□(dB) V (V)CNTRL PGA□=□20dB PGA□= 30dB PGA□=□27dBPGA□=□25dB /c45 /c45 1.2 Gain□(dB) V (V)CNTRL 30dB□at 40 C/c45 /c176 30dB□at□+25 C/c176 30dB□at□+85 C/c176 20dB□at C /c176/c45 40 20dB□at C /c176+25 20dB□at C /c176+85 0.1 0.2 1.50 1.25 1.00 0.75 0.50 0.25 0.25 0.50 0.75 1.00 1.25 1.50 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Gain□Error□(dB) V (V)CNTRL 30dB□at 40 C/c45 /c176 30dB□at□+85 C/c176 20dB□at 40 C/c45 /c176 20dB□at□+85 C/c176 0.20.1 /c45 /c45 1.2 Gain□(dB) V (V)CNTRL 30dB□at□2MHz 30dB□at□5MHz 30dB□at□10MHz 20dB□at□2MHz 20dB□at 5MHz 20dB□at 10MHz PGA□=□20dB□and□30dB 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 1.2 Gain□Matching□(dB) V (V)CNTRL PGA□=□20dB PGA□= 30dB VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 All specifications at T A +25 AVDD2 5.0V, AVDD1 DVDD 3.3V; single-ended, ac-coupled µ input configuration to the preamp (LNA), f IN 5MHz, V CNTL 1.0V, clamp disabled (CL 1), LPF 15MHz, and R LOAD Ω on each output to ground, unless otherwise noted. GAIN vs V CNTRL (at PGA GAIN ERROR vs V CNTRL Figure Figure GAIN vs V CNTRL OVER TEMPERATURE GAIN ERROR DRIFT vs V CNTRL Figure Figure GAIN vs V CNTRL OVER FREQUENCY GAIN MATCHING vs V CNTRL Figure Figure Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com 3000 2500 2000 1500 1000 500 Units /c68 Gain□(dB) Channel-to-Channel 3000 2500 2000 1500 1000 500 Units /c68 Gain□(dB) Channel-to-Channel 2000 1800 1600 1400 1200 1000 800 600 400 200 Units /c68 Gain□(dB) Channel-to-Channel 2500 2000 1500 1000 500 CW□Outputs Transconductance□(mA/V) 16.75 16.50 16.25 16.00 15.75 15.50 Transconductance□(mA/V) T emperature□( C)/c176 85/c45 40 603510/c45 15 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 Output□Offset□(mV) T emperature□( C)/c176 Differential 85/c45 40 603510/c45 15 VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) All specifications at T A +25 AVDD2 5.0V, AVDD1 DVDD 3.3V; single-ended, ac-coupled µ input configuration to the preamp (LNA), f IN 5MHz, V CNTL 1.0V, clamp disabled (CL 1), LPF 15MHz, and R LOAD Ω on each output to ground, unless otherwise noted. GAIN MATCH AT V CNTRL 0.1V GAIN MATCH AT V CNTRL 0.6V Figure Figure GAIN MATCH AT V CNTRL 1.2V CW ACCURACY Figure 10. Figure 11. TRANSCONDUCTANCE vs TEMPERATURE OUTPUT OFFSET vs TEMPERATURE Figure 12. Figure 13. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com 170 160 150 140 130 120 110 100 TGC□Current□(mA) T emperature□( C)/c176 +5V +3.3VA +3.3VD 85/c45 40 603510/c45 15 CW□Current□(mA) T emperature□( C)/c176 /c45 40 603510/c45 15 +5V +3.3VA +3.3VD 560 550 540 530 520 510 500 490 T otal□Power□(V) T emperature□( C)/c176 TGC Mode CW□Mode 85/c45 40 603510/c45 15 /c45 /c45 /c45 /c45 /c45 /c45 100 Gain□(dB) Frequency□(MHz) 0.1 101 10MHz 15MHz1.0VCNTRL 0.7VCNTRL 0.4VCNTRL 0.1VCNTRL /c45 /c45 /c45 /c45 100 Gain□(dB) Frequency□(MHz) 0.1 101 10MHz 15MHz 0.4VCNTRL 0.7VCNTRL 1.0VCNTRL 0.1VCNTRL 250 200 150 100 1.2 Noise□(nV/ /c214Hz V (V)CNTRL 0 0.20.1 PGA□= 30dB PGA□= 20dB Frequency□=□2MHz VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) All specifications at T A +25 AVDD2 5.0V, AVDD1 DVDD 3.3V; single-ended, ac-coupled µ input configuration to the preamp (LNA), f IN 5MHz, V CNTL 1.0V, clamp disabled (CL 1), LPF 15MHz, and R LOAD Ω on each output to ground, unless otherwise noted. TGC CURRENT vs TEMPERATURE CW CURRENT vs TEMPERATURE Figure 14. Figure 15. FREQUENCY RESPONSE vs V CNTRL AT PGA 20dB TOTAL POWER vs TEMPERATURE (LPF 15MHz and 10MHz) Figure 16. Figure 17. FREQUENCY RESPONSE vs V CNTRL AT PGA 30dB (LPF 15MHz and 10MHz) OUTPUT-REFERRED NOISE vs V CNTRL Figure 18. Figure 19. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com 250 200 150 100 1.2 Noise□(nV/ /c214Hz V (V)CNTRL 0 0.20.1 PGA□= 30dB PGA□= 20dB Frequency□=□5MHz 120 110 100 1.2 Noise□(nV/ /c214Hz V (V)CNTRL 0 0.20.1 PGA□=□20dB PGA□= 30dB Frequency□=□2MHz 120 110 100 1.2 Noise□(nV/ /c214Hz V (V)CNTRL 0 0.20.1 PGA□= 30dB PGA□= 20dB Frequency□=□5MHz 4.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 Current□Noise□(pA/ ) /c214Hz Frequency□(MHz) R =S 400/c87 R =S 1k/c87 R =□200 /c87S V =□1.2VCNTRL 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 Noise□(nV/ ) /c214Hz Frequency□(MHz) R =S 200/c87 R =S 400/c87 R =S 1k/c87 R =□50 /c87S V =□1.2VCNTRL 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Noise□(nV/ ) /c214Hz Frequency□(MHz) R =□200 /c87S R =S 400/c87 R =S 1k/c87 R =S 50/c87 V =□1.2VCNTRL VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) All specifications at T A +25 AVDD2 5.0V, AVDD1 DVDD 3.3V; single-ended, ac-coupled µ input configuration to the preamp (LNA), f IN 5MHz, V CNTL 1.0V, clamp disabled (CL 1), LPF 15MHz, and R LOAD Ω on each output to ground, unless otherwise noted. OUTPUT-REFERRED NOISE vs V CNTRL INPUT-REFERRED NOISE vs V CNTRL Figure 20. Figure 21. INPUT-REFERRED NOISE vs V CNTRL CURRENT NOISE vs FREQUENCY OVER R SOURCE Figure 22. Figure 23. OUTPUT-REFERRED NOISE vs FREQUENCY OVER R S INPUT-REFERRED NOISE vs FREQUENCY OVER R S Figure 24. Figure 25. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com 3.5 3.0 2.5 2.0 1.5 1.0 0.5 Noise□Figure□(dB) Frequency□(MHz) 1 10 R =S 50/c87 R =□200 /c87S R =S 400/c87 R =S 1k/c87 PGA□=□30dB V =□1.2VCNTRL 1.00 0.95 0.90 0.85 0.80 0.75 0.70 30dB Noise□(nV/ ) /c214Hz Gain□Setting□(PGA) 20dB 25dB 27dB 2MHz 5MHz R =□0 V =□1.2V /c87S CNTRL 12k 10k 100M Magnitude□( ) /c87 100 /c45 100 Phase□( ) /c176 /c45 80 /c45 20 /c45 40 /c45 60 Frequency□(Hz) 100k 1M 10M Magnitude□(Z )IN Phase 1.30 1.28 1.26 1.24 1.22 1.20 1.18 1.16 1.14 1.12 1.10 1.08 1.06 1.04 1.02 1.00 Noise□(nV/ ) /c214Hz Frequency□(MHz) 0.1 101.0 CW□Output /c4545 /c45 /c45 /c45 /c45 /c45 /c45 Distortion□(dBc) Frequency□(MHz) 30dB 25dB 27dB 20dB V =□1V V =□1.2V OUT PP CNTRL /c4545 /c45 /c45 /c45 /c45 /c45 /c45 Distortion□(dBc) Frequency□(MHz) 30dB 25dB 27dB 20dB V =□1V V =□1.2V OUT PP CNTRL VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) All specifications at T A +25 AVDD2 5.0V, AVDD1 DVDD 3.3V; single-ended, ac-coupled µ input configuration to the preamp (LNA), f IN 5MHz, V CNTL 1.0V, clamp disabled (CL 1), LPF 15MHz, and R LOAD Ω on each output to ground, unless otherwise noted. NOISE FIGURE vs FREQUENCY OVER R S INPUT-REFERRED NOISE Figure 26. Figure 27. INPUT-REFERRED NOISE vs FREQUENCY MAGNITUDE AND PHASE vs FREQUENCY Figure 28. Figure 29. 2ND HARMONIC vs FREQUENCY 3RD HARMONIC vs FREQUENCY Figure 30. Figure 31. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com /c45 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Distortion□(dB) V (V)CNTRL 0.6 30dB 25dB 27dB 20dB Frequency□=□5MHz V =□1VOUT PP /c45 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Distortion□(dBc) V (V)CNTRL 0.6 30dB 25dB 27dB 20dB Frequency□=□5MHz V =□1VOUT PP /c45 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Distortion□(dBc) V (V)CNTRL 0.6 2MHz 5MHz 10MHz PGA□=□20dB V =□1VOUT PP /c45 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Distortion□(dB) V (V)CNTRL 0.6 2MHz 5MHz 10MHz PGA□=□25dB V =□1VOUT PP /c45 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Distortion□(dB) V (V)CNTRL 0.6 2MHz 5MHz 10MHz PGA□=□27dB V =□1VOUT PP /c45 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Distortion□(dB) V (V)CNTRL 0.6 2MHz 5MHz 10MHz PGA□=□30dB V =□1VOUT PP VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) All specifications at T A +25 AVDD2 5.0V, AVDD1 DVDD 3.3V; single-ended, ac-coupled µ input configuration to the preamp (LNA), f IN 5MHz, V CNTL 1.0V, clamp disabled (CL 1), LPF 15MHz, and R LOAD Ω on each output to ground, unless otherwise noted. 2ND HARMONIC vs V CNTRL OVER PGA GAIN 3RD HARMONIC vs V CNTRL OVER PGA GAIN Figure 32. Figure 33. 2ND HARMONIC vs V CNTRL OVER FREQUENCY 2ND HARMONIC vs V CNTRL OVER FREQUENCY Figure 34. Figure 35. 2ND HARMONIC vs V CNTRL OVER FREQUENCY 2ND HARMONIC vs V CNTRL OVER FREQUENCY Figure 36. Figure 37. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com /c45 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Distortion□(dB) V (V)CNTRL 0.6 2MHz 10MHz 5MHz PGA□=□20dB V =□1VOUT PP /c45 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Distortion□(dB) V (V)CNTRL 0.6 2MHz 5MHz 10MHz PGA□=□25dB V =□1VOUT PP /c45 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Distortion□(dB) V (V)CNTRL 0.6 2MHz 5MHz 10MHz PGA□=□27dB V =□1VOUT PP /c45 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Distortion□(dB) V (V)CNTRL 0.6 2MHz 5MHz 10MHz PGA□=□30dB V =□1VOUT PP /c45 /c45 /c45 /c45 /c45 /c45 /c45 1500 Distortion□(dB) Output□Resistor□Load□( )/c87 750 2nd□Harmonic,□20dB 12501000 2nd□Harmonic,□30dB 3rd□Harmonic,□20dB 3rd□Harmonic,□30dB V =□1V V =□1V PGA□=□20dB□and□30dB OUT PP CNTRL /c45 /c45 /c45 /c45 /c45 /c45 /c45 1500 Distortion□(dB) Output□Resistor□Load□( )/c87 750 2nd□Harmonic,□20dB 12501000 2nd□Harmonic,□30dB 3rd□Harmonic,□20dB 3rd□Harmonic,□30dB V =□1V V =□1V PGA□=□20dB□and□30dB OUT PP CNTRL VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) All specifications at T A +25 AVDD2 5.0V, AVDD1 DVDD 3.3V; single-ended, ac-coupled µ input configuration to the preamp (LNA), f IN 5MHz, V CNTL 1.0V, clamp disabled (CL 1), LPF 15MHz, and R LOAD Ω on each output to ground, unless otherwise noted. 3RD HARMONIC vs V CNTRL OVER FREQUENCY 3RD HARMONIC vs V CNTRL OVER FREQUENCY Figure 38. Figure 39. 3RD HARMONIC vs V CNTRL OVER FREQUENCY 3RD HARMONIC vs V CNTRL OVER FREQUENCY Figure 40. Figure 41. DISTORTION vs R LOAD DISTORTION vs R LOAD (Clamp Disabled) (Clamp Enabled) Figure 42. Figure 43. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com /c45 /c45 /c45 /c45 /c45 /c45 /c45 Distortion□(dB) Frequency□(MHz) 2nd□Harmonic,□20dB 2nd□Harmonic,□30dB 3rd□Harmonic,□30dB 3rd□Harmonic,□20dB PGA□=□20dB□and□30dB V =□2VOUT PP V =□1VCNTRL /c45 /c45 /c45 /c45 /c45 /c45 /c45 Distortion□(dB) PGA□Gain□(dB) 2nd□Harmonic, 1.2VCNTRL 2725 2nd□Harmonic,□1.0VCNTRL 3rd□Harmonic, 1.2VCNTRL3rd□Harmonic, 1.0VCNTRL Frequency□=□5MHz V =□2VOUT PP /c45 /c45 /c45 /c45 /c45 /c45 /c45 2.0 Distortion□(dB) V (V )OUT PP 2nd□Harmonic 3rd□Harmonic PGA□=□30dB V =□1.2V Frequency□=□5MHz CNTRL /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 /c45 5.10 Magnitude□(dBm) Frequency□(MHz) 4.90 4.944.92 V =□1V PGA□=□30dB V =□1V OUT PP CNTRL /c4521.3 4.5 /c4573.5 /c4550 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Crosstalk□(dBc) V (V)CNTRL 0.5 0.7 0.6 Adjacent□Channels PGA□=□20dB V =□1VOUT PP 0.90.8 1.0 1.1 10MHz 2MHz 5MHz /c4550 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Crosstalk□(dBc) V (V)CNTRL 0.5 0.7 0.6 Adjacent□Channels PGA□=□25dB V =□1VOUT PP 0.90.8 1.0 1.1 10MHz 2MHz 5MHz 0.4 VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) All specifications at T A +25 AVDD2 5.0V, AVDD1 DVDD 3.3V; single-ended, ac-coupled µ input configuration to the preamp (LNA), f IN 5MHz, V CNTL 1.0V, clamp disabled (CL 1), LPF 15MHz, and R LOAD Ω on each output to ground, unless otherwise noted. DISTORTION vs FREQUENCY DISTORTION vs PGA GAIN Figure 44. Figure 45. INTERMODULATION DISTORTION DISTORTION vs V OUT PEAK-TO-PEAK (4.99MHz and 5.01MHz) Figure 46. Figure 47. CROSSTALK vs V CNTRL CROSSTALK vs V CNTRL Figure 48. Figure 49. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com /c4550 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Crosstalk□(dBc) V (V)CNTRL 0.5 0.70.6 Adjacent□Channels PGA□=□27dB V =□1VOUT PP 0.90.8 1.0 1.1 10MHz 2MHz 5MHz 0.40.3 /c4550 /c45 /c45 /c45 /c45 /c45 /c45 1.2 Crosstalk□(dBc) V (V)CNTRL 0.5 0.70.6 Adjacent□Channels PGA□=□30dB V =□1VOUT PP 0.90.8 1.0 1.1 10MHz 2MHz 5MHz 0.40.3 Input CH□1 (100mV/div) Time□(200ns/div) Output CH□2 (500mV/div) PGA□=□20dB V =□2VOUT PP V =□0.54VCNTRL Input CH□1 (200mV/div) Time□(200ns/div) PGA□=□20dB V =□2VOUT PP V =□0.54VCNTRL Output CH□2 (1V/div) Input CH□1 (20mV/div) Time□(200ns/div) PGA□=□20dB V =□2.5VOUT PP V =□1VCNTRL Output CH□2 (0.5V/div) Input CH□1 (50mV/div) Time□(200ns/div) PGA□=□20dB V =□2.8VOUT PP V =□1VCNTRL Output CH□2 (0.5V/div) VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) All specifications at T A +25 AVDD2 5.0V, AVDD1 DVDD 3.3V; single-ended, ac-coupled µ input configuration to the preamp (LNA), f IN 5MHz, V CNTL 1.0V, clamp disabled (CL 1), LPF 15MHz, and R LOAD Ω on each output to ground, unless otherwise noted. CROSSTALK vs V CNTRL CROSSTALK vs V CNTRL Figure 50. Figure 51. LNA OVERLOAD LNA OVERLOAD IN 300mV PP IN 400mV PP Figure 52. Figure 53. PGA OVERLOAD PGA OVERLOAD IN 34mV PP IN 50mV PP Figure 54. Figure 55. Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com Input CH□1 (50mV/div) Time□(200ns/div) PGA□=□20dB V =□1.7VOUT PP V =□1VCNTRL Output CH□2 (0.5V/div) Input CH□1 (22.4mV/div) Time□(200ns/div) PGA□=□30dB V =□2.8VOUT PP V =□1VCNTRL Output CH□2 (2.8V/div) V CH□1 (0.5V/div) CNTRL Time□(1 s/div)/c109 PGA□=□30dB V =□1VOUT PP Output CH□2 (0.5V/div) PD□Pin CH□1 (1V/div) Time□(1ms/div) Output CH□2 (0.2V/div) PGA□=□20dB V =□1VOUT PP CNTRLV =□0.6V VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 TYPICAL CHARACTERISTICS (continued) All specifications at T A +25 AVDD2 5.0V, AVDD1 DVDD 3.3V; single-ended, ac-coupled µ input configuration to the preamp (LNA), f IN 5MHz, V CNTL 1.0V, clamp disabled (CL 1), LPF 15MHz, and R LOAD Ω on each output to ground, unless otherwise noted. PGA OVERLOAD PGA OVERLOAD IN 50mV PP Clamp Enabled) IN 20mV PP Figure 56. Figure 57. V CNTRL RESPONSE TIME POWER-DOWN RESPONSE TIME Figure 58. Figure 59. Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com THEORY OF OPERATION CIN LNA V/I CW□Switch□Matrix Attenuator (VCA) PGA Clamp LPF CW/IOUT OUT OUT T/R Switch VCNTL VCA8500 VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 While the LNA is designed to be driven from a Built on TI s bipolar-complementary (BiCOM) single-ended source, the internal TGC signal path is process, the VCA8500 is a third-generation, octal designed to be fully differential to maximize dynamic variable gain amplifier that implements a number of range while also optimizing for low, even-order proprietary circuit design techniques to specifically harmonic distortion. address the performance demands of medical ultrasound systems. CW doppler signal processing is facilitated by routing the differential LNA outputs to V/I amplifier stages. The VCA8500 is an 8-channel VGA that is ideally The resulting signal currents of each channel then suited for portable ultrasound applications. It offers connect to an switch matrix that is controlled unparalleled low-noise and low-power performance at through the serial interface and a corresponding a high level of integration. For the TGC signal path, register. The CW outputs are typically routed to a each channel consists of a 20dB fixed-gain low-noise passive delay line that allows coherent summing amplifier (LNA), a linear-in-dB voltage-controlled (beam forming) of the active channels and additional attenuator (VCA), and a programmable gain amplifier off-chip signal processing, as shown in Figure (PGA), as well as a clamping and low-pass filter stage. Digitally controlled through the logic interface, settings: simply operate the VCA8500 in TGC mode. In this 20dB, 25dB, 27dB, and 30dB. At its highest setting, mode, the CW blocks (V/I amplifiers and switch the total available gain of the VCA8500 is therefore matrix) remain powered down, and the CW outputs 50dB, sufficient for 10-bit systems. To facilitate the can be unconnected. logarithmic time-gain compensation required for ultrasound systems, the VCA is designed to provide a 46dB attenuation range. Here, all channels are simultaneously controlled by an externally-applied control voltage CNTL in the range of to 1.2V. Figure 60. Functional Block Diagram Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com LOW-NOISE AMPLIFIER (LNA) VOLTAGE-CONTROLLED ATTENUATOR RSAttenuator Input Attenuator Output A1-A8□Attenuator□Stages Control Input VB Q2 Q3 QS C -C Clipping□Amplifiers1 8 Q5 Q6 Q7 Q8 A1 A2 A3 A4 A5 A6 A7 A8 VCNTRL VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 The attenuator is essentially a variable voltage divider that consists of the series input resistor S and As with many high-gain systems, the front-end eight identical shunt FETs placed in parallel and amplifier is critical to achieve a certain overall controlled by sequentially activated clipping amplifiers performance level. Using a proprietary new (A1 through A8). Each clipping amplifier can be architecture, the LNA of the VCA8500 delivers understood as a specialized voltage comparator with exceptional low-noise performance, while operating a soft transfer characteristic and well-controlled on a very low quiescent current of only 8.3mA per output limit voltage. Reference voltages through channel. This current consumption is significantly are equally spaced over the to 1.2V control lower compared to CMOS-based architectures with voltage range. As the control voltage rises through similar noise performances. the input range of each clipping amplifier, the amplifier output rises from (FET completely ON) to The LNA performs a single-ended input to differential V CM V T (FET nearly OFF), where V CM is the output voltage conversion and is configured for a common source voltage and V T is the threshold fixed gain of 20dB (10V/V). The ultralow voltage of the FET. As each FET approaches its off input-referred noise of only 0.7nV/ Hz along with the state and the control voltage continues to rise, the linear input range of 250mV PP results in a wide next clipping amplifier/FET combination takes over for dynamic range that supports the high demands of the next portion of the piecewise-linear attenuation PW and CW ultrasound imaging modes. Larger input characteristic. signals can be accepted by the LNA, but distortion performance degrades as input signals levels Thus, low control voltages have most of the FETs increase. The LNA input is internally biased to turned on, producing maximum signal attenuation. approximately 2.4V; the signal source should be Similarly, high control voltages turn the FETs off, ac-coupled to the LNA input by an adequately-sized leading to minimal signal attenuation. Therefore, each capacitor. Internally, the LNA directly drives the VCA, FET acts to decrease the shunt resistance of the avoiding the typical drawbacks of ac-coupled voltage divider formed by R S and the parallel FET architectures, such as slow overload recovery. network. (VCA) The amplified differential signal swing that comes from the LNA is reduced by the subsequent VCA stage. The VCA is designed to have a linear-in-dB attenuation characteristic; that is, the average gain loss in dB is constant for each equal increment of the control voltage CNTL Figure shows the simplified schematic of this VCA stage. Figure 61. Voltage-Controlled Attenuator Simplified Schematic Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com PROGRAMMABLE POST-GAIN AMPLIFIER PROGRAMMABLE CLAMPING LOW-PASS FILTER RG Clamp Gain Control Bits From Attenuator Clamp Control Bit T o Low-Pass Filter PGA VCM (+1.65V) OUT ( ) OUT VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 (PGA) To further optimize the overload recovery behavior of Following the VCA is a programmable post-gain a complete TGC channel, the VCA8500 integrates a amplifier (PGA). Figure shows a simplified programmable clamping stage, as shown in schematic of the PGA, including the clamping stage. Figure This clamping stage precedes the The gain of this PGA can be configured to four low-pass filter in order to prevent the filter circuit from different gain settings: 20dB, 25dB, 27dB, and 30dB, being driven into overload, the result of which would programmable through the serial port; see Table be an extended recovery time. Programmable through the serial interface, the clamping level can be The PGA structure consists of a differential, either set to clamp the output to approximately 1.7V PP programmable-gain voltage-to-current converter differential, or be disabled. Disabling the clamp stage followed by transimpedance amplifiers to create function increases the current consumption on the and buffer each side of the differential output. Low 3.3V analog supply (AVDD1) by about 3mA for the input noise is also a requirement for the PGA design full device. Note that with the clamp function enabled, as a result of the large amount of signal attenuation the third-harmonic distortion increases. that can be applied in the preceding VCA stage. At minimum VCA attenuation (used for small input signals), the LNA noise dominates; at maximum VCA attenuation (large input signals), the attenuator and As part of a typical data acquisition system, the signal PGA noise dominates. bandwidth generally must be limited by the use of an anti-aliasing filter before the analog-to-digital converter (ADC). The VCA8500 integrates such an anti-aliasing filter in the form of a programmable low-pass filter (LPF) for each channel. The LPF is designed as a differential, active, second-order filter that approximates a Butterworth characteristic, with typically 12dB per octave roll-off. Figure shows the simplified schematic of half the differential active low-pass filter. Programmable through the serial interface, the 3dB frequency corner can be set to either 10MHz or 15MHz. The filter is set for all channels simultaneously. Figure 62. Post-Gain Amplifier (Simplified Schematic) Figure 63. Clamping Stage and Low-Pass Filter (Simplified Schematic) Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com APPLICATION INFORMATION ANALOG INPUT AND LNA T o Attenuator 8k/c87 8k/c87 7pF0.1/c109F CIN /c179 /c1090.1 F VB (+2.4V) IN VBL T/R VCA8500 VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 This architecture minimizes any loading of the signal source that may otherwise lead to a frequency-dependent voltage divider. Moreover, the While the LNA is designed as a fully differential closed-loop design yields very low offsets and offset amplifier, it is optimized to perform a single-ended drift; this consideration is important because the LNA input to differential output conversion. A simplified directly drives the subsequent voltage-controlled schematic of an LNA channel is shown in Figure attenuator. A bias voltage B of +2.4V is internally applied to The LNA of the VCA8500 uses the benefits of a the LNA inputs through Ω resistors. In addition, the bipolar process technology to achieve an dedicated signal input (IN pin) includes a pair of exceptionally low-noise voltage of 0.7nV/ Hz and a back-to-back diodes that provide a coarse input low current noise of only 3pA/ Hz With these clamping function in case the input signal rises to input-referred noise specifications, the VCA8500 very large levels, exceeding 0.7V PP This achieves very low noise figure numbers over a wide configuration prevents the LNA from being driven into range of source resistances and frequencies (see a severe overload state, which may otherwise cause Figure in the Typical Characteristics). The optimal an extended overload recovery time. The integrated noise power matching is achieved for source diodes are designed to handle a dc current of up to impedances of around 200 Ω approximately 5mA. Depending on the application requirements, the system overload characteristics Further details of the VCA8500 input and output may be improved by adding external Schottky diodes noise performance are shown in the Typical at the LNA input, as shown in Figure Characteristic graphs; the input-referred noise voltage is derived by dividing the output-referred noise by the As Figure also shows, the complementary LNA measured gain at each point along the gain control input BL pin) is internally decoupled by a small range. capacitor. Furthermore, for each input channel, a separate V BL pin is brought out for external Noise Figure versus Source Resistance S bypassing. This bypassing should be done with a small, 0.1 µ F (typical) ceramic capacitor placed in R S Ω NOISE FIGURE (dB) close proximity to each V BL pin. Attention should be 2.21 given to provide a low-noise analog ground for this 200 1.10 bypass capacitor. A noisy ground potential may 400 1.14 cause noise to be picked up and injected into the signal path, leading to higher noise levels. 1000 2.06 The LNA closed-loop architecture is internally compensated for maximum stability without the need of external compensation components (inductors or capacitors). At the same time, the total input capacitance is kept to a minimum with only 30pF. Figure 64. LNA Channel (Simplified Schematic) Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com OVERLOAD RECOVERY LNA Cable Probe T ransducer From Pulser /c45 5V +5V VCA8500 3k/c87 C2 /c179 /c109 0.1 FC1 3k/c87 RTBAS40

0.1 F/c109

diodes, which can be set by adjusting the Ω The VCA8500 is designed in particular for ultrasound resistor values; for example, setting a higher current condition. Such and reduced noise contribution. A typical front-end an overload can either be the result of a transmit protection circuitry may add in the order of 2nV/ Hz pulse feed-through or a strong echo, which can cause of noise to the signal path. This slight increase also overload of the LNA, the PGA, or both. As discussed depends on the value of the termination resistor T earlier, the LNA inputs are internally protected by a pair of back-to-back diodes to prevent severe As Figure shows, the front-end circuitry should be overload of the LNA. Figure illustrates an capacitively coupled to the LNA signal input (IN). This ultrasound receive channel front-end that includes coupling ensures that the LNA input bias voltage of typical external overload protection elements. Here, +2.4V is maintained and decoupled from any other four high-voltage switching diodes are configured in a biasing voltage before the LNA. bridge configuration and form the transmit/receive Within the VCA8500, overload can occur in either the (T/R) switch. During the transmit period, high voltage LNA or the PGA. LNA overload can occur as the pulses from the pulser are applied to the transducer result of T/R switch feed-through; and the PGA can elements and the T/R switch isolates the sensitive be driven into an overload condition by a strong echo LNA input from being damaged by the high voltage in the near-field while the signal gain is high. In any signal. However, it is common that fast transients up case, the VCA8500 is optimized for very short to several volts leak through the T/R switch and recovery times, as shown in Figure potentially overload the receiver. Therefore, an additional pair of clamping diodes is placed between the T/R switch and the LNA input. In order to clamp the over-voltage to small levels, Schottky diodes (such as the BAS40 series by Infineon are commonly used. For example, clamping to levels of 0.3V can significantly reduce the overall overload recovery performance. The T/R switch characteristics Figure 65. Typical Input Overload Protection Circuit of an Ultrasound System Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com VCA GAIN CONTROL LNA RS RS RF CF T o PGA Attenuator VCNTRL VCA8500 OUTPUT VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 When the VCA8500 operates in CW mode, the attenuator stage remains connected to the LNA The attenuator (VCA) for each of the eight channels outputs. Therefore, it is recommended to set the of the VCA8500 is controlled by a single-ended V CNTRL voltage to +1.2V in order to minimize the control signal input, the V CNTRL pin. The control internal loading of the LNA outputs. Small voltage range spans from to 1.2V, referenced to improvements in reduced power dissipation and ground. This control voltage varies the attenuation of improved distortion performance may also be the VCA based on its linear-in-dB characteristic with realized. its maximum attenuation (minimum gain) at V CNTRL 0V, and minimum attenuation (maximum gain) at V CNTRL 1.2V. Table shows the nominal gains for each of the four PGA gain settings. The total gain range is typically 46dB and remains constant independent of the PGA selected; the Max Gain column reflects the absolute gain of the full signal path comprised of the fixed LNA gain of 20dB and the programmable PGA gain. Table 12. Nominal Gain Control Ranges for Each of the Four PGA Gain Settings MIN GAIN AT MAX GAIN AT PGA GAIN V CNTRL V CNTRL 1.2V 20dB 4.5dB 41.5dB 25dB 0.5dB 45.5dB 27dB 1.5dB 47.5dB 30dB 3.5dB 49.5dB As previously discussed, the VCA architecture uses eight attenuator segments that are equally spaced in Figure 66. External Filtering of the V CNTL Input order to approximate the linear-in-dB gain-control slope. This approximation results in a monotonic slope; gain ripple is typically less than 0.5dB. The VCA8500 gain-control input has a 3dB The output stage of the VCA8500 delivers a bandwidth of approximately 1.5MHz. This wide differential output signal that swings symmetrically bandwidth, although useful in many applications, can around a fixed common-mode output voltage of allow high-frequency noise to modulate the gain +1.65V. The design of the output stage includes a control input. In practice, this modulation can easily common-mode control loop to hold the output be avoided by additional external filtering F and C F common-mode voltage stable over a wide range of of the control input, as Figure shows. Stepping the operating conditions. At the same time the output control voltage from to 1.2V, the gain control offset and drift are kept to a minimum, allowing the response time is typically less than 500ns to settle VCA8500 to be dc-coupled directly to other devices within 10% of the final signal level of a PP output. (such as an ADC). In cases where the output of the The control voltage input CNTRL pin) represents a VCA8500 drives devices with a non-matching input high-impedance input. Multiple VCA8500 devices can common-mode level, small ac-coupling capacitors be connected in parallel with no significant loading (for instance, 0.1 µ should be used. effects using the V CNTRL pin of each device. Note that It should be noted, however, that unlike many other when the V CNTRL pin is left unconnected, it floats up high-speed operational amplifiers, the VCA8500 is to a potential of about +3.7V. For any voltage level designed to drive a typical output load of Ω above 1.2V and up to 5.0V, the VCA continues to single-ended (from each output to ground) or Ω operate at its minimum attenuation level; however, it differentially. For most applications, this consideration is recommended to limit the voltage to approximately should not represent a limitation; many high-speed 1.5V or less. ADCs have input impedances in the k Ω range. For the VCA8500 to maintain the ability to provide the full PP output swing, however, it is recommended to keep the output loading to 800 Ω single-ended (1.6k Ω differential), or higher. In addition, care should be taken to keep the capacitive loading of the outputs to Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com INTERFACING TO ADCs /c45 /c45 /c45 /c45 /c45 /c45 /c45 100 Normalized□Amplitude□(dB) Frequency□(MHz) 1 10 10MHz 15MHz CW DOPPLER PROCESSING ADS5281 12-Bit 40MSPS INP INN VCA8500 OUT OUT Optional LPF VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 a minimum LOAD 18pF, differential). The user uses sampling rates of up to 40MSPS. Here, the ratio should examine all factors that contribute to the total of the bandwidth (BW) to the Nyquist frequency S /2) load LTOTAL R L X L Depending on the overall is approximately 0.75, which provides a good system requirements, trade-offs can be made compromise between the passband area and the stop between the output loading and the desired distortion band attenuation. Choosing the lower 10MHz levels and output swing. bandwidth setting may be considered if the sampling rate is reduced further, or if the input signal bandwidth is lower. In this case, the reduced noise bandwidth can potentially improve the noise floor. The VCA8500 is ideally suited to drive the ADS5281 a low-power, octal, 12-bit ADC that can be operated at sampling rates of up to 50MSPS. The VCA outputs can be directly connected the ADC inputs without the need for any external components, as shown in Figure Observing proper layout considerations, the two devices can be placed in close proximity to each other and allow for a very compact printed circuit board (PCB) layout. The ADS5281 systems: low channel power of only 55mW/ch (at 40MSPS); high signal-to-noise ratio of 70dB; and fast overload recovery time of only one clock cycle. The VCA8500 can be configured to complement this level of performance by choosing the most suitable amplification setting of the post-gain Figure 68. Normalized Frequency Response of the amplifier. For example, the ADS5281 has a full-scale 10MHz and 15MHz Low-Pass Filter input of PP and an input-referred noise of approximately 50nV/ Hz In order to achieve the highest combined dynamic range performance, the PGA gain can be set to 20dB. With this gain setting, The VCA8500 integrates many of the elements the output-referred noise is dominated by the noise necessary to allow for the implementation of a CW contribution of the attenuator and PGA and remains doppler processing circuit, such as a V/I converter for constant over most of the gain control range each channel and a cross-point switch matrix with an (approximately 65nV/ Hz Only at the high end of 8-input into 10-output 10) configuration. the gain control range does the LNA and source-related noise contribution become the In order to switch the VCA8500 from the default TGC prevailing factor. Higher gain PGA settings may be mode operation into CW mode, bit of the control chosen to interface to lower resolution ADCs that register must be updated to low ('0'). This setting also have a higher noise floor. enables access to all other registers that determine the switch matrix configuration (see the Input Register Bit Map tables). In order to process CW signals, the LNA internally feeds into a differential V/I amplifier stage. The transconductance of the V/I amplifier is typically 16.4mA/V with a 100mV PP input signal. For proper operation, the CW outputs must be connected to an external bias voltage of +2.5V. Each CW output Figure 67. The VCA8500 Can Be Interfaced to the is designed to sink a small dc current of 0.9mA, and ADS5281 Without the Need for External can deliver a signal current up to 2.9mA PP Components Figure shows the normalized frequency response of the low-pass filter. The 15MHz bandwidth is intended to be the upper bandwidth for a system that Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com ADCVCM0 (+2.5V) Amplifier I□and□Q Channel ADC VCA8500 CW□Out 8□In□By□10□Out CW0 CW1 CW2 CW3 CW4 CW5 CW6 CW7 CW8 CW9 VCA8500 CW□Out 8□In□By□10□Out CW0 CW1 CW2 CW3 CW4 CW5 CW6 CW7 CW8 CW9 Passive Delay Line Clock L□220 H/c109 VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 The resulting signal current then passes through the After summing, the CW signal path further consists of switch matrix. Depending on the programmed a high dynamic range mixer for down-conversion to configuration of the switch matrix, any V/I amplifier I/Q base-band signals. The I/Q signals are then current output can be connected to any of CW band-limited (that is, low-frequency

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outputs. This design is a simple current-summing removed) in a filter stage that precedes a pair of circuit such that each CW output can represent the high-resolution, low sample rate ADCs. sum of any or all of the channel currents. The CW outputs are typically routed to a passive LC delay line, allowing coherent summing of the signals. Figure 69. Conceptual CW Doppler Signal Path Using Current Summing and a Passive Delay Line for Beamforming Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com POWER SUPPLIES POWER-DOWN MODES VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 respective charges, minimizing the wake-up response time. As an example, Figure illustrates the standby The VCA8500 operates on two supply rails, a +3.3V power-up/down response when the PD pin is toggled and a +5V supply. At initial power-up, the part with a period of approximately 7.7ms (130Hz) with a operates in the TGC mode, with the registers in the 50% duty cycle. Here, the wake-up response time is default configurations (see Table approximately µ while the power-down time is instantaneous 0.2 µ s). Factors such as the control In TGC mode, only the VCA (attenuator) draws a voltage setting, input signal level, PD pin toggle time, small current (typically 1.5mA) from the +5V supply. and duty cycle primarily affect the wake-up response Switching into the CW mode, the internal V/I time. Therefore, the user should evaluate the amplifiers are then powered from the +5V rails as VCA8500 performance under the desired system well, raising the operating current on the +5V rail. At conditions. the same time, the post-gain amplifiers (PGA) are powered down, reducing the current consumption on When in standby mode, the part typically dissipates the +3.3V rail (refer to the Electrical Characteristics only 104mW, representing an 80% power reduction table for details). compared to the normal operating mode. This function is controlled through the PD pin (pin 49), All supply rails for the VCA8500 should be clean, which is designed to interface to +3.3V low-voltage low-noise, analog supplies. This consideration logic. For normal operation, the PD pin should be tied includes the +3.3V digital supply DVDD (pin 59) that to a logic low ('0'); pulling this pin high ('1') places the connects to the internal logic blocks of the VCA8500. VCA into standby mode. It is recommended to tie the DVDD pin to the same +3.3V analog supply as the AVDD1 pins, rather than To achieve the lowest power dissipation of only a different +3.3V rail that may also power other logic 19mW, the VCA8500 can be placed in shutdown devices in the system. Transients and noise mode. This mode is controlled through the serial generated by those devices can couple into the interface by setting bit (PWR) of the control VCA8500 and degrade performance. register to '1'. When in shutdown mode, all circuits (including references) within the VCA8500 are While the VCA8500 uses a thermally-enhanced QFN powered-down, causing the bypass capacitors to be package that includes a PowerPAD on its backside, discharged. Consequently, the wake-up time depends the primary function of the PowerPAD is to provide a largely on the time needed to charge the bypass solid ground reference point. Care should be taken to capacitors back up. Another factor is the elapsed time use this package pad during the PCB layout phase as the VCA8500 spends in shutdown mode. the main ground return point. The VCA8500 a standby mode and a shutdown mode. The standby mode function allows the VCA8500 to be rapidly placed in a low-power state. When in this mode, most amplifiers in the signal path are powered-down, while the internal references remain active. This state ensures that the external bypass capacitors retain the Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

www.ti.com PD CW0 CW1 CW2 CW3 CW4 D_IN CLK D_OUT RST DVDD CW5 CW6 CW7 CW8 CW9 OUT8 OUT8 OUT7 OUT7 OUT6 OUT6 OUT5 OUT5 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 CW1 CW0 PD IN5 CW2 CW3 CW4 DIN CLK DOUT RST +3.3V CW5 CW6 CW7 CW8 CW9 OUT5N VBL1 1 2 3 5 6 7 8 VBL2VBL3 IN2 VBL4IN3IN1 AVDD1 IN4 9 10 11 13 14 15 16 VB1 VB5 VB3 AVDD1V CM VCNTRLAVDD2 VBL5 VBL6VBL7 IN6 VBL8 IN7IN5 AVDD1 IN8 VB4 V REFHVB6 AVDD1V REFL AVDD2 VB2 C22

2.2 F/c109

1 F/c109 C31

+3.3V IN6 C14

1 F/c109

+3.3V C14 48 47 46 44 43 42 414540 39 38 36 35 34 3337 VCA8500 OUT_QFN_RGC-64 +5V R10 0/c87 OUT5P R11 0/c87 OUT6N C42 R12 0/c87 OUT6P R13 0/c87 OUT7N C43 R14 0/c87 OUT7P R15 0/c87 OUT8N C44 R16 0/c87 OUT8P R17 0/c87 OUT1N C37 0/c87 OUT1P 0/c87 OUT2N C38 0/c87 OUT2P 0/c87 OUT3N C39 0/c87 OUT3P 0/c87 OUT4N C40 0/c87 OUT4P 0/c87 IN1 C10

0.01 F/c109

+3.3V IN2 C10 +3.3V +5V (1) V CONTROL Values for R and C should be selected for a desired time constant. (2) Optional components: Values for R to R and C to C should be selected based on the analog-to-digital converter selected. (3) The +3.3V supply connections for DVDD and AVDD1 should be joined to a low-noise +3.3V system supply. Consider filtering any supply noise with an LC filter. Figure 70. Typical Connection Diagram Submit Documentation Feedback Copyright 2008, Texas Instruments Incorporated Product Folder Link(s): VCA8500

www.ti.com GROUNDING AND BYPASSING BOARD LAYOUT VCA8500 SBOS390A JANUARY 2008 REVISED MARCH 2008 reference pins can be bypassed with smaller capacitor values, typically 0.1 µ For best results The VCA8500 uses a thermally-enhanced QFN choose low-inductance ceramic chip capacitors (size package, with an exposed PowerPAD on the back 402) and place them as close to the device pins as side of the package. This backside pad is the only possible. ground reference point of the VCA8500, and it should be connected to a low-noise system ground plane. All bypassing and power supplies for the VCA8500 should be referenced to this ground point. Proper grounding and bypassing, short lead length, and the use of ground planes are particularly All supply pins should be bypassed with 0.1 µ F important for high-frequency designs. Achieving ceramic chip capacitors (size 0603 or smaller). In optimum performance with a high gain amplifier such order to minimize lead and trace inductance, the as the VCA8500 requires careful attention to the PCB capacitors should be located as close to the supply layout to minimize the effect of board parasitics and pins as possible. Where double-sided component optimize component placement. A multilayer PCB mounting is allowed, these capacitors are best placed usually ensures best results and allows convenient directly under the package. In addition, larger bipolar component placement. decoupling capacitors (2.2 µ F to µ F), effective at lower frequencies, may also be used on the main More details on the PowerPAD PCB layout and supply pins. They can be placed on the PCB in assembly process can be found in the Texas proximity to (less than 0.5in, or 12.7mm from) the Instruments Application Reports, Power-Pad VCA8500. Thermally-Enhanced Package (SLMA002) and QFN/SON PCB Attachment (SLUA271A) These The VCA8500 internally generates a number of documents can be downloaded from the TI web site reference voltages, such as the bias voltages (VB1 www.ti.com through VB6). Note that in order to achieve the best low-noise performance, VB1 (pin 13) must be bypassed with a capacitor value of at least µ the recommended value is 2.2 µ All other designated Copyright 2008, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): VCA8500

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) VCA8500IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR VCA8500IRGCRG4 ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR VCA8500IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR VCA8500IRGCTG4 ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 11-Jul-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) VCA8500IRGCR VQFN RGC 64 2000 333.2 345.9 28.6 VCA8500IRGCT VQFN RGC 64 250 333.2 345.9 28.6 PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2008 Pack Materials-Page 2

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