VCA820

VCA820 Wideband, > 40-dB Adjust Range, Linear in dB Variable Gain Amplifier datasheet (Rev. D)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SBOS395,D]
• PDF pages: 51

Technical content

Frequency□(Hz) Common-Mode□Rejection□Ratio□(dB) 100k 100M 10M1M Input-Referred 1 kΩ +VIN RG+ RG- -V IN FB 200Ω RS RS 20Ω VIN+ VIN- VCA820 Av = 20 dB Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community VCA820 SBOS395D –OCTOBER 2007–REVISED SEPTEMBER 2015 VCA820Wideband,>40-dBAdjustRange,LinearindB VariableGainAmplifier The VCA820 internal architecture consists of two1 Features input buffers and an output current feedback amplifier 1• 150-MHz Small-Signal Bandwidth stage, integrated with a multiplier core to provide a

• 137-MHz, 5-VPP Bandwidth (G = +10 V/V) complete variable gain amplifier (VGA) system that does not require external buffering. The maximum• 0.1-dB Gain Flatness to 28 MHz gain is set externally with two resistors, providing• 1700-V/μs Slew Rate flexibility in designs. The maximum gain is intended• > 40-dB Gain Adjust Range to be set between +2 V/V and +100 V/V. Operating from ±5-V supplies, the gain control voltage for the• High Gain Accuracy: 20 dB ±0.4dB VCA820 adjusts the gain linearly in dB as the control• High Output Current: 160 mA voltage varies from 0 V to +2 V. For example, set for a maximum gain of +10 V/V, the VCA820 provides 202 Applications dB, at +2-V input, to –20 dB at 0-V input of gain
• AGC Receivers With RSSI control range. The VCA820 offers excellent gain linearity. For a 20-dB maximum gain, and a gain-• Differential Line Receivers control input voltage varying between 1 V and 2 V,• Pulse Amplitude Compensation the gain does not deviate by more than ±0.4dB
• Variable Attenuators (maximum at +25°C). Device Information(1)3 Description PART NUMBER PACKAGE BODY SIZE (NOM)The VCA820 is a dc-coupled, wideband, linear in dB, continuously variable, voltage-controlled gain SOIC (14) 8.65 mm × 3.91 mm VCA820amplifier. The VCA820 provides a differential input to VSSOP (10) 3.00 mm × 3.00 mm single-ended conversion with a high-impedance gain (1) For all available packages, see the orderable addendum atcontrol input, used to vary the gain down 40 dB from the end of the data sheet.the nominal maximum gain set by the gain resistor (RG) and feedback resistor (RF). space space space Wideband Differential to Single-Ended Amplifier Common-Mode Rejection Ratio An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SBOS395D –OCTOBER 2007–REVISED SEPTEMBER 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (October 2009) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision B (December 2008) to Revision C Page Changes from Revision A (August 2008) to Revision B Page

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Product Folder Links: VCA820

5 Device Options

Table 1. Wideband Variable Gain Amplifiers - VGAs

6 Pin Configuration and Functions

SBOS395D –OCTOBER 2007–REVISED SEPTEMBER 2015 www.ti.com

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Power supply ±6.3 V Internal power dissipation See Thermal Information Input voltage ±VS V Junction temperature (TJ) 150 °C Junction temperature (TJ), maximum continuous operation 140 °C Storage temperature –65 125 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged device model (CDM), per JEDEC specification JESD22- ±500V(ESD) Electrostatic discharge VC101(2) Machine model (MM) ±200 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Operating voltage 7 10 12 V Operating temperature –40 25 85 °C

7.4 Thermal Information

THERMAL METRIC(1) D [SOIC] DGS [VSSOP] UNIT

14 PINS 10 PINS

RθJA Junction-to-ambient thermal resistance 80 130 °C/W RθJC(top) Junction-to-case (top) thermal resistance 49.8 46.6 °C/W RθJB Junction-to-board thermal resistance 44.9 94.3 °C/W ψJT Junction-to-top characterization parameter 13.8 2.2 °C/W ψJB Junction-to-board characterization parameter 44.6 92.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

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Product Folder Links: VCA820

www.ti.com SBOS395D –OCTOBER 2007–REVISED SEPTEMBER 2015

7.5 Electrical Characteristics: VS = ±5 V

At AVMAX = 20 dB, RF = 1 kΩ, RG = 200 Ω, and RL = 100 Ω, unless otherwise noted. TESTPARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL(1) AC PERFORMANCE AVMAX = 6 dB, VO = 1 TJ = 25°C 168VPP, VG = +2 V Small-signal bandwidth (SO-14 AVMAX = 20 dB, VO = 1 TJ = 25°C 150 MHz Cpackage) VPP, VG = +2 V AVMAX = 40 dB, VO = 1 TJ = 25°C 118VPP, VG = +2 V AVMAX = 20 dB, VO = 5Large-signal bandwidth TJ = 25°C 137 MHz CVPP, VG = +2 V TJ = 25°C 170 200 TJ = 0°C to 70°C(2) 170Gain control bandwidth VG = 1 VDC + 10 mVPP MHz B TJ = –40°C to 16585°C(2) AVMAX = 20 dB, VO = 1Bandwidth for 0.1dB flatness TJ = 25°C 28 MHz CVPP, VG = +2 V TJ = 25°C 1500 1700 AVMAX = 20 dB, VO = 5-V TJ = 0°C to 70°C(2) 1500Slew rate V/μs Bstep, VG = +2 V TJ = –40°C to 145085°C(2) TJ = 25°C 2.5 3.1 AVMAX = 20 dB, VO = 5-V TJ = 0°C to 70°C(2) 3.2Rise-and-fall time ns Bstep, VG = +2 V TJ = –40°C to 3.285°C(2) AVMAX = 20 dB, VO = 5-VSettling time to 0.01% TJ = 25°C 11 ns Cstep, VG = +2 V Harmonic distortion TJ = 25°C –60 –62 TJ = 0°C to 70°C(2) –602nd-harmonic VO = 2 VPP, f = 20 MHz dBc B TJ = –40°C to –6085°C(2) TJ = 25°C –66 –68 TJ = 0°C to 70°C(2) –663rd-harmonic VO = 2 VPP, f = 20 MHz dBc B TJ = –40°C to –6685°C(2) Input voltage noise f > 100 kHz TJ = 25°C 8.2 nV/√Hz C Input current noise f > 100 kHz TJ = 25°C 2.6 pA/√Hz GAIN CONTROL TJ = 0°C to 70°C(2) ±0.5Absolute gain error AVMAX = 20 dB, VG = 2 V dB A VCTRL0 TJ = 25°C 0.85 V C VSLOPE TJ = 25°C 0.09 V C AVMAX = 20 dB, VG = 1 V, TJ = 0°C to 70°C(2) ±0.5Absolute gain error dB A(G = 18.06 dB) TJ = –40°C to ±0.685°C(2) (1) Test levels: (A) 100% tested at +25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Junction temperature = ambient at low temperature limit; junction temperature = ambient +23°C at high temperature limit for over temperature specifications. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: VCA820

SBOS395D –OCTOBER 2007–REVISED SEPTEMBER 2015 www.ti.com Electrical Characteristics: VS = ±5 V (continued) At AVMAX = 20 dB, RF = 1 kΩ, RG = 200 Ω, and RL = 100 Ω, unless otherwise noted. TESTPARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL(1) TJ = 25°C –26 –24 TJ = 0°C to 70°C(2) –24Gain at VG = 0.2V Relative to maximum gain dB A TJ = –40°C to –2385°C(2) TJ = 25°C –26 –24 TJ = 0°C to 70°C(2) –24Gain at VG = 0.2V Relative to maximum gain dB A TJ = –40°C to –2385°C(2) TJ = 25°C 10 16 TJ = 0°C to 70°C(2) 16.6Gain control bias current μA A TJ = 0°C to 70°C(2) ±12 Average gain control nA/°C BTJ = –40°C tobias current drift ±1285°C(2) Gain control input impedance TJ = 25°C 70 || 1 kΩ || pF C DC PERFORMANCE TJ = 25°C ±4 ±17 AVMAX = 20 dB, VCM = 0 TJ = 0°C to 70°C(2) ±17.8Input offset voltage mV AV, VG = 1 V TJ = –40°C to ±1985°C(2) TJ = 0°C to 70°C(2) 30 Average input offset AVMAX = 20 dB, VCM = 0 μV/°C BTJ = –40°C tovoltage drift V, VG = 1 V 3085°C(2) TJ = 25°C 19 25 AVMAX = 20 dB, VCM = 0 TJ = 0°C to 70°C(2) 29Input bias current μA AV, VG = 1 V TJ = –40°C to 3185°C(2) TJ = 0°C to 70°C(2) 90 Average input bias AVMAX = 20 dB, VCM = 0 nA/°C BTJ = –40°C tocurrent drift V, VG = 1 V 9085°C(2) AVMAX = 20 dB, VCM = 0 TJ = 0°C to 70°C(2) ±3.2Input offset current μA AV, VG = 1 V TJ = –40°C to ±3.585°C(2) TJ = 0°C to 70°C(2) ±16 Average input offset AVMAX = 20 dB, VCM = 0 nA/°C BTJ = –40°C tocurrent drift V, VG = 1 V ±1685°C(2) Maximum current through gain TJ = 0°C to 70°C(2) ±2.55 mA Bresistance TJ = –40°C to ±2.585°C(2)

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Product Folder Links: VCA820

www.ti.com SBOS395D –OCTOBER 2007–REVISED SEPTEMBER 2015 Electrical Characteristics: VS = ±5 V (continued) At AVMAX = 20 dB, RF = 1 kΩ, RG = 200 Ω, and RL = 100 Ω, unless otherwise noted. TESTPARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL(1) INPUT Most positive common-mode TJ = 0°C to 70°C(2) +1.6RL = 100 Ω V Ainput voltage TJ = –40°C to +1.685°C(2) Most negative common-mode TJ = 0°C to 70°C(2) –2.1RL = 100 Ω V Ainput voltage TJ = –40°C to –2.185°C(2) TJ = 25°C 65 80 TJ = 0°C to 70°C(2) 60Common-mode rejection ratio VCM = ±0.5 V dB A TJ = –40°C to 6085°C(2) Input impedance Differential TJ = 25°C 0.5 || 1 MΩ || pF C Common-mode TJ = 25°C 0.5 || 2 MΩ || pF C OUTPUT TJ = 0°C to 70°C(2) ±3.75RL = 1 kΩ V A Output voltage swing TJ = 0°C to 70°C(2) ±3.6RL = 100 Ω V A TJ = 25°C ±140 ±160 TJ = 0°C to 70°C(2) ±130Output current VO = 0 V, RL = 5 Ω mA A AVMAX = 20 dB, f > 100Output impedance TJ = 25°C 0.01 Ω CkHz, VG = +2 V POWER SUPPLY Specified operating voltage TJ = 25°C ±5 V C Minimum operating voltage TJ = 25°C ±3.5 V C TJ = 25°C ±6 TJ = 0°C to 70°C(2) ±6Maximum operating voltage V A TJ = –40°C to ±685°C(2) TJ = 25°C 34 35 TJ = 0°C to 70°C(2) 35.5Maximum quiescent current VG = 1 V mA A TJ = –40°C to 3685°C(2) TJ = 25°C 34 32.5 TJ = 0°C to 70°C(2) 32Minimum quiescent current VG = 1 V mA A Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: VCA820

SBOS395D –OCTOBER 2007–REVISED SEPTEMBER 2015 www.ti.com Electrical Characteristics: VS = ±5 V (continued) At AVMAX = 20 dB, RF = 1 kΩ, RG = 200 Ω, and RL = 100 Ω, unless otherwise noted. TESTPARAMETER TEST CONDITIONS MIN TYP MAX UNIT LEVEL(1) TJ = 25°C –61 –68 Power-supply rejection ratio TJ = 0°C to 70°C(2) –59 dB A(–PSRR) TJ = –40°C to –5885°C(2)

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Product Folder Links: VCA820

NOTE: 3dB□bandwidth□will□vary□with□the□package. See□the□Application□section□for□more□details.

7.6 Typical Characteristics: VS = ±5 V, DC Parameters

At TA = +25°C, RL = 100 Ω, VG = +1 V, and VIN = single-ended input on +VIN with –VIN at ground, unless otherwise noted. Figure 1. Maximum Differential Input Voltage vs Gain Figure 2. Maximum Gain Adjust Range vs Feedback Figure 3. Maximum Gain Adjust Range vs Peak-to-Peak Figure 4. Gain Error Band vs Gain Control Voltage Figure 5. Nominal Gain vs Calculated Gain Figure 6. Recommended RF and RG vs AVMAX

7.7 Typical Characteristics: VS = ±5 V, DC and Power-Supply Parameters

At TA = +25°C, RL = 100 Ω, VG = +1 V, and VIN = single-ended input on +VIN with –VIN at ground, unless otherwise noted. Figure 7. Supply Current vs Control Voltage (AVMAX = 6 dB) Figure 8. Supply Current vs Control Voltage (AVMAX = 20 dB) Figure 9. Supply Current vs Control Voltage (AVMAX = 40 dB) Figure 10. Typical DC Drift vs Temperature

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7.8 Typical Characteristics: VS = ±5 V, AVMAX = 6 dB

SO-14 package, unless otherwise noted. Figure 11. Small-Signal Frequency Response Figure 12. Large-Signal Frequency Response Figure 13. Small-Signal Pulse Response Figure 14. Large-Signal Pulse Response Figure 15. Video Differential Gain and Differential Phase Figure 16. Gain Flatness, Deviation From Linear Phase

SO-14 package, unless otherwise noted. Figure 17. Harmonic Distortion vs Frequency Figure 18. Harmonic Distortion vs Load Resistance Figure 19. Harmonic Distortion vs Output Voltage Figure 20. 20-MHz Harmonic Distortion vs Gain Control Figure 21. 2-Tone, 3rd-Order Intermodulation Intercept Figure 22. 2-Tone, 3rd-Order Intermodulation Intercept vs

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SO-14 package, unless otherwise noted. Figure 29. Recommended RS vs Capacitive Load Figure 30. Frequency Response vs Capacitive Load Figure 31. Output Voltage Noise Density Figure 32. Input Current Noise Density

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7.9 Typical Characteristics: VS = ±5 V, AVMAX = 20 dB

Figure 33. Small-Signal Pulse Response Figure 34. Large-Signal Pulse Response Figure 35. Gain Flatness, Deviation From Linear Phase Figure 36. Output Voltage Noise Density Figure 37. Harmonic Distortion vs Frequency Figure 38. Harmonic Distortion vs Load Resistance

Figure 39. Harmonic Distortion vs Output Voltage Figure 40. 20-MHz Harmonic Distortion vs Gain Control Figure 41. 2-Tone, 3rd-Order Intermodulation Intercept Figure 42. 2-Tone, 3rd-Order Intermodulation Intercept vs Figure 43. Gain vs Gain Control Voltage Figure 44. Gain Control Frequency Response

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Figure 51. Group Delay vs Frequency

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7.10 Typical Characteristics: VS = ±5 V, AVMAX = 40 dB

SO-14 package, unless otherwise noted. Figure 52. Small-Signal Frequency Response Figure 53. Large-Signal Frequency Response Figure 54. Small-Signal Pulse Response Figure 55. Large-Signal Pulse Response Figure 56. Gain Flatness Figure 57. Output Voltage Noise Density

SO-14 package, unless otherwise noted. Figure 58. Harmonic Distortion vs Frequency Figure 59. Harmonic Distortion vs Load Resistance Figure 60. Harmonic Distortion vs Output Voltage Figure 61. 20-MHz Harmonic Distortion vs Gain Control Figure 62. 2-Tone, 3rd-Order Intermodulation Intercept Figure 63. 2-Tone, 3rd-Order Intermodulation Intercept vs

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SO-14 package, unless otherwise noted. Figure 70. Group Delay vs Gain Control Voltage Figure 71. Group Delay vs Frequency

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R 200 G RG+ VIN RG- -VIN IRG VG VOUT FB RF VREF VOUT +VIN VCA820 www.ti.com SBOS395D –OCTOBER 2007–REVISED SEPTEMBER 2015

8 Detailed Description

8.1 Overview

The VCA820 is a voltage controlled variable gain amplifier with differential inputs and a single ended output. The maximum gain is set by external resistors while the gain range is controlled by an external analog voltage. The maximum gain is designed for gains of 2 V/V up to 100 V/V and the analog control allows a gain range of over 40 dB. The VCA820 Input consists of two buffers which, together create a fully symmetrical, high impedance differential input with a typical common mode rejection of 80 dB. The gain set resistor is connected between the two input buffer output pins, so that the input impedance is independent of the gain settings. The bipolar inputs have a input voltage range of +1.6 and –2.1 V on ±5-V supplies. The amplifier maximum gain is set by external resistors, but the internal gain control circuit is controlled by a continuously variable, analog voltage. The gain control is a multiplier stage which is linear in dB. The gain control input pin operates over a voltage range of 0 V to 2 V. The VCA820 contains a high-speed, high-current output buffer. The output stage can typically swing ±3.9 V and source and sink ±160 mA. The VCA820 can be operated over a voltage range of ±3.5 V to ±6 V.

8.2 Functional Block Diagram

8.3 Feature Description

The VCA820 can be operated with both single ended or differential input signals. The inputs present consistently high impedance across all gain configurations. By using an analog control signal the amplifier gain is continuously variable for smooth, glitch-free gain changes. With a large signal bandwidth of 137 MHz and a slew rate of 1700 V/µs the VCA820 offers linear performance over a wide range of signal amplitudes and gain settings. The low-impedance/high-current output buffer can drive loads ranging from low impedance transmission lines to high-impedance, switched-capacitor analog to digital converters. By using closely matched internal components the VCA820 offers gain accuracy of ±0.4 dB. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 23 Product Folder Links: VCA820

I =RG VOUT A R /c180VMAX G VCA820 SBOS395D –OCTOBER 2007–REVISED SEPTEMBER 2015 www.ti.com

8.4 Device Functional Modes

The VCA820 functions as a differential input, single-ended output variable gain amplifier. This functional mode is enabled by applying power to the amplifier supply pins and is disabled by turning the power off. The gain is continuously variable through the analog gain control input. While the gain range is fixed the maximum gain is set by two external components, Rf and Rg as shown in the Functional Block Diagram. The maximum gain is equal to 2x (Rf / Rg). This gain is achieved with a 2-V voltage on the gain adjust pin VG. As the voltage decreases on the VG pin, the gain decreases in a linear in dB fashion with over 40 dB of gain range from 2-V to 0-V control voltage. As with most other differential input amplifiers, inputs can be applied to either one or both of the amplifier inputs. The amplifier gain is controlled through the gain control pin.

8.4.1 Maximum Gain of Operation

This section describes the use of the VCA820 in a fixed-gain application in which the VG control pin is set at VG = +2 V. The tradeoffs described here are with bandwidth, gain, and output voltage range. In the case of an application that does not make use of the VGAIN, but requires some other characteristic of the VCA820, the RG resistor must be set such that the maximum current flowing through the resistance IRG is less than ±2.6-mA typical, or 5.2 mAPP as defined in the Electrical Characteristics: VS = ±5 V table, and must follow Equation 1. (1) As illustrated in Equation 1, once the output dynamic range and maximum gain are defined, the gain resistor is set. This gain setting in turn affects the bandwidth, because in order to achieve the gain (and with a set gain element), the feedback element of the output stage amplifier is set as well. Keeping in mind that the output amplifier of the VCA820 is a current-feedback amplifier, the larger the feedback element, the lower the bandwidth as the feedback resistor is the compensation element. Limiting the discussion to the input voltage only and ignoring the output voltage and gain, Figure 1 illustrates the tradeoff between the input voltage and the current flowing through the gain resistor.

8.4.2 Output Current and Voltage

The VCA820 provides output voltage and current capabilities that are unsurpassed in a low-cost monolithic VCA. Under no-load conditions at +25°C, the output voltage typically swings closer than 1 V to either supply rails; the +25°C swing limit is within 1.2 V of either rails. Into a 15-Ω load (the minimum tested load), it is tested to deliver more than ±160 mA. The specifications described above, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage × current, or V-I product, that is more relevant to circuit operation. Refer to the Output Voltage and Current Limitations plot (Figure 46) in the Typical Characteristics. The X- and Y-axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the VCA820 output drive capabilities, noting that the graph is bounded by a Safe Operating Area of 1W maximum internal power dissipation. Superimposing resistor load lines onto the plot shows that the VCA820 can drive ±2.5 V into 25 Ω or ±3.5 V into 50 Ω without exceeding the output capabilities or the 1-W dissipation limit. A 100-Ω load line (the standard test circuit load) shows the full ±3.9-V output swing capability, as shown in the Typical Characteristics. The minimum specified output voltage and current over-temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup do the output current and voltage decrease to the numbers shown in the Electrical Characteristics tables. As the output transistors deliver power, the respective junction temperatures increase, increasing the available output voltage swing, and increasing the available output current. In steady-state operation, the available output voltage and current is always greater than that temperature shown in the over-temperature specifications because the output stage junction temperatures are higher than the specified operating ambient.

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Product Folder Links: VCA820

e =□A /c180O VMAX 2 (R i ) +□e +□2 4kTR/c180 /c180 /c180S n n S 2 2 R =GMIN =□615.4/c87 3.2VPP 5.2mAPP V =□R I /c180IN(PP) RG(PP)G VCA820 www.ti.com SBOS395D –OCTOBER 2007–REVISED SEPTEMBER 2015 Device Functional Modes (continued)

8.4.3 Input Voltage Dynamic Range

The VCA820 has a input dynamic range limited to +1.6 V and –2.1 V. Increasing the input voltage dynamic range can be done by using an attenuator network on the input. If the VCA820 is trying to regulate the amplitude at the output, such as in an AGC application, the input voltage dynamic range is directly proportional to Equation 2. (2) As such, for unity-gain or under-attenuated conditions, the input voltage must be limited to the CMIR of ±1.6 V (3.2 VPP) and the current (IRQ) must flow through the gain resistor, ±2.6 mA (5.2 mAPP). This configuration sets a minimum value for RE such that the gain resistor has to be greater than Equation 3. (3) Values lower than 615.4Ω are gain elements that result in reduced input range, as the dynamic input range is limited by the current flowing through the gain resistor RG (IRG). If the IRG current is limiting the performance of the circuit, the input stage of the VCA820 goes into overdrive, resulting in limited output voltage range. Such IRG- limited overdrive conditions are shown in Figure 48 for the gain of 20 dB and Figure 68 for the 40-dB gain.

8.4.4 Output Voltage Dynamic Range

With its large output current capability and its wide output voltage swing of ±3.9-V typical on 100-Ω load, it is easy to forget other types of limitations that the VCA820 can encounter. For these limitations, careful analysis must be done to avoid input stage limitation, either voltage or IRG current; also, consider the gain limitation, as the control pin VG varies, affecting other aspects of the circuit.

8.4.5 Bandwidth

The output stage of the VCA820 is a wideband current-feedback amplifier. As such, the external feedback resistance is the compensation of the last stage. Reducing the feedback element and maintaining the gain constant limits the useful range of IRG, and therefore reducing the gain adjust range. For a given gain, reducing the gain element limits the maximum achievable output voltage swing.

8.4.6 Offset Adjustment

As a result of the internal architecture used on the VCA820, the output offset voltage originates from the output stage and from the input stage and multiplier core. Figure 87 illustrates how to compensate both sources of the output offset voltage. Use this procedure to compensate the output offset voltage: starting with the output stage compensation, set VG = 0 V to eliminate all offset contribution of the input stage and multiplier core. Adjust the output stage offset compensation potentiometer. Finally, set VG = +1 V to the maximum gain and adjust the input stage and multiplier core potentiometer. This procedure effectively eliminates all offset contribution at the maximum gain. Because adjusting the gain modifies the contribution of the input stage and the multiplier core, some residual output offset voltage remains.

8.4.7 Noise

The VCA820 offers 8.2-nV/√Hz input-referred voltage noise density at a gain of 20 dB and 1.8-pA/√Hz input- referred current noise density. The input-referred voltage noise density considers that all noise terms, except the input current noise on each of the two input pins but including the thermal noise of both the feedback resistor and the gain resistor, are expressed as one term. This model is formulated in Equation 4 and Figure 86. (4) A more complete model is illustrated in Figure 88. For additional information on this model and the actual modeled noise terms, please contact the High-Speed Product Application Support team at www.ti.com. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: VCA820

8.4.8 Input and ESD Protection

voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the table. Figure 72. Internal ESD Protection

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9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

gain range from 2-V to 0-V control voltage.

9.1.1 Design-In Tools

9.1.1.1 Demonstration Boards

with a user's guide. The summary information for these fixtures is shown in Table 2. Table 2. EVM Ordering Information

9.1.1.2 Macromodels and Applications Support

the relevant product data sheet.

9.1.2 Operating Suggestions

• VS = ±5 V DC Parameters and VS = ±5 V DC and Power-Supply Parameters, which include DC operation and the intrinsic limitation of a VCA820 design
• VS = ±5 V, AVMAX = 6 dB Gain of 6-dB Operation
• VS = ±5 V, AVMAX = 20 dB Gain of 20-dB Operation
• VS = ±5 V, AVMAX = 40 dB Gain of 40-dB Operation Where the Typical Characteristics describe the actual performance that can be achieved by using the amplifier properly, the following sections describe in detail the trade-offs needed to achieve this level of performance. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: VCA820

9.1.2.1 Package Considerations

the Electrical Characteristics table. Figure 73. Test Circuit Table 3. SO-14 and MSOP-10 RF and RG Configurations There are no differences between the packages in the recommended values for the gain and feedback resistors. as can be seen in Figure 74 and Figure 75. The scale must be changed to a linear scale to view the details. Figure 74. SO-14 Recommended RF and RG vs AVMAX Figure 75. MSOP-10 Recommended RF and RG vs AVMAX

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9.2 Typical Applications

9.2.1 Wideband Variable Gain Amplifier Operation

Figure 76. DC-Coupled, AVMAX = 20 dB, Bipolar Supply Specification and Test Circuit

9.2.1.1 Design Requirements

requires a maximum gain of 10 V/V and low noise.

9.2.1.2 Detailed Design Procedure

Characteristics table. More information on how the VCA820 operates can be found in the section.

9.2.1.3 Application Curves

Figure 78. Large-Signal Frequency ResponseFigure 77. Small-Signal Frequency Response

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9.2.2 Difference Amplifier

Figure 79. Wideband Differential to Single-Ended Amplifier

9.2.2.1 Design Requirements

load drive capability. This circuit delivers differential gain of 2* (Rf/Rg), and CMRR as shown in Figure 80.

9.2.2.2 Detailed Design Procedure

common-mode input voltage, the current flowing through RG, or any other limitation described in this data sheet.

9.2.2.3 Application Curve

Figure 80. Common-Mode Rejection Ratio

9.2.3 Differential Equalizer

Figure 81. Differential Equalizer

9.2.3.1 Design Requirements

stages can be added as shown in Figure 82.

9.2.3.2 Detailed Design Procedure

advantageously because its architecture allows the application to isolate the input from the gain setting elements. Figure 81 shows an implementation of such a configuration. The transfer function is shown in Equation 5. frequency response are illustrated in Figure 82.

9.2.3.3 Application Curve

Figure 82. Differential Equalization of an RC Load

32 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

75 Load/c87

9.2.4 Differential Cable Equalizer

Figure 83. Differential Cable Equalizer

9.2.4.1 Design Requirements

Figure 81, but is much more accurate in replicating the 1/(sqrt(f)) frequency response shape.

9.2.4.2 Detailed Design Procedure

Figure 84. This implementation has a maximum error of 0.2 dB from dc to 40 MHz. For a detailed design procedure, refer to to SBOA124.

9.2.4.3 Application Curve

Figure 84. Cable Attenuation versus Equalizer Gain

0.1 F/c109

9.2.5 AGC Loop

Figure 85. AGC Loop

9.2.5.1 Design Requirements

9.2.5.2 Detailed Design Procedure

In the typical AGC loop shown in Figure 85, the OPA695 follows the VCA820 to provide 40 dB of overall gain. output level exceeds the reference voltage (VREF), the integrator ramps down reducing the gain of the AGC loop. Conversely, if the output is too small, the integrator ramps up increasing the net gain and the output voltage.

34 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

9.3 System Examples

Figure 86. Simple Noise Model Figure 87. Adjusting the Input and Output Voltage Sources

Figure 88. Full Noise Model

36 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

www.ti.com SBOS395D –OCTOBER 2007–REVISED SEPTEMBER 2015

10 Power Supply Recommendations

High-speed amplifiers require low inductance power supply traces and low ESR bypass capacitors. The power supply voltage should be centered on the desired amplifier output voltage, so for ground referenced output signals, split supplies are required. The power supply voltage should be from 7 V to 12 V.

11 Layout

11.1 Layout Guidelines

Achieving optimum performance with a high-frequency amplifier such as the VCA820 requires careful attention to printed circuit board (PCB) layout parasitics and external component types. Recommendations to optimize performance include:

• Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. This recommendation includes the ground pin (pin 2). Parasitic capacitance on the output can cause instability: on both the inverting input and the noninverting input, it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. Place a small series resistance (greater than 25 Ω) with the input pin connected to ground to help decouple package parasitics.
• Minimize the distance (less than 0.25”) from the power-supply pins to high-frequency 0.1-μF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. Larger (2.2 μF to 6.8 μF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These capacitors may be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB.
• Careful selection and placement of external components preserve the high-frequency performance of the VCA820. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high- frequency performance. Again, keep the leads and PCB trace length as short as possible. Never use wire- wound type resistors in a high-frequency application. Because the output pin is the most sensitive to parasitic capacitance, always position the series output resistor, if any, as close as possible to the output pin. Other network components, such as inverting or non-inverting input termination resistors, should also be placed close to the package.
• Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils, or 1.27 mm to 2.54 mm) should be used, preferably with ground and power planes opened up around them.
• Socketing a high-speed part like the VCA820 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the VCA820 onto the board. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 37 Product Folder Links: VCA820

11.2 Layout Example

Figure 89. VCA820 Recommended Layout

11.3 Thermal Considerations

the maximum junction temperature be allowed to exceed +150°C. voltage at half the supply into a 100-ohm load. beyond the output voltage range for the VCA820.

38 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.3 Trademarks

E2E is a trademark of Texas Instruments. X2Y is a registered trademark of X2Y Attenuators LLC. All other trademarks are the property of their respective owners.

12.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 39 Product Folder Links: VCA820

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) VCA820ID Active Production SOIC (D) | 14 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 VCA820ID VCA820ID.A Active Production SOIC (D) | 14 50 | TUBE Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 VCA820ID VCA820IDGSR Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 85 BOQ VCA820IDGSR.A Active Production VSSOP (DGS) | 10 2500 | LARGE T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 85 BOQ VCA820IDGST Active Production VSSOP (DGS) | 10 250 | SMALL T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 85 BOQ VCA820IDGST.A Active Production VSSOP (DGS) | 10 250 | SMALL T&R Yes NIPDAUAG Level-2-260C-1 YEAR -40 to 85 BOQ VCA820IDR Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 VCA820ID VCA820IDR.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 85 VCA820ID (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1

www.ti.com 10-Nov-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) VCA820IDGSR VSSOP DGS 10 2500 353.0 353.0 32.0 VCA820IDGST VSSOP DGS 10 250 213.0 191.0 35.0 VCA820IDR SOIC D 14 2500 353.0 353.0 32.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) VCA820ID D SOIC 14 50 506.6 8 3940 4.32 VCA820ID.A D SOIC 14 50 506.6 8 3940 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C TYP6.2 5.8

1.75 MAX

12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14

0.25 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800

www.ti.com EXAMPLE BOARD LAYOUT (5.4)

0.07 MAX

0.07 MIN

14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X

www.ti.com PACKAGE OUTLINE C TYP5.05 4.75

1.1 MAX

8X 0.5 10X 0.27 0.17 0.15 0.05 TYP0.23 0.13 0 - 8 0.25 GAGE PLANE 0.7 0.4 A NOTE 3 3.1 2.9 B NOTE 4 3.1 2.9 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187, variation BA.

0.1 C A B

0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 3.200

www.ti.com EXAMPLE BOARD LAYOUT (4.4)

0.05 MAX

0.05 MIN

10X (1.45) 10X (0.3) 8X (0.5) (R ) TYP 0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE SYMM SYMM LAND PATTERN EXAMPLE SCALE:10X 5 6 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN (4.4) 8X (0.5) 10X (0.3) 10X (1.45) (R ) TYP0.05 4221984/A 05/2015 VSSOP - 1.1 mm max heightDGS0010A SMALL OUTLINE PACKAGE NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 5 6 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X

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