VCA810

VCA810 High Gain Adjust Range, Wideband and Variable Gain Amplifier datasheet (Rev. G)

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SBOS275,G]
• PDF pages: 42

Technical content

+5V /c45 5V VOUT VC 0 2V/c174 /c45 /c45 /c174 40dB +40dB Gain VCA810 V/c45 Gain Adjust Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community VCA810 SBOS275G –JUNE 2003–REVISED DECEMBER 2015 VCA810HighGainAdjustRange,WidebandandVariableGainAmplifier Operating from ±5-V supplies, the device gain control1 Features voltage adjusts the gain from –40 dB at a 0-V input to 1• High Gain Adjust Range: ±40 dB 40 dB at a –2-V input. Increasing the control voltage

• Differential In, Single-Ended Out above ground attenuates the signal path to greater than 80 dB. Signal bandwidth and slew rate remain• Low Input Noise Voltage: 2.4 nV/√Hz constant over the entire gain adjust range. This 40-• Constant Bandwidth vs Gain: 35 MHz dB/V gain control is accurate within ±1.5 dB (±0.9 dB• High dB/V Gain Linearity: ±0.3 dB for high grade), allowing the gain control voltage in an AGC application to be used as a received signal• Gain Control Bandwidth: 25 MHz strength indicator (RSSI) with ±1.5-dB accuracy.• Low Output DC Error: < ±40 mV Excellent common-mode rejection and common-• High Output Current: ±60 mA mode input range at the two high-impedance inputs• Low Supply Current: 24.8 mA allow the device to provide a differential receiver(Maximum for –40°C to 85°C Temperature Range) operation with gain adjust. The output signal is referenced to ground. Zero differential input voltage2 Applications gives a 0-V output with a small DC offset error. Low input noise voltage ensures good output SNR at the• Optical Receiver Time Gain Control highest gain settings.• Sonar Systems In applications where pulse edge information is• Voltage-Tunable Active Filters critical, and the device is being used to equalize• Log Amplifiers varying channel loss, minimal change in group delay• Pulse Amplitude Compensation over gain setting retains excellent pulse edge information.• AGC receivers With RSSI
• Improved Replacement for VCA610 An improved output stage provides adequate output current to drive the most demanding loads. Although

3 Description principally intended to drive analog-to-digital

converters (ADCs) or second-stage amplifiers, theThe VCA810 is a DC-coupled, wideband, ±60-mA output current easily drives doubly-continuously variable, voltage-controlled gain terminated 50-Ω lines or a passive post-filter stageamplifier. The device provides a differential input to over the ±1.7-V output voltage range.single-ended output conversion with a high- impedance gain control input used to vary the gain Device Informationover a –40-dB to 40-dB range linear in dB/V. PART NUMBER PACKAGE BODY SIZE (NOM) VCA810 SOIC (8) 4.90 mm × 3.91 mm Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SBOS275G –JUNE 2003–REVISED DECEMBER 2015 www.ti.com Table of Contents

4 Revision History

Changes from Revision F (December 2010) to Revision G Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Revision E (August 2008) to Revision F Page Changes from Revision D (February, 2006) to Revision E Page

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Control, VC /c45VS +VS /c45In A (1) VOUT VCA810 GND +In NC (2) VCA810 www.ti.com SBOS275G –JUNE 2003–REVISED DECEMBER 2015

5 Device Comparison Table

SINGLES DUALS GAIN ADJUST RANGE (dB) INPUT NOISE (nV/√Hz) SIGNAL BANDWIDTH (MHz) VCA811 — 80 2.4 80 — VCA2612 45 1.25 80 — VCA2613 45 1 80 — VCA2614 45 3.6 40 — VCA2616 45 3.3 40 — VCA2618 45 5.5 30

6 Pin Configuration and Functions

(1) High grade version indicator. (2) NC = Not connected. Pin Functions PIN I/O DESCRIPTION NO. NAME 1 +In I Noninverting input

2 GND P Ground, serves as reference for gain control pin

Gain Control,3 I Gain controlVC

4 NC — No connect

5 VOUT O Output

7 –VS P Negative supply 8 –In I Inverting input Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: VCA810

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7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range, unless otherwise noted.(1) MIN MAX UNIT Power supply ±6.5 V Internal power dissipation See Thermal Information Differential input voltage ±VS V Input common-mode voltage ±VS V Junction temperature, TJ 150 °C Storage temperature, Tstg –65 125 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 Charged-device model (CDM), per JEDEC specification JESD22-V(ESD) Electrostatic discharge ±1500 VC101(2) Machine Model (MM) ±200 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT Temperature –40 25 85 °C Supply voltage ±4 ±5 ±5.5 V

7.4 Thermal Information

THERMAL METRIC(1) D (SOIC) UNIT

8 PINS

RθJA Junction-to-ambient thermal resistance 80 °C/W RθJC(top) Junction-to-case (top) thermal resistance 51 °C/W RθJB Junction-to-board thermal resistance 45 °C/W ψJT Junction-to-top characterization parameter 14 °C/W ψJB Junction-to-board characterization parameter 45 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

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7.5 Electrical Characteristics

At RL = 500 Ω and VIN = single-ended input on V+ with V− at ground, VS = ±5 V, unless otherwise noted. PARAMETER TEST CONDITIONS TEST LEVEL(1) MIN TYP MAX UNIT AC PERFORMANCE TJ = 25°C 35 TJ = 25°C(2) 30Small-signal bandwidth (see −2 V ≤ VC ≤ 0 V MHzFunctional Block Diagram) TJ = 0°C to 70°C(3) B 29 TJ = –40°C to 85°C(3) 29 TJ = 25°C 35 TJ = 25°C(2) 30 Large-signal bandwidth VO = 2 VPP, −2 ≤ VC ≤ −1 B MHz TJ = 0°C to 70°C(3) 29 TJ = –40°C to 85°C(3) 29 TJ = 25°C 0.1 TJ = 25°C(2) 0.5 Frequency response peaking VO < 500 mVPP, −2 V ≤ VC ≤ 0 V B dB TJ = 0°C to 70°C(3) 0.5 TJ = 25°C 350 TJ = 25°C(2) 300VO = 3.5-V step, −2 ≤ VC ≤ −1,Slew rate B V/μs10% to 90% TJ = 0°C to 70°C(3) 300 TJ = –40°C to 85°C(3) 295 TJ = 25°C 30 TJ = 25°C(2) 40 Settling time to 0.01% VO = 1-V step, −2 ≤ VC ≤ −1 B ns TJ = 0°C to 70°C(3) 41 TJ = –40°C to 85°C(3) 41 TJ = 25°C 10 TJ = 25°C(2) 12 Rise-and-fall time VO = 1-V step, −2 ≤ VC ≤ −1 B ns TJ = 0°C to 70°C(3) 12.1 G = 0 dB, VC= −1 V, f = 5 MHz,Group delay TJ = 25°C C 6.2 nsVO = 500 mVPP VO < 500 mVPP, −2 V ≤ VC ≤ 0 V,Group delay variation TJ = 25°C C 3.5 nsf = 5 MHz TJ = 25°C –71 TJ = 25°C(2) –51VO = 1 VPP, f = 1 MHz,HD2 Second harmonic distortion B dBcVC = −1 V, G = 0 dB TJ = 0°C to 70°C(3) –50 TJ = 25°C −35 TJ = 25°C(2) –34VO = 1 VPP, f = 1 MHz,HD3 Third harmonic distortion B dBcVC = −1 V, G = 0 dB TJ = 0°C to 70°C(3) –32 TJ = 25°C 2.4 TJ = 25°C(2) 2.8 Input voltage noise VC = −2 V B nV/√Hz TJ = 0°C to 70°C(3) 3.4 TJ = 25°C 1.4 TJ = 25°C(2) 1.8 Input current noise −2 V ≤ VC ≤ 0 V B pA/√Hz TJ = 0°C to 70°C(3) 2 TJ = 25°C −80 Fully attenuated feedthrough f ≤ 1 MHz, VC > 200 mV B dB TJ = 25°C(2) −70 TJ = 25°C 100VIN = 2 V to 0 V, VC = −2 V,Overdrive recovery B nsG = 40 dB TJ = 25°C(2) 150 (1) Test levels: (A) 100% tested at 25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value; only for information. (2) Junction temperature = ambient for 25°C tested specifications. (3) Junction temperature = ambient at low temperature limit; junction temperature = ambient 30°C at high temperature limit for over temperature specifications. Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: VCA810

SBOS275G –JUNE 2003–REVISED DECEMBER 2015 www.ti.com Electrical Characteristics (continued) At RL = 500 Ω and VIN = single-ended input on V+ with V− at ground, VS = ±5 V, unless otherwise noted. PARAMETER TEST CONDITIONS TEST LEVEL(1) MIN TYP MAX UNIT DC PERFORMANCE (Single-Ended or Differential Input) TJ = 25°C ±4 TJ = 25°C(2) ±22Output offset voltage (both −2 V ≤ VC ≤ 0 V A mVinputs grounded)(4) TJ = 0°C to 70°C(3) ±30 TJ = 0°C to 70°C(3) ±125 Output offset voltage drift B V/°C TJ = 25°C ±0.1 TJ = 25°C(2) ±0.25 Input offset voltage(4) Both inputs grounded A mV TJ = 0°C to 70°C(3) ±0.3 TJ = 0°C to 70°C(3) ±1 input offset voltage drift B μV/°C TJ = 25°C −6 TJ = 25°C(2) –10 Input bias current −2 V ≤ VC ≤ 0 V A μA TJ = 0°C to 70°C(3) −12 TJ = 0°C to 70°C(3) ±25 Input bias current drift B nA/°C TJ = 25°C ±100 TJ = 25°C(2) ±600 Input offset current −2 V ≤ VC ≤ 0 V A nA TJ = 0°C to 70°C(3) ±700 TJ = 0°C to 70°C(3) ±1.4 Input offset current drift B nA/°C INPUT TJ = 25°C ±2.4 TJ = 25°C(2) ±2.3 Common-mode input range A V TJ = 0°C to 70°C(3) ±2.3 TJ = 25°C 95 TJ = 25°C(2) 85VCM = 0.5 V, VC = −2 V, input-Common-mode rejection ratio A dBreferred TJ = 0°C to 70°C(3) 83 TJ = –40°C to 85°C(3) 80 VCM = 0 V, single-ended TJ = 25°C C 1 || 1 MΩ || pF Input impedance VCM = 0 V, differential TJ = 25°C C > 10 || < 2 MΩ || pF Differential input range(5) VC = 0 V, VCM = 0 V TJ = 25°C C 3 VPP OUTPUT TJ = 25°C ±1.8 TJ = 25°C(2) ±1.7 VC = −2 V, RL = 100 Ω A V TJ = 0°C to 70°C(3) ±1.4 Voltage output swing TJ = 25°C ±1.7 TJ = 25°C(2) ±1.6 VC = −2 V, RL = 100 Ω A V TJ = 0°C to 70°C(3) ±1.3 TJ = 25°C ±60 TJ = 25°C(2) ±40 Output current VO = 0 V A mA TJ = 0°C to 70°C(3) ±35 Output short-circuit current VO = 0 V TJ = 25°C C ±120 mA Output impedance VO = 0 V, f < 100 kHz TJ = 25°C C 0.2 Ω (4) Total output offset is: (Output Offset Voltage ± Input Offset Voltage x Gain). (5) Maximum input at minimum gain for < 1-dB gain compression.

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www.ti.com SBOS275G –JUNE 2003–REVISED DECEMBER 2015 Electrical Characteristics (continued) At RL = 500 Ω and VIN = single-ended input on V+ with V− at ground, VS = ±5 V, unless otherwise noted. PARAMETER TEST CONDITIONS TEST LEVEL(1) MIN TYP MAX UNIT GAIN CONTROL (VC, Pin 3, Single-Ended or Differential Input) Specified gain range ΔVC / ΔdB = 25 mV/dB TJ = 25°C C ±40 dB Maximum control voltage G = −40 dB TJ = 25°C C 0 V Minimum control voltage G = 40 dB TJ = 25°C C –2 V TJ = 25°C ±0.4 TJ = 25°C(2) ±1.5 −1.8 V ≤ VC ≤ −0.2 V A dB TJ = 0°C to 70°C(3) ±2.5 Gain accuracy TJ = 25°C ±0.5 TJ = 25°C(2) ±2.2 VC < −1.8 V, VC > −0.2 V A dB TJ = 0°C to 70°C(3) ±3.7 −1.8 V ≤ VC ≤ −0.2 V B dB/°C Gain drift VC < −1.8 V, VC > −0.2 V B dB/°C Gain control slope 25°C C –40 dB/V TJ = 25°C ±0.3 TJ = 25°C(2) ±1 −1.8 V ≤ VC ≤ 0 V A dB TJ = 0°C to 70°C(3) ±1.1 Gain control linearity(6) TJ = 25°C ±0.7 TJ = 25°C(2) ±1.6 VC < −1.8 V A dB TJ = 0°C to 70°C(3) ±2.5 TJ = 25°C 25 TJ = 25°C(2) 20 Gain control bandwidth B MHz TJ = 0°C to 70°C(3) 19 TJ = –40°C to 85°C(3) 19 Gain control slew rate 80-dB gain step TJ = 25°C C 900 dB/ns Gain settling time 1%, 80-dB step TJ = 25°C C 0.8 μs TJ = 25°C –1.5 TJ = 25°C(2) –3.5 Input bias current VC = −1 V A μA TJ = 0°C to 70°C(3) –4.5 TJ = –40°C to 85°C(3) –8 TJ = 25°C 0.5 TJ = 25°C(2) 1.5Gain + power-supply rejection VC = −2 V, G = 40 dB, +VS = 5 V A dB/Vratio ± 0.5 V TJ = 0°C to 70°C(3) 1.8 TJ = –40°C to 85°C(3) 2 TJ = 25°C 0.7 TJ = 25°C(2) 1.5Gain – power-supply rejection VC = −2 V, G = 40 dB, A dB/Vratio –VS = –5 V ± 0.5 V TJ = 0°C to 70°C(3) 1.8 TJ = –40°C to 85°C(3) 2 POWER SUPPLY Specified operating voltage TJ = 25°C(2) C ±5 V TJ = 25°C(2) ±4 Minimum operating voltage TJ = 0°C to 70°C(3) A ±4 V TJ = –40°C to 85°C(3) ±4 TJ =25°C(2) ±6 Maximum operating voltage TJ = 0°C to 70°C(3) A ±6 V TJ = –40°C to 85°C(3) ±6 (6) Maximum deviation from best line fit. Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: VCA810

SBOS275G –JUNE 2003–REVISED DECEMBER 2015 www.ti.com Electrical Characteristics (continued) At RL = 500 Ω and VIN = single-ended input on V+ with V− at ground, VS = ±5 V, unless otherwise noted. PARAMETER TEST CONDITIONS TEST LEVEL(1) MIN TYP MAX UNIT TJ = 25°C 10 TJ = 25°C(2) 12.5 +VS = 5 V, G = −40 dB A mA TJ = 0°C to 70°C(3) 12.6 TJ = –40°C to 85°C(3) 12.7Positive maximum supply quiescent current TJ = 25°C 18 TJ = 25°C(2) 20.5 +VS = 5 V, G = 40 dB A mA TJ = 0°C to 70°C(3) 22 TJ = 25°C 10 TJ = 25°C(2) 7.5 +VS = 5 V, G = –40 dB A mA TJ = 0°C to 70°C(3) 7.2 TJ = –40°C to 85°C(3) 7.1Positive minimum supply quiescent current TJ = 25°C 18 TJ = 25°C(2) 15.5 +VS = 5 V, G = 40 dB A mA TJ = 0°C to 70°C(3) 14.5 TJ = 25°C 12 TJ = 25°C(2) 14.5 −VS = −5 V, G = −40 dB A mA TJ = 0°C to 70°C(3) 14.6 TJ = –40°C to 85°C(3) 14.7Negative maximum supply quiescent current(7) TJ = 25°C 20 TJ = 25°C(2) 22.5 −VS = −5 V, G = 40 dB A mA TJ = 0°C to 70°C(3) 24.5 TJ = 25°C 12 TJ = 25°C(2) 9.5 −VS = −5 V, G = −40 dB A mA TJ = 0°C to 70°C(3) 9.4 TJ = –40°C to 85°C(3) 9.3Negative minimum supply quiescent current(7) TJ = 25°C 20 TJ = 25°C(2) 17.5 −VS = −5 V, G = 40 dB A mA TJ = 0°C to 70°C(3) 16.5 TJ = –40°C to 85°C(3) 16 TJ = 25°C 90 TJ = 25°C(2) 75Positive power-supply rejection+PSRR Input-referred, VC = −2 V A dBratio TJ = 0°C to 70°C(3) 75 TJ = –40°C to 85°C(3) 73 TJ = 25°C 85 TJ = 25°C(2) 70Negative power-supply–PSRR Input-referred, VC = −2 V A dBrejection ratio TJ = 0°C to 70°C(3) 70 TJ = –40°C to 85°C(3) 68 THERMAL CHARACTERISTICS Specified operating range, ID C –40 85 °Cpackage (7) Magnitude.

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7.6 High Grade DC Characteristics: VS = ±5 V (VCA810AID)

At RL = 500 Ω and VIN = single-ended input on V+ with V− at ground, unless otherwise noted. PARAMETER TEST CONDITIONS TEST LEVEL(1) MIN TYP MAX UNIT DC PERFORMANCE (Single-Ended or Differential Input) TJ = 25°C ±4 TJ = 25°C(2) ±14 Output offset voltage −2 V < VC < 0 V A mV TJ = 0°C to 70°C(3) ±24 TJ = 25°C ±0.1 TJ = 25°C(2) ±0.2 Input offset voltage A mV TJ = 25°C ±100 TJ = 25°C(2) ±500 Input offset current A nA TJ = 0°C to 70°C(3) ±600 GAIN CONTROL (VC, Pin 3, Single-Ended or Differential Input) TJ = 25°C ±0.4 TJ = 25°C(2) ±0.9 −1.8 V ≤ VC ≤ −0.2 V A dB TJ = 0°C to 70°C(3) ±1.9 Gain accuracy TJ = 25°C ±0.5 TJ = 25°C(2) ±1.5 VC < −1.8 V, VC > −0.2 V A dB TJ = 0°C to 70°C(3) ±3.0 TJ = 25°C ±0.3 TJ = 25°C(2) ±0.6 −1.8 V ≤ VC ≤ 0 V A dB TJ = 0°C to 70°C(3) ±0.7 Gain control linearity(4) TJ = 25°C ±0.7 TJ = 25°C(2) ±1.1 VC < −1.8 V A dB/V TJ = 0°C to 70°C(3) ±1.9 POWER SUPPLY TJ = 25°C 10 TJ = 25°C(2) 11.5 +VS = 5 V, G = −40 dB A mA TJ = 0°C to 70°C(3) 11.6 TJ = –40°C to 85°C(3) 11.7Positive maximum supply quiescent current TJ = 25°C 18 TJ = 25°C(2) 19.5 +VS = 5 V, G = 40 dB A mA TJ = 0°C to 70°C(3) 21 TJ = 25°C 10 TJ = 25°C(2) 8.5 +VS = 5 V, G = −40 dB A mA TJ = 0°C to 70°C(3) 8.2 TJ = –40°C to 85°C(3) 8.1Positive minimum supply quiescent current TJ = 25°C 18 TJ = 25°C(2) 16.5 +VS = 5 V, G = 40 dB A mA TJ = 0°C to 70°C(3) 15.5 (1) Test levels: (A) 100% tested at 25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. (C) Typical value; only for information. (2) Junction temperature = ambient for 25°C tested specifications. (3) Junction temperature = ambient at low temperature limit; junction temperature = ambient 30°C at high temperature limit for over temperature specifications. (4) Maximum deviation from best line fit. Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: VCA810

SBOS275G –JUNE 2003–REVISED DECEMBER 2015 www.ti.com High Grade DC Characteristics: VS = ±5 V (VCA810AID) (continued) At RL = 500 Ω and VIN = single-ended input on V+ with V− at ground, unless otherwise noted. PARAMETER TEST CONDITIONS TEST LEVEL(1) MIN TYP MAX UNIT TJ = 25°C 12 TJ = 25°C(2) 14 −VS = −5 V, G = −40 dB A mA TJ = 0°C to 70°C(3) 14.1 TJ = –40°C to 85°C(3) 14.2Negative maximum supply quiescent current(5) TJ = 25°C 20 TJ = 25°C(2) 22 −VS = −5 V, G = 40 dB A mA TJ = 0°C to 70°C(3) 24 TJ = 25°C 12 TJ = 25°C(2) 10 −VS = −5 V, G = −40 dB A mA TJ = 0°C to 70°C(3) 9.9 TJ = –40°C to 85°C(3) 9.8Negative minimum supply quiescent current(5) TJ = 25°C 20 TJ = 25°C(2) 18 −VS = −5 V, G = 40 dB A mA TJ = 0°C to 70°C(3) 17 (5) Magnitude.

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7.7 Typical Characteristics

At RL = 500 Ω and VIN = single-ended input on V+ with V− at ground, VS = ±5 V, unless otherwise noted. Figure 1. Small-Signal Frequency Response Figure 2. Gain Control Frequency Response Figure 3. Attenuated Pulse Response Figure 4. High Gain Pulse Response Figure 5. Gain Control Pulse Response Figure 6. Gain vs Control Voltage

At RL = 500 Ω and VIN = single-ended input on V+ with V− at ground, VS = ±5 V, unless otherwise noted. Figure 7. Harmonic Distortion vs Frequency Figure 8. Harmonic Distortion vs RLOAD Figure 9. Harmonic Distortion vs Output Voltage Figure 10. Harmonic Distortion vs Gain Figure 11. Input, Output Range vs Gain Figure 12. Harmonic Distortion vs Attenuation

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At RL = 500 Ω and VIN = single-ended input on V+ with V− at ground, VS = ±5 V, unless otherwise noted. Figure 19. Group Delay vs Gain Figure 20. Group Delay vs Frequency Figure 21. Overdrive Recovery at Maximum Gain Figure 22. Overdrive Recovery at Maximum Attenuation Figure 23. Common-Mode Rejection Ratio and Figure 24. Common-Mode Rejection Ratio and

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+5V /c45 5V VOUT VC 0 2V/c174 /c45 /c45 /c174 40dB +40dB Gain VCA810 V/c45 Gain Adjust G =(V/V) 10 /c452(V + 1)C VCA810 SBOS275G –JUNE 2003–REVISED DECEMBER 2015 www.ti.com

8 Detailed Description

8.1 Overview

The VCA810 is a high gain adjust range, wideband, voltage amplifier with a voltage-controlled gain, as shown in Functional Block Diagram. The circuit’s basic voltage amplifier responds to the control of an internal gain-control amplifier. At its input, the voltage amplifier presents the high impedance of a differential stage, permitting flexible input impedance matching. To preserve termination options, no internal circuitry connects to the input bases of this differential stage. For this reason, the user must provide DC paths for the input base currents from a signal source, either through a grounded termination resistor or by a direct connection to ground. The differential input stage also permits rejection of common-mode signals. At its output, the voltage amplifier presents a low impedance, simplifying impedance matching. An open-loop design produces wide bandwidth at all gain settings. A ground-referenced differential to single-ended conversion at the output retains the low output offset voltage. A gain control voltage, VC, controls the amplifier gain magnitude through a high-speed control circuit. Gain polarity can be either inverting or noninverting, depending upon the amplifier input driven by the input signal. The gain control circuit presents the high-input impedance of a noninverting operational amplifier connection. The control voltage pin is referred to ground as shown in Functional Block Diagram. The control voltage VC varies the amplifier gain according to the exponential relationship: (1) This translates to the log gain relationship: G(dB) = –40 × (VC + 1)dB (2) Thus, G(dB) varies linearly over the specified −40 dB to 40 dB range as VC varies from 0 V to −2 V. Optionally, making VC slightly positive (≥ 0.15 V) effectively disables the amplifier, giving greater than 80 dB of signal path attenuation at low frequencies. Internally, the gain-control circuit varies the amplifier gain by varying the transconductance, gm, of a bipolar transistor using the transistor bias current. Varying the bias currents of differential stages varies gm to control the voltage gain of the VCA810. A gm-based gain adjust normally suffers poor thermal stability. The VCA810 includes circuitry to minimize this effect.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Input and Output Range

The VCA810’s 80 dB gain range allows the user to handle an exceptionally wide range of input signal levels. If the input and output voltage range specifications are exceeded, however, signal distortion and amplifier overdrive will occur. Figure 11 shows the maximum input and output voltage range. This chart plots input and output voltages versus gain in dB.

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The maximum input voltage range is the largest at full attenuation (−40 dB) and decreases as the gain increases. this type of overdrive is achieved by limiting the input voltage range. to 40 dB, the output stage is the limiting factor. rather than by current limiting. Table 1 summarizes these overdrive conditions. Table 1. Output Signal Compression

8.3.2 Overdrive Recovery

the overdrive plots for maximum gain and maximum attenuation.

8.3.3 Output Offset Error

• VOS = Output offset error
• VOSO = Output offset voltage
• GdB = VCA810 gain in dB
• VIOS = Input offset voltage (3) This is shown in Figure 29. Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: VCA810

1 F/c109 VCV/c45

Figure 29. Output Offset Error versus Gain Figure 18 shows the distribution for the output offset voltage at maximum gain.

8.3.4 Offset Adjustment

couple to the amplifier input. Figure 30. Optional Offset Adjustment the resistance seen at the wiper remains high, which stabilizes the filtering function.

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2 R C/c112 P P

8.3.5 Gain Control

gain control input bias current of 6 μA. Figure 31. Control Line Filtering

8.3.6 Gain Control and Teeple Point

proportional increase with the gain.

8.3.7 Noise Performance

density terms in either nV/√Hz or pA/√Hz. Figure 32. VCA810 Noise Analysis Model

input as shown by Equation 5.

8.3.8 Input and ESD Protection

Figure 33. Internal ESD Protection

8.4 Device Functional Modes

enabled by applying power to the amplifier supply pins and is disabled by turning the power off. amplifier inputs. The amplifier gain is controlled through the gain control pin. applying a slightly positive voltage to this pin. This is detailed Feature Description.

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0.1 F/c109

6.8 F/c109

9 Applications and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 VCA810 Operation

frequencies, and one small ceramic capacitor (0.1 μF) for high-frequency decoupling. Figure 34. Variable Gain, Specification and Test Circuit the DC source impedance looking out of each input will minimize input offset voltage error.

9.1.2 Range-Finding TGC Amplifier

systems. A photodiode preamp provides an initial gain stage to the photodiode.

0.1 VDC

Figure 35. Typical Range-Finding Application

9.1.3 Wide-Range AGC Amplifier

limit prevents input overload of the VCA810 gain control circuit. Figure 37 shows the AGC response for the values shown in Figure 36. Figure 36. 60-dB Input Range AGC

22 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated

1 F/c109

2 R C/c112W W

Figure 37. AGC Output Voltage for 100-kHz Sinewave at 10 mVPP, 100 mVPP, and 1 VPP

9.1.4 Stabilized Wein-Bridge Oscillator

produces a feedback factor of 1/3. Thus, self-sustaining oscillation requires a gain of three through the amplifier. produces amplitude modulation of the oscillator output. Figure 38. Amplitude-Stabilized Oscillator

9.1.5 Low-Drift Wideband Log Amplifier

Figure 39. Temperature-Compensated Log Response adjusts the gain of the VCA810 to change VOA. The operational amplifier forces this equality by supplying the gain control voltage, . argument restricts VIN to a unipolar range. Figure 40 illustrates these constraints.

24 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated

2 R C/c1122

Figure 40. Test Result for LOG Amp for VR = −100 mV will see ∼0 V. VOL is going to be the integration of the input signal. not exceed –2.5 V. A limiting action could be achieved by using a voltage limiting amplifier.

9.1.6 Voltage-Controlled Low-Pass Filter

In the circuit of Figure 41, the VCA810 serves as the variable-gain element of a voltage-controlled low-pass filter.

• (8) With the components shown, the circuit provides a linear variation of the low-pass cutoff from 300 Hz to 1 MHz. Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 25 Product Folder Links: VCA810

0.047 F/c109

2 R C/c112 2

Figure 41. Tunable Low-Pass Filter where the VCA810 produces G = 1. Then, the circuit performs as if this amplifier were replaced by a short circuit. circuit produces a response pole at . pole to a higher frequency, producing the response control. Figure 42 shows the low-pass frequency for different control voltages.

26 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated

2 F/c109

2 R GC/c1121

2 R C/c1121

2 GR C/c112 1

Figure 42. Voltage-Controlled Low-Pass Filter Frequency Response

9.1.7 Tunable Equalizer

amplifier with a capacitive bypass of R1. This circuit produces a response zero at . Figure 43. Tunable Equalizer

2 RC/c112

and stability are clearly shown in Figure 44. Figure 44. Amplifier Noise Gain and AOL for Different Gain input voltage to VI ≤ VOAL/G. decades of frequency for fZ = 1 Hz, dropping to one decade for fZ = 10 kHz.

9.1.8 Voltage-Controlled Band-Pass filter

selectivity of . Note that variation of control voltage VC alters Q but not bandwidth. voltage swings related by VOA = GVO. Thus, a swing limit VOAL imposes a circuit output limit of VOL ≤ VOAL/G. See Figure 46 for the frequency response for two different gain conditions of the schematic shown in Figure 45. In particular, notice the center frequency shift and the selectivity of Q changing as the gain is increased.

28 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated

Figure 45. Tunable Band-Pass Filter Figure 46. Tunable Band-Pass Filter Response

9.2 Typical Application

Figure 47. DC reference VR again sets the amplifier input voltage, and the input signal VIN now drives the gain function of the log amplifier. Testing the circuit given in Figure 47 gives the exponential response shown in Figure 48. Figure 47. Exponential Amplifier

9.2.1 Design Requirements

meets this criteria. It also has continuous voltage gain control and can support up to 100 V/V of voltage gain.

9.2.2 Detailed Design Procedure

outputs are not saturated. In Figure 47 design the reference voltage is set to –10 mV.

9.2.3 Application Curve

Figure 48. Exponential Amplifier Response

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www.ti.com SBOS275G –JUNE 2003–REVISED DECEMBER 2015

10 Power Supply Recommendations

The VCA810 is designed for split supply operation with a nominal supply condition of 6 V. A power supply in the range of 8 V to 12 V is acceptable, and balanced supplies (negative and positive voltages equal) are recommended. The power supply should be regulated to 10% or better accuracy and capable of sourcing 100 mA of current. The device quiescent current is approximately 20 mA and the load current can be up to 60 mA. Single supply applications are possible, however, the control voltage is referenced to the ground pin, so a single supply application will require a mid supply reference voltage that can be applied to the ground pin. This reference voltage should be set to 5% accuracy or better for accurate gain control.

11 Layout

11.1 Layout Guidelines

Achieving optimum performance with a high-frequency amplifier such as the VCA810 requires careful attention to board layout parasitic and external component types. Recommendations that will optimize performance include:

• Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. This includes the ground pin (pin 2). Parasitic capacitance on the output can cause instability: on both the inverting input and the noninverting input, it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. Place a small series resistance (> 25 Ω) with the input pin connected to ground to help decouple package parasitic.
• Minimize the distance (less than 0.25” or 6.35 mm) from the power-supply pins to high-frequency 0.1-μF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. Larger (2.2 μF to 6.8 μF) decoupling capacitors, effective at lower frequencies, should also be used on the main supply pins. These capacitors may be placed somewhat farther from the device and may be shared among several devices in the same area of the PCB.
• Careful selection and placement of external components will preserve the high-frequency performance of the VCA810. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high- frequency performance. Again, keep the leads and PCB trace length as short as possible. Never use wire- wound type resistors in a high-frequency application. Since the output pin is the most sensitive to parasitic capacitance, always position the series output resistor, if any, as close as possible to the output pin. Other network components, such as inverting or noninverting input termination resistors, should also be placed close to the package.
• Careful selection and placement of external components will preserve the high-frequency performance of the VCA810. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high- frequency performance. Again, keep the leads and PCB trace length as short as possible. Never use wire- wound type resistors in a high-frequency application. Since the output pin is the most sensitive to parasitic capacitance, always position the series output resistor, if any, as close as possible to the output pin. Other network components, such as inverting or noninverting input termination resistors, should also be placed close to the package.
• Socketing a high-speed part like the VCA810 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the VCA810 onto the board. Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 31 Product Folder Links: VCA810

11.2 Layout Example

Figure 49. Layout Example

11.2.1 Thermal Analysis

maximum junction temperature be allowed to exceed 150°C. operating at maximum gain and at the maximum specified ambient temperature of 85°C. the output voltage range for the VCA810.

32 Submit Documentation Feedback Copyright © 2003–2015, Texas Instruments Incorporated

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

12.1.1.1 Demonstration Boards

A printed circuit board (PCB) is available to assist in the initial evaluation of circuit performance using the VCA810. This evaluation board (EVM) is available free, as an unpopulated PCB delivered with descriptive documentation. The summary information for this board is shown in the DEM-VCA-SO-1A user's guide.

12.1.1.2 Macromodels and Applications Support

Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can play a major role in circuit performance. A SPICE model for the VCA810 is available through the TI web page. The applications group is also available for design assistance. The models available from TI predict typical small-signal AC performance, transient steps, DC performance, and noise under a wide variety of operating conditions. The models include the noise terms found in the electrical specifications of the relevant product data sheet.

12.2 Documentation Support

12.2.1 Related Documentation

Unity-Gain Stable, Low-Noise, Voltage-Feedback Operational Amplifier, SBOS303

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2003–2015, Texas Instruments Incorporated Submit Documentation Feedback 33 Product Folder Links: VCA810

www.ti.com 10-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) VCA810AID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 85 VCA 810 A VCA810AID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 85 VCA 810 A VCA810AIDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 85 VCA 810 A VCA810AIDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 85 VCA 810 A VCA810ID Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 85 VCA 810 VCA810ID.A Active Production SOIC (D) | 8 75 | TUBE Yes Call TI Level-2-260C-1 YEAR -40 to 85 VCA 810 VCA810IDG4 Active Production SOIC (D) | 8 75 | TUBE - Call TI Call TI -40 to 85 VCA810IDR Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 85 VCA 810 VCA810IDR.A Active Production SOIC (D) | 8 2500 | LARGE T&R Yes Call TI Level-2-260C-1 YEAR -40 to 85 VCA 810 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

www.ti.com 10-Nov-2025 (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) VCA810AIDR SOIC D 8 2500 353.0 353.0 32.0 VCA810IDR SOIC D 8 2500 353.0 353.0 32.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 10-Aug-2026 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) VCA810AID D SOIC 8 75 506.6 8 3940 4.32 VCA810AID.A D SOIC 8 75 506.6 8 3940 4.32 VCA810ID D SOIC 8 75 506.6 8 3940 4.32 VCA810ID.A D SOIC 8 75 506.6 8 3940 4.32 Pack Materials-Page 3

www.ti.com PACKAGE OUTLINE C .228-.244 TYP [5.80-6.19] .069 MAX [1.75] 6X .050 [1.27] 8X .012-.020 [0.31-0.51] .150 [3.81] .005-.010 TYP [0.13-0.25] 0 - 8 .004-.010 [0.11-0.25] .010 [0.25].016-.050 [0.41-1.27] 4X (0 -15 ) A .189-.197 [4.81-5.00] NOTE 3 B .150-.157 [3.81-3.98] NOTE 4 4X (0 -15 ) (.041) [1.04] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: 1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA. 1 8 .010 [0.25] C A B PIN 1 ID AREA SEATING PLANE .004 [0.1] C SEE DETAIL A DETAIL A TYPICAL SCALE 2.800

www.ti.com EXAMPLE BOARD LAYOUT .0028 MAX [0.07] ALL AROUND .0028 MIN [0.07] ALL AROUND (.213) [5.4] 6X (.050 ) [1.27] 8X (.061 ) [1.55] 8X (.024) [0.6] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METAL SOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS EXPOSED METAL OPENING SOLDER MASK METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X SYMM 4 5 SEE DETAILS SYMM

www.ti.com EXAMPLE STENCIL DESIGN 8X (.061 ) [1.55] 8X (.024) [0.6] 6X (.050 ) [1.27] (.213) [5.4] (R.002 ) TYP [0.05] SOIC - 1.75 mm max heightD0008A SMALL OUTLINE INTEGRATED CIRCUIT 4214825/C 02/2019 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X SYMM SYMM 4 5

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