VCA710

VCA710 Low-Noise, AC and DC Input-Capable Variable Gain Amplifier datasheet

Document overview

• Manufacturer or author: Texas Instruments, Incorporated [SLOSEB2,*]
• PDF pages: 34

Technical content

VCA710 Low-Noise, AC and DC Input-Capable Variable Gain Amplifier

1 Features

• Variable Gain Amplifier (VGA) – Supports AC and DC inputs along with single- ended and differential inputs – Small Signal and Large Signal bandwidth > 100MHz – Input voltage noise: 4.5nV/√Hz – Gain Adjust Control Range
• –12dB to +40dB; High Gain Mode
• –32dB to +20dB; Low Gain Mode – Absolute Gain Accuracy: ± 0.5dB maximum – Gain conformance: ± 0.2dB – Power Consumption (IQ): 15.5mA – Slew Rate: 415V/μs
• Low Noise Amplifier (LNA) – Bandwidth: 220MHz – Input voltage noise: 0.9nV/√Hz – Input current noise: 4.5pA/√Hz – Power Consumption (IQ): 11mA
• Supply voltage: 3.15V to 5.25V
• Operating temperature range: –55°C to +125°C

2 Applications

• Optoelectronic front-ends
• Sonar systems / Ultrasound front end
• AGC receivers
• Seeker front end

3 Description

The VCA710 is a single-channel, low-noise, low- power variable gain analog front end (AFE) optimized for high-performance signal conditioning. The VCA710 integrates two sub-blocks: a low-noise amplifier (LNA) with a fixed gain of 10V/V (20dB) and a variable gain amplifier (VGA) delivering high dynamic range and gain control flexibility. The LNA and the VGA blocks can be used independently or in conjunction based on the requirement. The VGA sub-block features a High Gain and Low Gain mode offering two gain ranges: –12dB to +40dB or –32dB to +20dB for optimizing output noise. The VGA supports both AC and DC coupled inputs as well as single-ended and differential inputs. The VCA710 features a fully differential output with an adjustable output common mode control feature. The VCA710 supports a wide-supply from 3.15V to 5.25V, temperature range of –55°C to +125°C, in a compact 3.5mm × 3.5mm 20-pin RGR (VQFN) package. The VCA710 is an excellent choice for applications like ultrasound, sonar, optoelectronic front-ends.

Package Information

COUNT(1) PACKAGE VCA710 Single RGR (VQFN, 20) (1) For all available packages, see the orderable addendum at the end of the data sheet. VIP_LNA VOP_VGA VOCM_ADJ HILO 20dB Fixed Gain LNA VCC_VGAVCC_LNA VEE_LNA VOM_VGA VIM_LNA RBIAS RBIAS VOM_LNA VIM_VGA VIP_VGA EN_LNA VREF VOP_LNA VICM Interpolated Attenuator Gain Control Interface 40dB/20dB Fixed Gain Amp GAIN_ADJ EN_VGA EN_VICM 0dB to –52dB LNA VGA VEE_VGA VGA Gain = Attenuator Gain + Fixed Gain Amplifier External Capacitor / BPF / Short External Capacitor / BPF / Short VICM Functional Block Diagram ADVANCE INFORMATION VCA710 SLOSEB2 – FEBRUARY 2026 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.

5.8 Typical Characteristics: Variable Gain Amplifier

5.9 Typical Characteristics: Low-Noise Amplifier +

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4 Pin Configuration and Functions

20 VEE_LNA6VEE_VGA

1VOP_LNA 15 HILO

19 VCC_LNA7VCC_VGA

2VOM_LNA 14 GAIN_ADJ

18 NC8EN_VICM

3EN_LNA 13 VREF

17 VIP_LNA9EN_VGA

4VIM_VGA 12 VOM_VGA

16 VIM_LNA10VOCM_ADJ

5VIP_VGA 11 VOP_VGA Not to scale Thermal Pad Figure 4-1. RGR Package, 20-pin VQFN (Top-View) Table 4-1. Pin Functions PIN TYPE DESCRIPTION No. NAME

1 VOP_LNA Output LNA non-inverting output

2 VOM_LNA Output LNA inverting output

3 EN_LNA Input LNA Enable, EN_LNA = 0 = Disable and EN_LNA = 1 = Enable

4 VIM_VGA Input VGA inverting Input

5 VIP_VGA Input VGA non-inverting input

6 VEE_VGA Power VGA negative supply

7 VCC_VGA Power VGA positive supply

8 EN_VICM Input VGA internal common mode enable. EN_VICM = 1; Input common mode = Mid Supply. For AC coupled inputs. EN_VICM = 0; Input common mode = (VIP_VGA+VIM_VGA)/2. For DC inputs.

9 EN_VGA Input VGA Enable, EN_VGA = 0 = Disable and EN_VGA = 1 = Enable

10 VOCM_ADJ Input Output Common-Mode Voltage adjust pin.

11 VOP_VGA Output Non-inverting VGA output

12 VOM_VGA Output Inverting VGA output

13 VREF Input External reference voltage. Can be left floating to use internal VREF but TI recommends decouple to ground using 1nF capacitor.

14 GAIN_ADJ Input Gain Control Voltage

15 HILO Input Gain Range Select. High Gain Mode = HILO = 1. Low Gain Mode = HILO = 0

16 VIM_LNA Input LNA inverting input

17 VIP_LNA Input LNA non-inverting input

18 NC NC No Connect

19 VCC_LNA Power LNA positive supply

20 VEE_LNA Power LNA negative supply

— Thermal Pad — Thermal pad. Electrically isolated from the device. Recommended connection to a heat spreading plane, typically VEE. www.ti.com VCA710 SLOSEB2 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: VCA710 ADVANCE INFORMATION

5 Specifications

5.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC_LNA – VEE_LNA, VCC_VGA – VEE_VGA Supply voltage 5.5 V VIP_LNA , VIM_LNA Input voltage VEE VCC V LNA differential Input / VGA differential input ±1/±4.5 V All other inputs Input voltage VEE + 0.5 VCC + 0.5 V VREF, GAIN_ADJ VEE VEE+2.5 V II / IO Continuous input / output current 10 / 50 mA Continuous power dissipation See Thermal Information TJ Junction temperature 150 ℃ Tstg Storage temperature –65 150 ℃ (1) Operation outside the Absolute Maximum Ratings can cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device can not be fully functional, and this can affect device reliability, functionality, performance, and shorten the device lifetime.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Thermal Information

THERMAL METRIC(1) VCA710 UNITRGR

20 PINS

RθJA Junction-to-ambient thermal resistance 43.7 ℃/W RθJC(top) Junction-to-case (top) thermal resistance 41.7 ℃/W RθJB Junction-to-board thermal resistance 19.5 ℃/W ΨJT Junction-to-top characterization parameter 0.8 ℃/W ΨJB Junction-to-board characterization parameter 19.4 ℃/W RθJC(bot) Junction-to-case (bottom) thermal resistance 5.3 ℃/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics report.

5.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VCC_LNA – VEE_LNA, VCC_VGA – VEE_VGA Total supply voltage 3.15 5 5.25 V Split supply voltage(1) ±1.6 ±2.5 ±2.6 V TA Ambient Temperature –55 25 125 ℃ (1) When VCA710 is used in split supply mode, all control signals have to be referenced to VEE. VCA710 SLOSEB2 – FEBRUARY 2026 www.ti.com

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5.5 Electrical Characteristics for LNA

at TA = 25oC, VCC – VEE = 5V, CS = 100nF, Differential Load : RL = 300Ω, CL = 5pF, AC coupled single-ended or differential input, always differential output.(1) (2)(unless otherwise specified) PARAMETER(3) TEST CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE Internal fixed gain 20 dB SSBW Small-signal bandwidth VO = 20mVPP 220 MHz LSBW Large-signal bandwidth VO = 4VPP 60 MHz VO = 4VPP, 0.1dB flatness 9.2 SR Slew rate VO = 4V step 455 V/µs en Input voltage noise density f = 1MHz 0.9 nV/√Hz in Input current noise density f = 1MHz, un-matched 4.5 pA/√Hz f = 1MHz, matched 2 HD2 Second-order harmonic distortion f = 5MHz, VO = 4VPP –90 dBc HD3 Third-order harmonic distortion f = 5MHz, VO = 4VPP –70 dBc Output overdrive recovery 20 ns Propagation delay f = 2MHz 1 ns INPUT PERFORMANCE Linear input voltage range Differential input 800 mVPP Single-ended input 800 mVPP RIN Input resistance Differential input 20 kΩ Pull up to VICM 10 CIN Input capacitance Common-mode 2 pF Differential-mode 2.3 VICM Input common-mode voltage Generated internal to device Mid-Supply – 0.8 V VOCM Output common-mode voltage Generated internal to device Mid-Supply V OUTPUT PERFORMANCE Maximum output voltage swing 8 VPP LNA output headroom Saturated output VEE_LNA + 0.3 VCC_LNA – 0.3 V Output short-circuit current 80 100 130 mA POWER SUPPLY IQ Quiescent current (LNA) 11 12.2 mA TA = –55℃ to +125℃ 12 LNA enable threshold Enable VEE_LNA + 1.4 V Disable VEE_LNA + 0.6 LNA enable time 0.5 µs LNA disable time 0.05 µs LNA disabled quiescent current 10 12.5 µA (1) TI recommends AC coupling both input and output for the LNA. LNA cannot be used in DC coupled mode. Provide an AC coupling capacitor at the input such that the added series capacitor in tandem with the input resistor RIN forms a high pass filter of ~ 1/10th the signal frequency. (2) All output voltages are always given as a differential output voltage. (3) LNA both inputs are terminated with same impedance. www.ti.com VCA710 SLOSEB2 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: VCA710 ADVANCE INFORMATION

5.6 Electrical Characteristics for VGA

at TA = 25oC, VCC – VEE = 5V, Differential Load : RL = 500Ω, CL = 5pF, VOCM_ADJ driven to mid-supply, VREF driven to 0.5V, single-ended and differential input, always differential output(1), HILO = 1(unless otherwise specified) PARAMETER TEST CONDITION MIN TYP MAX UNIT AC and DC PERFORMANCE SSBW Small-signal bandwidth Gain = 0dB, HILO = 1 VO = 20mVPP 110 MHz Gain = 40dB, HILO = 1 VO = 20mVPP 115 Gain = 0dB, HILO = 0 VO = 20mVPP 120 Gain = 20dB, HILO = 0 VO = 20mVPP 125 LSBW Large-signal bandwidth Gain = 0dB, HILO = 1 VO = 2VPP 100 MHz Gain = 40dB, HILO = 1 VO = 2VPP 100 Gain = 0dB, HILO = 0 VO = 2VPP 100 Gain = 20dB, HILO = 0 VO = 2VPP 110 SR Slew rate Gain = 0dB, HILO = 1 VO = 2VPP 340 V/µs Gain = 40dB, HILO = 1 VO = 2VPP 415 Gain = 0dB, HILO = 0 VO = 2VPP 270 Gain = 20dB, HILO = 0 VO = 2VPP 300 Output voltage noise(2) Gain = –12dB to 40dB HILO = 1, 1MHz 450 nV/√Hz Gain = –32dB to 20dB HILO = 0, 1MHz 80 HD2 Second-order harmonic distortion Gain = 0dB, HILO = 1 f = 5MHz, VO = 1VPP –80 dBc Gain = 40dB, HILO = 1 f = 5MHz, VO = 1VPP –75 Gain = 0dB, HILO = 0 f = 5MHz, VO = 1VPP –77 Gain = 20 dB, HILO = 0 f = 5MHz, VO = 1VPP –90 HD3 Third-order harmonic distortion Gain = 0dB, HILO = 1 f = 5MHz, VO = 1VPP –78 dBc Gain = 40dB, HILO = 1 f = 5MHz, VO = 1VPP –81 Gain = 0dB, HILO = 0 f = 5MHz, VO = 1VPP –65 Gain = 20dB, HILO = 0 f = 5MHz, VO = 1VPP –75 Overload recovery Gain = 40dB, output overdrive 40 ns GAIN CONTROL Typical VGA Gain range HILO = 1, High gain mode VGAIN_ADJ = 0V to 1V –14.9 41 dB HILO = 0, Low gain mode VGAIN_ADJ = 0V to 1V –34.5 21.4 dB Typical Gain equation VREF = 0.5V(3), VGAIN_ADJ (3) = 0V to 1V HILO = 1 Gain = VGAIN_ADJ × 55.9 – 14.9 dB HILO = 0 Gain = VGAIN_ADJ × 55.9 – 34.5 Absolute gain accuracy VGAIN_ADJ = 0.1V to 0.9V External VREF –0.5 0.5 dB Gain matching(5) VGAIN_ADJ = 0.1V to 0.9V ΔT = 20℃, between Absolute gain accuracy VGAIN_ADJ = 0.1V to 0.9V External VREF –2 2.6 dB Gain conformance error VGAIN_ADJ = 0.1V to 0.9V Based on best fit line –0.2 0.2 dB Gain response time VGAIN_ADJ = 0.1V to 0.9V 10% settling 600 ns Internal VREF(4) Measured on VREF pin VREF = 1nF to VEE 0.47 0.49 0.51 V HILO pin threshold HILO = 1, selects the FGA = 40dB internally VEE_VGA + 1.4 V HILO = 0, selects the FGA = 20dB internally VEE_VGA + 0.6 VCA710 SLOSEB2 – FEBRUARY 2026 www.ti.com

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5.6 Electrical Characteristics for VGA (continued)

at TA = 25oC, VCC – VEE = 5V, Differential Load : RL = 500Ω, CL = 5pF, VOCM_ADJ driven to mid-supply, VREF driven to 0.5V, single-ended and differential input, always differential output(1), HILO = 1(unless otherwise specified) PARAMETER TEST CONDITION MIN TYP MAX UNIT INPUT VIP_VGA and VIM_VGA input VEE_VGA VCC_VGA – 0.7 V Maximum differential input voltage VIP_VGA – VIM_VGA VCC – VEE = 5V ±4 V VIP_VGA – VIM_VGA VCC – VEE = 3.3V ±2.8 Input resistance Differential 300 Ω Common-mode 21 kΩ Input capacitance Differential 1.4 pF INPUT COMMON MODE (VICM) Common mode set internally EN_VICM = 1 AC Coupled input Mid-supply V Common mode set externally EN_VICM = 0 (VIP_VGA + VIM_VGA) / 2 VEE_VGA + 1.2 VCC_VGA – 0.7 V VICM enable threshold EN_VICM = 1, Enable VEE + 1.4 V EN_VICM = 0, Disable VEE + 0.6 OUTPUT Output voltage swing Abs Gain Error = 1dB, RL = 100Ω HILO = 1 8 VPP HILO = 0 5 Output short-circuit current Differential short circuit 65 100 135 mA Differential output impedance 1 Ω Output offset voltage VGAIN_ADJ = 0.1V to 0.9V, HILO = 1 –160 160 mV TA = –55℃ to +125℃ –190 183 VGAIN_ADJ = 0.1V to 0.9V, HILO = 0 –20 20 TA = –55℃ to +125℃ –36 25 OUTPUT COMMON MODE (VOCM) VOCM Common-mode voltage VOCM_ADJ = Floating TA = –55℃ to +125℃ Mid-supply V VOCM Adjustable common mode voltage range VOCM_ADJ = Driven VEE_VGA + 0.3 VCC_VGA –

1.2 V/V

ΔVOCM / ΔVOCM_ADJ(6) VOCM_ADJ = Driven 0.98 0.99 V/V VOCM Offset Error VOCM_ADJ = Driven –6 50 mV POWER SUPPLY IQ Quiescent current IOUT = 0mA TA = 25℃ 15.5 17.5 mA TA = –55℃ to +125℃ 25 Disabled quiescent current IOUT = 0mA 110 µA POWER DOWN Power down enable threshold VEE + 1.4 V Power down disable threshold VEE + 0.6 V Turn on time 3.5 µs Turn off time 0.5 µs (1) All output voltages are always given as a differential output voltage (2) The output noise remains fixed irrespective of the GAIN_ADJ voltage. However the output noise changes based on HILO = 1/0. (3) Both VREF and GAIN_ADJ are always referenced to VEE. (4) VCA710 comes with an internal 0.5V VREF. This can be used by floating VREF and connecting a 1nF cap to VEE. However the gain accuracy achieved with this VREF is inferior to that of an externally applied accurate 0.5V VREF. (5) Gain matching between 2 randomly chosen parts which are withing a window of 20℃ anywhere within the specified temperature range. Guaranteed by characterization and design. www.ti.com VCA710 SLOSEB2 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: VCA710 ADVANCE INFORMATION

(6) Output common mode voltage is directly equal to the applied voltage on the VOCM_ADJ pin VCA710 SLOSEB2 – FEBRUARY 2026 www.ti.com

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5.7 Typical Characteristics: Low-Noise Amplifier (LNA)

at TA = 25oC, VCC – VEE = 5V, CS= 100nF, Differential load : RL = 300Ω, CL = 5pF, LNA internal gain = 20dB, AC coupled single-ended or differential input, always differential output.(unless otherwise specified) F r e q u e n c y ( H z ) Gain (dB) 1 2 1 5 1 8 2 1 2 4 2 7 1 0 0 k 1 M 1 0 M 1 0 0 M 1 G Figure 5-1. Small Signal Frequency Response F r e q u e n c y ( H z ) Gain (dB) 1 2 1 5 1 8 2 1 2 4 1 0 0 k 1 M 1 0 M 1 0 0 M 1 G VO = 4VPP Figure 5-2. Large Signal Frequency Response T i m e ( 1 0 n s / d i v ) Output Voltage (VPP) - 3 - 2 . 5 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 2 . 5 L N A O u t p u t V V O P _ L N A V V O M _ L N A VOUT = 4VPP Figure 5-3. Large Signal Pulse Response T i m e ( 1 0 0 n s / d i v ) Output Voltage (VPP) - 6 - 5 - 4 - 3 - 2 - 1 I n p u t  1 0 L N A O u t p u t V V O P _ L N A V V O M _ L N A VIN = 1VPP Figure 5-4. Overdrive F r e q u e n c y ( H z ) Input Referred Noise (nV/Hz) 0 . 5 0 . 6 0 . 7 0 . 8 0 . 9 1 . 1 1 . 2 1 . 3 1 . 4 1 . 5 1 0 0 k 1 M 1 0 M 1 0 0 M Figure 5-5. Input Voltage Noise F r e q u e n c y ( H z ) Harmonic Distortion (dBc) - 1 0 0 - 9 0 - 8 0 - 7 0 - 6 0 - 5 0 - 4 0

1 M 1 0 M 1 0 0 M

VOUT = 4VPP Figure 5-6. Harmonic Distortion vs Frequency www.ti.com VCA710 SLOSEB2 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: VCA710 ADVANCE INFORMATION

5.8 Typical Characteristics: Variable Gain Amplifier (VGA)

at TA = 25oC, VCC – VEE = 5V, Differential load: RL = 500Ω, CL = 5pF, VOCM_ADJ driven to mid-supply, VREF driven to 0.5V, single-ended and differential input, always differential output, HILO = 1 (unless otherwise specified) F r e q u e n c y ( H z ) Gain (dB) - 4 2 - 3 6 - 3 0 - 2 4 - 1 8 - 1 2 - 6 1 2 1 8 2 4 3 0 3 6 4 2 1 0 0 k 1 M 1 0 M 1 0 0 M 1 G V G A I N _ A D J 0 . 1 V 0 . 2 V 0 . 3 V 0 . 4 V 0 . 5 V 0 . 6 V 0 . 7 V 0 . 8 V 0 . 9 V HILO = 1 Figure 5-7. Frequency Response for Various Values of VGAIN_ADJ F r e q u e n c y ( H z ) Gain (dB) - 6 0 - 5 4 - 4 8 - 4 2 - 3 6 - 3 0 - 2 4 - 1 8 - 1 2 - 6 1 2 1 8 2 4 1 0 0 k 1 M 1 0 M 1 0 0 M 1 G V G A I N _ A D J 0 . 1 V 0 . 2 V 0 . 3 V 0 . 4 V 0 . 5 V 0 . 6 V 0 . 7 V 0 . 8 V 0 . 9 V HILO = 0 Figure 5-8. Frequency Response for Various Values of VGAIN_ADJ T i m e ( 1 0 n s / d i v ) Output Voltage (VPP) - 1 . 2 - 1 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 1 . 2 V G A O u t p u t V G A I N _ A D J = 0 . 2 7 V V G A I N _ A D J = 1 V HILO = 1, VO = 2VPP Figure 5-9. Large Signal Pulse Response T i m e ( 1 0 n s / d i v ) Output Voltage (VPP) - 1 . 4 - 1 . 2 - 1 - 0 . 8 - 0 . 6 - 0 . 4 - 0 . 2 0 . 2 0 . 4 0 . 6 0 . 8 1 . 2 1 . 4 V G A O u t p u t V G A I N _ A D J = 0 . 6 2 V V G A I N _ A D J = 1 V HILO = 0, VO = 2VPP Figure 5-10. Large Signal Pulse Response T i m e ( 1 0 0 n s / d i v ) Output Voltage (VPP) - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 I n p u t  1 0 V G A O u t p u t V V O P _ V G A V V O M _ V G A HILO = 0, VGAIN_ADJ = 1V, VIN = 1.4VPP Figure 5-11. Overdrive Recovery T i m e ( 1 0 0 n s / d i v ) Output Voltage (VPP) - 6 - 5 - 4 - 3 - 2 - 1 I n p u t  1 0 0 V G A O u t p u t V V O P _ V G A V V O M _ V G A HILO = 1, VGAIN_ADJ = 1V, VIN = 0.1VPP Figure 5-12. Overdrive Recovery VCA710 SLOSEB2 – FEBRUARY 2026 www.ti.com

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5.8 Typical Characteristics: Variable Gain Amplifier (VGA) (continued)

at TA = 25oC, VCC – VEE = 5V, Differential load: RL = 500Ω, CL = 5pF, VOCM_ADJ driven to mid-supply, VREF driven to 0.5V, single-ended and differential input, always differential output, HILO = 1 (unless otherwise specified) V G A I N _ A D J ( V ) Gain (dB) - 4 0 - 3 0 - 2 0 - 1 0 1 0 2 0 3 0 4 0 5 0 H I L O = 0 H I L O = 1 Figure 5-13. Gain vs. VGAIN_ADJ F r e q u e n c y ( H z ) Output Referred Noise (nV/Hz) 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 1 0 0 k 1 M 1 0 M 1 0 0 M V G A I N _ A D J = 0 V , H I L O = 1 V G A I N _ A D J = 1 V , H I L O = 1 V G A I N _ A D J = 0 V , H I L O = 0 V G A I N _ A D J = 1 V , H I L O = 0 Figure 5-14. Output Referred Noise vs Frequency Figure 5-15. Gain Error vs. VGAIN_ADJ V G A I N _ A D J ( V ) Absolute Gain Error (dB) - 0 . 6 - 0 . 5 - 0 . 4 - 0 . 3 - 0 . 2 - 0 . 1 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 0 . 7 T A = 2 5  C T A = − 4 0  C T A = − 5 5  C T A = 1 2 5  C Figure 5-16. Gain Error vs VGAIN_ADJ at Various Temperature A b s o l u t e G a i n E r r o r ( d B ) Devices (Count) 1 0 0 2 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 9 0 0 1 0 0 0 1 1 0 0 1 2 0 0 1 3 0 0 1 4 0 0 -0.22 -0.2 -0.18 -0.16 -0.14 -0.12 -0.1 -0.08 -0.06 -0.04 -0.02 0.02 Figure 5-17. Absolute Gain Error Histogram HILO = 0 Figure 5-18. Output Offset Voltage vs VGAIN_ADJ at various Temperature www.ti.com VCA710 SLOSEB2 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: VCA710 ADVANCE INFORMATION

at TA = 25oC, VCC – VEE = 5V, Differential load: RL = 500Ω, CL = 5pF, VOCM_ADJ driven to mid-supply, VREF driven to 0.5V, single-ended and differential input, always differential output, HILO = 1 (unless otherwise specified) F r e q u e n c y ( H z ) Harmonic Distortion (dBc) - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 HILO = 1, VGAIN_ADJ = 0.27V, VOUT = 1VPP Figure 5-19. Harmonic Distortion vs Frequency F r e q u e n c y ( H z ) Harmonic Distortion (dBc) - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 - 3 5 HILO = 1, VGAIN_ADJ = 1V, VOUT = 1VPP Figure 5-20. Harmonic Distortion vs Frequency F r e q u e n c y ( H z ) Harmonic Distortion (dBc) - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 HILO = 0, VGAIN_ADJ = 0.62V, VOUT = 1VPP Figure 5-21. Harmonic Distortion vs Frequency F r e q u e n c y ( H z ) Harmonic Distortion (dBc) - 9 5 - 9 0 - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 HILO = 0, VGAIN_ADJ = 1V, VOUT = 1VPP Figure 5-22. Harmonic Distortion vs Frequency V G A I N _ A D J ( V ) Input Referred Noise (nV/Hz) 1 0 2 0 5 0 1 0 0 2 0 0 5 0 0 1 0 0 0 2 0 0 0 5 0 0 0 1 0 0 0 0 H I L O = 0 H I L O = 1 Figure 5-23. Input Referred Noise vs Gain V G A I N _ A D J ( V ) Output Referred Noise (nV/Hz) 5 0 1 0 0 1 5 0 2 0 0 2 5 0 3 0 0 3 5 0 4 0 0 4 5 0 5 0 0 H I L O = 0 H I L O = 1 Figure 5-24. Output Referred Noise vs Gain VCA710 SLOSEB2 – FEBRUARY 2026 www.ti.com

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5.9 Typical Characteristics: Low-Noise Amplifier + Variable Gain Amplifier

at TA = 25oC, VCC – VEE = 5V, Differential load: RL = 500Ω, CL = 5pF, VOCM_ADJ driven to mid-supply, VREF driven to 0.5V, single-ended and differential input, always differential output (unless otherwise specified) T i m e ( 1 0 n s / d i v ) LNA Differential Input Voltage (V) VGA Output Voltage (V) - 0 . 0 5 - 1 . 5 - 0 . 0 2 5 - 1 . 2 5 0 - 1 0 . 0 2 5 - 0 . 7 5 0 . 0 5 - 0 . 5 0 . 0 7 5 - 0 . 2 5 0 . 1 0 0 . 1 2 5 0 . 2 5 0 . 1 5 0 . 5 0 . 1 7 5 0 . 7 5 0 . 2 1 0 . 2 2 5 1 . 2 5 0 . 2 5 1 . 5 D i f f e r e n t i a l I n p u t O u t p u t f o r S E I n p u t O u t p u t f o r D E I n p u t HILO = 0, VGAIN_ADJ = 1V Figure 5-25. Large Signal Pulse Response F r e q u e n c y ( H z ) Harmonic Distortion (dBc) - 8 5 - 8 0 - 7 5 - 7 0 - 6 5 - 6 0 - 5 5 - 5 0 - 4 5 - 4 0 HILO = 0, VO = 2VPP, VGAIN_ADJ = 1V Figure 5-26. Harmonic Distortion vs Frequency HILO = 1 Figure 5-27. Input Referred Noise V G A I N _ A D J ( V ) Output Referred Noise (nV/Hz) 2 0 02 0 0 3 0 0 4 0 0 5 0 0 6 0 0 7 0 0 8 0 0 1 0 0 0 2 0 0 0 HILO = 1 Figure 5-28. Output Referred Noise www.ti.com VCA710 SLOSEB2 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: VCA710 ADVANCE INFORMATION

6 Parameter Measurement Information

VIP_LNA VOP_VGA VOCM_ADJ HILO 20dB Fixed Gain LNA VCC_VGAVCC_LNA VEE_LNA VOM_VGA VIM_LNA RIN RIN VOM_LNA VIM_VGA VIP_VGA EN_LNA VREF VOP_LNA VCM VCM Interpolated Attenuator Gain Control Interface 40dB/20dB Fixed Gain Amp GAIN_ADJ EN_VGA EN_VICM 0dB to –52dB LNA VGA VEE_VGA VGA Gain = Attenuator Gain + Fixed Gain Amplifier 0.1 F 0.01 F 1 F 0.1 F 10 F 237 237 0.1 F

0.1 FPre_Amplifier

0.1 F SE to DE Converter 221 64.9 64.9 221 Oscilloscope (50 ) Ch1 Ch2 0.5V Vector Network Analyzer (VNA) 100nF 100nF CS CS OR Vector Network Analyzer (VNA) Figure 6-1. LNA + VGA Gain Measurement VIP_LNA 20dB Fixed Gain LNA VCC_LNA VEE_LNA VIM_LNA RIN RIN VOM_LNA VOP_LNA VCM VCM LNA 0.01 F 1 F 0.1 F 10 F 136 136 Pre_Amplifier 120 120 Oscilloscope (50 ) LNA Output (VPP) = VOP_LNA – VOM_LNA Ch1 Ch2 EN_LNA LMH5401 0.1 F 0.1 F 0.1 F 0.1 F Single Ended Input (SE) VCC_LNA VEE_VGA EN_VGA 100nF 100nF CS CS Vector Network Analyzer (VNA) Vector Network Analyzer (VNA) SE to DE Converter OR Figure 6-2. LNA Measurement VCA710 SLOSEB2 – FEBRUARY 2026 www.ti.com

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7 Detailed Description

7.1 Overview

The VCA710 is an analog front-end device that consists of two main blocks: a Low Noise Amplifier (LNA) with a fixed internal gain of 20dB, and a Variable Gain Amplifier (VGA). The LNA accepts both differential and single ended input signals and provides differential outputs. The LNA operated only with AC coupled signals. The VGA accepts both AC and DC signals, which can be either single ended or differential input. Both sub blocks can be used independently owing to the separate enable functionality and separate inputs and outputs. For users requiring DC coupled capability TI recommends to disable the LNA and provide inputs directly to the VGA.

7.2 Functional Block Diagram

The VCA710 allows gain control to a dynamic range of 52dB via a programmable voltage between 0V and 1V applied on the GAIN_ADJ pin. Beside the fine gain adjust VCA710's VGA block also provides a course gain setting via the HILO mode pin. With the analog gain control block and the HILO pin the VCA710 provides gain range either between –32dB to +20dB or from –12dB to +40dB. This makes the gain highly configurable for different application needs. The different gain buckets provide different trade-offs as shown in the Electrical Characteristics For high accuracy and tight gain error tolerance TI recommends applying a 0.5V external reference on to the VREF pin. For applications where gain accuracy is not important the device includes an internal reference voltage which can be used by keeping the VREF pin floating. The VOCM_ADJ allows output common mode control to allow the common mode to be matched with that of the ADC. VIP_LNA VOP_VGA VOCM_ADJ HILO 20dB Fixed Gain LNA VCC_VGAVCC_LNA VEE_LNA VOM_VGA VIM_LNA RBIAS RBIAS VOM_LNA VIM_VGA VIP_VGA EN_LNA VREF VOP_LNA VICM Interpolated Attenuator Gain Control Interface 40dB/20dB Fixed Gain Amp GAIN_ADJ EN_VGA EN_VICM 0dB to –52dB LNA VGA VEE_VGA VGA Gain = Attenuator Gain + Fixed Gain Amplifier External Capacitor / BPF / Short External Capacitor / BPF / Short VICM Figure 7-1. Functional Block Diagram VCA710 SLOSEB2 – FEBRUARY 2026 www.ti.com

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7.3 Device Functional Modes

The VCA710 operates in several functional modes determined primarily by the control pins and the amplifiers supply conditions. These modes define how the device shapes, scales, and conditions signals across AC and DC applications. Normal Operation Mode In this mode, the device functions as a single-channel, low-noise variable-gain amplifier (VGA). Both the low- noise amplifier (LNA) and VGA paths operate from a 3.3V to 5.25V supply, providing low noise and high dynamic range. This is the default mode whenever the device is powered and all pins are within valid operating ranges and all the sub-blocks are enabled.

• LNA + VGA enabled – In this mode EN_ VGA is high and EN_ LNA is high, LNA is AC coupled and VGA is either AC or DC coupled.
• LNA only enabled – In this mode EN_LNA is high, EN_VGA is low. Only LNA is in enabled state and VGA is disabled. The LNA block is used independently as a 0.9nV/√Hz input referred 20dB gain block.
• VGA only enabled – In this mode EN_VGA is high, EN_LNA is low. Only VGA is in enabled state and LNA is disabled. For applications where internal LNA of the VCA710 cannot be used TI recommends using this mode. Gain Modes The VCA710 supports two selectable gain-scaling behaviors, controlled by the HILO pin. This pin selects an internal 40dB/20dB fixed gain amplifier (FGA).
• High Gain mode / FGA = 40dB (HILO = 1) – Gain range: –12 dB to +40dB – Optimized for higher overall gain, better distortions, better input and output noise at higher gains. – Suitable for broadband front ends and low-level inputs that require wide scaling.
• Low Gain mode / FGA = 20dB (HILO = 0) – Gain range: –32 dB to +20dB – Optimized for applications requiring lower noise at lower gain and better voltage offset. – Suitable for higher ENOB ADC. Besides the above two gains from the FGA the GAIN_ADJ pin accepts an analog control voltage that smoothly adjusts attenuation from 0dB to -52dB via an interpolator. Overall VGA gain = interpolator gain + FGA gain. Input common mode selection for VGA
• Input common mode generated internally, VICM enable – In this mode EN_VICM = 1, input common mode is set to mid supply internally and inputs are expected to be AC coupled.
• Input common mode set externally, VICM disable – In this mode EN_VICM = 0, input common mode is set externally via applied input signal. This mode allows DC coupling of input signals. The common mode = (VIP_VGA + VIM_VGA) / 2. Make sure the input common mode is within the specified range specified as per the electrical characteristics. www.ti.com VCA710 SLOSEB2 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: VCA710 ADVANCE INFORMATION

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Typical Application

8.1.1 Ultrasound Flow Meter Front-End

The VCA710 can be used as a complete front-end IC for ultrasound flow meters. With an input referred noise of 1nV/√Hz, maximum gain of 60dB and a dynamic range of 52dB, the VCA710 can be used to interface an ultrasound sensor, with an appropriate ADC. VIP_LNA VOP_VGA VOCM_ADJ HILO 20dB Fixed Gain LNA VCC_VGAVCC_LNA VEE_LNA VOM_VGA VIM_LNA RIN RIN VOM_LNA VIM_VGA VIP_VGA EN_LNA VREF VOP_LNA VCM VCM Interpolated Attenuator Gain Control Interface 40dB/20dB Fixed Gain Amp GAIN_ADJ EN_VGA EN_VICM 0dB to –52dB LNA VGA VEE_VGA VGA Gain = Attenuator Gain + Fixed Gain Amplifier R R C C Ultrasound sensor ADC Filter Filter Diode VCC_VGA Figure 8-1. Ultrasound flow meter front end

8.1.2 Design Requirements

Table 8-1. Design Parameters PARAMETER VALUE Input signal range to the VCA710 from the ultrasound sensor 100μVPP to 1VPP Min required SNR for measurement At least 20dB at 100μVPP Frequency of measurement / Transducer frequency 1MHz Input Impedance High

8.1.3 Detailed Design Procedure

The LNA sub-block inside the VCA710 supports both single ended and differential input. The ultrasound transducer can be connected either way as per the requirement to the input of the LNA. Beside providing a low input referred noise and an additional gain of 20dB, the LNA block also provides high input impedance making the part an excellent choice to be interfaced directly with high output impedance sensors. VCA710 SLOSEB2 – FEBRUARY 2026 www.ti.com

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Achieving an SNR of > 20dB is most challenging when the signal to the LNA is the lowest (100 μVPP in this case). Since our frequency of interest is confined in and around 1MHz TI recommends adding an additional Band Pass Filter between the LNA and the VGA sub blocks. This limits the overall integrated noise carried forward towards the ADC. Refer to the application section of LOG300 8.2.1 Ultrasonic Distance Measurement for recommendation and design of a 1MHz band pass filter. Assuming a bandpass filter of Pass Band frequency of 800kHz with a single pole roll of response, the overall integrated input referred noise of LNA is: V n I nput re f err ed = 1nV / H z × 800 k H z × 1.57 (1) V n = 1.4 µ V r ms (2) V n pe a k t o peak = 6 × 1.4µV r m s = 8.4 µ V pp (3) The 4.5nV/√Hz input referred noise of the VGA sub-block translates to 0.45nV/√Hz at the input of LNA allowing us to conveniently ignore it in our calculation since its ~ 1/3 rd the LNA's own input referred noise. 1.57 is the brickwall correction factor for single-pole role off. With a total input referred noise of 8.4μVPP, the achieved SNR at 100μVPP at input is SNR = 20 × log × 100 µV P P 8.4µV PP = 21.4 dB (4) To protect the LNA from high input voltage during burst / Tx mode or other unseen circumstances TI recommends to add a back to back diode at the input of the LNA to clamp the input voltage to 1.4VPP max. The EN_VICM is enabled by connecting the pin to VCC_VGA since this is an AC coupled application. Enabling the EN_VICM allows the VGA sub-block to set the internal common mode voltage appropriately. Applying an appropriate voltage between 0V to 1V on the GAIN_ADJ pin and toggling the HILO pin allows an overall gain of the VCA710 ( LNA + VGA ) from –12dB to +60dB, Using the VOCM_ADJ pin an appropriate output common mode voltage can be set as per the ADC requirements. With ADC requiring 0V common-mode voltage, TI recommends using VCA710 in bi-polar/split supply mode to enable 0V common mode support.

8.1.4 Optical Receiver Front-end

VCA710 can be used as a variable gain amplifier in the receive path of an optical signal chain. Since the VGA sub block of the VCA710 supports DC coupled connections the preceding TIA is directly connected to the non inverting input of the VGA. By shorting the EN_LNA to VEE_LNA, the LNA gets disabled thereby reducing overall power consumption. The VCA710 supports single ended DC input and translates the applied DC input to a differential output based on the applied GAIN_ADJ voltage. By applying an additional voltage on the VIM_VGA design for input common mode voltage to be within the tolerable input common mode voltage range. www.ti.com VCA710 SLOSEB2 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: VCA710 ADVANCE INFORMATION

VIP_LNA VOP_VGA VOCM_ADJ HILO 20dB Fixed Gain LNA VCC_VGAVCC_LNA VEE_LNA VOM_VGA VIM_LNA RIN RIN VOM_LNA VIM_VGA VIP_VGA EN_LNA VREF VOP_LNA VCM VCM Interpolated Attenuator Gain Control Interface 40dB/20dB Fixed Gain Amp GAIN_ADJ EN_VGA EN_VICM 0dB to –52dB LNA VGA VEE_VGA VGA Gain = Attenuator Gain + Fixed Gain Amplifier R R C C ADC OPA859 RF CFVBIAS Common Mode Voltage Common Mode Voltage VEE_VGA PD/APD Figure 8-2. Optical receiver front end

8.2 Power Supply Recommendations

A multilayer board with power and ground planes is recommended. Pour any blank areas in the signal layers with ground plane. Decouple the power supply pins with surface-mount capacitors as close as possible to the respective pins to minimize impedance paths to ground. Decouple the LNA power pins from the VGA supply using ferrite beads to avoid crosstalk.

8.3 Layout

8.3.1 Layout Guidelines

The VOP_LNA and VOM_LNA output traces must be as short as possible before connecting to VIP_VGA and VIM_VGA. Isolation resistors must be placed near to the respective output pins to mitigate loading effects of capacitance of connecting traces. Removing GND pour below these traces helps further reduce capacitance loading. Signal traces must be short and matched to avoid parasitic effects. With complementary signals, symmetrical layout helps in maintaining waveform balance. PCB traces kept adjacent when running differential signals over a long distance help cancel the mutual inductance component. Stitching of vias is preferable to reducing inductance Shielding and decoupling is recommended for all the analog pins like GAIN_ADJ, VREF, VOCM_ADJ as they may be sensitive to parasitic coupling. VCA710 SLOSEB2 – FEBRUARY 2026 www.ti.com

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8.3.2 Layout Example

EN_LNA VIM_VGA VIP_VGA EN_VICM EN_VGA VOCM_ADJ VOP_VGA VOM_VGA VREF GAIN_ADJ HILO VIM_LNA VIP_LNA NC C AGND VOP_LNA VOM_LNA Solid copper pour connected to thermal pad C AGND VEE_LNA VCC_LNA VEE_VGA VCC_VGA 100 differential controlled routing for impedance match 100 differential controlled routing for impedance match Trace length should be macthed C C Figure 8-3. Layout www.ti.com VCA710 SLOSEB2 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: VCA710 ADVANCE INFORMATION

AMPS278APCBNumber:PCBRev:PrintedCircuitBoard AssemblyNoteZZ1TheseassembliesareESDsensitive,ESDprecautionsshallbeobserved.AssemblyNoteZZ2Theseassembliesmustbecleanandfreefromfluxandallcontaminants.Useofnocleanfluxisnotacceptable.AssemblyNoteZZ3TheseassembliesmustcomplywithworkmanshipstandardsIPC-A-610Class2,unlessotherwisespecified. GND LNAVout-LNAVout+ 12345OUTM_LNA1 12345OUTP_LNA1142-0701-851GND VOM_LNA VOP_LNA Vinp_LNA Vinm_LNA GND GND 12345INP_LNA1142-0701-851 12345INM_LNA1142-0701-851 C14100nFC11 100nFC16 GND100nFC12 100nFC1510pFC13 0R9 0R13GND 50R7 50R16 GND Vinp_VGA Vinm_VGA GND GND 12345INP_VGA1142-0701-851 12345INM_VGA1142-0701-851 C190R19 0R31VOM_LNA 50R3050R220R25 VOP_LNA VCC_LNA19VCC_VGA7 EN_LNA3EN_VGA9VIM_LNA16VIM_VGA4VIP_LNA17VIP_VGA5 VOM_LNA2VOM_VGA12VOP_LNA1VOP_VGA11 NC18EP21HILO15 VICM_EN8VREF13 Gain_ADJ14 GND_LNA20GND_VGA6 VOCM_ADJ10 VCA710RGR EN_VGAEN_LNA GND VCC_LNAVCC_VGA HILO Gain_ADJVOCM_ADJVREF VOM_VGAVOP_VGA Vinp_VGAVinm_VGA VOP_LNAVOM_LNA GND Vinp_LNAVinm_LNA 0R18 VGAVout-12345OUTM_VGA1142-0701-85112345OUTP_VGA1142-0701-851GND VOM_VGA VOP_VGA GND10pFC20 0R26 GND 0R39 GNDVCC_VGA123J_HILOTSW-103-07-G-S GND HILO 100nFC26GND VOCM_ADJ 100nFC27 0R38GND123J_ENVGATSW-103-07-G-S GND EN_VGA 100nFC250R37 GND123J_ENLNATSW-103-07-G-S GND EN_LNA 100nFC24 VCC_LNA VCC_VGA GND123J_VICMENTSW-103-07-G-S GND VICM_EN100nFC23 VCC_VGA VOCM_ADJ1.00kR351.00kR40 VCC_VGA 0R36 VICM_EN GND VCC_LNA VCC_VGA GND GND GND L1MI1206K310R-10 L2MI1206K310R-10VCC_LNA16095 VCC_VGA16095 GND16095 12VCC_Short1PBC02SAAN Gain_ADJ1000pFC10GND0R3 100nFC9VREF GND Gain_ADJ VREF GND R2PV37W103C01B00VCC_VGA VGAVout+ 1µFC7 1µFC3100nFC6 100nFC210µFC8 10µFC4 0.01uFC10.01uFC5 22kR1 03063C103KAT2A VOCM_VGA5002 VOCM_LNA5002 1µFC18100nFC170R41 10µFC22 10µFC211.50kR421.00kR44GNDGND 0R43 0R34 0R17 120R4 120R14 10.0R5 10.0R15 221R20 221R32 64.2R2464.2R28 59.7R1159.7R8 VIN4EN3NR5 VREF6GND1GND2REF35125QDBVR Figure 8-4. VCA710RGREVM Schematic VCA710 Top Layer VCA710 Bottom Layer VCA710 SLOSEB2 – FEBRUARY 2026 www.ti.com

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9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

9.1 Device Support

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES February 2026 * Initial Release www.ti.com VCA710 SLOSEB2 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: VCA710 ADVANCE INFORMATION

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

11.1 Tape and Reel Information

Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant VCA710RGRR VQFN RGR0020 A 20 3000 330 12.4 3.75 3.75 1.15 8 12 2 VCA710 SLOSEB2 – FEBRUARY 2026 www.ti.com

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TAPE AND REEL BOX DIMENSIONS Width (mm) W L H Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) VCA710RGRR VQFN RGR0020A 20 3000 346 346 33 www.ti.com VCA710 SLOSEB2 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: VCA710 ADVANCE INFORMATION

11.2 Mechanical Data

www.ti.com PACKAGE OUTLINE C 3.653.35 3.653.35 1.00.80.050.00 2X 216X 0.5 2X 2 20X 0.50.320X 0.300.18 2.050.1 (DIM A) TYP VQFN - 1 mm max heightRGR0020APLASTIC QUAD FLATPACK - NO LEAD 4219031/B 04/2022 SIDE WALL METAL THICKNESSDIM AOPTION 1OPTION 20.10.20.08C PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMMEXPOSEDTHERMAL PADSYMM1 56 1011 151620 AB VCA710 SLOSEB2 – FEBRUARY 2026 www.ti.com

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www.ti.com EXAMPLE BOARD LAYOUT 16X (0.5)(0.775) (0.775)(0.2) TYPVIA(R0.05) TYP 0.07 MAXALL AROUND0.07 MINALL AROUND (3.3) (3.3)(2.05) (2.05)VQFN - 1 mm max heightRGR0020APLASTIC QUAD FLATPACK - NO LEAD SYMM SYMM LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 20X SEE SOLDER MASKDETAIL1 5 6 1011 151620 METAL EDGESOLDER MASKOPENINGEXPOSED METAL METAL UNDERSOLDER MASKSOLDER MASKOPENINGEXPOSEDMETALNON SOLDER MASKDEFINED(PREFERRED)SOLDER MASK DEFINEDSOLDER MASK DETAILS www.ti.com VCA710 SLOSEB2 – FEBRUARY 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: VCA710 ADVANCE INFORMATION

www.ti.com EXAMPLE STENCIL DESIGN (3.3) (3.3) (0.56) TYP 4X (0.92) (R0.05) TYP VQFN - 1 mm max heightRGR0020APLASTIC QUAD FLATPACK - NO LEAD 4219031/B 04/2022NOTES: (continued)6.Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations. SOLDER PASTE EXAMPLEBASED ON 0.125 MM THICK STENCILSCALE: 20XEXPOSED PAD 2181% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM 1 5 6 1011 151620 VCA710 SLOSEB2 – FEBRUARY 2026 www.ti.com

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www.ti.com 5-Mar-2026 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) XVCA710RGRR Active Preproduction VQFN (RGR) | 20 3000 | LARGE T&R - Call TI Call TI -40 to 125 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRGR 20 PLASTIC QUAD FLATPACK - NO LEAD3.5 x 3.5, 0.5 mm pitch 4228482/A

www.ti.com PACKAGE OUTLINE C 3.65 3.35 3.65 3.35 1.0 0.80.05 0.00 2X 2 16X 0.5 2X 2 20X 0.5 0.3 20X 0.30 0.18 2.05 0.1 (DIM A) TYP VQFN - 1 mm max heightRGR0020A PLASTIC QUAD FLATPACK - NO LEAD 4219031/B 04/2022 SIDE WALL METAL THICKNESS DIM A OPTION 1 OPTION 2 0.1 0.2 0.08 C

0.1 C A B

0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMM EXPOSED THERMAL PAD SYMM 6 10 1620 AB

www.ti.com EXAMPLE BOARD LAYOUT 16X (0.5) (0.775) (0.775) ( 0.2) TYP VIA (R0.05) TYP

0.07 MAX

0.07 MIN

20X (0.6) 20X (0.24) (3.3) (3.3) (2.05) (2.05) VQFN - 1 mm max heightRGR0020A PLASTIC QUAD FLATPACK - NO LEAD 4219031/B 04/2022 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SEE SOLDER MASK DETAIL 6 10 1620 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 20X (0.6) 20X (0.24) 16X (0.5) (3.3) (3.3) (0.56) TYP (0.56) TYP 4X (0.92) 4X (0.92) (R0.05) TYP VQFN - 1 mm max heightRGR0020A PLASTIC QUAD FLATPACK - NO LEAD 4219031/B 04/2022 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 20X EXPOSED PAD 21 81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM 6 10 1620

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