Amplifier

VCA5807

Texas Instruments

Fully Integrated, 8-Channel Voltage Controlled Amplifier for Ultrasound with Passive CW Mixer, 0.75 nV/rtHz, 99 mW/CH

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Fully Integrated, 8-Channel Voltage Controlled Amplifier for Ultrasound datasheet

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Manufacturer or author: Texas Instruments, Incorporated [SLOS727,*]
PDF pages: 65

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www.ti.com SLOS727 –DECEMBER 2012 FullyIntegrated,8-ChannelVoltageControlledAmplifierforUltrasoundwithPassiveCW Mixer,0.75nV/rtHz,99mW/CH Check forSamples: VCA5807 1FEATURES DESCRIPTION The VCA5807 is an integratedVoltageControlled• 8-ChannelVoltageControlledAmplifier Amplifier(VCA) specificallydesigned forultrasound– LNA, VCAT, PGA, LPF, and CW Mixer systems in which high performanceand smallsize

Programmable Low-Noise Amplifier(LNA) are required.The VCA5807 integratesa complete time-gain-control(TGC) imaging path and a– 24/18/12dB Gain continuouswave Doppler(CWD) path.Italsoenables– 0.25/0.5/1VPP LinearInputRange users to select one of various power/noise – 0.63/0.7/0.9nV/rtHzInputReferredNoise combinations to optimize system performance. Therefore,the VCA5807 is a suitableultrasound– Programmable ActiveTermination analog frontend solutionnot only for high-end• 40 dB Low Noise VoltageControlled systems,butalsoforportablesystems.Attenuator(VCAT) The VCA5807 containseightchannels of voltage• 24/30dB Programmable Gain Amplifier(PGA) controlledamplifier(VCA),and CW mixer.The VCA• 3rd Order LinearPhase Low-Pass Filter(LPF) includesLow noiseAmplifier(LNA),Voltagecontrolled – 10,15,20,30 MHz Attenuator(VCAT), Programmable Gain Amplifier (PGA), and Low-Pass Filter(LPF).The LNA gainis– ButterworthCharacteristics programmable to support250 mV PP to 1 VPP input• Noise/Power Optimizations(FullChain) signals.Programmable activeterminationis also – 99 mW/CH at0.75nV/rtHz supportedby the LNA. The ultra-lownoise VCAT providesan attenuationcontrolrange of 40dB and– 56 mW/CH at1.1nV/rtHz improves overalllow gain SNR which benefits– 80 mW/CH atCW Mode harmonicimagingand near fieldimaging.The PGA
ExcellentDevice-to-DeviceGain Matching providesgainoptionsof24 dB and 30 dB. Beforethe ADC, a LPF can be configuredas 10 MHz, 15 MHz,– ±0.5dB (typical)and ±1.05dB (max) 20 MHz, or 30 MHz to support ultrasound• Low Harmonic Distortion applicationswithdifferentfrequencies.Inaddition,the• Fastand ConsistentOverload Recovery signalchain of the VCA5807 can handle signal
Low Frequency Sonar SignalProcessing frequencylowerthan100 KHz, whichenablesittobe used not onlyin ultrasoundapplicationsbut alsoin• PassiveMixerforContinuous Wave Doppler sonarapplications.(CWD) The VCA5807 integratesa low power passivemixer– Low Close-inPhase Noise –156 dBc/Hz at1 and a low noisesumming amplifiertoaccomplishon-KHz off2.5MHz Carrier chipCWD beamformer.16 selectablephase-delays– Phase Resolutionof1/16λ can be applied to each analog input signal. – Support 32X,16X,8X,4X and 1X CW Clocks Meanwhile a unique 3rd and 5th order harmonic suppressionfilteris implemented to enhance CW– 12dB Suppression on 3rd and 5th Harmonics sensitivity.– FlexibleInputClocks The VCA5807 isavailableina 14mm x 14mm, 100-• 14mm x 14mm, 100-pinTQFP pin TQFP package and itisspecifiedforoperation from-40°C to85°C.APPLICATIONS
MedicalUltrasoundImaging
NondestructiveEvaluationEquipments
Sonar Imaging Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2012,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

24, 30dB 3rd LP Filter 10, 15, 20, 30 MHz

16 Phases

Generator CW Mixer Summing Amplifier/ Filter 1X CLK (Syc) 1X CLK LNA OUT CW I/Q Vout VCA5807 1 of 8 Channels Differential Outputs Reference Differential TGC Vcntl 16X1 Multiplexer VCA5807 SLOS727 –DECEMBER 2012 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. Figure1. Block Diagram PACKAGING/ORDERING INFORMATION (1) PRODUCT PACKAGE TYPE OPERATING ORDERING NUMBER PACKAGE QUANTITY VCA5807 TQFP -40°C to85°C VCA5807PZP 90 (1) Forthemost currentpackage and orderinginformationsee thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com. ABSOLUTE MAXIMUM RATINGS overoperatingfree-airtemperaturerange(unlessotherwisenoted)(1) VALUE UNIT MIN MAX AVDD –0.3 3.9 V Supplyvoltagerange AVDD_5V –0.3 6 V Voltageatanaloginputsand digitalinputs –0.3 min [3.6,AVDD+0.3] V Peak soldertemperature(2) 260 °C Maximum junctiontemperature(TJ),any condition 105 °C Storagetemperaturerange –55 150 °C Operatingtemperaturerange -40 85 °C HBM 2000 V ESD Ratings CDM 500 V (1) Stressesabove thoselistedunderabsolutemaximum ratingsmay cause permanentdamage tothedevice.These arestressratings onlyand functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimpliedExposuretoabsolutemaximum ratedconditionsforextendedperiodsmay degradedevicereliability. (2) DevicecomplieswithJSTD-020D.

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www.ti.com SLOS727 –DECEMBER 2012 THERMAL INFORMATION VCA5807 THERMAL METRIC (1) TQFP UNITS

100 PINS

θJA Junction-to-ambientthermalresistance 25.0 θJCtop Junction-to-case(top)thermalresistance 6.1 θJB Junction-to-boardthermalresistance 7.7 °C/W ψJT Junction-to-topcharacterizationparameter 0.2 ψJB Junction-to-boardcharacterizationparameter 7.6 θJCbot Junction-to-case(bottom)thermalresistance 0.2 (1) Formore informationabouttraditionaland new thermalmetrics,see theIC Package ThermalMetricsapplicationreport,SPRA953 . RECOMMENDED OPERATING CONDITIONS PARAMETER MIN MAX UNIT AVDD 3.15 3.6 V AVDD_5V 4.75 5.5 V AmbientTemperature,TA -40 85 °C Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLinks:VCA5807

SLOS727 –DECEMBER 2012 www.ti.com PINOUT INFORMATION TQFP PACKAGE (TOP VIEW) PIN FUNCTIONS PIN

DESCRIPTION

NO. NAME 17,20,23 27,28,29,43, AVDD 3.3VAnalogsupplyforLNA, VCAT, PGA, LPF and CWD blocks. 78,88,96,97, 98,100 50 AVDD_5V 5V AnalogsupplyforLNA, VCAT, PGA, LPF and CWD blocks. 26,31,32,37, 42,44,58,63, AVSS Analogground.68,79,82.89, 92,95,99 NegativeinputofdifferentialCW 16X clock.TietoGND when theCMOS clockmode isenabled.Inthe 4X,8X,and 32X CW clockmodes, thispinbecomes the4X,8X,or32X CLKM input.Inthe1X CW93 CLKM_16X clockmode, thispinbecomes thequadrature-phase1X CLKM fortheCW mixer.Can be floatedifCW mode isnotused.Pleasesee CW ClockSelection. PositiveinputofdifferentialCW 16X clock.In4X,8X,and 32X clockmodes, thispinbecomes the4X, 94 CLKP_16X 8X,or32X CLKP input.Inthe1X CW clockmode, thispinbecomes thequadrature-phase1X CLKP fortheCW mixer.Can be floatedifCW mode isnotused.Pleasesee CW ClockSelection.

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www.ti.com SLOS727 –DECEMBER 2012 PIN FUNCTIONS (continued) PIN NO. NAME NegativeinputofdifferentialCW 1X clock.TietoGND when theCMOS clockmode isenabled(Refer 90 CLKM_1X toFigure94 fordetails).Inthe1X clockmode, thispinistheIn-phase1X CLKM fortheCW mixer. Can be floatedifCW mode isnotused.Pleasesee CW ClockSelection. PositiveinputofdifferentialCW 1X clock.Inthe1X clockmode, thispinistheIn-phase1X CLKP for91 CLKP_1X theCW mixer.Can be floatedifCW mode isnotused.Pleasesee CW ClockSelection. Biasvoltageand bypasstoground.≥ 1µF isrecommended. To suppressultralowfrequencynoise,30 CM_BYP 10µF can be used. NegativedifferentialinputoftheIn-phasesumming amplifier.ExternalLPF capacitorhas tobe 34 CW_IP_AMPINM connectedbetween CW_IP_AMPINM and CW_IP_OUTP. Thispinbecomes theCH7 PGA negative outputwhen PGA testmode isenabled.Can be floatedifnotused. PositivedifferentialinputoftheIn-phasesumming amplifier.ExternalLPF capacitorhas tobe 35 CW_IP_AMPINP connectedbetween CW_IP_AMPINP and CW_IP_OUTM. Thispinbecomes theCH7 PGA positive outputwhen PGA testmode isenabled.Can be floatedifnotused. NegativedifferentialoutputfortheIn-phasesumming amplifier.ExternalLPF capacitorhas tobe36 CW_IP_OUTM connectedbetween CW_IP_AMPINP and CW_IP_OUTPM. Can be floatedifnotused. PositivedifferentialoutputfortheIn-phasesumming amplifier.ExternalLPF capacitorhas tobe33 CW_IP_OUTP connectedbetween CW_IP_AMPINM and CW_IP_OUTP. Can be floatedifnotused. Negativedifferentialinputofthequadrature-phasesumming amplifier.ExternalLPF capacitorhas toCW_QP_AMPIN39 be connectedbetween CW_QP_AMPINM and CW_QP_OUTP. Thispinbecomes CH8 PGA negativeM outputwhen PGA testmode isenabled.Can be floatedifnotused. Positivedifferentialinputofthequadrature-phasesumming amplifier.ExternalLPF capacitorhas tobe 40 CW_QP_AMPINP connectedbetween CW_QP_AMPINP and CW_QP_OUTM. Thispinbecomes CH8 PGA positive outputwhen PGA testmode isenabled.Can be floatedifnotused. Negativedifferentialoutputforthequadrature-phasesumming amplifier.ExternalLPF capacitorhas to41 CW_QP_OUTM be connectedbetween CW_QP_AMPINP and CW_QP_OUTM. Can be floatedifnotused. Positivedifferentialoutputforthequadrature-phasesumming amplifier.ExternalLPF capacitorhas to38 CW_QP_OUTP be connectedbetween CW_QP_AMPINM and CW_QP_OUTP. Can be floatedifnotused. 25,48,49,51, 52,53,73,74, NC Do notconnect.Must leavefloated 75,76,77 81 PDN_FAST VCA partial(fast)power down controlpinwithan internalpulldown resistorof20kΩ.ActiveHigh. Global(complete)power-down controlpinfortheentirechipwithan internalpulldown resistorof80 PDN_GLOBAL 20kΩ.ActiveHigh. 54,56,59,61, PGA_OUTMx NegativePGA output64,66,69,71 55,57,60,62, PGA_OUTPx PositivePGA output65,67,70,72 87 RESET Hardware resetpinwithan internalpull-downresistorof20kΩ.Activehigh.

86 SCLK Serialinterfaceclockinputwithan internalpull-downresistorof20kΩ

85 SDATA Serialinterfacedatainputwithan internalpull-downresistorof20kΩ

83 SDOUT Serialinterfacedatareadout.Highimpedance when readoutisdisabled. 84 SEN Serialinterfaceenablewithan internalpullup resistorof20kΩ.Activelow. 46 VCNTLM Negativedifferentialattenuationcontrolpin.

47 VCNTLP Positivedifferentialattenuationcontrolpin

u 8CH_SNR- 10N 10 1 1C = x - 1CH_SNRN + N 56 7 -C 1010 VCA5807 SLOS727 –DECEMBER 2012 www.ti.com

ELECTRICAL CHARACTERISTICS

AVDD_5V = 5V,AVDD = 3.3V,AC-coupledwith0.1µF atINP and bypassedtogroundwith15nF atINM, No active termination,VCNTL = 0V,fIN= 5MHz, LNA = 18dB,PGA = 24dB,LPF Filter= 15MHz, lownoisemode, VOUT = –1dBFS (1.8VPP ), single-endedVCNTL mode, VCNTLM = GND, 2 kΩ load(ADC Rin),internal500Ω CW feedbackresistor,CMOS CW clocks, atambienttemperatureTA = 25°C, unlessotherwisenoted.Min and max valuesarespecifiedacrossfull-temperaturerange withAVDD_5V=5V, AVDD=3.3V PARAMETER TEST CONDITION MIN TYP MAX UNITS TGC FULL SIGNAL CHANNEL (LNA+VCAT+LPF) en (RTI) Inputvoltagenoiseatlowfrequency f= 100 KHz, INM Cap = 1uF,PGA integratordisabled(0x33[4]=1) 0.9 nV/rtHz Inputreferredcurrentnoise Low NoiseMode/Medium Power Mode/Low Power Mode 2.7/2.1/2 pA/rtHz R S = 200Ω,200Ω activetermination,PGA = 24dB,LNA = 12/18/24dB 3.85/2.4/1.8 dB NF Noisefigure R S = 100Ω,100Ω activetermination,PGA = 24dB,LNA = 12/18/24dB 5.3/3.1/2.3 dB Rs = 500 Ω/1KΩ,no terminaiton,Low NF mode isenabled(Reg53[9]=1) 0.94/1.08 dB NF Noisefigure Rs=50Ω/200Ω,no terminaiton,Low noisemode (Reg53[9]=0) 2.35/1.05 dB VINMAX Maximum LinearInputVoltage LNA gain= 24/18/12dB 250/500/1000 mV PP VCLAMP Clamp Voltage Reg52[10:9]= 0,LNA = 24/18/12dB 350/600/1150 Low noisemode 24/30 PGA Gain dB Medium/Low power mode 24/28.5 LNA = 24dB,PGA = 30dB,Low noisemode 54 Totalgain LNA = 24dB,PGA = 30dB,Med power mode 52.5 dB LNA = 24dB,PGA = 30dB,Low power mode 52.5 VOUT MAX Maximum LinearOutputVoltage Definedas 0 dBFS 2 VPP Ch-CH NoiseCorrelationFactorwithout Summing of8 channels 0Signal(1) Fullband (VCNTL = 0/0.8) 0.15/0.17Ch-CH NoiseCorrelationFactorwith Signal(1) 1MHz band overcarrier(VCNTL = 0/0.8) 0.18/0.75 VCNTL = 0.6V(22dB totalchannelgain) 40 67 OutputReferredNoise VCNTL = 0,LNA = 18dB,PGA = 24dB 104 153 nV/rtHz VCNTL = 0,LNA = 24dB,PGA = 24dB 190 Narrow Band IntegratedOutputNoise Noiseover2MHz band aroundcarrieratVCNTL = 0.6V(22dB totalgain) 100 125 µVRMS InputCommon-mode Voltage AtINP and INM pins 2.4 V 8 kΩ Inputresistance Presetactiveterminationenabled 50/100/200/400 Ω Inputcapacitance 20 pF InputControlVoltage VCNTLP -VCNTLM 0 1.5 V Common-mode voltage VCNTLP and VCNTLM 0.75 V Gain Range -40 dB Gain Slope VCNTL = 0.1Vto1.1V 35 dB/V InputResistance Between VCNTLP and VCNTLM 200 KΩ InputCapacitance Between VCNTLP and VCNTLM 1 pF TGC Response Time VCNTL = 0V to1.5Vstepfunction 1.5 µs 3rdorder-Low-passFilter 10,15,20,30 MHz Settlingtimeforchange inLNA gain 14 µs Settlingtimeforchange inactive 1 µsterminationsetting (1) Noisecorrelationfactorisdefinedas Nc/(Nu+Nc),where Nc isthecorrelatednoisepower insinglechannel;and Nu istheuncorrelated noisepower insinglechannel.Itsmeasurement followsthebelowequation,inwhichtheSNR ofsinglechannelsignaland theSNR of summed eightchannelsignalaremeasured.

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www.ti.com SLOS727 –DECEMBER 2012 ELECTRICAL CHARACTERISTICS (continued) AVDD_5V = 5V,AVDD = 3.3V,AC-coupledwith0.1µF atINP and bypassedtogroundwith15nF atINM, No active termination,VCNTL = 0V,fIN= 5MHz, LNA = 18dB,PGA = 24dB,LPF Filter= 15MHz, lownoisemode, VOUT = –1dBFS (1.8VPP ), single-endedVCNTL mode, VCNTLM = GND, 2 kΩ load(ADC Rin),internal500Ω CW feedbackresistor,CMOS CW clocks, atambienttemperatureTA = 25°C, unlessotherwisenoted.Min and max valuesarespecifiedacrossfull-temperaturerange withAVDD_5V=5V, AVDD=3.3V PARAMETER TEST CONDITION MIN TYP MAX UNITS AC ACCURACY LPF Bandwidthtolerance ±5 % CH-CH groupdelayvariation 2MHz to15MHz 2 ns CH-CH Phase variation 15MHz signal 11 Degree 0V < VCNTL < 0.1V(Dev-to-Dev) ±0.5 Gain matching dB 1.1V< VCNTL < 1.5V(Dev-to-Dev) ±0.5 Gain matching Channel-to-Channel ±0.25 dB Outputoffset VCNTL = 0,PGA = 30dB,LNA = 24dB -6 6 mV AC PERFORMANCE FIN = 2MHz; VOUT = -1dBFS –60 FIN = 5MHz; VOUT = -1dBFS –60 FIN = 5MHz; VIN= 500mV PP ,HD2 Second-HarmonicDistortion dBc–55VOUT = –1dBFS, LNA = 18dB FIN = 5MHz; Vin= 250mV PP , –55VOUT =–1dBFS, LNA = 24dB FIN = 2MHz; VOUT = –1dBFS –53 FIN = 5MHz; VOUT = –1dBFS –55 FIN = 5MHz; VIN = 500mV PP ,HD3 Third-HarmonicDistortion dBc–55VOUT = –1dBFS, LNA = 18dB FIN = 5MHz; VIN = 250mV PP , –55VOUT = –1dBFS, LNA = 24dB FIN = 2MHz; VOUT = –1dBFS –52.5 THD TotalHarmonicDistortion dBc FIN = 5MHz; VOUT = –1dBFS –55 f1= 5MHz at–1dBFS,IMD3 Intermodulationdistortion –60 dBcf2= 5.01MHz at–27dBFS XTALK Cross-talk FIN = 5MHz; VOUT = –1dBFS –65 dBc Phase Noise 1kHz off5MHz (VCNTL =0V) –132 dBc/Hz LNA InputReferredVoltageNoise R S = 0Ω,f= 2MHz, R IN = HighZ,Gain = 24/18/12dB 0.63/0.70/0.9 nV/rtHz High-PassFilter -3dB Cut-offFrequency 50/100/150/200 KHz LNA linearoutput 4 Vpp VCAT+ PGA VCAT InputNoise 0dB/-40dBAttenuation 2/10.5 nV/rtHz PGA InputNoise 24dB/30dB 1.75 nV/rtHz -3dB HPF cut-offFrequency High-PassFilterisenabled 80 KHz OutputCommon Mode Voltage 0.9 V VOUT MAX Maximum LinearOutputVoltage Definedas 0 dBFS 2 VPP Minimum Load Impedance 1 KΩ Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLinks:VCA5807

SLOS727 –DECEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AVDD_5V = 5V,AVDD = 3.3V,AC-coupledwith0.1µF atINP and bypassedtogroundwith15nF atINM, No active termination,VCNTL = 0V,fIN= 5MHz, LNA = 18dB,PGA = 24dB,LPF Filter= 15MHz, lownoisemode, VOUT = –1dBFS (1.8VPP ), single-endedVCNTL mode, VCNTLM = GND, 2 kΩ load(ADC Rin),internal500Ω CW feedbackresistor,CMOS CW clocks, atambienttemperatureTA = 25°C, unlessotherwisenoted.Min and max valuesarespecifiedacrossfull-temperaturerange withAVDD_5V=5V, AVDD=3.3V PARAMETER TEST CONDITION MIN TYP MAX UNITS CW DOPPLER 1 channelmixer,LNA = 24dB,500Ω feedbackresistor 0.8 en (RTI) Inputvoltagenoise(CW) nV/rtHz 8 channelmixer,LNA = 24dB,62.5Ω feedbackresistor 0.33 1 channelmixer,LNA = 24dB,500Ω feedbackresistor 12 en (RTO) Outputvoltagenoise(CW) nV/rtHz 8 channelmixer,LNA = 24dB,62.5Ω feedbackresistor 5 1 channelmixer,LNA = 18dB,500Ω feedbackresistor 1.1 en (RTI) Inputvoltagenoise(CW) nV/rtHz 8 channelmixer,LNA = 18dB,62.5Ω feedbackresistor 0.5 1 channelmixer,LNA = 18dB,500Ω feedbackresistor 8.1 en (RTO) Outputvoltagenoise(CW) nV/rtHz 8 channelmixer,LNA = 18dB,62.5Ω feedbackresistor 4.0 R S = 100Ω,R IN = HighZ,FIN = 2MHz (LNA,I/Qmixerand summingNF Noisefigure 1.8 dBamplifier/filter) fCW CW OperationRange (2) CW signalcarrierfrequency,16X mode /32X mode 8/4 MHz 1X CLK (16X mode) 8 16X CLK(16X mode) 128 CW Clockfrequency MHz 4X CLK(4X mode) 32 32X CLK(32X mode) 128 AC coupledLVDS clockamplitude 0.7 CLKM_16X-CLKP_16X; CLKM_1X-CLKP_1X VPP AC coupledLVPECL clockamplitude 1.6 CLK dutycycle 1X and 16X CLKs 35 65 % Common-mode voltage Internalprovided 2.5 V VCMOS CMOS Inputclockamplitude 4 5 V CW Mixerconversionloss 4 dB CW Mixerphase noise 1kHz off2MHz carrier -156 dBc/Hz DR Inputdynamicrange FIN = 2MHz, LNA=24/18/12dB 160/164/165 dBFS/Hz f1= 5 MHz, f2= 5.01MHz, bothtonesat-8.5dBm amplitude,8 channels –50 dBcsummed up in-phase,CW feedbackresistor= 87 Ω IMD3 Intermodulationdistortion f1= 5 MHz, F2= 5.01MHz, bothtonesat–8.5dBm amplitude,Single –60 dBcchannelcase,CW feedback resistor= 500Ω I/QChannelgainmatching 16X mode ±0.04 dB I/QChannelphase matching 16X mode ±0.1 Degree I/QChannelgainmatching 4X mode ±0.04 dB I/QChannelphase matching 4X mode ±0.1 Degree Image rejectionratio fin= 2.01MHz,300mV inputamplitude,CW clockfrequency= 2.00MHz –50 dBc (2) The maximum clockfrequencyforthe16X and 32X CLK is128MHz. Hence,theCW operationrangeislimitedto8MHz inthe16X CW mode. Inthe8X,4X,and 1X modes, higherCW signalfrequenciesup to15 MHz can be supportedwithsmalldegradationin performance,pleasesee CW ClockSelection.

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www.ti.com SLOS727 –DECEMBER 2012 ELECTRICAL CHARACTERISTICS (continued) AVDD_5V = 5V,AVDD = 3.3V,AC-coupledwith0.1µF atINP and bypassedtogroundwith15nF atINM, No active termination,VCNTL = 0V,fIN= 5MHz, LNA = 18dB,PGA = 24dB,LPF Filter= 15MHz, lownoisemode, VOUT = –1dBFS (1.8VPP ), single-endedVCNTL mode, VCNTLM = GND, 2 kΩ load(ADC Rin),internal500Ω CW feedbackresistor,CMOS CW clocks, atambienttemperatureTA = 25°C, unlessotherwisenoted.Min and max valuesarespecifiedacrossfull-temperaturerange withAVDD_5V=5V, AVDD=3.3V PARAMETER TEST CONDITION MIN TYP MAX UNITS CW SUMMING AMPLIFIER VCMO Common-mode voltage Summing amplifierinputs/outputs 1.5 V Summing amplifieroutput 4 VPP 100Hz 2 nV/rtHz Inputreferredvoltagenoise(3) 1kHz 1.2 nV/rtHz 2KHz-100MHz 1 nV/rtHz 100Hz 7 pA/rtHz Inputreferredcurrentnoise(3) 1kHz 3 pA/rtHz 10KHz-100MHz 2.5 pA/rtHz Unitgainbandwidth 200 MHz Max outputcurrent Linearoperationrange 20 mA PP POWER DISSIPATION AVDD Voltage 3.15 3.3 3.6 V AVDD_5V Voltage 4.75 5 5.5 V TGC lownoisemode, no signal 203 235 TGC medium power mode, no signal 126 TGC lowpower mode, no signal 99 CW-mode, no signal 147 172 AVDD (3.3V)Current mA TGC lownoisemode, 500mV PP Input,1%dutycycle 210 TGC medium power mode, 500mV PP Input,1% dutycycle 133 TGC lowpower,500mV PP Input,1% dutycycle 105 CW-mode, 500mV PP Input 375 TGC mode no signal 25.5 35 CW Mode no signal,16X clock= 32MHz 32 AVDD_5V Current mA TGC mode, 500mV PP Input,1%dutycycle 16.5 CW-mode, 500mV PP Input 42.5 TGC lownoisemode, no signal 99 121 TGC medium power mode, no signal 68 TGC lowpower mode, no signal 55.5 VCA Power dissipation mW/CH TGC lownoisemode, 500mV PP input,1%dutycycle 102.5 TGC medium power mode, 500mV PP Input,1% dutycycle 71 TGC lowpower mode, 500mV PP input,1%dutycycle 59.5 CW Power dissipation No signal,CW Mode no signal,16X clock= 32MHz 80 mW/CH 500mV PP input,16X clock= 32MHz 173 Power dissipationinpower down mode PDN_FAST = High 12.5 mW/CH Completepower-down PDN_Global=High 0.6 2 Power-down responsetime Time takentoenterpower down 1 µs 2µs+1% ofPDNVCA power down µstimePower-upresponsetime Completepower down 2.5 ms fin= 5MHz, at50mVpp noiseat1KHz on supply(4) –65 dBcPower supplymodulationratio,AVDD and AVDD_5V (TGC Mode) fin= 5MHz, at50mV PP noiseat50KHz on supply(4) –65 dBc f= 10kHz,VCNTL = 0V (highgain),AVDD –40 dBc Power supplyrejectionratio(TGC Mode) f= 10kHz,VCNTL = 0V (highgain),AVDD_5V –55 dBc f= 10kHz,VCNTL = 1V (lowgain),AVDD –50 dBc fin= 5MHz, 1-20KHz 100mVpp noiseon theAVDD -57 dBcPower supplymodulationratio(CW Mode with8 mixersactive) fin= 5MHz, 1-20KHz 100mVpp noiseon theAVDD_5V -59 dBc fin= 5MHz, 5.001-5.02MHz 100mVpp noiseon theAVDD -75 dBcPower supplyrejectionratio(CW Mode with8 mixersactive) fin= 5MHz, 5.001-5.02MHz 100mVpp noiseon theAVDD_5V -40 dBc (3) By simulation. (4) PSMR specificationiswithrespecttoRF signalamplitude. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLinks:VCA5807

SLOS727 –DECEMBER 2012 www.ti.com DIGITAL CHARACTERISTICS (Note:Thistimingdatawas collectedunder14 bitoperation) Typicalvaluesareat25°C, AVDD = 3.3V,AVDD_5 = 5V unlessotherwisenoted.Minimum and maximum valuesareacross thefulltemperaturerange:TMIN = -40°C toTMAX = 85°C. PARAMETER CONDITION MIN TYP MAX UNITS DIGITAL INPUTS/OUTPUTS VIH Logichighinputvoltage 2 3.3 V VIL Logiclowinputvoltage 0 0.3 V Logichighinputcurrent 200 µA Logiclowinputcurrent 200 µA Inputcapacitance 5 pF VOH Logichighoutputvoltage SDOUT pin AVDD V VOL Logiclowoutputvoltage SDOUT pin 0 V

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180 Number of Occurances

Gain Error (dB) C001 100 120 140 160 Gain Error (dB) C002 VCA5807 www.ti.com SLOS727 –DECEMBER 2012 TYPICAL CHARACTERISTICS AVDD_5V = 5V, AVDD = 3.3V,ac-coupledwith0.1µF caps atINP and 15nF caps atINM, No activetermination, VCNTL = 0V,FIN = 5MHz, LNA = 18dB,PGA = 24dB,LPF Filter= 15MHz, lownoisemode, single-endedVCNTL mode, VCNTLM = GND, VOUT = -1dBFS (1.8VPP ),2 kΩ load(ADC Rin),500Ω CW feedbackresistor,CMOS 16X clock,atambienttemperatureTA = 25C, unlessotherwisenoted. Figure2.Gain vs.VCNTL, LNA = 18dB and PGA = 24dB Figure3.Gain vs.Temperature,LNA = 18dB and PGA = 24dB Figure4.Gain Matching Histogram, Figure5.Gain Matching Histogram, VCNTL = 0.3V(1336channels) VCNTL = 0.6V(1336channels) Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLinks:VCA5807

−90 −80 −70 −60 −50 −40 −30 −20 −10 Impedance Phase Response Frequency (Hz) Phase (Degrees)

50 Ohms

100 Ohms

200 Ohms

400 Ohms

−30 −25 −20 −15 −10 0 10 20 30 40 50 60 Frequency (MHz) Amplitude (dB) 10MHz 15MHz 20MHz 30MHz −90 −80 −70 −60 −50 −40 −30 −20 −10 Impedance Phase Response Frequency (Hz) Phase (Degrees) Open 100 150 200 250 300 350 400 450 500 Impedance Magnitude Response Frequency (Hz) Impedance (Ohms) Impedance Magnitude Response Frequency (Hz) Impedance (Ohms) Open 100 120 140 160 Gain Error (dB) C003 VCA5807 SLOS727 –DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure6.Gain Matching Histogram, Figure7.InputImpedance withoutActiveTermination (Magnitude)VCNTL = 0.9V(1336channels) Figure8.InputImpedance withoutActiveTermination Figure9.InputImpedance withActiveTermination (Phase) (Magnitude) Figure10.InputImpedance withActiveTermination(Phase) Figure11.Low-Pass FilterResponse

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−170 −168 −166 −164 −162 −160 −158 −156 −154 −152 −150 −148 −146 −144 100 1000 10000 50000 Eight Channel CW PN Offset frequency (Hz) Phase Noise (dBc/Hz) 16X Clock Mode 8X Clock Mode 4X Clock Mode −170 −168 −166 −164 −162 −160 −158 −156 −154 −152 −150 −148 −146 −144 100 1000 10000 50000 Single Channel CW PN Offset frequency (Hz) Phase Noise (dBc/Hz) 16X Clock Mode 8X Clock Mode 4X Clock Mode −170 −168 −166 −164 −162 −160 −158 −156 −154 −152 −150 −148 −146 −144 100 1000 10000 50000 Phase Noise Frequency Offset (Hz) Phase Noise (dBc/Hz) PN 1 Ch PN 8 Ch −30 −27 −24 −21 −18 −15 −12 10 100 500 LNA INPUT HPF CHARECTERISTICS Frequency (KHz) Amplitude (dB) −40 −35 −30 −25 −20 −15 −10 10 100 500 HPF CHARECTERISTICS (LNA+VCA+PGA) Frequency (KHz) Amplitude (dB) VCA5807 www.ti.com SLOS727 –DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) Figure12.LNA High-Pass FilterResponse vs.Reg59[3:2] Figure13.FullChannel High-Pass FilterResponse at DefaultRegisterSetting Figure14.1-CH CW Phase Noise,Fin= 2MHz Figure15.CW Phase Noise,Fin= 2MHz, 1-CH vs.8-CHs Figure16.8-CHs CW Phase Noise vs.Clock Modes, Fin= Figure17.CW Thermal Noise 1-CH vs 8-CHs 2MHz Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLinks:VCA5807

SLOS727 –DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure18.IRN,PGA = 24dB and Low Noise Mode Figure19.IRN,PGA = 24dB and Low Noise Mode Zoomed Figure20. IRN,PGA = 24dB and Medium Power Mode Figure21.IRN,PGA = 24dB and Medium Power Mode Zoomed Figure22. IRN,PGA = 24dB and Low Power Mode Figure23. IRN,PGA = 24dB and Low Power Mode Zoomed

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www.ti.com SLOS727 –DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) Figure24.ORN, PGA = 24dB and Low Noise Mode Figure25. ORN PGA=24dB and Med Power Mode Figure26. ORN, PGA = 24dB and Low Power Mode Figure27.IRN vs Frequency,PGA = 24dB and Low Noise Mode Figure28.ORN vs Frequency,PGA = 24dB and Low Noise Figure29.IRN vs Frequency,PGA = 24dB and Low NF Mode Mode Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLinks:VCA5807

SLOS727 –DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure30.ORN vs Frequency,PGA = 24dB and Low NF Figure31.TGC Noise Figure,LNA = 12dB and Mode Low Noise Mode Figure32.TGC Noise Figure,LNA = 18dB and Figure33.TGC Noise Figure,LNA = 24dB and Low Noise Mode Low Noise Mode Figure34.Noise Figurevs.Power Modes with400Ω Active Figure35.Noise Figurevs.Power Modes without Termination Termination

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www.ti.com SLOS727 –DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) Figure36.HD2 vs.Frequency,Vin = 500mVpp and Figure37.HD3 vs.Frequency,Vin = 500mVpp and Vout = -1dBFS Vout = -1dBFS Figure38.HD2 vs.Gain,LNA = 12dB and PGA = 24dB and Figure39.HD3 vs.Gain,LNA = 12dB and PGA = 24dB and Vout = -1dBFS Vout = -1dBFS Figure40.HD2 vs.Gain,LNA = 18dB and PGA = 24dB and Figure41.HD3 vs.Gain,LNA = 18dB and PGA = 24dB and Vout = -1dBFS Vout = -1dBFS Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17 ProductFolderLinks:VCA5807

−75 −70 −65 −60 5 10 100 1000 2000 PSMR vs SUPPLY FREQUENCY Supply frequency (kHz) PSMR (dBc) Vcntl = 0 Vcntl = 0.3 Vcntl = 0.6 Vcntl = 0.9 −80 −75 −70 −65 −60 −55 5 10 100 1000 2000 PSMR vs SUPPLY FREQUENCY Supply frequency (kHz) PSMR (dBc) Vcntl = 0 Vcntl = 0.3 Vcntl = 0.6 Vcntl = 0.9 VCA5807 SLOS727 –DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure42.HD2 vs.Gain,LNA = 24dB and PGA = 24dB and Figure43.HD3 vs.Gain,LNA = 24dB and PGA = 24dB and Vout = -1dBFS Vout = -1dBFS Figure44.IMD3, Fout1 = -7dBFS and Fout2 = -7dBFS Figure45.IMD3, Fout1 = -21dBFS and Fout2 = -21dBFS Figure46.AVDD Power Supply ModulationRatio,100mVpp Figure47.AVDD_5V Power Supply ModulationRatio, Supply Noise withDifferentFrequencies(TGC Mode) 100mVpp Supply Noise withDifferentFrequencies(TGC Mode)

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−70 −65 −60 −55 −50 5 10 100 500 Supply Frequency (kHz) PSMR (dBc) PSMR 1 CH PSMR 8 CH G000 −70 −65 −60 −55 −50 5 10 100 500 Supply Frequency (kHz) PSMR (dBc) PSMR 1 CH PSMR 8 CH G000 −90 −85 −80 −75 −70 −65 5 10 100 500 Supply Frequency (kHz) PSRR wrt supply tone (dB) PSRR 1 CH PSRR 8 CH G000 −45 −43 −41 −39 −37 −35 5 10 100 500 Supply Frequency (kHz) PSRR wrt supply tone (dB) PSRR 1 CH PSRR 8 CH G000 −90 −80 −70 −60 −50 −40 −30 −20 5 10 100 1000 2000 3V PSRR vs SUPPLY FREQUENCY Supply frequency (kHz) PSRR wrt supply tone (dB) Vcntl = 0 Vcntl = 0.3 Vcntl = 0.6 Vcntl = 0.9 −90 −80 −70 −60 −50 −40 −30 −20 5 10 100 1000 2000 5V PSRR vs SUPPLY FREQUENCY Supply frequency (kHz) PSRR wrt supply tone (dB) Vcntl = 0 Vcntl = 0.3 Vcntl = 0.6 Vcntl = 0.9 VCA5807 www.ti.com SLOS727 –DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) Figure48.AVDD Power Supply RejectionRatio,100mVpp Figure49.AVDD_5V Power Supply RejectionRatio, Supply Noise withDifferentFrequencies(TGC Mode) 100mVpp Supply Noise withDifferentFrequencies(TGC Mode) Figure50.AVDD Power Supply RejectionRatio,Vnoise=100 Figure51.AVDD_5V Power Supply RejectionRatio, mVpp, Freqnoise=5-500KHz (CW Mode) Vnoise=100 mVpp, Freqnoise=5-500KHz (CW Mode) Figure52.AVDD Power Supply ModulationRatio,Vnoise=100 Figure53.AVDD_5V Power Supply ModulationRatio, mVpp, Freqnoise=5.005-5.5MHz (CW Mode) Vnoise=100 mVpp, Freqnoise=5.005-5.5MHz (CW Mode) Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLinks:VCA5807

−10000.0 −8000.0 −6000.0 −4000.0 −2000.0 0.0 2000.0 4000.0 6000.0 8000.0 10000.0 Time (µs) Output Code Positive overload Negative overload Average −10000 −8000 −6000 −4000 −2000 2000 4000 6000 8000 10000 Time (µs) Output Code 47nF 15nF −1.2 −1.0 −0.8 −0.6 −0.4 −0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Time (µs) Input (V) −1.2 −1.0 −0.8 −0.6 −0.4 −0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.2 Time (µs) Input (V) 0.0 2000.0 4000.0 6000.0 8000.0 10000.0 12000.0 14000.0 16000.0 18000.0 20000.0 −0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Time (µs) Output Code Vcntl (V) Output Code Vcntl 0.0 2000.0 4000.0 6000.0 8000.0 10000.0 12000.0 14000.0 16000.0 18000.0 20000.0 −0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 Time (µs) Output Code Vcntl (V) Output Code Vcntl VCA5807 SLOS727 –DECEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Figure54.VCNTL Response Time,LNA = 18dB and Figure55.VCNTL Response Time,LNA = 18dB and PGA = 24dB PGA = 24dB Figure56.Pulse InversionAsymmetrical PositiveInput Figure57.Pulse InversionAsymmetrical NegativeInput Figure58.Pulse Inversion,Vin = 2Vpp, PRF = 1KHz, Figure59.Overload Recovery Response vs.INM capacitor, Vin = 50 mVpp/100 µVpp, Max GainGain = 21dB

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−2000 −1600 −1200 −800 −400 400 800 1200 1600 2000 1 1.5 2 2.5 3 3.5 4 4.5 5 Time (µs) Output Code 47nF 15nF VCA5807 www.ti.com SLOS727 –DECEMBER 2012 TYPICAL CHARACTERISTICS (continued) Figure60.Overload Recovery Response vs.INM Figure61. SignalChain Low Frequency Response withINM capacitor(Zoomed),Vin = 50 mVpp/100 µVpp, Max Gain Capacitor= 1 µF Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLinks:VCA5807

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0A7 A6 A5 A4 A3 A2 A1 A0 SEN SCLK SDATA RESET Data□Latched□On□Rising□Edge□of□SCLK Start□Sequence Start□Sequence End□Sequence End□Sequence T0384-01 VCA5807 SLOS727 –DECEMBER 2012 www.ti.com SerialPeripheralInterface(SPI)Operation RegisterWriteDescription Programming ofdifferentmodes can be done throughtheserialinterfaceformed by pinsSEN (serialinterface enable),SCLK (serialinterfaceclock),SDATA (serialinterfacedata)and RESET. Allthesepinshave a pull-down resistortoGND of20kΩ.Serialshiftofbitsintothedeviceisenabledwhen SEN islow.SerialdataSDATA is latchedat everyrisingedge of SCLK when SEN isactive(low).The serialdata isloadedintothe registerat every24thSCLK risingedge when SEN islow.Iftheword lengthexceeds a multipleof24 bits,theexcessbits areignored.Data can be loadedinmultipleof24-bitwords withina singleactiveSEN pulse(thereisan internal counterthatcountsgroupsof24 clocksafterthefallingedge ofSEN). The interfacecan work withtheSCLK frequencyfrom 20 MHz down tolow speeds (fewHertz)and even withnon-50% dutycycleSCLK. The datais dividedintotwo main portions:a registeraddress(8bits)and thedataitself(16bits),toloadon theaddressed register.When writingtoa registerwithunused bits,theseshouldbe setto0.Figure62 illustratesthisprocess. NOTE RESET must be keptas '1'more than100 ns.Afterresetting,>100 ns isrecommended beforewritingSPI registers. TypicallytheVCA5807 respondstonew registersettingsimmediatelyafter24 bits(8-bitaddressand 16-bitdata) arewrittentoVCA5807. Figure62. SerialInterfaceRegisterWriteTiming RegisterReadout Description The deviceincludesan optionwhere thecontentsoftheinternalregisterscan be readback.Thismay be useful as a diagnostictestto verifythe serialinterfacecommunicationbetween the externalcontrollerand the VCA. First,the <REGISTER READOUT ENABLE > bit(Reg0[1])needs to be setto '1'.Then user shouldinitiatea serialinterfacecyclespecifyingtheaddressoftheregister(A7-A0)whose contenthas tobe read.The databits are "don’tcare".The devicewilloutputthecontents(D15-D0)oftheselectedregisteron theSDOUT pin.The SDOUT has a typicaldelayt8 of20 nS fromthefallingedge oftheSCLK. Forlowerspeed SCLK, SDOUT can be latchedon therisingedge ofSCLK. For higherspeed SCLK, thatis,theSCLK periodlesserthan60nS, itwould be bettertolatchtheSDOUT atthenextfallingedge ofSCLK. The followingtimingdiagramshows thisoperation (thetimespecificationsfollowthe same informationprovided.In the readoutmode, usersstillcan access the <REGISTER_READOUT_ENABLE > through SDATA/SCLK/SEN. To enable serialregisterwrites,set the <REGISTER_READOUT_ENABLE > bitback to'0'.

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x x x x x x x x x x x x x x x xA7 A6 A5 A4 A3 A2 A1 A0 SEN SCLK SDATA SDOUT Start Sequence End Sequence D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 VCA5807 www.ti.com SLOS727 –DECEMBER 2012 Figure63. SerialInterfaceRegisterReadout Timing The VCA5807 SDOUT bufferis3-statedand willgetenabledonlywhen 01 isenabled.SDOUT pinsfrommultipleVCA5807s can be tiedtogetherwithoutany pull-upresistors.Levelshifter SN74AUP1T34 can be used toconvert3.3Vlogicto2.5V/1.8Vlogicsifneeded. SPI Timing Characteristics Minimum valuesacrossfulltemperaturerangetMIN = –40°C totMAX = 85°C, AVDD_5V = 5V,AVDD = 3.3V PARAMETER DESCRIPTION MIN TYP MAX UNIT t1 SCLK period 50 ns t2 SCLK hightime 20 ns t3 SCLK lowtime 20 ns t4 Data setuptime 5 ns t5 Data holdtime 5 ns t6 SEN falltoSCLK rise 8 ns t7 Time between lastSCLK risingedge toSEN risingedge 8 ns t8 SDOUT Delay 12 20 28 ns Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLinks:VCA5807

SLOS727 –DECEMBER 2012 www.ti.com VCA RegisterMap A resetprocessisrequiredattheVCA5807 initializationstage.Initializationcan be done inone oftwo ways: 1. Througha hardwarereset,by applyinga positivepulseintheRESET pin 2. Through a softwarereset,usingtheserialinterface,by settingtheSOFTWARE_RESET bittohigh.Setting thisbitinitializesthe internalregistersto the respectivedefaultvalues(allzeros)and then self-resetsthe SOFTWARE_RESET bittolow.Inthiscase,theRESET pincan staylow(inactive). Afterreset,allVCA registersare set to ‘0’, that is,defaultsetting.During registerprogramming, all reserved/unlistedregisterbitsneed to be setas ‘0’.Registersettingsare maintainedwhen the VCA5807 isin eitherpartialpower down mode orcompletepower down mode. Table1.VCA RegisterMap ADDRESS ADDRESS Default FUNCTION DESCRIPTION(DEC) (HEX) Value 0[0] 0x0[0] 0 SOFTWARE_RESET 0:Normal operation 1:Resetthedevice 0[1] 0[1] 0 REGISTER_READOUT_ENABLE 0:Disablereadout 1:EnablereadoutofregisteratSDOUT Pin 51[0] 0x33[0] 0 RESERVED 0 51[3:1] 0x33[3:1] 0 LPF_PROGRAMMABILITY 000:15MHz, 010:20MHz, 011:30MHz, 100:10MHz 51[4] 0x33[4] 0 PGA_INTEGRATOR_DISABLE 0:Enable (PGA_HPF_DISABLE) 1:DisablesoffsetintegratorforPGA. Pleasesee explanation forthePGA integratorfunctioninPROGRAMMABLE GAIN AMPLIFIER (PGA) and PGA OUTPUT CONFIGURATION section 51[7:5] 0x33[7:5] 0 PGA_CLAMP_LEVEL Low Noisemode: 53[11:10]=00 000:–2 dBFS 010:0 dBFS 1XX: Clamp isdisabled Low power/Medium Power mode; 53[11:10]=01/10 100:–2 dBFS 110:0 dBFS 0XX: clamp isdisabled Note:At000 setting,PGA outputHD3 willbe worsen by 3 dB at–2 dBFS ADC input.Innormaloperation,clamp functioncan be setas 000 inthelownoisemode. The maximum PGA outputlevelcan exceed 2Vpp withtheclamp circuitenabled. Note:inthelowpower and medium power modes, PGA_CLAMP isdisabledforsavingpower if51[7]=0.Please see PGA OUTPUT CONFIGURATION . 51[13] 0x33[13] 0 PGA_GAIN_CONTROL 0:24dB; 1:30dB. 52[4:0] 0x34[4:0] 0 ACTIVE_TERMINATION_ See Table3 Reg 52[5]shouldbe setas '1'toaccessthesebits INDIVIDUAL_RESISTOR_CNTL 52[5] 0x34[5] 0 ACTIVE_TERMINATION_ 0:Disable; INDIVIDUAL_RESISTOR_ENABLE 1:Enableinternalactiveterminationindividualresistorcontrol 52[7:6] 0x34[7:6] 0 PRESET_ACTIVE_ TERMINATIONS 00:50ohm, 01:100ohm, 10:200ohm, 11:400ohm. (Note:thedevicewilladjustresistormapping (52[4:0]) automatically.50ohm activeterminationisNOT supportedin 12dB LNA setting.Instead,'00'representshighimpedance mode when LNA gainis12dB) 52[8] 0x34[8] 0 ACTIVE TERMINATION ENABLE 0:Disable; 1:Enableactivetermination

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www.ti.com SLOS727 –DECEMBER 2012 Table1.VCA RegisterMap (continued) ADDRESS ADDRESS Default FUNCTION DESCRIPTION(DEC) (HEX) Value 52[10:9] 0x34[10:9]0 LNA_INPUT_CLAMP_SETTING 00:Autosetting 01:1.5Vpp 10:1.15Vpp 11:0.6Vpp 52[11] 0x34[11] 0 RESERVED Setto0 52[12] 0x34[12] 0 LNA_INTEGRATOR_DISABLE 0:Enable; (LNA_HPF_DISABLE) 1:DisableoffsetintegratorforLNA. Pleasesee theexplanation forthisfunctioninthefollowingsection 52[14:13] 0x34[14:1 0 LNA_GAIN 00:18dB; 3] 01:24dB; 10:12dB; 11:Reserved 52[15] 0x34[15] 0 LNA_INDIVIDUAL_CH_CNTL 0:Disable; 1:EnableLNA individualchannelcontrol.See Register57 for details 53[7:0] 0x35[7:0] 0 PDN_CH <7:0> 0:Normal operation; 1:Powers down correspondingchannels.Bit7→CH8, Bit6→CH7 … Bit0→CH1. PDN_CH willshutdown whichever blocksareactivedependingon TGC mode orCW mode 53[8] 0x35[8] 0 RESERVED Setto0 53[9] 0x35[9] 0 LOW_NF 0:Normal operation 1:Enablelownoisefiguremode forhighimpedance probes 53[11:10] 0x35[11:1 0 POWER_MODES 00:Low noisemode; 0] 01:Low power mode. At30dB PGA, totalchaingainmay slightlychange.See typicalcharacteristics 10:Medium power mode. At30dB PGA, totalchaingainmay slightlychange.See typicalcharacteristics 11:Reserved Note:inthelowpower and medium power modes, PGA_CLAMP isdisabledforsavingpower if51[7]=0. 53[12] 0x35[12] 0 PDN_VCAT_PGA 0:Normal operation; 1:Power down VCAT (voltage-controlled-attenuator)and PGA 53[13] 0x35[13] 0 PDN_LNA 0:Normal operation; 1:Power down LNA only 53[14] 0x35[14] 0 VCA_PARTIAL_PDN 0:Normal operation; 1:Power down LNA, VCAT, and PGA partially(fastwake response) 53[15] 0x35[15] 0 VCA_COMPLETE_PDN 0:Normal operation; 1:Power down LNA, VCAT, and PGA completely(slowwake response).Thisbitcan overwrite53[14]. 54[4:0] 0x36[4:0] 0 CW_SUM_AMP_GAIN_CNTL SelectFeedback resistorfortheCW Amplifieras perTable3 below 54[5] 0x36[5] 0 CW_16X_CLK_SEL 0:Acceptdifferentialclock; 1:AcceptCMOS clock 54[6] 0x36[6] 0 CW_1X_CLK_SEL 0:AcceptCMOS clock; 1:Acceptdifferentialclock 54[7] 0x36[7] 0 RESERVED Setto0 54[8] 0x36[8] 0 CW_TGC_SEL 0:TGC Mode; 1 :CW Mode Note :VCAT and PGA arestillworkingintheCW mode. They shouldbe powered down separatelythrough53[12] 54[9] 0x36[9] 0 CW_SUM_AMP_ENABLE 0:EnableCW summing amplifier; 1:DisableCW summing amplifier.Note:54[9]isonlyeffective intheCW mode. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLinks:VCA5807

SLOS727 –DECEMBER 2012 www.ti.com Table1.VCA RegisterMap (continued) ADDRESS ADDRESS Default FUNCTION DESCRIPTION(DEC) (HEX) Value 54[11:10] 0x36[11:1 0 CW_CLK_MODE_SEL 00:16X mode; 0] 01:8X mode; 10:4X mode; 11:1X mode; Note:0x3B[10]=0. 55[3:0] 0x37[3:0] 0 CH1_CW_MIXER_PHASE 55[7:4] 0x37[7:4] 0 CH2_CW_MIXER_PHASE 55[11:8] 0x37[11:8]0 CH3_CW_MIXER_PHASE 55[15:12] 0x37[15:1 0 CH4_CW_MIXER_PHASE 0000→1111,16 differentphase delays,see Table6 56[3:0] 0x38[3:0] 0 CH5_CW_MIXER_PHASE 56[7:4] 0x38[7:4] 0 CH6_CW_MIXER_PHASE 56[11:8] 0x38[11:8]0 CH7_CW_MIXER_PHASE 56[15:12] 0x38[15:1 0 CH8_CW_MIXER_PHASE 57[1:0] 0x39[1:0] 0 CH1_LNA_GAIN_CNTL 00:18dB; CH2_LNA_GAIN_CNTL 11:Reserved REG52[15] shouldbe setas '1' 57[5:4] 0x39[5:4] 0 CH3_LNA_GAIN_CNTL 00:18dB; 01:24dB;57[7:6] 0x39[7:6] 0 CH4_LNA_GAIN_CNTL 10:12dB; 57[9:8] 0x39[9:8] 0 CH5_LNA_GAIN_CNTL 11:Reserved REG52[15] shouldbe setas '1'57[11:10] 0x39[11:1 0 CH6_LNA_GAIN_CNTL 57[13:12] 0x39[13:1 0 CH7_LNA_GAIN_CNTL 57[15:14] 0x39[15:1 0 CH8_LNA_GAIN_CNTL 59[3:2] 0x3B[3:2] 0 HPF_LNA 00:100KHz; 01:50KHz; 10:200KHz; 11:150KHz Note:theabove frequenciesisbased on 0.015uFcapacitorsat INMx. 59[6:4] 0x3B[6:4] 0 DIG_TGC_ATT_GAIN 000:0dB attenuation; 001:6dB attenuation; N: ~N ×6dB attenuationwhen 59[7]= 1 59[7] 0x3B[7] 0 DIG_TGC_ATT 0:DisabledigitalTGC attenuator; 1:EnabledigitalTGC attenuator 59[8] 0x3B[8] 0 CW_SUM_AMP_PDN 0:Power down CW summing amplifier; 1:Normal operation.Note:59[8]isonlyeffectiveinTGC test mode. 59[9] 0x3B[9] 0 PGA_TEST_MODE 0:Normal CW operation; 1:PGA outputsappearattheCW outputs 59[10] 0x3B[10] 0 CW_32X_CLK_MODE_ENABLE 0:CW clockmode isdeterminedby 0x36[11:10]; 1:EnableCW 32X mode

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www.ti.com SLOS727 –DECEMBER 2012 VCA RegisterDescription LNA InputImpedances Configuration(ActiveTerminationProgrammability) DifferentLNA inputimpedances can be configuredthroughthe register52[4:0].By enablingand disablingthe feedbackresistorsbetween LNA outputsand ACTx pins,LNA inputimpedance isadjustableaccordingly.Table2 describestherelationshipbetween LNA gainand 52[4:0]settings.The inputimpedance settingsarethesame for bothTGC and CW paths. The VCA5807 alsohas 4 presetactiveterminationimpedances as describedin52[7:6].An internaldecoderis used toselectappropriateresistorscorrespondingtodifferentLNA gain. Table2.Register52[4:0]Description 52[4:0]/0x34[4:0] FUNCTION

00000 No feedbackresistorenabled

00001 Enables450 Ω feedbackresistor

00010 Enables900 Ω feedbackresistor

00100 Enables1800 Ω feedbackresistor

01000 Enables3600 Ω feedbackresistor

10000 Enables4500 Ω feedbackresistor

Table3.Register52[4:0]vs LNA InputImpedances 52[4:0]/0x34[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 LNA:12dB HighZ 150 Ω 300 Ω 100 Ω 600 Ω 120 Ω 200 Ω 86 Ω LNA:18dB HighZ 90 Ω 180 Ω 60 Ω 360 Ω 72 Ω 120 Ω 51 Ω LNA:24dB HighZ 50 Ω 100 Ω 33 Ω 200 Ω 40 Ω 66.67Ω 29 Ω 52[4:0]/0x34[4:0] 01000 01001 01010 01011 01100 01101 01110 01111 LNA:12dB 1200 Ω 133 Ω 240 Ω 92 Ω 400 Ω 109 Ω 171 Ω 80 Ω LNA:18dB 720 Ω 80 Ω 144 Ω 55 Ω 240 Ω 65 Ω 103 Ω 48 Ω LNA:24dB 400 Ω 44 Ω 80 Ω 31 Ω 133 Ω 36 Ω 57 Ω 27 Ω 52[4:0]/0x34[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 LNA:12dB 1500 Ω 136 Ω 250 Ω 94 Ω 429 Ω 111 Ω 176 Ω 81 Ω LNA:18dB 900 Ω 82 Ω 150 Ω 56 Ω 257 Ω 67 Ω 106 Ω 49 Ω LNA:24dB 500 Ω 45 Ω 83 Ω 31 Ω 143 Ω 37 Ω 59 Ω 27 Ω 52[4:0]/0x34[4:0] 11000 11001 11010 11011 11100 11101 11110 11111 LNA:12dB 667 Ω 122 Ω 207 Ω 87 Ω 316 Ω 102 Ω 154 Ω 76 Ω LNA:18dB 400 Ω 73 Ω 124 Ω 52 Ω 189 Ω 61 Ω 92 Ω 46 Ω LNA:24dB 222 Ω 41 Ω 69 Ω 29 Ω 105 Ω 34 Ω 51 Ω 25 Ω Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLinks:VCA5807

1 λ16 VCA5807 SLOS727 –DECEMBER 2012 www.ti.com Programmable Gain forCW Summing Amplifier Differentgaincan be configuredforthe CW summing amplifierthroughthe register54[4:0].By enablingand disablingthe feedback resistorsbetween the summing amplifierinputsand outputs,the gain is adjustable accordinglytomaximizethedynamicrangeofCW path.Table4 describestherelationshipbetween thesumming amplifiergainand 54[4:0]settings. Table4.Register54[4:0]Description 54[4:0]/0x36[4:0] FUNCTION

00000 No feedbackresistor

00001 Enables250 Ω feedbackresistor

00010 Enables250 Ω feedbackresistor

00100 Enables500 Ω feedbackresistor

01000 Enables1000 Ω feedbackresistor

10000 Enables2000 Ω feedbackresistor

Table5.Register54[4:0]vs CW Summing AmplifierGain 54[4:0]/0x36[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 54[4:0]/0x36[4:0] 01000 01001 01010 01011 01100 01101 01110 01111 54[4:0]/0x36[4:0] 10000 10001 10010 10011 10100 10101 10110 10111 54[4:0]/0x36[4:0] 11000 11001 11010 11011 11100 11101 11110 11111 Programmable Phase Delay forCW Mixer AccurateCW beamformingisachievedthroughadjustingthephase delayofeach channel.IntheVCA5807, 16 differentphase delayscan be appliedto each LNA output;and itmeets the standardrequirementof typical ultrasoundbeamformer,thatis, beamformer resolution.Table 4 describesthe relationshipbetween the phase delaysand theregister55 and 56 settings. Table6.CW MixerPhase Delay vs RegisterSettings CHX_CW_MIXER_PHASE 0000 0001 0010 0011 0100 0101 0110 0111 PHASE SHIFT 0 22.5° 45° 67.5° 90° 112.5° 135° 157.5° CHX_CW_MIXER_PHASE 1000 1001 1010 1011 1100 1101 1110 1111 PHASE SHIFT 180° 202.5° 225° 247.5° 270° 292.5° 315° 337.5°

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24, 30dB 3rd LP Filter 10, 15, 20, 30 MHz Generator CW Mixer Summing Amplifier/ Filter 1X CLK (Syc) 1X CLK LNA OUT CW I/Q Vout VCA5807 1 of 8 Channels Differential Outputs Reference Differential TGC Vcntl 16X1 Multiplexer VCA5807 www.ti.com SLOS727 –DECEMBER 2012 THEORY OF OPERATION VCA5807 OVERVIEW The VCA5807 isan integratedVoltageControlledAmplifier(VCA) solutionspecificallydesignedforultrasound systemsinwhichhighperformanceand smallsizearerequired.The VCA5807 integratesa completetime-gain- control(TGC) imagingpathand a continuouswave Doppler(CWD) path.Italsoenablesuserstoselectone of variouspower/noisecombinationstooptimizesystem performance.The VCA5807 containseightchannels;each channelsincludesa Low-NoiseAmplifier(LNA),a VoltageControlledAttenuator(VCAT),a Programmable Gain Amplifier(PGA),a Low-passFilter(LPF),and a CW mixer. Inaddition,multiplefeaturesintheVCA5807 aresuitableforultrasoundapplications,such as activetermination, individualchannel control,fastpower up/down response,programmable clamp voltagecontrol,fastand consistentoverload recovery,ands o on. Therefore,the VCA5807 brings premium image qualityto ultra–portable,handheldsystems alltheway up tohigh-endultrasoundsystems.Inaddition,theVCA5807 can supportsonarapplications,consideringitsexcellentlow frequency(<100 KHz) response.Itssimplifiedfunction blockdiagramislistedinFigure64. Figure64. FunctionalBlock Diagram LOW-NOISE AMPLIFIER (LNA) In many high-gainsystems,a low noise amplifieris criticalto achieveoverallperformance.Using a new proprietaryarchitecture,theLNA intheVCA5807 deliversexceptionallow-noiseperformance,whileoperatingon a verylow quiescentcurrentcompared toCMOS-based architectureswithsimilarnoiseperformance.The LNA performssingle-endedinputtodifferentialoutputvoltageconversion.Itisconfigurablefora programmable gain of24/18/12dBand itsinput-referrednoiseisonly0.63/0.70/0.9nV/√Hz respectively.Programmable gainsettings resultina flexiblelinearinputrange up to 1Vpp, realizinghighsignalhandlingcapabilitydemanded by new transducertechnologies.Largerinputsignalcan be acceptedby theLNA; however thesignalcan be distorted sinceitexceeds theLNA ’s linearoperationregion.Combining thelow noiseand highinputrange,a wide input dynamic range isachievedconsequentlyforsupportingthe high demands from variousultrasoundimaging modes. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLinks:VCA5807

SLOS727 –DECEMBER 2012 www.ti.com The LNA inputisinternallybiasedatapproximately+2.4V;thesignalsourceshouldbe ac-coupledtotheLNA inputby an adequately-sizedcapacitor,thatis,≥ 0.1µF. To achieve low DC offsetdrift,the VCA5807 incorporatesa DC offsetcorrectioncircuitforeach amplifierstage.To improve the overloadrecovery,an integratorcircuitis used to extractthe DC component of the LNA outputand then fed back to the LNA ’s complementaryinputforDC offsetcorrection.ThisDC offsetcorrectioncircuithas a high-passresponseand can be treatedas a high-passfilter.The effectivecornerfrequencyisdeterminedby thecapacitorC BYPASS connected atINM. Withlargercapacitors,thecornerfrequencyislower.For stableoperationatthehighestHP filercut-off frequency,a ≥15nF capacitorcan be selected.Thiscornerfrequencyscalesalmostlinearlywiththevalueofthe C BYPASS . For example, 15nF givesa cornerfrequencyof approximately100 kHz, while47nF can give an effectivecornerfrequencyof33 KHz. Iflow frequencyoperationisdesired,theDC offsetcorrectioncircuitcan alsobe disabled/enabledthroughregister52[12].A largecapacitorlike1 µF can be used forsettinglow corner frequency(<2 KHz) oftheLNA DC offsetcorrectioncircuit.Figure61 shows thefrequencyresponsesforlow frequencyapplications. The VCA5807 can be terminatedpassivelyor actively.Activeterminationispreferredinultrasoundapplication forreducingreflectionfrom mismatches and achievingbetteraxialresolutionwithoutdegradingnoisefiguretoo much. Activeterminationvaluescan be presetto50,100,200,400Ω;othervaluesalsocan be programmed by users throughregister52[4:0].A feedback capacitoris requiredbetween ACTx and the signalsource as Figure65 shows.On theactiveterminationpath,a clampingcircuitisalsoused tocreatea low impedance path when overloadsignalisseen by theVCA5807. The clamp circuitlimitslargeinputsignalsattheLNA inputsand improves the overloadrecoveryperformanceof the VCA5807. The clamp levelcan be set to 350mV PP , 600mV PP , 1.15VPP automaticallydepending on the LNA gain settingswhen register52[10:9]=0.Other clamp voltages,such as 1.15VPP ,0.6VPP ,and 1.5VPP ,are alsoachievableby settingregister52[10:9].Thisclamping circuitisalsodesignedto obtaingood pulseinversionperformanceand reduce the impactfrom asymmetric inputs.Pleasenotethattheclamp settingsmay change duringLNA gainswitching.Thus theclamp settlingtime has tobe consideredwhen adjustingLNA gain,especiallywhen overloadsignalsexceed theclampingvoltage. Figure65. VCA5807 LNA withDC OffsetCorrectionCircuit VOLTAGE-CONTROLLED ATTENUATOR The voltage-controlledattenuatoris designed to have a linear-in-dBattenuationcharacteristic;thatis,the averagegainlossindB (seeFigure2) isconstantforeach equalincrementofthecontrolvoltage(VCNTL) as shown inFigure66.A differentialcontrolstructureisused toreducecommon mode noise.A simplifiedattenuator structureisshown inthefollowingFigure66 and Figure67. The attenuatorisessentiallya variablevoltagedividerthatconsistsoftheseriesinputresistor(RS) and seven shuntFETs placedinparalleland controlledby sequentiallyactivatedclippingamplifiers(A1 throughA7).VCNTL isthe effectivedifferencebetween VCNTLP and VCNTLM. Each clippingamplifiercan be understoodas a specializedvoltagecomparator with a softtransfercharacteristicand well-controlledoutputlimitvoltage. ReferencevoltagesV1 throughV7 areequallyspaced overthe0V to1.5V controlvoltagerange.As thecontrol voltageincreasesthroughthe inputrange of each clippingamplifier,the amplifieroutputrisesfrom a voltage

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SW1 SW2 SW3 SW4 SW5 SW6 SW7 RS Control Input VB Q2 Q3 Q4 Q5 Q6 Q7 VCNTL A1 A1 A1 A1 A1 A1 Attenuator Output C - C Clipping Amplifiers1 8 A1 - A7 Attenuator Stages Attenuator Input VCA5807 www.ti.com SLOS727 –DECEMBER 2012 where theFET isnearlyOFF toVHIGH where theFET iscompletelyON. As each FET approachesitsON state and the controlvoltagecontinuesto rise,the nextclippingamplifier/FETcombinationtakesover forthe next portionof the piecewise-linearattenuationcharacteristic.Thus, low controlvoltageshave most of the FETs turnedOFF, producingminimum signalattenuation.Similarly,highcontrolvoltagesturntheFETs ON, leadingto maximum signalattenuation.Therefore,each FET actstodecreasetheshuntresistanceofthevoltagedivider formedby Rs and theparallelFET network. Additionally,a digitallycontrolledTGC mode isimplementedtoachievebetterphase-noiseperformanceinthe VCA5807. The attenuatorcan be controlleddigitallyinsteadoftheanalogcontrolvoltageVCNTL .Thismode can be setby theregisterbit59[7].The variablevoltagedividerisimplementedas a fixedseriesresistanceand FET as theshuntresistance.Each FET can be turnedON by connectingtheswitchesSW1-7. Turningon each ofthe switchescan giveapproximately6dB of attenuation.Thiscan be controlledby the registerbits59[6:4].This digitalcontrolfeaturecan eliminatethenoisefromtheVCNTL circuitand ensurethebetterSNR and phase noise fortheTGC path. Figure66. SimplifiedVoltageControlledAttenuator(AnalogStructure) Figure67. SimplifiedVoltageControlledAttenuator(DigitalStructure) The voltagecontrolledattenuator’s noisefollowsa monotonicrelationshiptotheattenuationcoefficient.At higher attenuation,theinput-referrednoiseishigherand vice-versa.The attenuator’s noiseisthenamplifiedby thePGA and becomes thenoiseflooratADC input.Intheattenuator’s highattenuationoperatingrange,thatis,VCNTL is high,theattenuator’s inputnoisemay exceed theLNA ’s outputnoise;theattenuatorthenbecomes thedominant noisesource forthe followingPGA stage and ADC. Therefore,the attenuator’s noiseshouldbe minimized compared totheLNA outputnoise.The VCA5807 ’s attenuatorisdesignedforachievingverylow noiseeven at high attenuation(low channel gain)and realizingbetterSNR in near field.Please see PGA OUTPUT CONFIGURATION .The inputreferrednoisefordifferentattenuationsislistedinthebelowtable: Table7.Voltage-Controlled-Attenuatornoisevs Attenuation Attenuation(dB) AttenuatorInputReferrednoise(nV/rtHz) –40 10.5 –36 10 –30 9 –24 8.5 Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLinks:VCA5807

SLOS727 –DECEMBER 2012 www.ti.com Table7.Voltage-Controlled-Attenuatornoisevs Attenuation(continued) Attenuation(dB) AttenuatorInputReferrednoise(nV/rtHz) –18 6 –12 4 –6 3 0 2 PROGRAMMABLE GAIN AMPLIFIER (PGA) Afterthevoltagecontrolledattenuator,a programmablegainamplifiercan be configuredas 24dB or30dB witha constantinputreferrednoise of 1.75nV/rtHz.The PGA structureconsistsof a differentialvoltage-to-current converterwithprogrammable gain,currentclamping(biascontrol)circuits,a transimpedanceamplifierwitha programmablelow-passfilter,and a DC offsetcorrectioncircuit.Itssimplifiedblockdiagramisshown below: Figure68. SimplifiedBlock Diagram ofPGA Low inputnoiseisalwayspreferredina PGA and itsnoisecontributionshouldnotdegrade theADC SNR too much aftertheattenuator.Attheminimum attenuation(usedforsmallinputsignals),theLNA noisedominates;at the maximum attenuation(largeinputsignals),the PGA and ADC noisedominates.Thus 24dB gainof PGA achievesbetterSNR as longas theamplifiedsignalscan exceed thenoiseflooroftheADC. The PGA currentclampingcircuitcan be enabled(register51)toimprovetheoverloadrecoveryperformanceof theVCA. Ifwe measure thestandarddeviationoftheoutputjustafteroverload,for0.5V VCNTL ,itisabout3.2 LSBs innormalcase,thatistheoutputisstableinabout1 clockcycleafteroverload.With thecurrentclamp circuitdisabled,the valueapproaches 4 LSBs meaning a longertime durationbeforethe outputstabilizes; however,withthe currentclamp circuitenabled,therewillbe degradationinHD3 forPGA outputlevels> - 2dBFS. For example,fora –2dBFS outputlevel,theHD3 degradesby approximately3dB. Inordertomaximize theoutputdynamic range,themaximum PGA outputlevelcan exceed 2Vpp (0 dBFS linearoutputrange)with theclamp circuit.Thus ADCs withexcellentoverloadrecoveryperformanceshouldbe selected. NOTE Inthelow power and medium power modes, PGA_CLAMP isdisabledforsavingpower if 51[7]=0 The VCA5807 integratesan anti-aliasingfilterin the form of a programmable low-passfilter(LPF) in the transimpedanceamplifier.The LPF is designed as a differential,active,3rd order filterwith Butterworth characteristicsand a typical18dB per octave roll-off.Programmable throughthe serialinterface,the –1dB frequencycornercan be settoone of10MHz, 15MHz, 20MHz, and 30MHz. The filterbandwidthissetforall channelssimultaneously. A selectableDC offsetcorrectioncircuitisimplementedinthePGA as well.Thiscorrectioncircuitissimilartothe one used in the LNA. Itextractsthe DC component of the PGA outputsand feeds back to the PGA ’s complimentaryinputsforDC offsetcorrection.ThisDC offsetcorrectioncircuitalsohas a high-passresponse witha cut-offfrequencyof80KHz. If<80KHz operationisneeded,theDC offsetcorrectioncircuitcan be disabled throughtheregister0x33[4].

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1×fcw CLK N×fcw CLK VCA5807 www.ti.com SLOS727 –DECEMBER 2012 CONTINUOUS-WAVE (CW) BEAMFORMER Continuous-waveDopplerisa key functioninmid-endtohigh-endultrasoundsystems.Compared totheTGC mode, the CW path needs to handle high dynamic range along withstrictphase noise performance.CW beamforming is oftenimplemented in analog domain due to the mentioned strictrequirements.Multiple beamformingmethods are beingimplementedinultrasoundsystems,includingpassivedelayline,activemixer, and passivemixer.Among allof them, the passivemixer approach achievesoptimizedpower and noise.It satisfiesthe CW processingrequirements,such as wide dynamic range,low phase noise,accurategainand phase matching. A simplifiedCW pathblockdiagramand an In-phaseor Quadrature(I/Q)channelblockdiagramare illustrated below respectively.Each CW channelincludesa LNA, a voltage-to-currentconverter,a switch-basedmixer,a sharedsumming amplifierwitha low-passfilter,and clockingcircuits.Allblocksincludewell-matchedin-phase and quadraturechannelsto achievegood image frequencyrejectionas wellas beamforming accuracy.As a result,theimage rejectionratiofroman I/Qchannelisbetterthan-46dBcwhichisdesiredinultrasoundsystems. Figure69. SimplifiedBlock Diagram ofCW Path Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLinks:VCA5807

/c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 /c40 /c41 0 d 0 0 0 0 d 0 d Vi(t) sin t t t 4 1 1LO(t) sin t sin 3 t sin 5 t ...3 5 2Vo(t) cos t cos 2 t t ... /c61 /c119 /c43 /c119 /c43 /c106 /c43 /c119 /c233 /c249/c61 /c119 /c43 /c119 /c43 /c119 /c234 /c250/c112 /c235 /c251 /c233 /c249/c61 /c119 /c43 /c102 /c45 /c119 /c45 /c119 /c43 /c102/c235 /c251/c112 f Vi(t) Vo (t) LO(t) 500Ω 500Ω 500Ω 500Ω 500Ω 500Ω I/V Sum Amp Cext Cext Rint/Rext Rint/Rext CW_OUTM CW_OUTP Mixer Clock 1 Mixer Clock 2 Mixer Clock 8 LNA1 IN1 INM1 LNA2 IN2 INM2 LNA8 IN8 INM8 ACT1 ACT2 ACT8 CW I or Q CHANNEL Structure INPUT1 INPUT2 INPUT8 CW_AMPINP CW_AMPINM 10Ω 10Ω VCA5807 SLOS727 –DECEMBER 2012 www.ti.com Note:the10~15Ω resistorsatCW_AMPINM/P aredue tointernalIC routingand can createslightattenuation. Figure70. A Complete In-phaseor QuadraturePhase Channel The CW mixerintheVCA5807 ispassiveand switchbased;passivemixeradds lessnoisethanactivemixers.It achievesgood performanceatlow power.The below illustrationand equationsdescribetheprinciplesofmixer operation,where Vi(t),Vo(t)and LO(t)areinput,outputand localoscillator(LO)signalsfora mixerrespectively. The LO(t)issquare-wavebased and includesodd harmoniccomponents as thebelowequationexpresses: Figure71. Block Diagram ofMixerOperation (1) From theabove equations,the3rdand 5thorderharmonicsfromtheLO can interfacewiththe3rdand 5thorder harmonicsignalsinthe Vi(t);or the noisearound the 3rd and 5th orderharmonicsinthe Vi(t).Therefore,the mixer’s performanceisdegraded.Inordertoeliminatethissideeffectdue tothesquare-wavedemodulation,a proprietaryharmonicsuppressioncircuitisimplementedintheVCA5807. The 3rdand 5thharmoniccomponents from the LO can be suppressed by over 12dB. Thus the LNA outputnoise around the 3rd and 5th order harmonicbands willnotbe down-convertedtobase band.Hence,betternoisefigureisachieved.The conversion lossofthemixerisabout-4dB whichisderivedfrom:

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/c91 /c93 /c91 /c93 /c40 /c41 /c40 /c41 0 d 0 d 0 0 d n 1Vi(t) sin t t sin t 22.5 t16 4 1 4LO(t) sin t sin t 22.5 16 2Vo(t) cos t t /c233 /c249 /c230 /c246/c61 /c119 /c43 /c43 /c119 /c61 /c119 /c43 /c176 /c43 /c119/c234 /c250 /c231 /c247/c234 /c250 /c232 /c248/c235 /c251 /c233 /c249 /c230 /c246/c61 /c119 /c43 /c61 /c119 /c43 /c176 /c234 /c250 /c231 /c247/c112 /c112 /c234 /c250 /c232 /c248/c235 /c251 /c61 /c119 /c43 /c119 /c112 f f f 220 log /c112 VCA5807 www.ti.com SLOS727 –DECEMBER 2012 (2) The mixed currentoutputsofthe8 channelsare summed togetherinternally.An internallow noiseoperational amplifierisused toconvertthesummed currenttoa voltageoutput.The internalsumming amplifierisdesigned toaccomplishlow power consumption,low noise,and ease ofuse.CW outputsfrommultipleVCA5807s can be furthercombined on system board to implementa CW beamformer withmore than 8 channels.More detail informationcan be foundinFigure92. Multipleclockoptionsare supportedintheVCA5807 CW path.Two CW clockinputsare required:N ×ƒcw clock and 1 × ƒcw clock,where ƒcw istheCW transmittingfrequencyand N couldbe 32,16,8,4,or1.Users have the flexibilitytoselectthemost convenientsystem clocksolutionfortheVCA5807. Inthe32× ƒcw,16 × ƒcw and 8× ƒcw modes, the 3rd and 5th harmonicsuppressionfeaturecan be supported.Thus, the 16 × ƒcw and 8 × ƒcw modes achievesbetterperformancethanthe4 × ƒcw and 1 × ƒcw modes. 16 × ƒcw and 32 × ƒcw Mode The 16 × ƒcw mode achievesthebestphase accuracycompared toothermodes. Itisthedefaultmode forCW operation.Inthismode, 16 × ƒcw and 1 × ƒcw clocksarerequired.16×ƒcw generatesLO signalswith16 accurate phases.MultipleVCA5807s can be synchronizedby the1 × ƒcw ,thatis,LO signalsinmultipleVCAs can have thesame startingphase.The phase noisespec iscriticalonlyfor16X clock.1X clockisforsynchronizationonly and doesn’trequirelow phase noise.See thephase noiserequirementinCW ClockSelection.Inaddition,the 1X clockcan be eithera continuewave witha frequencyofƒcw or a singlepulsewitha pulsewidthT>(1/16x ƒcw ). The toplevelclockdistributiondiagramisshown inFigure72.Each mixer'sclockisdistributedthrougha 16 × 8 cross-pointswitch.The inputsof the cross-pointswitchare 16 differentphases of the 1x clock.Itis recommended toaligntherisingedges ofthe1 x ƒcw and 16 x ƒcw clocks. The cross-pointswitchdistributestheclockswithappropriatephase delaytoeach mixer.For example,VI(t)isa receivedsignalwitha delayof1/16T ,a delayedLO (t)shouldbe appliedtothemixerinordertocompensate for the 1/16 T delay.Thus a 22.5⁰ delayedclock,thatis,2π/16 , isselectedforthischannel.The mathematic calculationisexpressedinthefollowingequations: (3) Vo(t)representsthedemodulatedDopplersignalofeach channel.When theDopplersignalsfrom N channels aresummed, thesignaltonoiseratioimproves. Comparing tothe16x ƒcw configuration,an extra2X clockdividerisadded inthe32x ƒcw configuration.Same CW performanceisachievedinbothconfigurations. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLinks:VCA5807

Phase 337.5º 16-to-8 Cross Point Switch 1X Clock Phase 0º 1X Clock Phase 22.5º 1X Clock Phase 315º 1X Clock Phase 292.5º Mixer 1 1X Clock Mixer 2 1X Clock Mixer 3 1X Clock Mixer 6 1X Clock Mixer 7 1X Clock Mixer 8 1X Clock Fin 16X Clock SPI D Q Fin 1X Clock INV

16 Phase Generator

SLOS727 –DECEMBER 2012 www.ti.com Figure72. Block Diagram of1x and 16x CW Clock Distribution Figure73. 1x and 16x CW Clock Timing 8 × ƒcw and 4 × ƒcw Modes 8 × ƒcw and 4 × ƒcw modes arealternativemodes when higherfrequencyclocksolution(thatis,16 × ƒcw clock)is notavailableinsystem.The blockdiagramofthesetwo modes isshown below.

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LNA2~8 In-phase CLK Quadrature CLK I/V I/V Summed In-Phase Summed Quadrature delayed in in in delayed in in in 2 2 1I (t) I cos Q sin I t16 16 16 2 2 1Q (t) Q cos I sin Q t16 16 16 /c230 /c246/c112 /c112/c230 /c246 /c230 /c246/c61 /c43 /c61 /c43 /c231 /c247/c231 /c247 /c231 /c247 /c232 /c248 /c232 /c248 /c232 /c248 /c230 /c246/c112 /c112/c230 /c246 /c230 /c246/c61 /c45 /c61 /c43 /c231 /c247/c231 /c247 /c231 /c247 /c232 /c248 /c232 /c248 /c232 /c248 f f VCA5807 www.ti.com SLOS727 –DECEMBER 2012 Good phase accuracyand matchingarealsomaintained.Quadatureclockgeneratorisused tocreatein-phase and quadratureclockswithexact90° phase difference.The onlydifferencebetween 8 × ƒcw and 4 × ƒcw modes istheaccessibilityofthe3rdand 5thharmonicsuppressionfilter.Inthe8 × ƒcw mode, thesuppressionfiltercan be supported.In both modes, 1/16 T phase delay resolutionis achieved by weightingthe in-phaseand quadraturepaths correspondingly.For example, ifa delay of 1/16 T or 22.5° is targeted,the weighting coefficientsshouldfollowthebelowequations,assumingIinand Q inaresin(ω0t)and cos(ω0t)respectively: (4) Therefore,afterI/Q mixers,phase delay in the receivedsignalsis compensated. Mixers'outputsfrom all channelsarealignedand added linearlytoimprovethesignaltonoiseratio.Itispreferredtohave the4 × ƒcw or 8 × ƒcw and 1 × ƒcw clocksalignedbothattherisingedge. Figure74. 8 X ƒcw and 4 X ƒcw Block Diagram Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLinks:VCA5807

1 T16

SLOS727 –DECEMBER 2012 www.ti.com Figure75. 8 x ƒcw and 4 x ƒcw Timing Diagram 1 × ƒcw Mode The 1x ƒcw mode requiresin-phaseand quadratureclockswithlow phase noisespecifications.The phase delayresolutionisalsoachievedby weightingthein-phaseand quadraturesignalsas describedinthe8 × ƒcw and 4 × ƒcw modes.

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(a)□INP (b)□INM (c) ACT CM CM LNA1 Weight Weight Weight Weight LNA2~8 In-phase CLK Quadrature CLK I/V I/V Summed In-Phase Summed Quadrature Syncronized I/Q CLOCKs VCA5807 www.ti.com SLOS727 –DECEMBER 2012 Figure76. Block Diagram of1 x ƒcw mode EQUIVALENT CIRCUITS Figure77. EquivalentCircuitsofLNA inputs Figure78. EquivalentCircuitsofVCNTLP/M Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLinks:VCA5807

(a)□CW_OUTP/M (b)□CW_AMPINP/M VCA5807 SLOS727 –DECEMBER 2012 www.ti.com Figure79. CW 1X and 16X Clocks Figure80. EquivalentCircuitsofCW Summing AmplifierInputsand Outputs

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PGA_OUTP2 PGA_OUTM2 CW_IP_AMPINP CW_IP_AMPINM CW_IP_OUTM CW_IP_OUTP VCA5807 CLOCK INPUTS VCA5807 DIGITAL INPUTS CLKM_16X CLKP_16X CLKM_1X CLKP_1X 0.1μF 0.1μF 0.1μF 0.1μF SCLK SDATA RESET SEN SOUT PDN_FAST PDN_GLOBAL AVSS AVSS AVSS OTHER VCA5807 OUTPUT OTHER VCA5807 OUTPUT OTHER VCA5807 OUTPUT DNCs TO SUMMING AMP CAC CCW CCW CAC CAC CAC RSUM CVCNTL 470pF CVCNTL 470pF REXT (optional) REXT (optional) RSUM RSUM RSUM CW_QP_AMPINP CW_QP_AMPINM CW_QP_OUTM CW_QP_OUTP OTHER VCA5807 OUTPUT TO SUMMING AMP CAC CCW CCW CAC CAC CAC RSUM REXT (optional) REXT (optional) RSUM RSUM RSUM Clock termination depends on clock types PECL, or CMOS 5VA AVDD_5V AVDD 3.3VA 10μF 1μF 1μF 1μF 1μF 1μF 1μF 1μF 1μF >1μF >1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 0.1μF 15nF 15nF 15nF 15nF 15nF 15nF 15nF 15nF 10μF 0.1μF N*0.1 Fμ CM_BYP VHIGH VCNTLP IN VCNTLP VCNTLM VREF_IN RVCNTL 200Ω RVCNTL 200Ω VCNTLM IN PGA_OUTP3 PGA_OUTP5 PGA_OUTP1 PGA_OUTP6 PGA_OUTP7 PGA_OUTP8 PGA_OUTP4 PGA_OUTM3 PGA_OUTM5 PGA_OUTM1 PGA_OUTM6 PGA_OUTM7 PGA_OUTM8 PGA_OUTM4 VCA5807 www.ti.com SLOS727 –DECEMBER 2012

APPLICATION INFORMATION

0.1 F/c109

RPGA _OUTP PGA _OUTM VCA5807 OUTPUTS R R R OUTPUT High Speed 12~14 Bit ADCs ADS529x INP INM 0.1 F 2 pF 0.1 F PGA_OUTP PGA_OUTM VCA5807 OUTPUTS VCA5807 SLOS727 –DECEMBER 2012 www.ti.com Note:The optionalR-C filter(10Ω and 2 pF)acrosstheADC inputsistoabsorbtheglitchescaused by theopening and closingofthesamplingcapacitors.See thecorrespondingADC datasheets. Figure82. TypicalApplicationCircuitbetween VCA5807 and ADC Note:R ≥ 500 Ω tomeet theVCA Minimum loadresistanceof1 KΩ. Figure83. TypicalApplicationCircuitbetween VCA5807 and OperationalAmplifier A typicalapplicationcircuitdiagramislistedabove.The configurationforeach blockisdiscussedbelow. LNA CONFIGURATION LNA InputCoupling and Decoupling The LNA closed-looparchitectureisinternallycompensated formaximum stabilitywithouttheneed ofexternal compensationcomponents.The LNA inputsare biasedat 2.4V and AC couplingisrequired.A typicalinput configurationisshown inFigure84.C IN istheinputAC couplingcapacitor.C ACT isa partoftheactivetermination feedback path.Even ifthe activeterminationis not used, the C ACT is requiredforthe clamp functionality. Recommended valuesforC ACT ≥ 1µF and C IN are ≥ 0.1µF. A pairof clampingdiodesiscommonly placed between the T/R switchand the LNA input.Schottkydiodeswithsuitableforwarddrop voltage(thatis,the BAT754/54 series,the BAS40 series,the MMBD7000 series,or similar)can be considereddependingon the transducerecho amplitude.

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total LNAnoise s LNAnoiseLNA _ Noise V R I/c61 /c43 /c180 LNAx INPx INMx ACTx INPUT C ACT C IN C BYPSS CLAMP DC Offset Correction Optional Diodes VCA5807 www.ti.com SLOS727 –DECEMBER 2012 Figure84. LNA InputConfigurations Thisarchitectureminimizesany loadingofthesignalsourcethatmay otherwiseleadtoa frequency-dependent voltagedivider.The closed-loopdesignyieldsverylow offsetsand offsetdrift.C BYPASS (≥0.015µF) isused toset the high-passfiltercut-offfrequencyand decouplethe complimentaryinput.Itscut-offfrequencyisinversely proportionalto the C BYPASS value.The HPF cut-offfrequencycan be adjustedthroughthe register59[3:2]as Table8 lists.Low frequencysignalsatT/R switchoutput,such as signalswithslowringing,can be filteredout.In addition,theHPF can minimizesystem noisefrom DC-DC converters,pulserepetitionfrequency(PRF) trigger, and frame clock.Most ultrasoundsystems’signalprocessingunitincludesdigitalhigh-passfiltersor band-pass filters(BPFs) inFPGAs or ASICs. Furthernoisesuppressioncan be achievedintheseblocks.Iflow frequency signaldetectionisdesiredinsome applications,theLNA HPF can be disabled. Table8.LNA HPF Settings(CBYPASS = 15 nF) Reg59[3:2](0x3B[3:2]) Frequency 00 100 KHz 01 50 KHz 10 200 KHz 11 150 KHz CM_BYP and VHIGH pins,which generateinternalreferencevoltages,need to be decoupled with ≥1uF capacitors.Biggerbypassingcapacitors(>2.2uF)may be beneficialiflowfrequencynoiseexistsinsystem. LNA Noise Contribution The noisespec iscriticalforLNA and itdeterminesthe dynamic range of entiresystem.The LNA of the VCA5807 achieveslow power and an exceptionallylow-noisevoltageof0.63nV/√Hz, and a low currentnoiseof 2.7pA/√Hz. Typicalultrasonictransducer’s impedance Rs variesfrom tensof ohms to severalhundreds of ohms. Voltage noise is the dominant noise in most cases; however, the LNA currentnoise flowingthroughthe source impedance (Rs)generatesadditionalvoltagenoise. (5) Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLinks:VCA5807

(b) Active Termination S0499-01 LNARs (a)□No Termination (c)□Passive Termination LNARs Rf LNARs Rt VCA5807 SLOS727 –DECEMBER 2012 www.ti.com The VCA5807 achieveslow noisefigure(NF) overa wide range ofsourceresistancesas shown inFigure31, Figure32,and Figure33. Inaddition,a low noisefiguremode has been implementedby optimizingthecurrentnoiseand voltagenoise contribution.When high impedance transducersappear,the VCA5807's noise figurecan be improved by enablingthelow noisefiguremode (register0x35[9]).Figure34 shows theadvantagesofthelow noisefigure mode. ActiveTermination In ultrasoundapplications,signalreflectionexistsdue to long cablesbetween transducerand system.The reflectionresultsinextraringingadded to echo signalsinpulsed-wave(PW) mode. Since the axialresolution depends on echo signallength,such ringingeffectcan degrade the axialresolution.Hence, eitherpassive terminationor activetermination,is preferredifgood axialresolutionis desired.Figure85 shows three terminationconfigurations: Figure85. TerminationConfigurations Under theno terminationconfiguration,theinputimpedance oftheVCA5807 isabout6KΩ (8K//20pF)at1 MHz. PassiveterminationrequiresexternalterminationresistorRt,whichcontributestoadditionalthermalnoise. The LNA supportsactiveterminationwithprogrammablevalues,as shown inFigure86 .

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/c61 /c110/c43 f IN LNA RZ A1 2 /c61 /c110/c43 f S0500-01 LNAx ACTx INPx INMx Input 4500Ω 3600Ω 1800Ω 900Ω 450Ω VCA5807 www.ti.com SLOS727 –DECEMBER 2012 Figure86. ActiveTerminationImplementation The VCA5807 has fourpre-settings50,100,200 and 400Ω which are configurablethroughtheregisters.Other terminationvaluescan be realizedby settingtheterminationswitchesshown inFigure86.Register[52]isused to enable these switches.The inputimpedance of the LNA under the activeterminationconfiguration approximatelyfollows: (6) Table 2 liststhe LNA R IN under differentLNA gains.System designerscan achievefinetuningfordifferent probes. The equivalentinputimpedance isgivenby Equation7 where R IN (8K)and C IN (20pF)are theinputresistance and capacitanceoftheLNA. (7) Therefore,the ZIN isfrequencydependent and itdecreasesas frequencyincreasesshown inFigure9. Since 2MHz~10MHz isthemost commonly used frequencyrange inmedicalultrasound,thisrolling-offeffectdoesn’t impactsystem performancegreatly.Activeterminationcan be appliedtobothCW and TGC modes. Sinceeach ultrasoundsystem includesmultipletransducerswith differentimpedances, the flexibilityof impedance configurationisa greatplus. Figure31,Figure32,and Figure33 shows theNF underdifferentterminationconfigurations.Itindicatesthatno terminationachievesthe bestnoisefigure;activeterminationadds lessnoisethan passivetermination.Thus terminationtopologyshouldbe carefullyselectedbased on each use scenarioinultrasound. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLinks:VCA5807

SLOS727 –DECEMBER 2012 www.ti.com LNA Gain Switch Response The LNA gainisprogrammablethroughSPI.The gainswitchingtimedepends on theSPI speed as wellas the LNA gainresponsetime.Duringtheswitching,glitchesmightoccurand theycan appearas artifactsinimages. LNA gainswitchingina singleimaginglinemay not be preferred,althoughdigitalsignalprocessingmightbe used hereforglitchsuppression. NOTE The clamp settingsmay change duringLNA gainswitching.The clamp settlingtimeneeds tobe consideredwhen adjustingLNA gaindynamically,especiallywhen overloadsignals exceed theclampingvoltage. VOLTAGE-CONTROLLED-ATTENUATOR The attenuatorin the VCA5807 is controlledby a pairof differentialcontrolinputs,the VCNTLM/P pins.The differentialcontrolvoltagespans from 0V to1.5V.Thiscontrolvoltagevariestheattenuationoftheattenuator based on itslinear-in-dBcharacteristic.Itsmaximum attenuation(minimum channelgain)appears at VCNTLP - VCNTLM = 1.5V,and minimum attenuation(maximum channelgain)occursatVCNTLP -VCNTLM = 0.The typicalgain rangeis40dB and remainsconstant,independentofthePGA setting. When onlysingle-endedVCNTL signalisavailable,this1.5Vpp signalcan be appliedon theVCNTLP pinwiththe VCNTLM pinconnectedto ground.As the below figuresshow, TGC gaincurveisinverselyproportionalto the VCNTLP -VCNTLM .

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(a) Single-Ended Input at VCNTLP (b) Differential Inputs at V and VCNTLP CNTLM TGC Gain V = 0VCNTLM VCNTLP 1.5V XdB X+40dB TGC Gain VCNTLM VCNTLP XdB X+40dB 1.5V 0.75V VCA5807 www.ti.com SLOS727 –DECEMBER 2012 Figure87. VCNTLP and VCNTLM Configurations As discussedinthe theoryof operation,the attenuatorarchitectureuses seven attenuatorsegments thatare equallyspaced in orderto approximatethe linear-in-dBgain-controlslope.This approximationresultsin a monotonicslope;thegainrippleistypicallylessthan±0.5dB. The controlvoltageinput(VCNTLM/P pins)representsa high-impedanceinput.The VCNTLM/P pins of multiple VCA5807 devicescan be connected in parallelwithno significantloadingeffects.When the voltagelevel (VCNTLP -VCNTLM )isabove 1.5V orbelow 0V, theattenuatorcontinuestooperateatitsmaximum attenuationlevel orminimum attenuationlevelrespectively.Itisrecommended tolimitthevoltagefrom-0.3Vto2V. When the VCA5807 operatesin CW mode, the attenuatorstage remains connected to the LNA outputs. Therefore,itisrecommended topower down theVCAT and PGA usingcorrespondingregisterbits.Inthiscase, VCNTLP -VCNTLM voltagedoes notmatter. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLinks:VCA5807

SLOS727 –DECEMBER 2012 www.ti.com The VCA5807 gain-controlinputhas a –3dB bandwidthofapproximately800KHz. Thiswide bandwidth,although usefulinmany applications(thatis,fastVCNTL response),can alsoallowhigh-frequencynoisetomodulatethe gaincontrolinputand finallyaffectthe Dopplerperformance.In practice,thismodulationcan be avoidedby additionalexternalfiltering(RVCNTL and CV CNTL )atVCNTLM/P pinsas Table9 shows.However,theexternalfilter's cutofffrequencycannotbe kepttoolow as thisresultsinlow gainresponsetime.Withoutexternalfiltering,the gain controlresponse time istypicallylessthan 1 μs to settlewithin10% of the finalsignallevelof 1VPP (–6dBFS) outputas indicatedinFigure54 and Figure55. TypicalVCNTLM/P signalsare generatedby an 8bitto 12bit10MSPS digitalto analogconverter(DAC) and a differentialoperationamplifier.TI’s DACs, such as TLV5626 and DAC7821/11 (10MSPS/12bit),couldbe used to generateTGC controlwaveforms.Differentialamplifierswithoutputcommon mode voltagecontrol(thatis, THS4130 and OPA1632) can connecttheDAC totheVCNTLM/P pins.The bufferamplifiercan alsobe configured as an activefiltertosuppresslow frequencynoise.More informationcan be foundintheliteraturesSLOS318F and SBAA150. The VCNTL vs Gain curvescan be foundinFigure2.The below tablealsoshows theabsolute gainvs VCNTL atroom temperature,whichmay helpprogramDAC correspondingly. InPW Dopplerand colorDopplermodes, VCNTL noiseshouldbe minimizedtoachievethebestclose-inphase noiseand SNR. DigitalVCNTL featureisimplementedtoaddressthisneed intheVCA5807. InthedigitalVCNTL mode, no externalVCNTL isneeded. Table9.VCNTLP – VCNTLM vs Gain Under DifferentLNA and PGA Gain Settings(Low Noise Mode and Room Temperature) Gain (dB) Gain (dB) Gain (dB) Gain (dB) Gain (dB) Gain (dB)VCNTLP –VCNTLM LNA = 12 dB LNA = 18 dB LNA = 24 dB LNA = 12 dB LNA = 18 dB LNA = 24 dB(V) PGA = 24 dB PGA = 24 dB PGA = 24 dB PGA = 30 dB PGA = 30 dB PGA = 30 dB 0.3 27 33 39 32.8 38.8 44.8 0.5 20.2 26.2 32.2 26 32 38 0.7 13 19 25 18.8 24.8 30.8 1.0 2.2 8.2 14.2 8 14 20 PGA OUTPUT CONFIGURATION As illustratedinFigure68,thePGA currentclampingcircuitcan be enabled(register51)toimprovetheoverload recoveryperformanceoftheVCA. Ifwe measure thestandarddeviationoftheoutputjustafteroverload,for0.5V VCNTL ,itisabout3.2LSBs innormalcase,thatis,theoutputisstableinabout1 clockcycleafteroverload.With the currentclamp circuitdisabled,the valueapproaches 4 LSBs meaning a longertime durationbeforethe outputstabilizes;however,withthe currentclamp circuitenabled,therewillbe degradationinHD3 forPGA outputlevels> -2dBFS. For example,fora –2dBFS outputlevel,theHD3 degradesby approximately3dB. In ordertomaximize theoutputdynamic range,themaximum PGA outputlevelcan exceed 2Vpp (0 dBFS linear outputrange)withthe clamp circuit.Thus ADCs withexcellentoverloadrecoveryperformanceshould be selected.

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www.ti.com SLOS727 –DECEMBER 2012 NOTE Inthelow power and medium power modes, PGA_CLAMP isdisabledforsavingpower if 51[7]=0 Figure82 and Figure83 show thatthePGA outputscan be furtherprocessedby eitherhighspeed 12-14 Bit ADCs or operationalamplifiers.The selectionof ADCs or OPAMPs shallminimizeperformanceimpactof the VCA5807, thatis,selectingdeviceswithsignificantlowerinputnoisefloorcompared toVCA5807's outputnoise. TI'smulti-channelhigh-speedADCs, such as ADS5294 and ADS5292 and low noiseopamps OPA842 and THS4130, are suitablecandidates.Inportableapplications,lowerpower ADCs and OPAMPs may be selected. The impacton performancedegradationcan be predictedby comparingtheVCA5807 outputnoisetothetotal noiseofVCA5807 and itssubsequentdevice. The below figuresshow theSNR curveswhen VCA5807 issampled by ADS5294. Betterthan70dBFS SNR is achieved.Furtherimprovementisexpectedwhen a 16-bitADC, e.g.ADS5263, isused. Figure88.SNR vs Gain atPGA Low Noise Mode Figure89.SNR vs Gain atPGA Low Power Mode Figure90.SNR vs Gain vs Power Modes at24dB PGA LOW FREQUENCY SUPPORT The signalchainoftheVCA5807 can handlesignalfrequencylowerthan100 KHz, whichenablestheVCA5807 tobe used notonlyinmedicalultrasoundapplicationsbutalsoinsonarapplications.The PGA integratorhas to be turnedoffinordertoenablethelowfrequencysupport.Meanwhile,a largecapacitorlike1 µF can be used for settinglow cornerfrequencyof the LNA DC offsetcorrectioncircuitas shown in Figure65. VCA5807's low frequencyresponsecan be foundinFigure61. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 49 ProductFolderLinks:VCA5807

2 R C/c61 /c112f

SLOS727 –DECEMBER 2012 www.ti.com CW CONFIGURATION CW Summing Amplifier InordertosimplifyCW system design,a summing amplifierisimplementedintheVCA5807 tosum and convert 8-channelmixercurrentoutputsto a differentialvoltageoutput.Low noiseand low power are achievedinthe summing amplifierwhilemaintainingthefulldynamicrangerequiredinCW operation. Thissumming amplifierhas 5 internalgainadjustmentresistorswhich can provide32 differentgainsettings (register54[4:0],Figure86 and Table4).System designerscan easilyadjusttheCW pathgaindependingon signalstrengthand transducersensitivity.Forany othergainvalues,an externalresistoroptionissupported.The gainofthesummation amplifierisdeterminedby theratiobetween the500Ω resistorsafterLNA and theinternal orexternalresistornetworkR EXT/INT.Thus thematchingbetween theseresistorsplaysa more importantrolethan absoluteresistorvalues.Betterthan1% matchingisachievedon chip.Due toprocessvariation,theabsolute resistortolerancecouldbe higher.Ifexternalresistorsareused,thegainerrorbetween I/Qchannelsoramong multipleVCAs may increase.Itisrecommended touse internalresistorstosetthegaininordertoachievebetter gainmatching(acrosschannelsand multipleVCAs). With theexternalcapacitorC EXT ,thissumming amplifier has 1storderLPF responsetoremove highfrequencycomponents from themixers,such as 2f0±fd.Itscut-off frequencyisdeterminedby: (8) Note thatwhen differentgainisconfiguredthroughregister54[4:0],theLPF responsevariesas well.

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I/V□Sum Amp CW_AMPINP CW_OUTM CW_AMPINM CW_OUTP CEXT CEXT REXT REXT RINT RINT 2000Ω 2000Ω 1000Ω 1000Ω 500Ω 500Ω 250Ω 250Ω 250Ω 250Ω VCA5807 www.ti.com SLOS727 –DECEMBER 2012 Figure91. CW Summing AmplifierBlock Diagram MultipleVCA5807s are usuallyutilizedinparalleltoexpand CW beamformer channelcount.These VCA5807s ’ CW outputscan be summed and filteredexternallyfurtherto achievedesiredgain and filterresponse.AC couplingcapacitorsC AC arerequiredtoblockDC component oftheCW carriersignal.C AC can varyfrom1uF to 10s μF dependingon the desiredlow frequencyDopplersignalfrom slow bloodflow.MultipleVCA5807s ’I/Q outputscan be summed togetherwitha low noiseexternaldifferentialamplifiersbefore16/18-bitdifferential audioADCs. UltralownoisedifferentialprecisionamplifierOPA1632 and THS4130 can be considered. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 51 ProductFolderLinks:VCA5807

500 Ω I/V Sum Amp Cext Cext Rint/Rext Rint/Rext CW_OUTM CW_OUTP Ext Sum Amp LNA1 INM1 LNA2INM2 LNA8INM8 CW I or Q CHANNEL Structure INPUT1 INPUT2 INPUT8 VCA No.2 VCA No.3 VCA No.4 VCA No.1 CW_AMPINP CW_AMPINM Mixer 1 Clock Mixer 2 Clock Mixer 8 Clock ACT1 ACT2 ACT8 CAC RSUM INP1 INP2 INP8 500 Ω 500 Ω 500 Ω 500 Ω 500 Ω VCA5807 SLOS727 –DECEMBER 2012 www.ti.com An alternativecurrentsumming circuitis shown in Figure 93. However thiscircuitonly achieves good performancewhen a lowernoiseoperationalamplifierisavailablecompared totheVCA5807's internalsumming differentialamplifier. Figure92. CW circuitwithMultipleVCA5807s (Voltageoutputmode)

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CW_AMPINM CW_AMPINP ACT1 IN1 Mixer 1 Clock Mixer 1 Clock Mixer 1 Clock Dev No.2 Dev No.X Dev No.1 CM_BYP CW_AMPINM CW_AMPINP CM_BYP Prefer to use an ultra-low noise fully differential amplifier with high output driving current Ultra-low noise single-ended amplifiers is an option as well VCA5807 www.ti.com SLOS727 –DECEMBER 2012 Figure93. CW CircuitwithMultipleVCA5807s (Currentoutputmode) The CW I/Qchannelsarewellmatched internallytosuppressimage frequencycomponents inDopplerspectrum. Low tolerancecomponents and preciseoperationalamplifiersshouldbe used forachievinggood matchinginthe externalcircuitsas well. CW Clock Selection The VCA5807 can acceptdifferentialLVDS, LVPECL, and otherdifferentialclockinputsas wellas single-ended CMOS clock.An internallygeneratedVCM of2.5V isappliedtoCW clockinputs,thatis,CLKP_16X/ CLKM_16X and CLKP_1X/ CLKM_1X. Since this2.5V VCM isdifferentfrom the one used instandardLVDS or LVPECL clocks,AC couplingisrequiredbetween clockdriversand theVCA5807 CW clockinputs.When CMOS clockis used, CLKM_1X and CLKM_16X should be tiedto ground.Common clockconfigurationsare illustratedin Figure94.Appropriateterminationisrecommended toachievegood signalintegrity. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 53 ProductFolderLinks:VCA5807

(a) LVPECL Configuration (c) Transformer Based Configuration (d) CMOS Configuration (b) LVDS Configuration CMOS CLK Driver VCA CMOS CLK CMOS VCA CLOCKs CLOCK SOURCE 50 Ω

0.1 F μ

CLOCKs100 Ω LVDS 130 Ω LVPECL 83 Ω 3.3 V 3.3 V 130 Ω VCA5807 SLOS727 –DECEMBER 2012 www.ti.com Figure94. Clock Configurations The combinationof the clocknoiseand the CW path noisecan degrade the CW performance.The internal clockingcircuitisdesignedforachievingexcellentphase noiserequiredby CW operation.The phase noiseof theVCA5807 CW pathisbetterthan155dBc/Hz at1KHz offset.Consequentlythephase noiseofthemixerclock inputsneeds tobe betterthan155dBc/Hz. In the 16, 8, 4 × ƒcw operationsmodes, low phase noiseclockisrequiredfor16, 8, 4 × ƒcw clocks(thatis, CLKP_16X/ CLKM_16X pins)inordertomaintaingood CW phase noiseperformance.The 1 × ƒcw clock(thatis, CLKP_1X/ CLKM_1X pins)is only used to synchronizethe multipleVCA5807 chips and is not used for demodulation.Thus 1 ƒcw clock’s phase noiseisnota concern.Eithera continueclockwitha frequencyofƒcw or a singlepulsewitha width>1/(Nƒcw)can be used.

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www.ti.com SLOS727 –DECEMBER 2012 On the otherhand, inthe 1 × ƒcw operationmode, low phase noiseclocksare requiredforboth CLKP_16X/ CLKM_16X and CLKP_1X/ CLKM_1X pinssinceboth of them are used formixer demodulation.In general, higherslewrateclockhas lowerphase noise;thusclockswithhighamplitudeand fastslewratearepreferredin CW operation.IntheCMOS clockmode, 5V CMOS clockcan achievethehighestslewrate. Clockphase noisecan be improvedby a divideras longas thedivider’s phase noiseislowerthanthetarget phase noise.The phase noiseof a dividedclockcan be improvedapproximatelyby a factorof 20log10N dB where N isthedividingfactorof16,8,or4.Ifthetargetphase noiseofmixerLO clock1 × ƒcw is160dBc/Hz at 1KHz offcarrier,the 16 × ƒcw clockphase noiseshouldbe betterthan 160-20log1016 = 136dBc/Hz.TI’s jitter cleanersLMK048X /CDCM7005/CDCE72010 exceed thisrequirementand can be selectedfortheVCA5807. In the4X/1X modes, higherqualityinputclocksareexpectedtoachievethesame performancesinceN issmaller. Thus the16X mode isa preferredmode sinceitreducesthephase noiserequirementforsystemclockdesign.In addition,thephase delayaccuracyisspecifiedby theinternalclockdividerand distributioncircuit.Inthe16X operationmode, theCW operationrangeislimitedto8 MHz due tothe16X CLK. The maximum clockfrequency forthe16X CLK is128 MHz. Inthe8X, 4X, and 1X modes, higherCW signalfrequenciesup to15 MHz can be supportedwithsmalldegradationin performance,e.g.the phase noise is degraded by 9 dB at 15 MHz, compared to2 MHz. As thechannelnumber ina system increases,clockdistributionbecomes more complex.Itisnotpreferredto use one clockdriveroutputtodrivemultipleVCAs sincetheclockbuffer’s loadcapacitanceincreasesby a factor ofN. As a result,thefallingand risingtimeofa clocksignalisdegraded.A typicalclockarrangementformultiple VCA5807s isillustratedinFigure95.Each clockbufferoutputdrivesone VCA5807 inordertoachievethebest signalintegrityand fastestslew rate,thatis,betterphase noiseperformance.When clockphase noiseisnota concern,thaiis.the1 × ƒcw clockinthe32,16,8,4 × ƒcw operationmodes, one clockdriveroutputmay excite more than one VCA5807s. Nevertheless,specialconsiderationsshouldbe appliedinsuch a clockdistribution networkdesign.In typicalultrasoundsystems,itispreferredthatallclocksare generatedfrom a same clock source,such as 16 × ƒcw ,1 × ƒcw clocks,audioADC clocks,RF ADC clock,pulserepetitionfrequencysignal, frameclockand so on.By doingthis,interferencedue toclockasynchronizationcan be minimized Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 55 ProductFolderLinks:VCA5807

n×16×CW Freq LMK048K CDCE72010/ CDCM7005 CDCLVP1208 LMK0030x LMK01000 CDCLVP1208 LMK0030x LMK01000 16X CW CLK 1X CW CLK

8 Synchronized

SLOS727 –DECEMBER 2012 www.ti.com Figure95. CW Clock Distribution CW SupportingCircuits As a generalpracticeinCW circuitdesign,in-phaseand quadraturechannelsshouldbe strictlysymmetricalby usingwellmatched layoutand highaccuracycomponents. Insystems,additionalhigh-passwallfilters(20Hz to500Hz) and low-passaudiofilters(10KHz to100KHz) with multiplepolesareusuallyneeded.SinceCW Dopplersignalrangesfrom20Hz to20KHz, noiseunderthisrange iscritical.Consequentlylow noiseaudiooperationalamplifiersare suitableto buildtheseactivefiltersforCW post-processing,thatis,OPA1632, OPA2211, LME49990, LMH6629, orTHS4130 .More filterdesigntechniques designer.html The filteredaudioCW I/Qsignalsare sampled by audioADCs and processedby DSP or PC. AlthoughCW signalfrequencyisfrom 20 Hz to20 KHz, highersamplingrateADCs are stillpreferredforfurtherdecimation and SNR enhancement. Due to the largedynamic range of CW signals,high resolutionADCs (≥16bit)are required,such as ADS8413 (2MSPS/16it/92dBFSSNR) and ADS8472 (1MSPS/16bit/95dBFSSNR). ADCs for in-phaseand quadature-phasechannelsmust be strictlymatched,notonlyamplitudematchingbutalsophase matching,inorderto achievethe bestI/Qmatching,.In addition,the in-phaseand quadratureADC channels must be sampled simultaneously.

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www.ti.com SLOS727 –DECEMBER 2012 POWER MANAGEMENT Power/Performance Optimization The VCA5807 has optionsto adjustpower consumptionand meet differentnoiseperformances.Thisfeature would be usefulforportablesystems operatedby batterieswhen low power ismore desired.Please referto characteristicsinformationlistedinthetableofelectricalcharacteristicsas wellas thetypicalcharacteristicplots. Power Management Priority Power management playsa criticalroletoextendbatterylifeand ensurelongoperationtime.The VCA5807 has fastand flexiblepower down/up controlwhichcan maximizebatterylife.The VCA5807 can be powered down/up throughexternalpinsor internalregisters.The followingtableindicatestheaffectedcircuitblocksand priorities when the power management isinvoked.In the device,allthe power down controlsare logicallyORed to generatefinalpower down fordifferentblocks.Thus,thehigherprioritycontrolscan coverthelowerpriorityones. The VCA5807 registersettingsare maintainedwhen the VCA5807 isin eitherpartialpower down mode or completepower down mode. Table10.Power Management Priority Name Blocks Priority Pin PDN_GLOBAL All High Pin PDN_FAST LNA + VCAT+ PGA Medium Register VCA_PARTIAL_PDN LNA + VCAT+ PGA Low Register VCA_COMPLETE_PDN LNA + VCAT+ PGA Medium Register PDN_VCAT_PGA VCAT + PGA Lowest Register PDN_LNA LNA Lowest PartialPower-Up/Down Mode The partialpower up/down mode isalsocalledas fastpower up/down mode. Inthismode, most amplifiersinthe signalpatharepowered down, whiletheinternalreferencecircuitsremainactive. The partialpower down functionallowsthe VCA5807 to be wake up from a low-powerstatequickly.This configurationensures thatthe externalcapacitorsare dischargedslowly;thus a minimum wake-up time is needed as longas thechargeson thosecapacitorsarerestored.The VCA wake-up responseistypicallyabout2 μs or1% ofthepower down durationwhicheverislarger.The longestwake-up timedepends on thecapacitors connectedat INP and INM, as the wake-up time isthe time requiredto rechargethe caps to the desired operatingvoltages.For 0.1μF atINP and 15nF atINM can givea wake-up timeof2.5ms.For largercapacitors thistimewillbe longer.Thus, the VCA5807 wake-up timeismore dependent on the VCA wake-up time.The power-down timeisinstantaneous,lessthan1µs. Thisfastwake-up responseisdesiredforportableultrasoundapplicationsinwhich thepower savingiscritical. The pulserepetitionfrequencyofa ultrasoundsystem couldvaryfrom50KHz to500Hz, whiletheimagingdepth (thatis,the activeperiodfora receivepath)variesfrom 10 μs to hundreds of us.The power savingcan be significantwhen a system’s PRF islow.Insome cases,onlytheVCA would be powered down whiletheADC keeps runningnormallytoensureminimum impacttoFPGAs. Inthepartialpower-down mode, theVCA5807 typicallydissipatesonly12.5mW/ch, representinga >80% power reductioncompared tothenormaloperatingmode. Thismode can be setusingeitherpinPDN_FAST orregister bitVCA_PARTIAL_PDN. Complete Power-Down Mode To achievethelowestpower dissipationof0.7mW/CH, theVCA5807 can be placedintoa completepower-down mode. This mode is controlledthroughthe registersVCA_COMPLETE_PDN or PDN_GLOBAL pin.In the completepower-down mode, allcircuitsincludingreferencecircuitswithintheVCA5807 arepowered down; and the capacitorsconnectedto the VCA5807 are discharged.The wake-up timedepends on the timeneeded to rechargethesecapacitors.The wake-up timedepends on thetimethattheVCA5807 spends inshutdown mode. 0.1μF atINP and 15nF atINM can givea wake-up timecloseto2.5ms. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 57 ProductFolderLinks:VCA5807

500 Ω I/V□Sum Amp Cext Rint/Rext Rint/Rext CW_OUTM CW_OUTP LNA INP INM ACT INPUT CW_AMPINM CW_AMPINP Mixer Clock PGA_P PGA_M Cext 5 K 500 Ω S0504-01 VCA5807 SLOS727 –DECEMBER 2012 www.ti.com Power Saving inCW Mode Usuallyonlyhalfthenumber ofchannelsina system are activeintheCW mode. Thus theindividualchannel controlthroughVCA_PDN_CH <7:0> can power down unused channelsand save power consumptiongreatly. Under thedefaultregistersettingintheCW mode, thevoltagecontrolledattenuator,PGA, isstillactive.During the debug phase,both the PW and CW pathscan be runningsimultaneously.In realoperation,theseblocks need tobe powered down manually. TEST MODES When directprobingVCA outputsisnotfeasible,theVCA5807 has a testmode inwhichtheCH7 and CH8 PGA outputscan be broughttotheCW pins.By monitoringtheseCW pins,thefunctionalityofVCA operationcan be verified.The PGA outputsareconnectedtothevirtualgroundpinsofthesumming amplifier(CW_IP_AMPINM/P, CW_QP_AMPINM/P) through5KΩ resistors.The PGA outputscan be monitoredat the summing amplifier outputswhen theLPF capacitorsC EXT areremoved.Note thatthesignalsatthesumming amplifieroutputsare attenuateddue tothe5KΩ resistors.The attenuationcoefficientisR INT/EXT/5KΩ Ifuserswould liketocheck thePGA outputswithoutremovingCEXT, an alternativeway istomeasure thePGA outputsdirectlyattheCW_IP_AMPINM/P and CW_QP_AMPINM/P when theCW summing amplifierispowered down Some registersare relatedtothistestmode. PGA TestMode Enable:Reg59[9];BufferAmplifierPower Down Reg59[8];and BufferAmplifierGain ControlReg54[4:0].Based on thebufferamplifierconfiguration,theregisters can be setindifferentways: Configuration1: Inthisconfiguration,thetestoutputscan be monitoredatCW_AMPINP/M Reg59[9]=1;Testmode enabled Reg59[8]=0;Bufferamplifierpowered down Configuration2: Inthisconfiguration,thetestoutputscan be monitoredatCW_OUTP/M Reg59[9]=1;Testmode enabled Reg59[8]=1;Bufferamplifierpowered on Reg54[4:0]=10H;Internalfeedback2K resistorenabled.Differentvaluescan be used as well Figure96. VCA5807 PGA TestMode

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www.ti.com SLOS727 –DECEMBER 2012 POWER SUPPLY, GROUNDING AND BYPASSING Ina mixed-signalsystem design,power supplyand groundingdesignplaysa significantrole.Inmost cases,it shouldbe adequate to layout the printedcircuitboard (PCB) to use a singleground planeforthe VCA5807. Care shouldbe takenthatthisgroundplaneisproperlypartitionedbetween varioussectionswithinthesystem to minimizeinteractionsbetween analogand digitalcircuitry.Inaddition,opticalisolatorordigitalisolators,such as ISO7240,can separatetheanalogportionfromthedigitalportioncompletely.Consequentlytheypreventdigital noisetocontaminatetheanalogportion.Table10 liststherelatedcircuitblocksforeach power supply. Table11.Supply vs CircuitBlocks Power Supply Ground CircuitBlocks LNA, attenuator,PGA withclamp and BPF, referencecircuits,CWAVDD (3.3VA) AVSS summing amplifier,CW mixer, VCA SPI LNA, CW clockcircuits,referenceAVDD_5V (5VA) AVSS circuits Allbypassingand power suppliesfortheVCA5807 shouldbe referencedtotheircorrespondingground planes. Allsupplypinsshouldbe bypassed with0.1µF ceramicchipcapacitors(size0603 or smaller).In orderto minimizetheleadand traceinductance,thecapacitorsshouldbe locatedas closetothesupplypinsas possible. Where double-sidedcomponent mounting is allowed,these capacitorsare best placed directlyunder the package.Inaddition,largerbipolardecouplingcapacitors2.2µF to10µF,effectiveatlowerfrequencies)may also be used on themain supplypins.These components can be placedon thePCB inproximity(< 0.5inor 12.7 mm) totheVCA5807 itself. The VCA5807 has a number of referencesuppliesneeded to be bypassed,such CM_BYP, VHIGH, and VREF_IN. These pinsshouldbe bypassed withatleast1µF;highervaluecapacitorscan be used forbetterlow- frequencynoisesuppression.Forbestresults,choose low-inductanceceramicchipcapacitors(size0402,> 1µF) and placethem as closeas possibletothedevicepins. High-speedmixed signaldevicesaresensitivetovarioustypesofnoisecoupling.One primarysourceofnoiseis theswitchingnoisefrom theserializerand theoutputbuffer/drivers.For theVCA5807, carehas been takento ensure thatthe interactionbetween the analog and digitalsupplieswithinthe deviceiskept to a minimum amount. The extentof noisecoupledand transmittedfrom the digitaland analog sectionsdepends on the effectiveinductancesofeach ofthesupplyand ground connections.Smallereffectiveinductanceofthesupply and ground pinsleadstoimprovednoisesuppression.For thisreason,multiplepinsare used toconnecteach supplyand ground sets.Itisimportanttomaintainlow inductancepropertiesthroughoutthedesignofthePCB layoutby use ofproperplanesand layerthickness. BOARD LAYOUT Proper groundingand bypassing,shortlead length,and the use of ground and power-supplyplanes are particularlyimportantforhigh-frequencydesigns.Achievingoptimum performancewith a high-performance devicesuch as the VCA5807 requirescarefulattentionto the PCB layoutto minimizethe effectsof board parasiticsand optimizecomponent placement.A multilayerPCB usuallyensures best resultsand allows convenientcomponent placement. Inaddition,appropriatedelaymatchingshouldbe consideredfortheCW clockpath,especiallyinsystems with highchannelcount.For example,ifclockdelayishalfofthe16x clockperiod,a phase errorof22.5°C could exist.Thus thetimingdelaydifferenceamong channelscontributestothebeamformeraccuracy. To avoid noise couplingthrough supply pins,itisrecommended to keep sensitiveinputpins,such as INM, INP,ACT pins always from the AVDD 3.3V and AVDD 5V planes.For example, eitherthe tracesor viasconnected tothesepinsshould NOT be routedacross theAVDD 3.3V and AVDD 5V planes. Copyright© 2012,Texas InstrumentsIncorporated SubmitDocumentationFeedback 59 ProductFolderLinks:VCA5807

www.ti.com 11-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) VCA5807PZP Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 VCA5807 VCA5807PZP.B Active Production HTQFP (PZP) | 100 90 | JEDEC TRAY (5+1) Yes NIPDAU Level-3-260C-168 HR -40 to 85 VCA5807 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. TQFP - 1.2 mm max height TM PowerPAD PZP 100 PLASTIC QUAD FLATPACK14 x 14 mm Pkg Body, 0.5 mm pitch 16 x 16 mm Pkg Area 4224739/B

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Product Information

VCA5807 specifications and overview.

Summary

Fully Integrated, 8-Channel Voltage Controlled Amplifier for Ultrasound with Passive CW Mixer, 0.75 nV/rtHz, 99 mW/CH

Description

Fully Integrated, 8-Channel Voltage Controlled Amplifier for Ultrasound with Passive CW Mixer, 0.75 nV/rtHz, 99 mW/CH

Source title VCA5807 Datasheet(PDF) - Texas Instruments

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VCA5807

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Fully Integrated, 8-Channel Voltage Controlled Amplifier for Ultrasound datasheet

Document overview

Technical content

16 Phases

2 SubmitDocumentationFeedback Copyright© 2012,Texas InstrumentsIncorporated

100 PINS

DESCRIPTION

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86 SCLK Serialinterfaceclockinputwithan internalpull-downresistorof20kΩ

85 SDATA Serialinterfacedatainputwithan internalpull-downresistorof20kΩ

47 VCNTLP Positivedifferentialattenuationcontrolpin

ELECTRICAL CHARACTERISTICS

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180 Number of Occurances

50 Ohms

100 Ohms

200 Ohms

400 Ohms

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00000 No feedbackresistorenabled

00001 Enables450 Ω feedbackresistor

00010 Enables900 Ω feedbackresistor

00100 Enables1800 Ω feedbackresistor

01000 Enables3600 Ω feedbackresistor

10000 Enables4500 Ω feedbackresistor

00000 No feedbackresistor

00001 Enables250 Ω feedbackresistor

00010 Enables250 Ω feedbackresistor

00100 Enables500 Ω feedbackresistor

01000 Enables1000 Ω feedbackresistor

10000 Enables2000 Ω feedbackresistor

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16 Phase Generator

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1 T16

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APPLICATION INFORMATION

0.1 F/c109

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2 R C/c61 /c112f

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0.1 F μ

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8 Synchronized

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VCA5807 specifications and overview.

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