V850E2

V850E2 RENESAS | Alldatasheet

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32-bit Single-Chip Microcontroller R01DS0141ED0100 2013-05-24 Renesas Electronics www.renesas.com µPD70F3555 µPD70F3556 µPD70F3557 µPD70F3558 µPD70F3592 µPD70F4007 µPD70F4008 µPD70F4009 µPD70F4010 dfgdfg Data Sheet Cover

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(1) Precaution against ESD for semiconductors Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All text and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. (2) Handling of unused input pins for CMOS No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. (3) Status before initialization of MOS devices Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

6.1 Supply current of µPDF70F4007 / µPDF70F4008 / µPDF70F4009 / µPDF70F4010 36

6.2 Supply current of µPDF70F3555 / µPDF70F3556 / µPDF70F3557 / µPDF70F3558 38

1.1 Naming

1.1.1 Alternative function pins

Example: – TAUB0I0, TAUB1I5 – URTE0TX, URTE0RX, URTE1TX, URTE1RX – CSIG0SO, CSIG0SI, CSIG0SC, CSIG0RY

1.1.2 Power supply pins

Example: – E0VDDn, REG0VSS If not mentioned otherwise this document neglects suffixes for power supply pins with same functions that can be treated as equal. Peripheral Prefix Function name Suffix Short-cut of macro name Consecutive number for same peripheral modulea a) This is an option that can be omitted if meaning is obvious Peripheral Macro pin naming Consecutive number for same pin namesa Function Prefix Kind of supply Suffix Symbol Consecutive number for different functionsa a) This is an option that can be omitted if meaning is obvious VDD or VSS Consecutive number for different pins with same meaninga Table 1-1 Selection for Functions Function Explanation C Core supply REG Internal regulator supply OSC Oscillator supply F Flash module supply E Standard buffer supply (mainly 5V or up to 40Mhz) B Standard buffer supply (mainly 3.3V or beyond 40Mhz) A Analog module supply (e.g. ADC)

1.2 Pin Groups

1.3 General measurement conditions

1.3.1 AC characteristic measurement condition

Standard AC test condition is 70%/30% of the applied IO supply voltage (XmVDD) if not otherwise stated in the according AC timing specification of an interface. AC Test Condition: Ext. Capacitive Load Symbol Pin group supplied by Related pins / ports PgE0 E0VDD JP0, P0, _RESET, FLMD0, WAKE, VCPC0IN, VCPC1IN PgE1 E1VDD / E1VSS P1, P2, P3, P4 PgB0 B0VDD / B0VSS P21, P25, P27 PgOSC OSCVDD / OSCVSS X1, X2, XT1, XT2 PgA0 A0VDD / A0VSS P10, P11, ADCA0Im PgA1 A1VDD / A1VSS P12 xVSS xVDD .FBTVSFNFOU 7*) NJO 7*- NBY 7*) NJO 7*- NBY xVSS xVDD .FBTVSFNFOU 70) NJO 70- NBY 70) NJO 70- NBY DUT Load on test: CL= 50pF

Chapter 2 Absolute maximum ratings Chapter 2 Absolute maximum ratings

2.1 Supply voltages

Parameter Symbol Condition Ratings Unit System CVDD M2 products only -0.5 ~ 1.6 V System FVDD -0.5 ~ 6.0 V OSCVDD -0.5 ~ 6.0 V REG0VDD -0.5 ~ 6.0 V REG1VDD -0.5 ~ 6.0 V REG2VDD -0.5 ~ 6.0 V REG3VDD -0.5 ~ 6.0 V Ports E0VDD -0.5 ~ 6.0 V E1VDD -0.5 ~ 6.0 V Port B0VDD -0.5 ~ 6.0 V ADCA0 A0VREFP -0.3 ~ A0VDD+0.3 -0.3~6.0 V ADCA0 A0VDD -0.5 ~ 6.0 V ADCA1 A1VDD -0.5 ~ 6.0 V A1VREFP -0.3 ~ A1VDD+0.3 -0.3~6.0 V Table 2-2 VSS Data Parameter Symbol Condition Ratings Unit System CVSS M2 products only -0.5 ~0.5 V System FVSS -0.5 ~0.5 V OSCVSS -0.5 ~0.5 V REG0VSS -0.5 ~0.5 V REG1VSS -0.5 ~0.5 V REG2VSS -0.5 ~0.5 V REG3VSS -0.5 ~0.5 V Ports E1VSS -0.5 ~0.5 V B0VSS -0.5 ~0.5 V ADC0 A0VSS -0.5 ~0.5 V A0VREFM -0.3 ~ A0VDD+0.3 -0.3~6.0 V ADC1 A1VSS -0.5 ~0.5 V A1VREFM -0.3 ~ A1VDD+0.3 -0.3~6.0 V

Chapter 2 Absolute maximum ratings

2.2 Port voltages

Table 2-3 Port Input voltage Parameter Pin Group Symbola a) The symbols reflect all supplies within the device series. Therefore not every symbol is available for each product. Condition Ratings Unit Input voltageb b) The characteristics of the alternative-function pins are the same as those of the port pins unless otherwise specified. PgE0 V I0 E0VDD≤5.5 -0.5 ~ E0VDD+0.5 V PgE1 V I1 E1VDD≤5.5 -0.5 ~ E1VDD+0.5 V PgB0 V I2 B0VDD≤5.5 -0.5 ~ B0VDD+0.5 V PgOSC V I5 OSCVDD≤5.5 -0.5 ~ OSCVDD+0.5 V PgA0 V I3 A0VDD+0.3 V PgA1 V I4 A1VDD+0.3 V

Chapter 2 Absolute maximum ratings

2.3 Port current

2.4 Capacitance

Table 2-4 High level port output current Parameter Pin Groupa a) The column reflects all supplies within the device series. Therefore not each pin group is available for each product. Symbol Condition Max. spec Unit High level output current PgE0 IOH 1 pin of PgE0 -10 mA Power supply of PgE0 -50 PgE1 1 pin of PgE1 -10 Power supply of PgE1 -150 PgA0 1 pin of PgA0 -10 Power supply of PgA0 -25 High level output current PgA1 IOH 1 pin of PgA1 -10 mA Power supply of PgA1 -25 High level output current PgB0 IOH 1 pin of PgB0 -10 mA Power supply of PgB0 -150 Table 2-5 Low level port output current Parameter Pin Groupa Symbol Condition Max. spec Unit Low level output current PgE0 IOL 1 pin of PgE0 10 mA Power supply of PgE0 50 PgE1 1 pin of PgE1 10 Power supply of PgE1 150 PgA0 1 pin of PgA0 10 Power supply of PgA0 25 Low level output current PgA1 IOL 1 pin of PgA1 10 mA Power supply of PgA1 25 Low level output current PgB0 IOL 1 pin of PgB0 10 mA Power supply of PgB0 100 a) The column reflects all supplies within the device series. Therefore not each pin group is available for each product. Parameter Symbol Condition Max. spec Unit Input capacitance C I f = 1 MHz 0V for non measurement pins 15 pF Input/Output capacitance C IO 15 pF Output capacitance C O 15 pF

Chapter 2 Absolute maximum ratings

2.5 Thermal characteristics

This section specifies the absolute maximum limitation of operating and storage temperature. The device’s functions are not guaranteed outside of the specified maximum temperature ratings. Table 2-6 Thermal characteristics Parameter Symbol Condition Ratings Unit Storage temperature T STG -65 ~150 °COperating ambient temperature Ta (A) grade products -40 ~85 (A1) grade products -40 ~110 (A2) grade products -40 ~125 Junction temperature T j -40 ~150

Chapter 3 Power supply specification Chapter 3 Power supply specification

3.1 Requirements for external power supply

The user has to ensure a low resistive connection of all VSS pins on the PCB. This specification denotes ground supply pins as:

• VSS = OSCVSS = REGnVSS = EnVSS = BnVSS = AnVSS = AnVREM = CVSS = 0V in the further text. With
• EnVSS = E1VSS
• BnVSS = B0VSS
• REGnVSS = REG0VSS = REG1VSS = REG2VSS = REG3VSS
• AnVSS = A0VSS = A1VSSAnVREFM = A0VREFM = A1VREFM The user has to ensure a low resistive connection of all VDD pins to the related power supply. This specification denotes power supply pins as:
• EnVDD, BnVDD, FVDD, REGnVDD, OSCVDDCVDD, AnVDD and AnVREFP . in the further text. With
• EnVDD = E0VDD = E1VDD
• BnVDD = B0VDD
• REGnVDD = REG0VDD = REG1VDD = REG2VDD = REG3VDD.
• AnVDD = A0VDD = A1VDD
• AnVREFP = A0VREFP = A1VREFP
• I/OVDD = AnVDD, EnVDD, B0VDD, FVDD, OSCVDD

3.2 Power area definitions

The device consists of the following power areas:

• AWO (Always On area)
• ISO0 (Isolated area 0)
• ISO1 (Isolated area 1) The table below lists the related core and port voltage supply of each power area:

Chapter 3 Power supply specification

3.3 Power supply groups

For each of the following power supply groups the same voltage must by supplied: Table 3-1 Power areas supply voltages Power Area Supply voltage Related pins AWO Core supply REG0VDD, REG0VSS, REG0C Port Supply E0VDD Other OSCVDD, OSCVSS FVDD0 ISO0 Core supply REG1VDD, REG1VSS, REG1C REG2VDD, REG2VSS, REG2C REG3VDD, REG3VSS, REG3C Port Supply E1VDD, E1VSS Other A0VREFP, A0VREFM A0VDD, A0VSS ISO1 Core supply REG1VDD, REG1VSS, REG1C REG2VDD, REG2VSS, REG2C REG3VDD, REG3VSS, REG3C CVDD, CVSS Port Supply B0VDD, B0VSS Other A1VDD, A1VSS A1VREFP, A1VREFM Table 3-2 Power supply groups Power supply group Related pins #1 REG0VDD, REG1VDD, FVDD, OSCVDD, E0VDD, E1VDD #2 B0VDD #3 M1 products: REG2VDD, REG3VDD M2 products: n.a. #4 M1 products: n.a. M2 products: CVDD #5 A0VDD, A0VREFP #6 A1VDD, A1VREFP #7 All VSS

Chapter 3 Power supply specification

3.4 Supply voltages

Parameter Symbol Condition Ratings Unit Min Typ Max System supply voltage FVDD VPOC - 5.5 V System supply voltage OSCVDD VPOC - 5.5 V System supply voltage REG0VDD REG0VDD = REG1VDD = REG2VDD = REG3VDD VPOC - 5.5 V System supply voltage REG1VDD VPOC - 5.5 V System supply voltage REG2VDD VPOC - 5.5 V System supply voltage REG3VDD VPOC - 5.5 V System supply voltage CVDD M2 products only 1.1 - 1.3 V System supply voltage slopes AIVS M2 products; REG1VDD = 3.0V to 5.5V -- 5 . 6 V / m s Port supply voltages E0VDD VPOC - 5.5 V Port supply voltages E1VDD VPOC - 5.5 V Port supply voltages B0VDD B0VDD ≤ power supply group #1 voltages VPOC - 5.5 V ADC supply voltages A0VDD 12bit resolution 4.5 - 5.5 V ADC supply voltages A0VDD 10bit resolution VPOC - 5.5 V ADC supply voltages A0VREFP A0VDD - A0VDD V ADC supply voltages A1VDD 12bit resolution 4.5 - 5.5 V ADC supply voltages 10bit resolution VPOC - 5.5 V ADC supply voltages A1VREFP A1VREFP-A1VREFM > A1VDD/2 A1VDD - A1VDD V

Chapter 3 Power supply specification

3.4.1 AWO Regulator characteristics

Table 3-4 AWO Regulator characteristics Parameter Symbol Condition Ratings Unit Min Typ Max Regulator Output voltage VRO 1.1 1.2 1.3 V System supply voltage slope RAVS 0V to 3.0V - - 1800 V/ms Capacitance on REG0C REG0C 3.29 4.7 6.11 µF Output voltage stabilization time TRAA After REG0VDD reaches 3.0V - - 1 ms After DeepStop mode - - 0.5 ms REG0VDD VPOC RAVS TRAA VROMINVRO REG0VDD VPOC to 5.5V TRAA VROMIN VRO DeepStop Release timing During power-up sequence After DeepStop mode

Chapter 3 Power supply specification

3.4.2 ISO0/ISO1 Regulator ch aracteristics (M1 products)

Table 3-5 ISO0/ISO1 regulator characteristics Note n=1-3

3.4.3 Amplifier characteristics (M2 products)

Parameter Symbol Condition Ratings Unit Min Typ Max Output voltage VROI 1.1 1.2 1.3 V Capacitance on REGnC REGnC 3.29 4.7 6.11 µF Voltage slope RIVS 0V to 5.5V - - 5600 V/s Output voltage stabilization time TRAI After REGnVDD reaches 3.0V - - 1 ms After DeepStop mode - - 0.5 ms REGnVDD 3.0V RIVS TRAI VROIMINVROI During power-up sequence REGnVDD VPOC to 5.5V TRAI VROIMIN VROI DeepStop Release timing After DeepStop mode Parameter Symbol Condition Ratings Unit Min Typ Max System supply voltage REG1VDD VPOC 5.5 V Capacitance on CVDD CVDDC For each CVDD a 3.29 4.7 6.11 µF Voltage slope AIVS 3.0V to 5.5V - - 5.6 V/ms PTCTL1 stabilization time TRAI After REG1VDD reaches 3.0V - - 1 ms After DeepStop mode - - 0.5 ms PTCTL1 output current IPTCTL - - 1.55 mA

Chapter 3 Power supply specification a) Required when using an external power transistor such as 2SD1584 (base connected to PTCTL1) REG1VDD 3.0V AIVS TRAI PTCTL1 REG1VDD VPOC to 5.5V TRAI PTCTL1 DeepStop Release timing During power-up sequence After DeepStop mode

Chapter 3 Power supply specification

3.4.4 POC characteristics

Table 3-6 POC characteristics

3.4.5 Voltage Comparator characteristics

Table 3-7 VCMP characteristics Note VDD: REG0VDD Parameter Symbol Condition Ratings Unit Min Typ Max Detection voltage VPOC 2.8 2.9 3.0 V Voltage slope 1 PVS1 0.18 - 1800 V/ms Voltage slope 2 PVS2 0.0018 - 1800 V/ms Response time 1 tPTHD From detect voltage to release of reset signal. Voltage slope = PVS1, PVS2 --2 m s Response time 2 tPD From detect voltage to occurence of reset signal Voltage slope = PVS2 --2 m s VDD minimum width tPW 0.2 - - ms Parameter Symbol Condition Ratings Unit Min Typ Max Input voltage range of VCPCnIN VICMP REG0VSS - REG0VDD V VDD tPW Detect voltage(MAX.) Detect voltage(TYP.) Detect voltage(MIN.) tPTHD tPTHD tPD P vs1 Pvs2

Chapter 3 Power supply specification

3.5 Power-up/-down sequence of external supply

3.5.1 External FLMDn Resistors

Valid for all conditions described in the following

3.5.2 Condition 1

M1products: RESET is not used M2 products: RESET, WAKE and PTCTL1 are not used Normal operating mode Note IOVDD: AnVDD, B0VDD, EnVDD, FVDD, OSCVDD Parameter Symbol Condition Ratings Unit Min Typ Max FLMD0 external pull-down resistor R1 82 - - k Ω FLMD1 external pull-down resistor R2 - 10 - k Ω Parameter Symbol Condition Ratings Unit Min Typ Max REG0VDD, REG1VDD, IOVDD (rise) to CVDD (rise) tR0CON 1 - 10 ms REG0VDD, IOVDD (rise) to FLMD0,1(≤VIL) hold time tR0MDH 2 - - ms FLMD0,1 (≤VIL) to REG0VDD, IOVDD (fall) tMDR0OF 0 - - ms CVDD (0V) to REG0VDD, IOVDD (fall) tCR0OF 0 - - ms REGnVDD IOVDD CVDD (M2) FLMD0 P0_1/FLMD1 3.0V tROCON tROMDH VIL 1.1V tROCOF tMDR0OF VIL 3.0V

Chapter 3 Power supply specification

3.5.3 Condition 2

M1products: RESET is used M2 products: RESET is used; WAKE and PTCTL1 are not used Normal operating mode / Serial programming mode Note There is no specification for _RESET rise and fall times. Parameter Symbol Condition Ratings Unit Min Typ Max REGnVDD, IOVDD (rise) to CVDD (0V) hold time tR0CH 1 - - ms REG0VDD, REG1VDD, IOVDD (rise) to FLMD0,1(≤VIL) hold time tR0MDH 1 - - ms CVDD (rise) to _RESET (rise) tCRR 0 - - ms FLMD0,1 (≥VIH or VIL1) a to _RESET(≤VIL) (rise) tMDRR 1 - - ms _RESET (rise) to FLMD0,1(≥VIH or ≤VIL) hold time tRMDH 1 - - ms FLMD0,1,MODE0,1(≤VIL) to _RESET (≥VIH) (fall) setup time tMDRF 0 - - ms _RESET (fall) to CVDD (fall) tRCF 0 - - ms CVDD (0V) to REGnVDD, IOVDD (fall) tCR0OF 0 - - ms _RESET (≤VIL) (fall) to REGnVDD, IOVDD (fall) hold time tRR0OF 0 - - ms a) In case of BSCAN mode set also the MODE0,1 pins. REGnVDD IOVDD CVDD (M2) FLMD0 P0_1/FLMD1 3.0V tMDRRtROMDH VIL 1.1V tCROOF VIL 3.0V _RESET 1.1V VIL tRCFtCRRtR0CH tRMDH VIH VIH tMDRF tRR0OF

Chapter 3 Power supply specification

3.5.4 Condition 5

M2 products only. RESET is not used; PTCTL1 is used Normal operating mode Parameter Symbol Condition Ratings Unit Min Typ Max REG0VDD, REG1VDD, IOVDD (rise) to PTCTL1 (rise) setup time tR1PTON - - 1 ms REG0VDD, REG1VDD, IOVDD (rise) to CVDD (rise) byPTCTL1 (rise) tR0CON 1 - 10 ms REG0VDD, REG1VDD, IOVDD (rise) to FLMD0,1(≤VIL) hold time tR0MDH 2 - - ms FLMD0,1 (≤VIL) to REG0VDD, REG1VDD, IOVDD (fall) tMDR0OF 0 - - ms REG0VDD, REG1VDD, IOVDD (fall) to PTCTL1 (fall) tR1PTOF - - 1 ms PTCTL1 (fall) to CVDD (fall) tPTCOF 0 - 8 ms REG0VDD REG1VDD IOVDD CVDD FLMD0 P0_1/FLMD1 3.0V VIL VIL tR0CON 1.1V PTCTL1 tR0MDH tR1PTON 3.0V tPTCOF tMDR0OF tR1PTOF

Chapter 3 Power supply specification

3.5.5 Condition 6

M2 products only. RESET is used; PTCTL1 is used Normal operating mode / Serial programming mode / BSCAN mode Note There is no specification for _RESET rise and fall times. Parameter Symbol Condition Ratings Unit Min Typ Max REG0VDD, REG1VDD, IOVDD (rise) to CVDD (0V) hold time tR0CH - - 1 ms REG1VDD (rise) to PTCTL1 (rise) setup time tR1PTON - - 1 ms REG0VDD, IOVDD (rise) to FLMD0,1 (≤VIL) hold time tR0MDH 1 - - ms CVDD (rise) to _RESET (rise) tCRR 0 - - ms FLMD0,1 (VIH or VIL) a to _RESET (rise) tMDRR 1 - - ms _RESET (rise) to FLMD0,1 (VIH or VIL) hold time tRMDH 1 - - ms FLMD0,1,MODE0,1 (≤VIL) a to _RESET (fall) tMDRF 0 - - ms _RESET (fall) to REG0VDD, IOVDD (fall) tRR0OF 0 - - ms REG1VDD (fall) to PTCTL1 (fall) tR1PTOF - - 1 ms PTCTL1 (fall) to CVDD (fall) tPTCOF 0 - 8 ms a) In case of BSCAN mode set also the MODE0,1 pins. REG0VDD REG1VDD IOVDD CVDD FLMD0 P0_1/FLMD1 3.0V VIL VIL 1.1V PTCTL1 tR0MDH tR1PTON 3.0V tPTCOF tR1PTOF _RESET tRR0OFtMDRF tCRRtR0CH VIH VIH tMDRR tRMDH

Chapter 4 Clock generators Chapter 4 Clock generators

4.1 CPU clock

Table 4-1 CPU clock frequency

4.2 Peripheral clock

Table 4-2 Peripheral clock frequency

4.3 Oscillator characteristics

4.3.1 Main oscillator

A ceramic or crystal resonator can be connected to the main clock input pins as shown in figure 4-1 “Recommended Main Oscillator Circuit” Figure 4-1 Recommended Main Oscillator Circuit Caution Values of C1, C2 and Rd and the best setting for MOSCC.AMPSEL[1:0] register depend on the used ceramic or crystal resonator and must be specified in cooperation with ceramic or crystal resonator manufacturer. Parameter Symbol Condition Ratings Unit Min Typ Max CPU clock frequency fCPU PLL based - - 80 MHz SSCG based - - 88.32 MHz Parameter Symbol Condition Ratings Unit Min Typ Max Peripheral clock frequency fPERI - - 48 a a) Some peripherals can be operated at 80MHz. Refer to the chapter ‘Clock Selection’ in the UM for details. MHz X1 X2 C1 C2 Rd internal external

Chapter 4 Clock generators The main oscillator amplifier gain for the external resonator can be selected by MOSCC.MOSCCAMPSEL[1:0]. Thereby it can be adjusted to support a wide range of frequencies to cope with different external resonators and their external circuitry. As an example a typical setting for quartz crystals is shown in Table 4-3 “Typical setting of MOSCC.AMPSEL[1:0] for different quartz crystals frequencies”. Note For details to the setting of MOSCC.MOSCCAMPSEL[1:0] please refer to the user manual. (1) Main oscillator charactrisitics Table 4-4 Main oscillator characteristics Cautions 1. External clock input is prohibited. 2. General guidance for PCB layout:

• Keep the wiring length as short as possible.
• Do not cross the wiring with other signal lines.
• Do not route this circuit close to a signal line with high fluctuating current flow.
• Always make the ground point of the oscillator capacitor the same potential as REG0VSS and OSCVSS.
• Do not ground the capacitor to a ground pattern with high current flow.
• Do not tap signals from the oscillator.

4.3.2 Sub-oscillator

A crystal resonator can be connected to the sub clock input pins as shown in figure 4-2 “Recommended Sub Oscillator Circuit” Table 4-3 Typical setting of MOSCC.AMPSEL[1:0] for different quartz crystals frequencies MOSCC.AMPSEL[ 1:0] Amplification gain Typical condition for quartz crystals 00 high 16 < f MOSC ≤ 20 MHz 01 medium 8 < f MOSC ≤ 16 MHz 10 low 4 < f MOSC≤ 8 MHz 11 very low 4 MHz Parameter Symbol Condition Ratings Unit Min Typ Max MainOSC frequency f MOSC 4- 2 0 M H z

Chapter 4 Clock generators Figure 4-2 Recommended Sub Oscillator Circuit Caution Values of C1s, C2s and Rds depend on the used crystal and must be specified in cooperation with crystal manufacturer. (1) Sub-oscillator characteristics Table 4-5 Sub-oscillator characteristics

4.3.3 Internal oscillator

Table 4-6 Internal oscillator characteristics XT1 XT2 C1s C2s Rds internal external Parameter Symbol Condition Ratings Unit Min Typ Max MainOSC frequency fSOSC - 32.768 - kHz Parameter Symbol Condition Ratings Unit Min Typ Max Lowspeed OSC frequency fRL

• Other than DeepStop mode
• DeepStop mode with PSC0.REGSTP = 0 220.8 240 259.2 kHz fRLLP • DeepStop mode with PSC0.REGSTP = 1 216 240 264 kHz Highspeed OSC frequency fRH
• Other than DeepStop mode
• DeepStop mode with PSC0.REGSTP = 0 7.2 8.0 8.8 MHz fRHLP • DeepStop mode with PSC0.REGSTP = 1 6.64 8.0 8.8 MHz Highspeed OSC stabilization time TRHSTB - - 19 µs

Chapter 4 Clock generators

4.4 PLL Characteristics

Table 4-7 PLL characteristics Parameter Symbol Condition Ratings Unit Min Typ Max Input frequency fxn PLL mode and SSCG mode 4 - 20 MHz Output frequency fxxn PLL mode 25 - 80 MHz SSCG mode 22.40 - 88.32 MHz Lock time TLCKPn PLL mode - - 650 µs TLCKSn SSCG mode - - 1300 µs Period jittera a) Not tested in production. Specified by design. tPJn Peak to peak, fixed frequency mode, Pr=2 -150 - 150 ps Long term jitter a tLTJn PLL mode, Peak to peak, term=1µs fVCOOUT=160MHz (Pr=2) -1.275 - 1.275 ns

Chapter 5 I/O specification Chapter 5 I/O specification

5.1 Port Characteristics

5.1.1 Condition settings

Some of the conditions mentioned in this chapter can be selected by software. The related register settings are described below: (1) Input characteristic The input characteristics can be selected by the registers PIS and PISE with the following coding: Table 5-1 Input characteristic selection PISE PIS Reference in UserManual Electrical characteristic

00 T y p e 1 C M O S a

a) Default setting after reset 0 1 Type 2 Schmitt2 1 0 Type 3 Schmitt1 1 1 Type 4 Schmitt4

Chapter 5 I/O specification

5.1.2 PgE0

Table 5-2 PgE0 characteristics Parameter Symbol Condition Ratings Unit Min Typ Max High level input voltage VIH CMOS 0.7·E0VDD - E0VDD+0.3 V Schmitt1 0.7·E0VDD - E0VDD+0.3 Schmitt2 0.8·E0VDD - E0VDD+0.3 Schmitt4 (E0VDD=VPOC~3.0) 0.84·E0VDD - E0VDD+0.3 Schmitt4 (E0VDD=3.0~5.5) 0.8·E0VDD - E0VDD+0.3 Low level input voltage VIL CMOS -0.5 - 0.3·E0VDD V Schmitt1 -0.5 - 0.3·E0VDD Schmitt2 -0.5 - 0.2·E0VDD Schmitt4 (E0VDD=VPOC~3.0) -0.5 - 0.4·E0VDD Schmitt4 (E0VDD=3.0~5.5) -0.5 - 0.5·E0VDD High level output voltage VOH IOH = -5mA E0VDD-1.0 - V IOH = -100µA E0VDD-0.5 - Low level output voltage VOL IOL = 5mA - - 0.4 V IOL = 100µA - - 0.4 Input hysteresis of Schmit VH Schmitt1 0.3 - VSchmitt2 0.3 - Schmitt4 0.1 - Internal pull-up resistor RU 20 40 100 k Ω Internal pull-down resistor RD 20 40 100 k Ω High level port output current IOH Power supply of PgE0 - - -20 mA Low level port output current IOL Power supply of PgE0 - - 20 mA High level input leakage current ILIH VI = E0VDD - - 0.5 µA Low level input leakage current ILIL VI = 0V - - -0.5 µA High level output leakage current ILOH VO = E0VDD - - 0.5 µA Low level output leakage current ILOL VO = 0V - - -0.5 µA Output frequency fO Slow mode - - 25 MHz Fast mode - - 40 Rise time (output) tKRP Slow mode - - 15 ns Fast mode - - 8 ns Fall time (output) tKFP Slow mode - - 15 ns Fast mode - - 8 ns

Chapter 5 I/O specification

5.1.3 PgE1

Table 5-3 PgE1 characteristics Parameter Symbol Condition Ratings Unit Min Typ Max High level input voltage VIH CMOS 0.7·E1VDD - E1VDD+0.3 V Schmitt1 0.7·E1VDD - E1VDD+0.3 Schmitt2 0.8·E1VDD - E1VDD+0.3 Schmitt4 (E1VDD=VPOC~3.0) 0.84·E1VDD - E1VDD+0.3 Schmitt4 (E1VDD=3.0~5.5) 0.8·E1VDD - E1VDD+0.3 Low level input voltage VIL CMOS -0.5 - 0.3·E1VDD V Schmitt1 -0.5 - 0.3·E1VDD Schmitt2 -0.5 - 0.2·E1VDD Schmitt4 (E1VDD=VPOC~3.0) -0.5 - 0.4·E1VDD Schmitt4 (E1VDD=3.0~5.5) -0.5 - 0.5·E1VDD High level output voltage VOH IOH = -5mA a a) The maximum number of PgE1 pins with ‘ON’ signal at the same time is 5 in ‘Slow mode’. The maximum number of PgE1 pins with ‘ON’ signal at the same time is 8 in ‘Fast mode’. See the UM for the related description of the Port drive strength control. E1VDD-1.0 - V IOH = -100µA E1VDD-0.5 - Low level output voltage VOL IOL = 5mAa -- 0 . 4 V IOL = 100µA - - 0.4 Input hysteresis of Schmit VH Schmitt1 0.3 - VSchmitt2 0.3 - Schmitt4 0.1 - Internal pull-up resistor RU 20 40 100 k Ω Internal pull-down resistor RD 20 40 100 k Ω High level port output current IOH Power supply of PgE1 - - -150 mA Low level port output current IOL Power supply of PgE1 - - 150 mA High level input leakage current ILIH VI = E1VDD - - 0.5 µA Low level input leakage current ILIL VI = 0V - - -0.5 µA High level output leakage current ILOH VO = E1VDD - - 0.5 µA Low level output leakage current ILOL VO = 0V - - -0.5 µA Output frequency fO Slow mode - - 25 MHz Fast mode - - 40 Rise time (output) tKRP Slow mode - - 15 ns Fast mode - - 8 ns Fall time (output) tKFP Slow mode - - 15 ns Fast mode - - 8 ns

Chapter 5 I/O specification

5.1.4 PgB0

Table 5-4 PgB0 characteristics Parameter Symbol Condition Ratings Unit Min Typ Max High level input voltage VIH CMOS 0.7·B0VDD - B0VDD+0.3 V Schmitt1 0.7·B0VDD - B0VDD+0.3 Schmitt2 0.8·B0VDD - B0VDD+0.3 Schmitt4 (B0VDD=VPOC~3.0) 0.84·B0VDD - B0VDD+0.3 Schmitt4 (B0VDD=3.0~5.5) 0.8·B0VDD - B0VDD+0.3 Low level input voltage VIL CMOS -0.5 - 0.3·B0VDD V Schmitt1 -0.5 - 0.3·B0VDD Schmitt2 -0.5 - 0.2·B0VDD Schmitt4 (B0VDD=VPOC~3.0) -0.5 - 0.4·B0VDD Schmitt4 (B0VDD=3.0~5.5) -0.5 - 0.5·B0VDD High level output voltage VOH IOH = -5mA a a) The maximum number of PgB0 pins with ‘ON’ signal at the same time is 5 in ‘Slow mode’ (Except the pins related to the external memory interface (MEMC)). The maximum number of PgB0 pins with ‘ON’ signal at the same time is 8 in ‘Fast mode’. See the UM for the related description of the Port drive strength control. B0VDD-1.0 - - V IOH = -100µA B0VDD-0.5 - - Low level output voltage VOL IOL = 5mAa -- 0 . 4 V IOL = 100µA - - 0.4 Input hysteresis of Schmit VH Schmitt1 0.3 - - VSchmitt2 0.3 - - Schmitt4 0.1 - - Internal pull-up resistor RU 20 40 100 k Ω Internal pull-down resistor RD 20 40 100 k Ω High level port output current IOH Power supply of PgB0 - - -100 mA Low level port output current IOL Power supply of PgB0 - - 100 mA High level input leakage current ILIH VI =B0VDD - - 0.5 µA Low level input leakage current ILIL VI = 0V - - -0.5 µA High level output leakage current ILOH VO = B0VDD - - 0.5 µA Low level output leakage current ILOL VO = 0V - - -0.5 µA Output frequency fO Slow mode - - 25 MHz Fast mode - - 40 Rise time (output) tKRP Slow mode - - 15 ns Fast mode - - 8 ns Fall time (output) tKFP Slow mode - - 15 ns Fast mode - - 8 ns

Chapter 5 I/O specification

5.1.5 PgA0 and PgA1

Table 5-5 PgA0 and PGA1 characteristics Parameter Symbol Condition Ratings Unit Min Typ Max High level input voltage VIH CMOS 0.7·AnVDD - AnVDD+0.3 V Low level input voltage VIL CMOS -0.5 - 0.3·AnVDD V High level output voltage VOH IOH = -1mA AnVDD-1.0 - - V IOH = -100µA AnVDD-0.5 - - Low level output voltage VOL IOL = 1mA - - 0.4 V IOL = 100µA - - 0.4 High level port output current IOH Power supply of PgA0 and PgA1 -- - 2 0 m A Low level port output current IOL Power supply of PgA0 and PgA1 -- 2 0 m A High level input leakage current ILIH VI = AnVDD - - 0.2 µA Low level input leakage current ILIL VI = 0V - - -0.2 µA High level output leakage current ILOH VO = AnVDD - - 0.2 µA Low level output leakage current ILOL VO = 0V - - -0.2 µA Output frequency fO - - 25 MHz Rise time (output) tKRP - - 15 ns Fall time (output) tKFP - - 15 ns

Chapter 6 Supply current specification Chapter 6 Supply current specification

6.1 Supply current of µPDF70F4007 / µPDF70F4008 /

µPDF70F4009 / µPDF70F4010 Total supply current Notes 1. The above currents do not include port buffer currents or ADC currents. 2. The currents in run mode include currents for self-programming and EEPROM emulation. 3. The current of FlexRay is not included in case of CPU frequency = 8MHz. 4. The ‘typical’ specification is for reference only and not a guaranteed value. The ‘typical’ specification is applicable under the following conditions:

• Ta = 25°C
• REGnVDD=FVDD=OSCVDD=EmVDD=B0VDD=AmVDD=AmVREFP=5.0V (n=0-3, m=0-1).
• M2 products: CVDD = 1.2V
• REGnVSS=OSCVSS=EmVSS=B0VSS=AmVSS=AmVREFM=0V (n=0-3, m=0-1) Item Powera Conditionb Specification Unit ISO0 ISO1 8MHz intOSC Main OSC Sub OSC PLL CPU Freq Peripherals Typ. (A) (A1) (A2) RUN mode ON ON ON ON ON ON 80 WORKING 139 178 180 181 mA ON ON ON ON ON ON 80 STOPPED 76 - - - mA ON ON ON OFF ON OFF 8 WORKING 27 45 46 46 mA ON ON ON OFF ON OFF 8 STOPPED 19 - - - mA ON OFF ON ON ON ON 80 WORKING 104 138 139 140 mA ON OFF ON ON ON ON 80 STOPPED 74 - - - mA ON OFF ON OFF ON OFF 8 WORKING 21 40 40 40 mA ON OFF ON OFF ON OFF 8 STOPPED 19 - - - mA HALT mode ON ON ON ON ON ON 80 WORKING 134 174 176 177 mA ON ON ON ON ON ON 80 STOPPED 74 - - - mA ON ON ON OFF ON OFF 8 WORKING 26 45 45 45 mA ON ON ON OFF ON OFF 8 STOPPED 19 - - - mA STOP mode ON ON OFF OFF OFF OFF - STOPPED 0.7 19 20 22 mA ON OFF OFF OFF OFF OFF - STOPPED 0.6 19 19 21 mA DEEPSTOP mode OFF OFF OFF OFF OFF OFF - STOPPED 0.06 0.86 0.88 1.1 mA OFF OFF ON OFF OFF OFF - STOPPED 0.6 2.1 2.3 2.5 mA OFF OFF ON OFF ON OFF - STOPPED 0.6 2.1 2.3 2.5 mA a) The AWO is always ON. b) The 240kHz IntOSC is always ON.

Chapter 6 Supply current specification Current supplied by CVDD (for M2 products) Item Powera Conditionb Specification Unit ISO0 ISO1 8MHz intOSC Main OSC Sub OSC PLL CPU Freq Peripherals Min. Typ. (A) (A1) (A2) RUN mode ON ON ON ON ON ON 80 WORKING 115 150 152 153 mA ON ON ON ON ON ON 80 STOPPED 56 - - - mA ON ON ON OFF ON OFF 8 WORKING 15 32 32 32 mA ON ON ON OFF ON OFF 8 STOPPED 8 - - - mA ON OFF ON ON ON ON 80 WORKING 81 110 111 112 mA O N O F F O N O NO NO N 8 0 S T O P P E D 5 4 - - - m A ON OFF ON OFF ON OFF 8 WORKING 10 27 27 27 mA ON OFF ON OFF ON OFF 8 STOPPED 8 - - - mA HALT mode ON ON ON ON ON ON 80 WORKING 108 144 145 146 mA ON ON ON ON ON ON 80 STOPPED 54 - - - mA ON ON ON OFF ON OFF 8 WORKING 14 31 32 32 mA ON ON ON OFF ON OFF 8 STOPPED 8 - - - mA STOP mode ON ON OFF OFF OFF OFF - STOPPED 0.6 15 16 18 mA ON OFF OFF OFF OFF OFF - STOPPED 0.4 15 15 17 mA DEEPSTOP mode OFF OFF OFF OFF OFF OFF - STOPPED 0 0 0 0 mA OFF OFF ON OFF OFF OFF - STOPPED 0 0 0 0 mA OFF OFF ON OFF ON OFF - STOPPED 0 0 0 0 mA a) The AWO is always ON. b) The 240kHz IntOSC is always ON.

Chapter 6 Supply current specification

6.2 Supply current of µPDF70F3555 / µPDF70F3556 /

µPDF70F3557 / µPDF70F3558 Total supply current Notes 1. The above currents do not include port buffer currents or ADC currents. 2. The currents in run mode include currents for self-programming and EEPROM emulation. 3. The ‘typical’ specification is for reference only and not a guaranteed value. The ‘typical’ specification is applicable under the following conditions:

• Ta = 25°C
• REGnVDD=FVDD=OSCVDD=EmVDD=B0VDD=AmVDD=AmVREFP=5.0V (n=0-3, m=0-1).
• M2 products: CVDD = 1.2V
• REGnVSS=OSCVSS=EmVSS=B0VSS=AmVSS=AmVREFM=0V (n=0-3, m=0-1) Item Powera Conditionb Specification Unit ISO0 ISO1 8MHz intOSC Main OSC Sub OSC PLL CPU Freq Peripherals Min. Typ. (A) (A1) (A2) RUN mode ON ON ON ON ON ON 80 WORKING 121 157 159 160 mA ON ON ON ON ON ON 80 STOPPED 73 - - - mA ON ON ON OFF ON OFF 8 WORKING 27 45 46 46 mA ON ON ON OFF ON OFF 8 STOPPED 19 - - - mA ON OFF ON ON ON ON 80 WORKING 94 126 127 128 mA O N O F F O N O NO NO N 8 0 S T O P P E D 7 1 - - - m A ON OFF ON OFF ON OFF 8 WORKING 21 40 40 40 mA ON OFF ON OFF ON OFF 8 STOPPED 19 - - - mA HALT mode ON ON ON ON ON ON 80 WORKING 114 151 152 153 mA ON ON ON ON ON ON 80 STOPPED 71 - - - mA ON ON ON OFF ON OFF 8 WORKING 26 45 45 45 mA ON ON ON OFF ON OFF 8 STOPPED 19 - - - mA STOP mode ON ON OFF OFF OFF OFF - STOPPED 0.7 19 20 22 mA ON OFF OFF OFF OFF OFF - STOPPED 0.6 19 19 21 mA DEEPSTOP mode OFF OFF OFF OFF OFF OFF - STOPPED 0.06 0.86 0.88 1.1 mA OFF OFF ON OFF OFF OFF - STOPPED 0.6 2.1 2.3 2.5 mA OFF OFF ON OFF ON OFF - STOPPED 0.6 2.1 2.3 2.5 mA a) The AWO is always ON. b) The 240kHz IntOSC is always ON.

Chapter 6 Supply current specification

6.3 Supply current of µPDF70F3592

Notes 1. The above currents do not include port buffer currents or ADC currents. 2. The currents in run mode include currents for self-programming and EEPROM emulation. 3. The current of FlexRay is not included in case of CPU frequency = 8MHz. 4. The ‘typical’ specification is for reference only and not a guaranteed value. The ‘typical’ specification is applicable under the following conditions:

• Ta = 25°C
• REGnVDD=FVDD=OSCVDD=EmVDD=B0VDD=AmVDD=AmVREFP=5.0V (n=0-3, m=0-1).
• M2 products: CVDD = 1.2V
• REGnVSS=OSCVSS=EmVSS=B0VSS=AmVSS=AmVREFM=0V (n=0-3, m=0-1) Item Powera Conditionb Specification Unit ISO0 ISO1 8MHz intOSC Main OSC Sub OSC PLL CPU Freq Peripherals Min. Typ. (A) (A1) (A2) RUN mode ON ON ON ON ON ON 80 WORKING 134 174 176 - mA ON ON ON ON ON ON 80 STOPPED 76 - - - mA ON ON ON OFF ON OFF 8 WORKING 26 45 45 - mA ON ON ON OFF ON OFF 8 STOPPED 19 - - - mA ON OFF ON ON ON ON 80 WORKING 104 138 139 - mA O N O F F O N O NO NO N 8 0 S T O P P E D 7 4 - - - m A ON OFF ON OFF ON OFF 8 WORKING 21 39 40 - mA ON OFF ON OFF ON OFF 8 STOPPED 19 - - - mA HALT mode ON ON ON ON ON ON 80 WORKING 127 169 170 - mA ON ON ON ON ON ON 80 STOPPED 74 - - - mA ON ON ON OFF ON OFF 8 WORKING 25 44 45 - mA ON ON ON OFF ON OFF 8 STOPPED 19 - - - mA STOP mode ON ON OFF OFF OFF OFF - STOPPED 0.7 16 17 - mA ON OFF OFF OFF OFF OFF - STOPPED 0.6 15 16 - mA DEEPSTOP mode OFF OFF OFF OFF OFF OFF - STOPPED 0.06 0.86 0.88 - mA OFF OFF ON OFF OFF OFF - STOPPED 0.6 2.1 2.3 - mA OFF OFF ON OFF ON OFF - STOPPED 0.6 2.1 2.3 - mA a) The AWO is always ON. b) The 240kHz IntOSC is always ON.

Chapter 6 Supply current specification

6.3.1 Voltage Comparator characteristics

Table 6-1 VCMP characteristics Parameter Symbol Condition Ratings Unit Min Typ Max VCMP current IVCMP - 200 300 µA

Chapter 7 Periphera ls specification Chapter 7 Peripherals specification

7.1 Reset timing

7.2 NMI timing

Parameter Symbol Condition Ratings Unit Min Typ Max RESET input High level width tWRSH Highspeed OSC is operating 450 - - ns Highspeed OSC is stopped 4.7 - - µs RESET input Low level width tWRSL Highspeed OSC is operating 450 - - ns Highspeed OSC is stopped 4.7 - - µs Parameter Symbol Condition Ratings Unit Min Typ Max NMI input High level width tWNIH 300 - - ns NMI input Low level width tWNIL 300 - - ns tWRSH tWRSL _RESET tWKRH tWKRL KRn

Chapter 7 Periphera ls specification

7.3 INTP timing

7.4 FLMD0 timing

7.5 _DCUTRST timing Parameter Symbol Condition Ratings Unit Min Typ Max INTPn input High level width tWITH 300 - - ns INTPn input Low level width tWITL 300 - - ns Parameter Symbol Condition Ratings Unit Min Typ Max FLMD0 input High level width tWMDH 300 - - ns FLMD0 input Low level width tWMDL 300 - - ns FLMD0 external pull down resistor R FLMD0 82 - - k Ω tWITH tWITL INTPn tWMDH tWMDL FLMD0 Parameter Symbol Condition Ratings Unit Min Typ Max _DCUTRST input High level width tWRH 450 - - ns _DCUTRST input Low level width tWTRL 450 - - ns tWTRH tWTRL _TRST

Chapter 7 Periphera ls specification

7.6 Timer timing

Parameter Symbol Condition Ratings Unit Min Typ Max TAUAnI input High level width tTAIH n=0 a,b -- n s TAUAnI input Low level width tTAIL n=0 a,b -- n s TAUBnI input High level width tTBIH n=1 a,b a) With digital noise filter enabled: 2, 3, 4 or 5 x Tsamp + 20 (Tsamp shows sampling period specified in Noise filter macro. More than 1 PCLK width of Timer macro must be kept regarding DNF pass through pulse width. b) With digital noise filter disabled: 1xtSYNC+20 ( tSYNC: 1 PCLK of Timer macro) -- n s TAUBnI input Low level width tTBIL n=0 a,b -- n s TAUJnI input High level width tTJIH n=0,1 300 - - ns TAUJnI input High level width tTJIH 4.7 - - µs TAUJnI input High level width tTJIH b - - ns TAUJnI input Low level width tTJIL n=0,1 300 - - ns TAUJnI input Low level width tTJIL 4.7 - - µs TAUJnI input Low level width tTJIL b -- n s TAUAnO output cycle tTACYK n=0 - - 20 MHz TAUBnO output cycle tTBCYK n=1 - - 20 MHz TAUCnO output cycle tTCCYK n=2-7 - - 20 MHz TAUJnO output cycle t TJCYK n=0,1 - - 20 MHz TAPAnESO input High level width tWESH n=0 300 - - ns TAPAnESO input Low level width tWESL n=0 300 - - ns ENCAnTmIN high level width tWENmH n=0, m=A,B,Z a,b -- n s ENCAnTmIN low level width tWENmL n=0, m=A,B,Z a,b -- n s ENCAnTINm high level width tWENmH n=0, m=0-1 a,b -- n s ENCAnTINm low level width tWENmL n=0, m=0-1 a,b -- n s

Chapter 7 Periphera ls specification

7.7 Multiplexed bus timing

Parameter Symbol Condition Ratings Unit Min Typ Max MEMC0CLK output cycle tMEMC 25 - - ns MEMC0CLK high level width tWKHMEM tMEMC / 2 - 10 - - ns MEMC0CLK low level width tWKLMEM tMEMC / 2 - 10 - - ns MEMC0CLK rise time tKRMEM - - 10 ns MEMC0CLK fall time tKFMEM - - 10 ns tKRM BM tKF MB M tWKH MBM tWKLMB M tMB MC MEMC0CLK

Chapter 7 Periphera ls specification

7.7.1 MEMC0CLK asynchronous timing

Notes 1. ASW: Number of Address Setup Wait for multiplex bus 2. AHW: Number of Address Hold Wait for multiplex bus 3. w: Number of data wait 4. In case the bus operational period (T) is shorter then 41ns, tDRDID requires at least 1 data wait (w=1). Parameter Symbol Condition Ratings Unit Min Typ Max Bus operational period T - 25 - - ns Address setup time to MEMC0ASTBZ (f) tSAST <1> (1+ASW)·T-15 - - ns Address hold time from MEMC0ASTBZ (f) tHSTA <2> (1+AHW)·T-15 - - ns Address float delay time from MEMC0RDZ (f) tFRDA <3> - - 6 ns Address hold time from MEMC0RDZ (r) tHRDA <4> 0 - - ns Data input delay time from MEMC0RDZ (f) tDRDID <5> 6 - (1+w)·T-35 ns Data input hold time from MEMC0RDZ (r) tHRDID <6> 0 - - ns Delay time from ASTB(f) to MEMC0RDZ (f) tDSTRD <7> (1+AHW)·T-15 - - ns Delay time from ASTB(f) to MEMC0WRZ (f) tDSTWR <8> (1+AHW)·T-15 - - ns MEMC0RDZ, MEMC0WRZ low level width tWRDST <9> (1+w)·T-10 - - ns Data output delay time from MEMC0WRZ (f) tDWROD <10> - - 10 ns Address hold time from MEMC0WRZ (r) tHWRA <11> T-15 - - ns Data output setup time to MEMC0WRZ (r) tSODWR <12> (1+w)·T-15 - - ns Data output hold time from MEMC0WRZ (r) tHWROD <13> T-15 - - ns MEMC0WAITZ setting delay from MEMC0ASTBZ (f) tSSTWT1 <14> - - (1+AHW)·T - (2·HEAPCLK+35) ns MEMC0WAITZ hold time from MEMC0ASTBZ (f) tSSTWT2 <15> w ≥1- - (1+w+AHW)·T - (2·HEAPCLK+35) ns MEMC0WAITZ setting delay from Address tHSTWT1 <16> w ≥1 (w+AHW)·T- (2*HEAPCLK+20) -- n s MEMC0WAITZ hold time from Address tHSTWT2 <17> w ≥1 (1+w+AHW)·T- 2*HEAPCLK+20) -- n s

Chapter 7 Periphera ls specification (1) Multiplex write cycle (Asynchronous; 1 data wait) T1 TA TDEW T2 Data TDHW <1> MEMC0CLK (output) MEMC0CSZ4-2 (output) MEMC0A18-16 (output) MEMC0ASTBZ (output) MEMC0WRZ (output) MEMC0WAITZ (input) MEMC0AD15-0 (I/O) Address Address <14> <2> <8> <9> <10> <11><12> <13> <16> <15> <17>

Chapter 7 Periphera ls specification (2) Multiplex read cycle (Asynchronous; 1 data wait) MEMC0CLK (output) MEMC0CSZ4-2 (output) MEMC0A18-16 output) MEMC0ASTBZ (output) MEMC0RDZ (output) MEMC0WAITZ (input) MEMC0AD15-0 (I/O) T1 TA TDEW T2 <3> Address Data Address <1> <2> <4> <9><14> <16> <15> <17>

Chapter 7 Periphera ls specification

7.7.2 MEMC0CLK synchronous timing

Parameter Symbol Condition Ratings Unit Min Typ Max Bus operational period T 25 - - ns Delay time from MEMC0CLK (r) to address tDKA <18> 0 - 12 ns Delay time from MEMC0CLK (r) to address float tFKA <19> 0 - 12 ns Delay time from MEMC0CLK (r) to ASTB (f) tDKST <20> 0 - 11 ns Delay time from MEMC0CLK (r) to MEMC0RDZ and MEMC0WRZ tDKRDWR <21> -2.5 - 6 ns Data input setup time (from MEMC0CLK (r)) tSIDK <22> 10 - - ns Data input hold time (from MEMC0CLK (r)) tHKID <23> 2.5 - - ns Data output delay time (from MEMC0CLK (r)) tDKOD <24> - - 11 ns MEMC0WAITZ setup time (to MEMC0CLK (r)) tSWTK <25> B0VDD≥3.5V 23 - - ns <25> B0VDD<3.5V 27 - - ns MEMC0WAITZ hold time (from MEMC0CLK (r)) tHKWT <26> 2.5 - - ns

Chapter 7 Periphera ls specification (1) Multiplex write cycle (Synchronous; 1 data wait) T1 TA TDEW T2 Data TDHW <18> <20> <24> MEMC0CLK (output) MEMC0CSZ4-2 (output) MEMC0A18-16 (output) MEMC0ASTBZ (output) MEMC0WRZ (output) MEMC0WAITZ (input) MEMC0AD15-0 (I/O) Address Address <21> <21> TDEW

Chapter 7 Periphera ls specification (2) Multiplex read cycle (Synchronous; 1 data wait) MEMC0CLK (output) MEMC0CSZ4-2 (output) MEMC0A18-16 output) MEMC0ASTBZ (output) MEMC0RDZ (output) MEMC0WAITZ (input) MEMC0AD15-0 (I/O) T1 TA TDEW T2 <19><18> <20> <21> <22> <23> Address Data Address <21> TDEW

Chapter 7 Periphera ls specification

7.8 CSI timing

7.8.1 Master modes

(1) CSIG timing Table 7-3 CSIG timing (Master mode) Note n: Number of macro instances. Refer to the User Manual for the detailed specification. Parameter Symbol Condition Ratings Unit Min Typ Max Macro Operation clock cycle time tKCYGn 20.8 - - ns CSIGnSC cycle time tKCYMGn 100 - - ns CSIGnSC high level width tKWHMGn 0.5 · tKCYMGn-10 - - ns CSIGnSC low level width tKW LMGn 0.5 · tKCYMGn-10 - - ns CSIGnSI setup time (vs. CSIGnSC ) tSSIMGn CSIGnSC@PDSC=1 30 - - ns CSIGnSI setup time (vs. CSIGnSC ) tSSIMGn CSIGnSC@PDSC=0 38 - - ns CSIGnSI hold time (vs. CSIGnSC) tHSIMGn 0 - - ns CSIGnSO output delay (vs. CSIGnSC) tDSOMGn - - 7 ns CSIGnRYI setup time (vs. CSIGnSC) tSRYIGn CSIGnCTL1.CSIGnSIT=x CSIGnCTL1.CSIGnHSE=1 2 · tKCYGn+25 - - ns CSIGnRYI High level width tWRYIGn CSI GnCTL1.CSIGnHSE=1 tKCYGn- 5.0 - - ns

Chapter 7 Periphera ls specification (2) CSIH timing master mode Table 7-4 CSIH timing (Master mode) Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed specification. 2. CSSETUP: Value of CSIHnCFG0-7.CSIHnSP0-7[3:0] 3. CSHOLD: Value of CSIHnCFG0-7.CSIHnHD0-7[3:0] 4. CSIDLE: Value of CSIHnCFG0-7.CSIHnID0-7[2:0] Parameter Symbol Condition Ratings Unit Min Typ Max Macro Operation clock cycle time tKCYHn 20.8 - - ns CSIHnSC cycle time tKCYMHn 100 - - ns CSIHnSC high level width tKWHMHn 0.5 · tKCYMHn-10 - - ns CSIHnSC low level width tKWLMHn 0.5 · tKCYMHn-10 - - ns CSIHnSI setup time (vs. CSIHnSC ) tSSIMHn CSIHnSC@PDSC=1 30 - - ns CSIHnSC@PDSC=0 38 - - ns CSIHnSI hold time (vs. CSIHnSC) tHSIMHn 0 - - ns CSIHnSO output delay (vs. CSIHnSC) tDSOMHn - - 7 ns CSIHnRYI setup time (vs. CSIHnSC) tSRYIHn CSIHnCTL1.CSIHnSIT=x CSIHnCTL1.CSIHnHSE=1 2 · tKCYHn+25 - - ns CSIHnRYI High level width tWRYIHn CSIHnCTL1.CSIHnHSE=1 tKCYHn- 5.0 - - ns CSIHnCSS0-7 inactive width tWSCSBHn CSIDLE × tKCYMHn - 5.0 -- n s CSIHnCSS0-7 setup time ( vs. CSIHnSC ) tSSCSBHn0 CSIHnCT L1.CSIHnDAP=0 CSSETUP × tKCYMHn-5.0 -- n s tSSCSBHn1 CSIHnCT L1.CSIHnDAP=1 (CSSETUP + 0.5 ) × tKCYMHn-5.0 -- n s CSIHnCSS0-7 hold time ( vs. CSIHnSC ) tHSCSBHn0 CSIHnCTL1.CSIHnSIT=0 CSHOLD × tKCYMHn-10.0 -- n s tHSCSBHn1 CSIHnCTL1.CSIHnSIT=1 (CSSHOLD + 0.5) × tKCYMHn-5.0 -- n s

Chapter 7 Periphera ls specification (3) Timing diagrams SCKO / SI / SO CSIG ( CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0 / 0 or 1 / 1 ) CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0 /0 or 1/1 ) CSIG( CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 1 / 0 or 0 / 1) CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 1/ 0 or 0/ 1 ) tKCYGn tKCYMGn tKWLMGn tKWLMHn Clock CSIGnSC CSIGnSI CSIGnSO tKCYHn tKCYMHn tKW HMG n tKW HMHn tDS OM Gn tDS OM H n tHSIMGn tHSIMH n tSSIMGn tSSIMHn CSIHnSC CSIHnSO CSIHnSI tKCYG n tKCYMGn tKWHMGn tKWHMH n Clock CSIGnSC CSIGnSI CSIGnSO tKCYHn tKCYMHn tKW LMG n tKW LMHn tDSOMGn tDSOMHn tHSIMGn tHSIMHn tSSIMGn tSSIMHn CSIHnSC CSIHnSO CSIHnSI

Chapter 7 Periphera ls specification RYI CSIGnCTL1 : CSIGnHSE=1, CSIGnCTL1 : CSIGnSIT = 0 ) CSIHnCTL1 : CSIHnHSE=1, CSIHnCTL1 : CSIHnSIT = 0 ) CSIG (CSIGnCTL1 :CSIGnCKR= 0) CSIH (CSIHnCFGm:CSIHnCKPm= 0) CSIG (CSIGnCTL1 :CSIGnCKR= 1) CSIH (CSIHnCFGm:CSIHnCKPm= 1) tKCYGn tSRYIGn Clock CSIGnSC CSIGnRYI tKCYHn tSRYIHn CSIHnSC CSIHnRYI tWRYIG n tWRYIHn Clock CSIGnSC CSIGnRYI CSIHnSC CSIHnRYI tKCYGn tKCYHn tSRYIGn tSRYIHn tWRYIGn tWRYIHn

Chapter 7 Periphera ls specification CSSn CSIHnCFGm:CSIHnCKPm= 0,CSIHnCFGm:CHIHnDAPm= 0 CSIHnCFGm:CSIHnCKPm= 0,CSIHnCFGm:CHIHnDAPm= 1 Clock tKCYHn CSIHnSC CSIHnCSS0-7 tSS CSBHn 0 CSIHnSO Clock tKCYHn CSIHnSC CSIHnCSS0-7 tSSCSBHn 1 CSIHnSO tKCYMH nCSSETUP xt KCYMHn0.5x

Chapter 7 Periphera ls specification CSIHnCTL1 : CSIHnSIT=0, CSIHnCFGm: CSIHnCKPm= 0,CSIHnCFGm: CHIHnDAPm= 0 CSIHnCTL1 : CSIHnSIT=1, CSIHnCFGm: CSIHnCKPm= 0,CSIHnCFGm: CHIHnDAPm= 0 Clock tKCYHn CSIHnSC CSHnCSS0-7 tHSCSBHn0 Clock tKCYHn CSIHnSC CSHnCSS0-7 tHSCSBHn1 tKCYM HnCSHOLD xtKCYMH n0.5 x

Chapter 7 Periphera ls specification

7.8.2 Slave mode

(1) CSIG timing slave mode Table 7-5 CSIG timing (Slave mode) Note n: Number of macro instances. Refer to the User Manual for the detailed specification. (2) CSIH timing slave mode Table 7-6 CSIH timing (Slave mode) Note n: Number of macro instances. Refer to the User Manual for the detailed specification. Parameter Symbol Condition Ratings Unit Min Typ Max Macro Operation clock cycle time tKCYGn 20.820.83 - - ns CSIGnSC cycle time tKCYSGn 200 - - ns CSIGnSC high level width tKWHSGn 0.5 · tKCYSGn-10 - - ns CSIGnSC low level width tKWLSGn 0.5 · tKCYSGn-10 - - ns CSIGnSI setup time (vs. CSIGnSC ) tSSISGn 20 - - ns CSIGnSI hold time (vs. CSIGnSC) tHSISGn tKCYGn+5.0 - - ns SO output delay (vs SCKI) tDSOSGn - - 35 ns CSIGnRYO output delay tSRYOGn - - 35 ns _CSIGnSSI setup time (vs CSIGnSC) tSSSISGn 0.5 · tKCYSn-5.0 - - ns _CSIGnSSI hold time (vs CSIGnSC) tHSSISGn tKCY+5.0 - - ns Parameter Symbol Condition Ratings Unit Min Typ Max Macro Operation clock cycle time tKCYHn 20.8 - - ns CSIHnSC cycle time tKCYSHn 200 - - ns CSIHnSC high level width tKWHSHn 0.5 · tKCYSHn-10 - - ns CSIHnSC low level width tKWLSHn 0.5 · tKCYSHn-10 - - ns CSIHnSI setup time (vs. CSIHnSC ) tSSISHn 20 - - ns CSIHnSI hold time (vs. CSIHnSC) tHSISHn tKCYHn+5.0 - - ns SO output delay (vs SCKI) tDSOSHn - - 35 ns CSIHnRYO output delay tSRYOHn - - 35 ns CSIHnSSI setup time (vs. CSIHnSC) tSSSISHn 0.5 · tKCYSn-5:0 - - ns CSIHnSSI hold time (vs. CSIHnSC) tHSSISHn tKCYn* 5.0 - - ns

Chapter 7 Periphera ls specification (3) Timing diagrams SCKO / SI / SO CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0/0 or 1/1) CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0/0 or 1/1) CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 1/0 or 0/1) CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 1/0 or 0/1) tKCYGn tKCYSGn tKWLSGn tKWLSHn Clock CSIGnSC CSIGnSI CSIGnSO tKCYHn tKCYSHn tKWHSGn tKWHSH n tDS OS Gn tDS OS H n tHSISGn tHSISH n tSSISGn tSSISHn CSIHnSC CSIHnSO CSIHnSI tKCYGn tKCYSGn tKWHSGn tKWHSH n Clock CSIGnSC CSIGnSI CSIGnSO tKCYHn tKCYSHn tKWLSG n tKWLSHn tD SOSGn tD SOSHn tHSISGn tHSISH n tSSISGn tSSISHn CSIHnSC CSIHnSO CSIHnSI

Chapter 7 Periphera ls specification RYO CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0/0) CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0/0) CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 0/1) CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 0/1) CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 1/0) CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 1/0) CSIG (CSIGnCTL1 : CSIGnCKR/ CSIGnCFG0 :CHIGnDAP0 = 1/1) CSIH (CSIHnCFGm:CSIHnCKPm/ CSIHnCFGm: CHIHnDAPm= 1/1) CSIGnSC CSIGnRYO CSIHnSC CSIHnRYO tSRYOGn tSRYOHn CSIGnSC CSIGnRYO CSIHnSC CSIHnRYO tSRYOGn tSRYOHn CSIGnSC CSIGnRYO CSIHnSC CSIHnRYO CSIHnTIC tSRYOGn tSRYOHn CSIGnSC CSIGnRYO CSIHnSC CSIHnRYO tSRYOGn tSRYOHn

Chapter 7 Periphera ls specification SSI: CSIG (CSIGnCTL1 :CSIGnSSE=1, CSIGnCTL1 : CSIGnCKR,/ CSIGnCFG0 : CHIGnDAP0 = 0/0 or 1/1) CSIH (CSIHnCTL1 : CSIHnSSE=1, CSIHnCFGm : CSIHnCKPm / CSIHnCFGm : CHIHnDAPm = 0/0 or 1/1) CSIG (CSIGnCTL1 :CSIGnSSE=1, CSIGnCTL1 : CSIGnCKR,/ CSIGnCFG0 : CHIGnDAP0 = 1/0 or 0/1 ) n=0, 4 CSIH (CSIHnCTL1 : CSIHnSSE=1, CSIHnCFGm : CSIHnCKPm / CSIHnCFGm : CHIHnDAPm = 1/0 or 0/1)

7.9 UART timing

_CSIGnSSI _CSIHnSSI Hi-Z CSIGnSC CSIGnSO tSSS ISGn tSSS ISHn tHSSI SGn tHSSI SHn CSIHnSC CSIHnSO _CSIGnSSI _CSIHnSSI Hi-Z Parameter Symbol Condition Ratings Unit Min Typ Max Transfer rate - - 1.5 Mbps

Chapter 7 Periphera ls specification FCnRX pin ( Receive data ) FCnTX pin ( Transfer data ) FCnTX pin FCnRX pin Image of Internal delay time Output delay time (tOUTPUT) Input gate delay time (tGATE) toutput V850E2/Fx4 tGATE CAN node delay time (tNODE) = INPUT delay time (tinput) + Output delay time (toutput) Internal delay time (tINTDEL) = Internal gate delay time (tGATE) + Output delay time (toutput) tCYCLE tINPUT = tGATE + tCYCLE CAN macro Input delay time (tINPUT) CAN macro clock

7.10 FCN timing

Parameter Symbol Condition Ratings Unit Min Typ Max Transfer rate - - 1 Mbps Internal delay time tINTDEL - - 37.5 ns CAN Node delay time tNODE tCYCLE = 62.5ns - - 100 ns

Chapter 7 Periphera ls specification

7.11 FlexRay timing

Parameter Symbol Condition Ratings Unit Min Typ Max Transfer rate - - 10 Mbps Node Output Delay tOUTPUT FLX0TXDA, FLX0TXDB, - - 25 ns FLX0TXENA, FLX0TXENB - - Node Input Delay tINPUT FLX0RXDA, FLX0RXDB - - 10 ns I/O Port I/O Buf I/O Port I/O Buf Pxx/TXDx Pxx/RXDx FRTXDx FRRXDx eray_sclk (internal system clock) Node Input Delay DQ DQ FlexRay macro uCOM device with FlexRay macro Node Output Delay TXDx* FRSCLK (internal clock) FRTXDx (macro output) (chip output) RXDx* (chip input) FRRXDx (macro input) tinput touput

Chapter 7 Periphera ls specification Port Name Condition Ratings Unit Min Typ Max FLX0TXENA FLX0TXENB dTxENRISE-FALL Cload=25pF, measured at 20-80% E1VDD --9 n s dCCTxEN01 - - 25 ns dCCTxEN10 - - 25 ns FLX0TXDA FLX0TXDB dCCTxAsym measured at 50% E1VDD - - 2.45 ns dCCTxDRISE25 + dCCTxDFALL25 Cload=25pF, measured at 20-80% E1VDD --9 n s Cload=10pF, measured at 20-80% E1VDD at the end of a 50ohm, 1ns microstripline --9 n s dCCTxD01 - - - 25 ns dCCTxD10 - - - 25 ns FLX0RXDA FLX0RXDB dCCRxAsmAccept measured at 50% of E1VDD Input signal: Cload=25pF, 6.5ns (20-80% E1VDD) -- 5 . 5 n s C_CCRxD - -- 1 0 p f uLogic_1 - 35 - 70 % uLogic_0 - 30 - 65 % dCCRxD01 - - - 10 ns dCCRxD10 - - - 10 ns

Chapter 7 Periphera ls specification

7.12 IIC timing

Parameter Symbol Condition Ratings Unit Min Typ Max SCL clock period fCLK 0 100 kHz Bus free time (between stop condition and start condition) tBUF 4.7 - - µs Start/Restart Hold time (New clock pulse is generated after this hold time as a master.) tHD:STA 4 - - µs SCL clock low state hold time tLOW 4.7 - - µs SCL clock high state hold time tHIGH 4 - - µs Setup time for start/restart condition tSU:STA 4.7 - - µs Data hold time tHD:DAT CBUS compatible 5 - - µs IIC bus 0 - - µs Data setup time tSU:DAT 250 - - ns Rising transition time of SDA or SCL tR - - 1000 ns Falling transition time of SDA or SCL tF - - 300 ns Setup time of stop condition tSU:STO 4 - - µs Bus capacitance Cb - - 400 pF

Chapter 7 Periphera ls specification Table 7-8 Fast mode Notes 1. P: Stop condition Notes 1. S: Start condition Notes 1. Sr: Restart condition Parameter Symbol Condition Ratings Unit Min Typ Max SCL clock period fCLK 0 - 400 kHz Bus free time (between stop condition and start condition) tBUF 1.3 - - µs Start/Restart Hold time (New clock pulse is generated after this hold time as a master.) tHD:STA 0.6 - - µs SCL clock low state hold time tLOW 1.3 - - µs SCL clock high state hold time tHIGH 0.6 - - µs Setup time for start/restart condition tSU:STA 0.6 - - µs Data hold time tHD:DAT IIC bus 0 - 0.9 µs Data setup time tSU:DAT 100 - - ns Rising transition time of SDA or SCL tR 20+0.1Cb - 300 ns Falling transition time of SDA or SCL tF 20+0.1Cb - 300 ns Setup time of stop condition tSU:STO 0.6 - - µs Noise elimination width tSP 0 - 50 ns Bus capacitance Cb - - 400 pF SCL0 P tSU: S TA tHD: STA tLOW tHI GH tBUF SDA0 tSP tR tHD: DAT tF tSU: D AT S tHD: STA Sr P tSU: S TO

Chapter 7 Periphera ls specification

7.13 Frequency Output Function (FOUT)

Table 7-9 Frequency Output Function (FOUT)

7.14 VLVI characteristics

Table 7-10 VLVI characteristics Note VDD: REG0VDD Parameter Symbol Condition Ratings Unit Min Typ Max CSCXFOUTP output cycle tFO 50 - - ns CSCXFOUTP high level width tWKHFO tFOUT / 2 - 10 - - ns CSCXFOUTP low level width tWKLFO tFOUT / 2 - 10 - - ns CSCXFOUTP rise time tKRFO - - 10 ns CSCXFOUTP fall time tKFFO - - 10 ns Parameter Symbol Condition Ratings Unit Min Typ Max Detection voltage VRAMHF 1.8 1.9 2.0 V Voltage slope1 Rvs1 0.18 - 1800 V/ms Voltage slope2 Rvs2 0.0018 - 1800 V/ms Response time a a) From detection voltage to setting of VLVF bit (VLVF.bit0) tRAMHD - - 2 ms CSCXFOUT tWKHFO tFO tWKLFO tKRFO tKFFO VDD Detectvoltage(MAX.) Detectvoltage(TYP.) Detectvoltage(MIN.) tRAMHDtRAMHD Rvs1 Rvs2 tRAMHD

Chapter 7 Periphera ls specification

7.15 Voltage comparator characteristics

Parameter Symbol Condition Ratings Unit Min Typ Max VCMP current IVCMP - 200 300 µA Threshould voltage (rise) VCMPR 1.745 1.780 1.815 V Threshould voltage (fall) VCMPF 1.645 1.680 1.715 V Voltage slope VCVS - - 50 mV/µs Detection time tVCMPD - - 2 µs Stabilization time tVCMPST VCMP operation readyness after VCPC0OEn is set to 1 --2 m s VCPCnIN VCMPF(MIN.) tVCMPD VCMPR (MAX.) tVCMPD VC PCn OUT n=0,1 VCMPR(TYP.) VCMPR(MIN.) VCMPF(TYP.) VCMPF(MAX.)

Chapter 7 Periphera ls specification

7.16 LVI characteristics

Table 7-11 LVI characteristics Parameter Symbol Condition Ratings Unit Min Typ Max Detection voltage VLVI0 LVICNT.LV ICNT[2:0]=001B 3.9 4.0 4.1 V VLVI1 LVICNT.LV ICNT[2:0]=010B 3.6 3.7 3.8 V VLVI2 LVICNT.LV ICNT[2:0]=011B 3.4 3.5 3.6 V Voltage slope1 LVS1 0.18 - 1800 V/ms Voltage slope2 LVS2 0.0018 - 1800 V/ms Response time tLD - - 2.0 ms VDD minimum width tLW 2 - - ms Stabilization time tLVIST LVICNT0,1 is set to 1, then LVI is ready to operate - - 350 µs VDD tLW Detect voltage(MAX.) Detect voltage(TYP.) Detect voltage(MIN.) tLD tLD LVS1 LVS2

Chapter 7 Periphera ls specification

7.17 A/D Converter characteristics

7.17.1 12bit A/D (for ADC cha nnels without S/H functionality) Table 7-12 12bit A/D Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed specification. 2. m: Number of channels. Refer to the User Manual for the detailed specification. Parameter Symbol Condition Ratings Unit Min Typ Max Resolution RESn 12 12 12 bit Total conversion time TCONn 1.5 - 10 µs Overall error a a) The specification does not include the quantization error. TOEn - - ±6.0 LSB Non-liniarity errora ILEn - - ±2.5 LSB Differencial liniarity errora DLEn - - ±1.5 LSB Zero scale errora ZSEn - - ±5.0 LSB Full scale errora FSEn - - ±5.0 LSB Analog input voltagea VAIN AnVREFM AnVREFP V Power on stabilization timeb b) ‘Power on’ refers to - setting ADCAnGPS = 1 --1 µ s AnVDD current AIDDn ADAnBPC=0, withDiagnosis function -4 . 0 6 . 3 m A ADAnBPC=0, w/o Diagnosis function -5 . 2 8 . 1 m A ADAnBPC=1, with Diagnosis function -4 . 6 7 . 4 m A ADAnBPC=1, w/o Diagnosis function -6 . 2 9 . 2 m A AIDDnPD Power down - 1 - µA AnVREFP current AIREFn - 650 - µA Conversion result by Diagnosis functionc c) The values given do not include influence of injected current TESHn AnVDD was converted 4015 - 4095 LSB TESHLn3 2/3 AnVDD was converted 2691 2731 2771 LSB TESHLn2 1/2 AnVDD was converted 2018 2048 2078 LSB TESHLn1 1/3 AnVDD was converted 1325 1365 1405 LSB TESLn AGND was converted 0 - 80 LSB

Chapter 7 Periphera ls specification 7.17.2 12bit A/D (For channel ADCA 0I0-5 when the S/H function is not used) Table 7-13 12bit A/D (When channel Sample & Hold function is not used) Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed specification. 2. m: Number of channels. Refer to the User Manual for the detailed specification. Parameter Symbol Condition Ratings Unit Min Typ Max Resolution RES0SN 12 12 12 bit Total conversion time TCON0SN 1.5 - 10 µs Overall errora a) The specification does not include the quantization error. TOE0SN - - ±6.0 LSB Non-liniarity errora ILE0SN - - ±2.5 LSB Differencial liniarity errora DLE0SN - - ±1.5 LSB Zero scale errora ZSE0SN - - ±5.0 LSB Full scale errora FSE0SN - - ±5.0 LSB Analog input voltagea VAIN0SN A0VREFM - A0VREFP V Power on stabilization timeb b) ‘Power on’ refers to - setting ADCAnGPS = 1 --1 µ s A0VDD current AIDD0SN ADA0BPC=0, withDiagnosis function -4 . 0 6 . 3 m A ADA0BPC=0, w/o Diagnosis function -5 . 2 8 . 1 m A ADA0BPC=1, with Diagnosis function -4 . 6 7 . 4 m A ADA0BPC=1, w/o Diagnosis function -6 . 2 9 . 2 m A AIDD0SNPD Power down - 1 - µA A0VREFP current AIREF0SN - 650 - µA Conversion result by Diagnosis functionc c) The values given do not include influence of injected current TESH0SN A0VDD was converted 4015 - 4095 LSB TESHL0SN3 2/3 A0VDD was converted 2691 2731 2771 LSB TESHL0SN2 1/2 A0VDD was converted 2018 2048 2078 LSB TESHL0SN1 1/3 A0VDD was converted 1325 1365 1405 LSB TESL0SN AGND was converted 0 - 80 LSB

Chapter 7 Periphera ls specification 7.17.3 12bit A/D (When channe l S/H function is used) Table 7-14 12bit A/D (When channel Sample & Hold function is used [ADCA0I0 to ADCA0I5]) Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed specification. 2. m: Number of channels. Refer to the User Manual for the detailed specification. 3. AIDDn + 1.72mA x (number of channels used with S/H) Parameter Symbol Condition Ratings Unit Min Typ Max Resolution RES0S 12 12 12 bit Total conversion time TCON0SN 1.8 - 12 µs Sample & Hold time 50 - - µs Overall error a a) The specification does not include the quantization error. TOE0S - - ±8.0 LSB Non-liniarity errora ILE0S - - ±4.0 LSB Differencial liniarity errora DLE0S - - ±2.5 LSB Zero scale errora ZSE0S - - ±6.0 LSB Full scale errora FSE0S - - ±6.0 LSB Analog input voltage VAIN0S 0.2 - A0VREFP-0.2 V Power on stabilization time b b) ‘Power on’ refers to - setting ADCAnGPS = 1 -- 1 µ s A0VDD current AIDD0S withDiagnosis function - Note3 22.1 mA w/o Diagnosis function - Note3 24.0 mA AIDD0SPD Power down - 1 - µA A0VREFP current AIREF0S - 650 - µA Conversion result by Diagnosis functionc c) The values given do not include influence of injected current TESHLS3 2/3 A0VDD was converted 2689 2731 2773 LSB TESHLS2 1/2 A0VDD was converted 2016 2048 2080 LSB TESHLS1 1/3 A0VDD was converted 1323 1365 1407 LSB

Chapter 7 Periphera ls specification 7.17.4 10bit A/D (for ADC cha nnels without S/H functionality) Table 7-15 10 bit A/D Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed specification. 2. m: Number of channels. Refer to the User Manual for the detailed specification. Parameter Symbol Condition Ratings Unit Min Typ Max Resolution RESn 10 10 10 bit Total conversion time TCONn 1.5 10 µs Overall error a a) The specification does not include the quantization error. TOEn Excluding quantization error - - ±2.0 LSB Non-liniarity errora ILEn - - ±1.5 LSB Differencial liniarity errora DLEn - - ±1.0 LSB Zero scale errora ZSEn - - ±1.5 LSB Full scale errora FSEn - - ±1.5 LSB Analog input voltagea VAIN AnVREFM AnVREFP V Power on stabilization timeb b) ‘Power on’ refers to - setting ADCAnGPS = 1 -1 µ s AnVDD current AIDDn ADAnBPC=0, withDiagnosis function -4 . 0 6 . 3 m A ADAnBPC=0, w/o Diagnosis function -5 . 2 8 . 1 m A ADAnBPC=1, with Diagnosis function -4 . 6 7 . 4 m A ADAnBPC=1, w/o Diagnosis function -6 . 2 9 . 2 m A AIDDnPD Power down - 1 - µA AnVREFP current AIREFn - 500 - µA Conversion result by Diagnosis functionc c) The values given do not include influence of injected current TESHn AnVDD was converted 1003 1023 LSB TESHLn3 2/3 AnVDD was converted 673 683 693 LSB TESHLn2 1/2 AnVDD was converted 504 512 520 LSB TESHLn1 1/3 AnVDD was converted 331 341 351 LSB TESLn AGND was converted 0 20 LSB

Chapter 7 Periphera ls specification 7.17.5 10bit A/D (For channel ADCA 0I0-5 when the S/H function is not used) Table 7-16 10 bit A/D Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed specification. 2. m: Number of channels. Refer to the User Manual for the detailed specification. 3. AIDDn + 1.72mA x (number of channels used with S/H) Parameter Symbol Condition Ratings Unit Min Typ Max Resolution RES0SN 10 10 10 bit Total conversion time TCON0SN 1.5 10 µs Overall errora a) The specification does not include the quantization error. TOE0SN - - ±2.0 LSB Non-liniarity errora ILE0SN - - ±1.5 LSB Differencial liniarity errora DLE0SN - - ±1.0 LSB Zero scale errora ZSE0SN - - ±1.5 LSB Full scale errora FSE0SN - - ±1.5 LSB Analog input voltagea VAIN0SN AnVREFM AnVREFP V Power on stabilization timeb b) ‘Power on’ refers to - setting ADCAnGPS = 1 --1 µ s AnVDD current AIDD0SN ADAnBPC=0, withDiagnosis function -4 . 0 6 . 3 m A ADAnBPC=0, w/o Diagnosis function -5 . 2 8 . 1 m A ADAnBPC=1, with Diagnosis function -4 . 6 7 . 4 m A ADAnBPC=1, w/o Diagnosis function -6 . 2 9 . 2 m A AIDD0SNPD Power down - 1 - µA AnVREFP current AIREF0SN - 500 - µA Conversion result by Diagnosis functionc c) The values given do not include influence of injected current TESH0SN AnVDD was converted 1003 - 1023 LSB TESHL0SN3 2/3 AnVDD was converted 673 683 693 LSB TESHL0SN2 1/2 AnVDD was converted 504 512 520 LSB TESHL0SN1 1/3 AnVDD was converted 331 341 351 LSB TESL0SN AGND was converted 0 - 20 LSB

Chapter 7 Periphera ls specification 7.17.6 10bit A/D (When channe l S/H function is used) Table 7-17 10 bit A/D Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed specification. 2. m: Number of channels. Refer to the User Manual for the detailed specification. Parameter Symbol Condition Ratings Unit Min Typ Max Resolution RES0S 10 10 10 bit Total conversion time TCON0S 1.84 - 12.2 µs Sample & Hold time 50 - - µs Overall error a a) The specification does not include the quantization error. TOE0S - - ±2.5 LSB Non-liniarity errora ILE0S - - ±2.0 LSB Differencial liniarity errora DLE0S - - ±1.5 LSB Zero scale errora ZSE0S - - ±2.0 LSB Full scale errora FSE0S - - ±2.0 LSB Analog input voltagea VAIN0S 0.2 - A0VREFP- 0.2 V Power on stabilization timeb b) ‘Power on’ refers to - setting ADCAnGPS = 1 --1 µ s AnVDD current AIDD0S ADAnBPC=1, with Diagnosis function - c c) AIDDn x 1.72 x the number of used channels with Sample & Hold 22.1 mA ADAnBPC=1, w/o Diagnosis function - c 24.0 mA AIDD0SPD Power down - 1 - µA AnVREFP current AIREF0S - 500 - µA Conversion result by Diagnosis functiond d) The values given do not include influence of injected current TESHL0S3 2/3 AnVDD was converted 672 683 694 LSB TESHL0S2 1/2 AnVDD was converted 503 512 521 LSB TESHL0S1 1/3 AnVDD was converted 330 341 352 LSB

Chapter 7 Periphera ls specification

7.17.7 Equivalent circuit

Caution These specifications are not tested in outgoing inspection. Therefore RIN and CIN values are not guaranteed and are reference values only. Additionally these values are specified as maximum values.

7.17.8 ADTRG timing

Notes 1. n: Number of macro instances. Refer to the User Manual for the detailed specification. 2. m: Number of channels. Refer to the User Manual for the detailed specification. RIN CIN ADCAnIm (n=0, m=0-23) (n=1, m=0-23) RIN CIN ADCAnIm (n=0, m=0-23) (n=1, m=0-23) Terminals Condition RIN[kΩ] CIN[pF] ADCA0I0-ADCA0I5 When S&H is used 0.7 3.6 When S&H is not used ADA0BPC=0 1.6 12.6 ADA0BPC=1 1.5 7.1 ADCA0I6-ADCA0I23 ADA0BPC=0 1.2 11.9 ADA0BPC=1 1.1 7.1 ADCA1I0-ADCA1I23 ADA0BPC=0 1.2 11.9 ADA0BPC=1 1.1 7.1 Parameter Symbol Condition Ratings Unit Min Typ Max ADCAnTRGm input High level width tWADH with digital noise filter a a) 2, 3, 4 or 5 x Tsamp + 20 (Tsamp shows sampling period specified in noise filter). More than 1 PCLK width of ADC macro must be kept regarding DNF pass through pulse width. -- n s without digital noise filter b b) 1 × tSYNC+20 ( tSYNC: 1 PCLK of ADC macro) -- n s ADCAnTRGm input Low level width tWADL with digital noise filter a -- n s without digital noise filter b -- n s

Chapter 7 Periphera ls specification

7.18 Key Return

Note n: Number of instances. Refer to the User Manual for the detailed specification. Parameter Symbol Condition Ratings Unit Min Typ Max KRn input High level width tWKRH 300 - - ns KRn input Low level width tWKRL 300 - - ns tWADH tWADL ADCAn tWNIH tWNIL NMI

Chapter 8 Memory specification Chapter 8 Memory specification

8.1 Code flash specification

8.2 Data flash specification

8.3 Serial write operation specification

Parameter Symbol Condition Ratings Unit Min Typ Max Number of Re-Writesa a) Please contact RENESAS sales office regarding specification other than the above. CWRT Data retention 20 years - - 100 times Programming Temperature tPRG (A) grade products -40 - 85 °C (A1) grade products -40 - 110 °C (A2) grade products -40 - 125 °CParameter Symbol Condition Ratings Unit Min Typ Max Number of Re-Writesa a) Please contact RENESAS sales office regarding specification other than the above. DWRT1 Data retention 20 years - - 1000 times DWRT2 Data retention 15 years - - 5000 times DWRT3 Data retention 5 years - - 15000 times Programming Temperature tPRG (A) grade products -40 - 85 °C (A1) grade products -40 - 110 °C (A2) grade products -40 - 125 °C Parameter Symbol Condition Ratings Unit Min Typ Max FLMD0 setup time tDR 1 - - ms RESET release tPR 2 - - ms FLMD0 pulse input start tRP - 100 - ms FLMD0 low/high level width tPW 10 - 100 µs FLMD0 raise time tR - - 20 ns FLMD0 fall time tF - - 20 ns Programming time per 128 bit - - 50 µs Erase time per 4KB - - 54 ms

Chapter 9 Pinning and package specification Chapter 9 Pinning and package specification

9.1 Pinning specification

(1) M1 Product P21_3 P21_2 REG3VDD REG3C REG3VSS 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 _RESET REG0VDD REG0C REG0VSS WAKE E0VDD VCPC1IN VCPC0IN JP0_0 JP0_1 JP0_2 JP0_3 JP0_4 JP0_5 OSCVSS OSCVDD XT2 XT1 P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 P0_8 P0_9 P0_10 E0VDD P0_11 P0_12 P0_15 P0_14 P0_13 FLMD0 FVDD P12_3 P12_2 P12_1 P12_0 P21_6 P21_5 B0VDD P27_4 P27_3 REG1VDD REG1C REG1VSS P2_1 P2_0 E1VDD E1VSS REG2VDD REG2C REG2VSS ADCA0I5 ADCA0I4 ADCA0I3 ADCA0I2 ADCA0I1 ADCA0I0 P10_15 P10_14 P10_13 P10_12 P10_11 P10_10 P10_9 P10_8 P10_7 P10_6 A0VREFM A0VREFP A0VSS A0VDD P21_4 P27_5 P27_2 P27_1 B0VDD P27_0 P25_15 P25_14 P25_13 P25_12 P25_11 P25_10 P25_9 P25_8 P25_7 P25_6 P25_5 P25_4 B0VDD P25_3 P25_2 P25_1 P25_0 P21_11 P21_10 P21_9 P21_8 P21_7 P12_15 P12_14 P12_13 P12_12 P12_11 P12_10 P12_9 P12_8 P12_7 P12_6 P12_5 P12_4 A1VREFM A1VREFP A1VSS A1VDD P4_11 P4_10 P4_9 E1VDD P4_8 P4_7 P4_6 P4_5 P4_4 P4_3 P4_2 P4_1 P4_0 P3_9 P3_8 P3_7 P3_6 P3_5 P3_4 P2_2 P1_15 P1_14 P1_13 P1_12 E1VDD P1_11 P1_10 P1_9 P1_8 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P11_0 B0VSS V850E2/FK4 M1 V850E2/FKG4 103 102 101 100 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 P3_3 P3_2 P3_1 P3_0

Chapter 9 Pinning and package specification (2) M2 Product P21_3 P21_2 NC CVDD CVSS 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 _RESET REG0VDD REG0C REG0VSS WAKE E0VDD VCPC1IN VCPC0IN JP0_0 JP0_1 JP0_2 JP0_3 JP0_4 JP0_5 OSCVSS OSCVDD XT2 XT1 P0_0 P0_1 P0_2 P0_3 P0_4 P0_5 P0_6 P0_7 P0_8 P0_9 P0_10 E0VDD P0_11 P0_12 P0_15 P0_14 P0_13 FLMD0 FVDD P12_3 P12_2 P12_1 P12_0 P21_6 P21_5 B0VDD P27_4 PTCTL1 REG1VDD CVDD REG1VSS P2_1 P2_0 E1VDD E1VSS NC CVDD CVSS ADCA0I5 ADCA0I4 ADCA0I3 ADCA0I2 ADCA0I1 ADCA0I0 P10_15 P10_14 P10_13 P10_12 P10_11 P10_10 P10_9 P10_8 P10_7 P10_6 A0VREFM A0VREFP A0VSS A0VDD P21_4 P27_5 P27_2 P27_1 B0VDD P27_0 P25_15 P25_14 P25_13 P25_12 P25_11 P25_10 P25_9 P25_8 P25_7 P25_6 P25_5 P25_4 B0VDD P25_3 P25_2 P25_1 P25_0 P21_11 P21_10 P21_9 P21_8 P21_7 P12_15 P12_14 P12_13 P12_12 P12_11 P12_10 P12_9 P12_8 P12_7 P12_6 P12_5 P12_4 A1VREFM A1VREFP A1VSS A1VDD P4_11 P4_10 P4_9 E1VDD P4_8 P4_7 P4_6 P4_5 P4_4 P4_3 P4_2 P4_1 P4_0 P3_9 P3_8 P3_7 P3_6 P3_5 P3_4 P2_2 P1_15 P1_14 P1_13 P1_12 E1VDD P1_11 P1_10 P1_9 P1_8 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 P1_1 P11_7 P11_6 P11_5 P11_4 P11_3 P11_2 P11_1 P11_0 B0VSS V850E2/FK4 103 102 101 100 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 P3_3 P3_2 P3_1 P3_0

Chapter 9 Pinning and package specification

9.2 Package specification

Chapter 10 Definition of terms Chapter 10 Definition of terms The following sections describe the meaning of several terms used in this document.

10.1 How to Read A/D Conver ter Characteristics Table

This section describes the meanings of the terms peculiar to the A/D converter. (1) Resolution The minimum analog input voltage that can be identified, i.e. the ratio of the analog input voltage to 1 digital output is called 1 LSB (Least Significant Bit). The ratio of 1 LSB to the full scale is expressed as %FSR (Full Scale Range). %FSR is the ratio, in percentage, of the range in which an analog input voltage can be converted, and is expressed as follows regardless of the resolution. 1%FSR = (Maximum value of analog input voltage that can be converted − Minimum value of analog input voltage that can be converted)/100 = (AV REFP − AVREFM)/100

1 LSB is as follows at a resolution of 10 bits:

1 LSB = 1/2 10

= 1/1,024 = 0.098%FSR

1 LSB is as follows at a resolution of 12 bits:

1 LSB = 1/2 12

= 1/4,096 = 0.024%FSR The accuracy is determined by the total error, regardless of the resolution.

Chapter 10 Definition of terms (2) Total error This is the maximum value of the difference between the actually measured value and the theoretical value. It is the total of the zero-scale error, full-scale error, linearity error, and a combination of these errors. The total error shown in the characteristics table does not include the quantization error. Figure 10-1 Total error 1………1 0………0 AVREFPAVREFM Total error Digital output Analog input Ideal linearity

Chapter 10 Definition of terms (3) Quantization error This is the error of ±1/2 LSB that always occurs when an analog value is converted into a digital value. Because the A/D converter converts an analog input voltage in a range of ±1/2 LSB into the same digital code, the quantization error is unavoidable. Note that this error is not included in the total error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 10-2 Quantization error 1………1 0………0 AVREFPAVREFM 1/2LSB 1/2LSB Quantization error Digital output Analog input Quantization error

Chapter 10 Definition of terms (4) Zero-scale error This is the difference between the actually measured value of the analog input voltage and the theoretical value (1/2 LSB) when the digital output changes from 0…000 to 0…001. Figure 10-3 Zero-scale error 111 000 Ideal linearity Analog input AVREFPAVREFM Digital output (lower 3 bits) Zero-scale error AVREFM 001 100 010 011 AVREFM +2x AVREFM +3x AVREFM Note: x: Voltage equivalent to 1 LSB x = (AVREP − AVREFM) × 1 LSB

Chapter 10 Definition of terms (5) Full-scale error This is the difference between the actually measured value of the analog input voltage and the theoretical value (full scale -3/2 LSB) when the digital output changes from 1…110 to 1…111. Figure 10-4 Full-scale error 111 000 Analog input AVREFP Digital output (lower 3 bits) Full-scale error 100 010 011 AVREFM AVREFP AVREFP −2x AVREFP −3x Note: x: Voltage equivalent to 1 LSB x = (AVREP - AVREFM) × 1 LSB

Chapter 10 Definition of terms (6) Differential linearity error Ideally, the width at which a specific code is output is 1 LSB. The differential linearity error is the difference between the actually measured value of the width at which a specific code is output and the ideal value. Figure 10-5 Differential linearity error 1………1 0………0 AVREFPAVREFM Non- differential linearity Digital output Analog input Ideal width of 1 LSB

Chapter 10 Definition of terms (7) Integral linearity error This indicates the degree to which the conversion characteristic shifts from the ideal linearity, and indicates the maximum value of the difference between the actually measured value and the ideal linearity where the zero-scale error and full-scale error are 0. Figure 10-6 Integral linearity error (8) Conversion time This is the time from when an analog voltage is input until digital output is produced. The conversion time in the characteristics table includes sampling time. (9) Sampling time This is the time during which the analog switch is on to input the analog voltage to the sample & hold circuit. (10) A/D start time This is the time from the A/D conversion trigger to the start of A/D conversion. Ideal linearity 1………1 0………0 Integral linearity error Analog input AVREFPAVREFM Digital output

Revision History

Version Date Document number Description 1.0 2013-05-24 R01DS0141ED0100 Initial version Document was EASE-DS-0029-1.3 Changes: - RIVS ISO0/ISO1 regulator value was 1.8V/µs is 5600V/s - Added FLMD0 / FLMD1 resistor values - Package drawing updated