V751180330PDSQRG4

TLV751 TI | Alldatasheet

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Technical content

Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLV751 SBVS385B –DECEMBER 2019–REVISED APRIL 2020 TLV751Dual,500-mA,High-Accuracy,LDOinaSmall-SizePackage

1 Features

1• Input voltage range: 1.5 V to 6.0 V

• Output voltage range: – Adjustable option: 0.55 V to 5.5 V – Fixed option: 0.65 V to 5.0 V
• Low dropout: – 130 mV (max) at 500 mA (3.3 VOUT)
• High output accuracy: 1.5% (maximum over temperature)
• IQ: 25 µA (typical)
• Built-in soft-start with monotonic VOUT rise
• Package: – 2-mm × 2-mm WSON-10 (DSQ)
• Active output discharge

2 Applications

• Microservers and tower servers
• Door and window sensors
• Portable point-of-sale (EPOS)
• Wearable fitness and activity monitors
• Scanners
• Wi-Fi access points
• Communication modules

3 Description

The TLV751 is a dual, adjustable, 500-mA low- dropout (LDO) regulator. This device is available in a small, 10-pin, 2-mm × 2-mm WSON package and consumes 25-µA quiescent current while providing fast line and load transient response. The TLV751 features an low dropout of 130 mV that can help improve the overall power efficiency. The TLV751 wide input-and-output voltage ranges, when combined with its output current capability in a small printed circuit board (PCB) footprint help support a wide variety of applications from sensor supplies, to auxiliary rails, and modern microcontrollers with lower core voltages. The TLV751 is stable with small ceramic output capacitors, allowing for a small overall solution size. A precision band-gap and error amplifier provides high accuracy of 1.5% (max) over temperature. This device includes integrated thermal shutdown, current limit, active output-discharge, and undervoltage lockout (UVLO) features. The TLV751 has an internal fold-back current-limit to reduce thermal dissipation during short-circuit events. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLV751 WSON (10) 2.00 mm × 2.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) Preview device. Typical Application

SBVS385B –DECEMBER 2019–REVISED APRIL 2020 www.ti.com Product Folder Links: TLV751 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Table of Contents

11.2 Receiving Notification of Documentation Updates 23

12 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (February 2020) to Revision B Page Changes from Original (December 2019) to Revision A Page

8 OUT2

9 IN1

10 OUT1

7 FB2

www.ti.com SBVS385B –DECEMBER 2019–REVISED APRIL 2020 Product Folder Links: TLV751 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

5 Pin Configuration and Functions

(Adjustable) DSQ (Fixed) EN1 3 3 Input Enable pin. Drive EN1 greater than VEN1(HI) to turn on the regulator. Drive EN1 less than VEN1(LO) to put the low-dropout (LDO) regulator into shutdown mode. EN2 5 5 Input Enable pin. Drive EN2 greater than VEN2(HI) to turn on the regulator. Drive EN2 less than VEN2(LO) to put the LDO into shutdown mode. FB1 1 — — For the adjustable version, this pin is used as an input to the control loop error amplifier and is used to set the output voltage of the LDO. FB2 7 — — For the adjustable version, this pin is used as an input to the control loop error amplifier and is used to set the output voltage of the LDO. GND 2, 4 2, 4 — Ground pin IN1 9 9 Input Input pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground; see the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the input capacitor as close to the output of the device as possible. IN2 6 6 Input Input pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground; see the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the input capacitor as close to the output of the device as possible. NC — 1, 7 — For the fixed version, this pin is not connected internally. OUT1 10 10 Output Regulated output voltage pin. A capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to ground; see the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the output capacitor as close to output of the device as possible. OUT2 8 8 Output Regulated output voltage pin. A capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to ground; see the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the output capacitor as close to output of the device as possible. Thermal pad — Connect the thermal pad to a large area GND plane for improved thermal performance.

SBVS385B –DECEMBER 2019–REVISED APRIL 2020 www.ti.com Product Folder Links: TLV751 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability. (2) The absolute maximum rating is VIN + 0.3V or 6.5 V, whichever is smaller.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Voltage Supply, VIN –0.3 6.5 V Enable, VEN –0.3 6.5 Feedback, VFB –0.3 2 Voltage Output, VOUT –0.3 VIN + 0.3(2) Temperature Operating junction, TJ –40 150 Storage, Tstg –65 150 (1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM ispossible with the necessary precautions. (2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM ispossible with the necessary precautions.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) Minimum derated capacitance of 0.47 µF is required for stability (2) If VEN > VIN, when VEN > VUVLO rising (min), the input pin (IN) must sink 1 mA of current to avoid the device being turn on with floating input pin.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT VIN Input voltage 1.5 6.0 V VOUT Output voltage 0.55 5.5 V IOUT Output current 0 500 mA CIN Input capacitor 1 µF COUT Output capacitor(1) 1 220 µF VEN Enable voltage(2) 0 6.0 V fEN Enable toggle frequency 10 kHz TJ Junction temperature –40 125 °C

www.ti.com SBVS385B –DECEMBER 2019–REVISED APRIL 2020 Product Folder Links: TLV751 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated (1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) TLV751P UNITDSQ (WSON)

10 PINS

RθJA Junction-to-ambient thermal resistance 74.6 °C/W RθJC(top) Junction-to-case (top) thermal resistance 90.5 °C/W RθJB Junction-to-board thermal resistance 39.7 °C/W ψJT Junction-to-top characterization parameter 3.8 °C/W ψJB Junction-to-board characterization parameter 39.7 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 17 °C/W (1) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included. (2) VIN = 1.5 V for VOUT < 1.0 V. (3) VIN = 2.0 V for VOUT < 1.5 V.

6.5 Electrical Characteristics

At operating temperature range (TJ = –40°C to +125°C),VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever isgreater), IOUT = 1 mA, VEN =VIN, and CIN = COUT = 1 uF(unless otherwise noted); all typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VFB Feedback voltage TJ = 25°C 0.55 V Output accuracy(1) TJ = 25°C –0.5% 0.5% Line regulation VOUT(NOM) + 0.5 V(2) ≤ VIN ≤ 6.0 V 2 mV Load regulation 0.1 mA ≤ IOUT ≤ 500 mA, VIN = VOUT + 0.5 V(3) 0.030 V/A IGND Ground current IOUT = 0 mA TJ = 25°C 10 25 31 µA –40°C ≤ TJ ≤ +125°C 35 µA ISHDN Shutdown current VEN ≤ 0.3 V, 1.5 V ≤ VIN ≤ 6.0 V 0.1 1 µA IFB Feedback pin current 0.01 0.1 µA ICL Output current limit VIN = 2 V with VOUT < 1 V; otherwise VIN = VOUT(NOM) + 1.0 V VOUT = VOUT(NOM) – 0.2 V, VOUT < 1.5 V 530 720 865 mA VOUT = 0.9 V × VOUT(NOM), VOUT ≥ 1.5 V 530 720 865 ISC Short-circuit current limit VIN = 2 V with VOUT < 1 V; otherwise VIN = VOUT(NOM) + 1.0 V VOUT = 0 V 310 400 mA VDO Dropout voltage IOUT = 500 mA, VOUT = 0.95 × VOUT(NOM) 0.65 V ≤ VOUT < 0.8 V 720 880 mV 0.8 V ≤ VOUT < 1.0 V 585 750 1.0 V ≤ VOUT < 1.2 V 420 570 1.2 V ≤ VOUT < 1.5 V 285 400 1.5 V ≤ VOUT < 1.8 V 180 240 1.8 V ≤ VOUT < 2.5 V 140 190 2.5 V ≤ VOUT < 3.3 V 102 140 3.3 V ≤ VOUT ≤ 5.5 V 95 130 PSRR Power-supply rejection ratio VIN = VOUT(NOM) + 1.0 V, IOUT = 50 mA f = 1 kHz 50 dBf = 100 kHz 45 f = 1 MHz 30 Vn Output noise voltage BW = 10 Hz to 100 kHz, VOUT = 0.9 V 53 µVRMS VUVLO Undervoltage lockout VIN rising 1.21 1.33 1.47 V VIN falling 1.17 1.29 1.42 V VUVLO, HYST Undervoltage lockout hysteresis VIN hysteresis 45 mV tSTR Startup time From EN low-to-high transition to VOUT = VOUT(NOM) × 95% 500 700 µs VEN(HI) EN pin high voltage 1.0 V VEN(LO) EN pin low voltage 0.3 V IEN Enable pin current VIN = EN = 6.0 V 10 nA

SBVS385B –DECEMBER 2019–REVISED APRIL 2020 www.ti.com Product Folder Links: TLV751 Submit Documentation Feedback Copyright © 2019–2020, Texas Instruments Incorporated Electrical Characteristics (continued) At operating temperature range (TJ = –40°C to +125°C),VIN = VOUT(NOM) + 0.5 V or 1.5 V (whichever isgreater), IOUT = 1 mA, VEN =VIN, and CIN = COUT = 1 uF(unless otherwise noted); all typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RPULL DOWN Pulldown resistance VIN = 6.0 V 95 Ω TSD Thermal shutdown Shutdown, temperature increasing 170 Reset, temperature decreasing 155

6.6 Typical Characteristics

Figure 1. 3.3-V Line Regulation vs VIN Figure 2. 0.55-V Line Regulation vs VIN Figure 3. 5.5-V Line Regulation vs VIN Figure 4. 3.3-V Dropout Voltage vs IOUT Figure 5. 0.55-V Dropout Voltage vs IOUT Figure 6. 5.5-V Dropout Voltage vs IOUT

www.ti.com SBVS385B –DECEMBER 2019–REVISED APRIL 2020 Product Folder Links: TLV751 Submit Documentation FeedbackCopyright © 2019–2020, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TLV751 low-dropout regulator (LDO) consumes low quiescent current and delivers excellent line and load transient performance. These characteristics, combined with low noise and good PSRR with low dropout voltage, make this device ideal for portable consumer applications. This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature for this device is –40°C to +125°C.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Undervoltage Lockout (UVLO)

The TLV751 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is greater than the rising UVLO voltage (VUVLO). This circuit ensures that the device does not exhibit any unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry. When VIN is less than VUVLO, the output is connected to ground with a pulldown resistor (RPULLDOWN).

7.3.2 Shutdown

The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI). Turn off the device by forcing the EN pin to drop below VEN(LO). If shutdown capability is not required, connect EN to IN. The TLV751 has an internal pulldown MOSFET that connects an RPULLDOWN resistor to ground when the device is disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel with the pulldown resistor (RPULLDOWN). Equation 1 calculates the time constant: τ = ( RPULLDOWN × RL) / (RPULLDOWN + RL) (1)

7.3.3 Foldback Current Limit

The device has an internal current limit circuit that protects the regulator during transient high-load current faults or shorting events. The current limit is a hybrid brickwall-foldback scheme. The current limit transitions from a brickwall scheme to a foldback scheme at the foldback voltage (VFOLDBACK). In a high-load current fault with the output voltage above VFOLDBACK, the brickwall scheme limits the output current to the current limit (ICL). When the voltage drops below VFOLDBACK, a foldback current limit activates that scales back the current as the output voltage approaches GND. When the output is shorted, the device supplies a typical current called the short- circuit current limit (ISC). ICL and ISC are listed in the Electrical Characteristics table.

For this device, VFOLDBACK = 0.4 V × VOUT(NOM). more information on current limits, see the Know Your Limits application report. Figure 37 shows a diagram of the foldback current limit. Figure 37. Foldback Current Limit

7.3.4 Thermal Shutdown

Thermal shutdown protection disables the output when the junction temperature rises to approximately 170°C. dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits regulator dissipation, protecting the LDO from damage as a result of overheating. thermal protection is triggered; use worst-case loads and signal conditions. normal operation. Continuously running the TLV751 into thermal shutdown degrades device reliability.

7.4 Device Functional Modes

7.4.1 Device Functional Mode Comparison

operation. See the Electrical Characteristics table for parameter values. Table 1. Device Functional Mode Comparison

7.4.2 Normal Operation

• The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(nom) + VDO)
• The output current is less than the current limit (IOUT < ICL)
• The device junction temperature is less than the thermal shutdown temperature (TJ < TSD)
• The enable voltage has previously exceeded the enable rising threshold voltage and has not yet decreased to less than the enable falling threshold

7.4.3 Dropout Operation

transients in dropout can result in large output-voltage deviations. while the device pulls the pass transistor back into the linear region.

7.4.4 Disabled

discharge circuit from the output to ground.

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Adjustable Device Feedback Resistors

Figure 38. Adjustable Operation For this device, VFB = 0.55 V. For this device, IFB = 10 nA.

8.1.2 Input and Output Capacitor Selection

maximum recommended output capacitance is 220 µF. inches from the input power source.

8.1.3 Dropout Voltage

(VIN – VOUT) approaches dropout operation.

8.1.4 Exiting Dropout

Some applications have transients that place the LDO into dropout, such as slower ramps on VIN during start-up. range. Use an enable signal to avoid this condition. Figure 39. Startup Into Dropout slow enough to reduce the overshoot.

Figure 40. Line Transients From Dropout

8.1.5 Reverse Current

As with most LDOs, excessive reverse current can damage this device.

• Degradation caused by electromigration
• Excessive heat dissipation
• Potential for a latch-up condition Conditions where reverse current can occur are outlined in this section, all of which can exceed the absolute maximum rating of VOUT > VIN + 0.3 V:
• If the device has a large COUT and the input supply collapses with little or no load current
• The output is biased when the input supply is not established
• The output is biased above the input supply

If reverse current flow is expected in the application, external protection must be used to protect the device. Figure 41 shows one approach of protecting the device. Figure 41. Example Circuit for Reverse Current Protection Using a Schottky Diode

8.1.6 Power Dissipation (PD)

other heat-generating devices that cause added thermal stress. and load conditions. Equation 4 calculates power dissipation (PD). minimum input voltage required for correct output regulation. array of plated vias that conduct heat to additional copper planes for increased heat dissipation. The maximum power dissipation determines the maximum allowable ambient temperature (TA) for the device. standard PCB and copper-spreading area, and is used as a relative measure of package thermal performance.

8.1.7 Feed-Forward Capacitor (CFF)

the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability. Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report.

8.2 Typical Application

Figure 42. TLV751 Typical Application

8.2.1 Design Requirements

Use the parameters listed in Table 2 for typical linear regulator applications. Table 2. Design Parameters

8.2.2 Detailed Design Procedure

Input and Output Capacitor Selection section for details. Figure 38 illustrates the output voltage of the TLV751; set the output voltage using the resistor divider.

8.2.2.1 Input Current

During normal operation, the input current to the LDO is approximately equal to the output current of the LDO. Equation 6 to calculate the current through the input.

• VOUT(t) is the instantaneous output voltage of the turn-on ramp
• dVOUT(t) / dt is the slope of the VOUT ramp
• RLOAD is the resistive load impedance (6)

8.2.2.2 Thermal Dissipation

shows and add the ambient temperature (TA) to calculate the junction temperature (TJ). Calculate the maximum ambient temperature as Equation 9 shows if the (TJ(MAX)) value does not exceed 125°C. Equation 10 calculates the maximum ambient temperature with a value of 104.93°C.

8.2.3 Application Curve

Figure 43. PSRR vs Frequency and ILOAD

9 Power Supply Recommendations

Connect a low output impedance power supply directly to the IN pin of the TLV751.

10 Layout

10.1 Layout Guidelines

• Place input and output capacitors as close to the device as possible.
• Use copper planes for device connections, in order to optimize thermal performance.
• Place thermal vias around the device to distribute the heat.
• Do not place a thermal via directly beneath the thermal pad of the DSQ package. A via can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder joint on the thermal pad.

10.2 Layout Example

Figure 44. DSQ Package Layout Example

device product folder on www.ti.com. (2) Output voltages from 0.6 V to 5.0 V in 50-mV increments are available. Contact the factory for details and availability.

11 Device and Documentation Support

11.1 Device Support

11.1.1 Device Nomenclature

Table 3. Device Nomenclature(1)(2) TLV75101Pyyyz yyy is the package designator. z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces). yyy is the package designator. z is the package quantity. R is for reel (3000 pieces).

11.2 Receiving Notification of Documentation Updates

changed. For change details, review the revision history included in any revised document.

11.3 Support Resources

from the experts. Search existing answers or ask your own question to get the quick design help you need. not necessarily reflect TI's views; see TI's Terms of Use.

11.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge Caution

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

11.6 Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 17-Jun-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) PTLV75101PDSQR Obsolete Preproduction WSON (DSQ) | 10 - - Call TI Call TI - TLV75101PDSQR Active Production WSON (DSQ) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1XUH TLV75101PDSQR.A Active Production WSON (DSQ) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1XUH TLV75101PDSQT Active Production WSON (DSQ) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1XUH TLV75101PDSQT.A Active Production WSON (DSQ) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1XUH TLV75101PDSQTG4 Active Production WSON (DSQ) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1XUH TLV75101PDSQTG4.A Active Production WSON (DSQ) | 10 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1XUH TLV751120280PDSQR Active Production WSON (DSQ) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2AOH TLV751120280PDSQR.A Active Production WSON (DSQ) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2AOH TLV751180280PDSQR Active Production WSON (DSQ) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2ALH TLV751180280PDSQR.A Active Production WSON (DSQ) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2ALH TLV751180300PDSQR Active Production WSON (DSQ) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2A1H TLV751180300PDSQR.A Active Production WSON (DSQ) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2A1H TLV751180330PDSQR Active Production WSON (DSQ) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2AMH TLV751180330PDSQR.A Active Production WSON (DSQ) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2AMH TLV751330500PDSQR Active Production WSON (DSQ) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2ANH TLV751330500PDSQR.A Active Production WSON (DSQ) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2ANH V751180330PDSQRG4 Active Production WSON (DSQ) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2AMH V751180330PDSQRG4.A Active Production WSON (DSQ) | 10 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 2AMH (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

www.ti.com 17-Jun-2025 (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV75101PDSQR WSON DSQ 10 3000 210.0 185.0 35.0 TLV75101PDSQT WSON DSQ 10 250 210.0 185.0 35.0 TLV75101PDSQTG4 WSON DSQ 10 250 210.0 185.0 35.0 TLV751120280PDSQR WSON DSQ 10 3000 210.0 185.0 35.0 TLV751180280PDSQR WSON DSQ 10 3000 210.0 185.0 35.0 TLV751180300PDSQR WSON DSQ 10 3000 210.0 185.0 35.0 TLV751180330PDSQR WSON DSQ 10 3000 210.0 185.0 35.0 TLV751330500PDSQR WSON DSQ 10 3000 210.0 185.0 35.0 V751180330PDSQRG4 WSON DSQ 10 3000 210.0 185.0 35.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 2.1 1.9 2.1 1.9 0.8 0.7 0.05 0.00 2X 1.6 8X 0.4 10X 0.4 0.2 10X 0.25 0.15 1.5 0.1 0.9 0.1 (0.2) TYP WSON - 0.8 mm max heightDSQ0010A PLASTIC SMALL OUTLINE - NO LEAD 4218906/A 04/2019 0.08 C

0.1 C A B

0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMMEXPOSED THERMAL PAD SYMM 5 6 SCALE 5.000 AB

www.ti.com EXAMPLE BOARD LAYOUT 8X (0.4) (0.5) (R0.05) TYP

0.07 MAX

0.07 MIN

10X (0.5) 10X (0.2) (1.9) (1.5) (0.9) ( 0.2) TYP VIA WSON - 0.8 mm max heightDSQ0010A PLASTIC SMALL OUTLINE - NO LEAD 4218906/A 04/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X SEE SOLDER MASK DETAIL 5 6 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 10X (0.5) 10X (0.2) 8X (0.4) (1.9) (1.38) (0.85) (R0.05) TYP WSON - 0.8 mm max heightDSQ0010A PLASTIC SMALL OUTLINE - NO LEAD 4218906/A 04/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 20X EXPOSED PAD 11 87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM 5 6

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