V716120275PDPQRG4

TLV716 TI | Alldatasheet

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Technical content

1.4 V to 5.5 V VOUT1 VOUT2 1.0 V to 3.3 V 1.0 V to 3.3 V TL V716 Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community TLV716,TLV716P SBVS217B –JUNE 2013–REVISED NOVEMBER 2015 TLV716/PCapacitor-Free,Dual,150-mA, Low-DropoutVoltageRegulatorin1.2-mm×1.2-mmSONPackage

1 Features 3 Description

The TLV716 is a family of dual-channel, capacitor- 1• No Input or Output Capacitors Required free,150-mA, low-dropout (LDO) voltage regulators• Inrush Current Control with multiple fixed-output options available from 1 V

• Low Crosstalk to 3.3 V. These devices provide an initial 1% accuracy and 1.5% accuracy overtemperature.• Accuracy: 1.5% (–40°C to 125°C
• Input Voltage Range: 1.4 V to 5.5 V The TLV716 family is designed to be stable with or without an input or output capacitor. Eliminating the• Multiple Fixed-Output Voltage Combinations output capacitor allows for a very small solution size.Possible from 1 V to 3.3 V The TLV716P series provides an active pulldown• Foldback Current Limit Protection circuit to quickly discharge the output voltage if the
• Package: 1.2-mm × 1.2-mm SON-6 (DPQ) application requires an output capacitor. The device provides inrush current control during2 Applications device power up and enabling. Inrush control
• Wireless Handsets, Smart Phones, Tablets provides constant-current charging of the output load during start-up, thereby reducing the risk of an• Set-Top Boxes (STBs), Cameras, Modems undesired overcurrent fault from the input supply or• Portable Battery-Powered Products battery. The TLV716 family is available in a 1.2-mm × 1.2-mm SON-6 package and is ideal for space-constrained applications. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TLV716 X2SON (6) 1.20 mm × 1.20 mm TLV716P (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Circuit An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLV716,TLV716P SBVS217B –JUNE 2013–REVISED NOVEMBER 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (September 2013) to Revision B Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Changes from Original (June 2013) to Revision A Page

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Product Folder Links: TLV716 TLV716P

TLV716,TLV716P www.ti.com SBVS217B –JUNE 2013–REVISED NOVEMBER 2015

5 Pin Configuration and Functions

NAME NO. Regulated output voltage pin.OUT1 1 O See the Input and Output Capacitor Requirements section for more details. Regulated output voltage pin.OUT2 2 O See the Input and Output Capacitor Requirements section for more details. GND 3 — Ground pin. Input voltage pin.IN 5 I See the Input and Output Capacitor Requirements section for more details. PAD — — Connecting the thermal pad to the ground plane improves the thermal performance. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TLV716 TLV716P

TLV716,TLV716P SBVS217B –JUNE 2013–REVISED NOVEMBER 2015 www.ti.com

6 Specifications

6.1 Absolute Maximum Ratings

at TJ = –40°C to 125°C, unless otherwise noted. (1) MIN MAX UNIT IN –0.3 6 V Voltage (2) EN1, EN2 –0.3 VIN + 0.3 V OUT1, OUT2 –0.3 3.6 or VIN + 0.3 V Current, OUT1, OUT2 –30 Internally limited mA Output short circuit duration Indefinite s TJ Operating junction temperature –55 150 °C Tstg Storage temperature –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to ground.

6.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 V(ESD) Electrostatic discharge VCharged device model (CDM), per JEDEC specification JESD22-C101, all ±500pins (2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted). MIN NOM MAX UNIT VIN Input voltage 1.4 5.5 V VEN Enable range: VEN1, VEN2 0 VIN V IOUT Output current: IOUT1, IOUT2 0 150 mA CIN Input capacitor 0 1 µF COUT Output capacitor: COUT1, COUT2 0 0.1 100 µF TJ Operating junction temperature range –40 125 °C

6.4 Thermal Information

TLV716, TLV716P THERMAL METRIC (1) DPQ (X2SON) UNIT

6 PINS

RθJA Junction-to-ambient thermal resistance 149.3 °C/W RθJC(top) Junction-to-case (top) thermal resistance 93 °C/W RθJB Junction-to-board thermal resistance 110.1 °C/W ψJT Junction-to-top characterization parameter 3.4 °C/W ψJB Junction-to-board characterization parameter 114.9 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 91 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

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TLV716,TLV716P www.ti.com SBVS217B –JUNE 2013–REVISED NOVEMBER 2015

6.5 Electrical Characteristics

over operating temperature range of TA = –40°C to 85°C, VIN = VOUT(TYP) + 0.5 V or 2 V (whichever is greater), IOUT = 1 mA, VEN1 = VEN2 = 0.9 V, and CIN = COUT1 = COUT2 = 1 μF, unless otherwise noted. Typical values are at TJ = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage range 1.4 5.5 V TJ = 25°C, VOUT ≤ 1.2 V –20 20 mV VOUT Output voltage accuracy TJ = –40°C to 85°C, VOUT > 1.2 V –1.5% 1.5% TJ = –40°C to 85°C, VOUT ≤ 1.2 V –50 50 mV IOUT Output current Each channel 150 mA ΔVOUT / ΔVIN Line regulation VOUT + 0.5 V < VIN ≤ 5.5 V 0.02 0.2 %/V ΔVOUT / ΔIOUT Load regulation 1 mA < IOUT < 150 mA 0.07 0.2 mV/mA ΔVOUT / ΔIOUT Cross load regulation 1 mA < IOUT < 150 mA 0.005 0.066 mV/mA IOUT = 150 mA, 1 V ≤ VOUT < 1.2 V 0.78 1 V IOUT = 150 mA, 1.2 V ≤ VOUT < 1.8 V 0.6 0.9 V IOUT = 150 mA, 1.8 V ≤ VOUT < 2.1 V 0.35 0.575 V VDO Dropout voltage IOUT = 150 mA, 2.1 V ≤ VOUT < 2.5 V 0.29 0.48 V IOUT = 150 mA, 2.5 V ≤ VOUT < 3 V 0.23 0.45 V IOUT = 150 mA, 3 V ≤ VOUT < 3.3 V 0.21 0.42 V VHI Enable high voltage 0.9 VIN V VLO Enable low voltage 0 0.4 V RPD Output pulldown resistance TLV716P only 120 Ω VIN = VOUT(TYP) + 0.5 V or 2.1 VICL Output current limit 160 500 mA(whichever is greater) ISC Output short current limit VOUT = 0 V 40 mA IGND Ground pin current Per channel, IOUT = 0 mA, VIN = 5.5 V 50 75 µA ISHUTDOWN Shutdown current Per channel, VIN = 5.5 V, TJ = 25°C 0.1 1 μA f = 100 Hz, VOUT = 2.8 V, IOUT = 30 mA 80 dB PSRR Power-supply rejection ratio f = 10 kHz, VOUT = 2.8 V, IOUT = 30 mA 46 dB BW = 10 Hz to 100 kHz, VOUT = 1.8 V,VN Output noise voltage 70 μVRMSVIN = 2.3 V, IOUT = 10 mA VOUT = 1 V, IOUT = 150 mA 170 μs tSTR Start-up time (1) VOUT = 3.3 V, IOUT = 150 mA 900 μs Shutdown, temperature increasing 158 °C TSD Thermal shutdown temperature Reset, temperature decreasing 140 °C TJ Operating Junction Temperature –40 125 °C (1) Start-up time = time from EN assertion to 0.98 × VOUT(NOM). Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TLV716 TLV716P

6.6 Typical Characteristics

typical performance with a single output current sweep. Typical values are at TJ = 25°C. Figure 1. Line Regulation Figure 2. Line Regulation Figure 3. Load Regulation Figure 4. Load Regulation Figure 5. Shutdown Current vs VIN Figure 6. Ground Pin Current vs VIN

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typical performance with a single output current sweep. Typical values are at TJ = 25°C. Figure 13. Line Transient Figure 14. Line Transient Figure 15. Line Transient Figure 16. Load Transient Figure 17. Load Transient Figure 18. Foldback Current Limit

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0.8 V Enable and Power Control Logic Bandgap and Reference 0.8 V EN2 EN1 IN TLV716,TLV716P SBVS217B –JUNE 2013–REVISED NOVEMBER 2015 www.ti.com

7 Detailed Description

7.1 Overview

The TLV716 and TLV716P devices belong to a new family of next-generation of dual-value, low-dropout (LDO) regulators. These devices consume low quiescent current and deliver excellent line and load transient performance. These characteristics, combined with low noise, very good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal for RF portable applications. This family of regulators offers current limit and thermal protection. Device operating junction temperature is –40°C to 125°C.

7.2 Functional Block Diagram

NOTE: Dashed lines are for the TLV716P only.

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TLV716,TLV716P www.ti.com SBVS217B –JUNE 2013–REVISED NOVEMBER 2015

7.3 Feature Description

7.3.1 Internal Current Limit

The TLV716 and TLV716P have an internal foldback current limit that helps protect the regulator during fault conditions. The current supplied by the device gradually reduces while the output voltage decreases. When the output is connected to ground, the LDO supplies a typical current of 40 mA. When in current limit, the output voltage is not regulated and VOUT = IOUT × RLOAD; see Figure 10 and Figure 11. The PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT] until thermal shutdown is triggered and the device turns off. When the device cools down, the internal thermal shutdown circuit turns on the device. If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal Considerations section for more details. The TLV716 PMOS pass element has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended. A small schottky diode connected with the anode to OUT and the cathode to IN can accomplish this limiting.

7.3.2 Shutdown

The enable pin (EN) is active high. The device is enabled when the EN pin goes above 0.9 V. This relatively low value of voltage required to turn the LDO regulator on can be used to enable the device with the general-purpose input/output (GPIO) of recent processors whose GPIO voltage is lower than traditional microcontrollers. The device is turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, the EN pin can connected to the IN pin. The TLV716P will pull down the output with a 120-Ω resistor when the EN pin falls below 0.4 V.

7.3.3 Undervoltage Lockout (UVLO)

The TLV716 and TLV716P use an undervoltage lockout circuit (1.3 V, typical) to keep the output shut off until the internal circuitry is operating properly.

7.4 Device Functional Modes

7.4.1 Capacitor-Free Operation

The TLV716 and TLV716P are stable without the use of input or output capacitors. This functionality results in a reduction of component count, cost, and solution size. In addition, without the need of external capacitors, the ultra-small, 1.2-mm × 1.2-mm DPQ package optimizes the solution size for board space-constrained applications. To optimize device AC performance, an input and output capacitor is recommended, as described in the Input and Output Capacitor Requirements section. Copyright © 2013–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TLV716 TLV716P

8 Application and Implementation

validate and test their design implementation to confirm system functionality.

8.1 Application Information

to 85°C. Figure 24 shows an application circuit for this family of devices.

8.2 Typical Application

Figure 24. Typical Application Circuit

8.2.1 Design Requirements

Table 1 lists the design requirements. Table 1. Design Parameters

8.2.2 Detailed Design Procedure

An input capacitor is not required for this design because of the low impedance connection directly to the battery. thermal information see the Thermal Considerations and Power Dissipation sections.

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8.2.2.1 Input and Output Capacitor Requirements

resistance (ESR) over temperature. load transients are anticipated or if the device is located several inches from the input power source.

8.2.2.2 Dropout Voltage

the PMOS device behaves like a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN – VOUT) approaches dropout.

8.2.3 Application Curves

Figure 25. Power-Supply Rejection Ratio vs Frequency Figure 26. Output Spectral Noise Density

9 Power Supply Recommendations

the output noise performance.

10 Layout

10.1 Layout Guidelines

performance refer to Figure 27.

10.2 Layout Example

Figure 27. Layout Recommendation

10.3 Thermal Considerations

device is 33°C higher (158°C - 125°C) than the maximum recommended operating conditions. The internal protection circuitry of the TLV716 and TLV716P is designed to protect against overload conditions. thermal shutdown degrades reliability.

10.4 Power Dissipation

Thermal Information table. Using heavier copper increases effectiveness in removing heat from the device.

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11 Device and Documentation Support

11.1 Related Links

resources, tools and software, and quick access to sample or buy. Table 2. Related Links

11.2 Community Resources

solve problems with fellow engineers. contact information for technical support.

11.3 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) TLV716120275PDPQR Active Production X2SON (DPQ) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 EI TLV716120275PDPQR.B Active Production X2SON (DPQ) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 EI TLV716120275PDPQT Active Production X2SON (DPQ) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 EI TLV716120275PDPQT.B Active Production X2SON (DPQ) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 EI TLV7162818PDPQR Active Production X2SON (DPQ) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CW TLV7162818PDPQR.B Active Production X2SON (DPQ) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CW TLV7162818PDPQT Active Production X2SON (DPQ) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CW TLV7162818PDPQT.B Active Production X2SON (DPQ) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CW TLV7162828PDPQR Active Production X2SON (DPQ) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CX TLV7162828PDPQR.B Active Production X2SON (DPQ) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CX TLV7162828PDPQT Active Production X2SON (DPQ) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CX TLV7162828PDPQT.B Active Production X2SON (DPQ) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CX TLV7163030PDPQR Active Production X2SON (DPQ) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CY TLV7163030PDPQR.B Active Production X2SON (DPQ) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CY TLV7163030PDPQT Active Production X2SON (DPQ) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CY TLV7163030PDPQT.B Active Production X2SON (DPQ) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CY TLV7163318PDPQR Active Production X2SON (DPQ) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CZ TLV7163318PDPQR.B Active Production X2SON (DPQ) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CZ TLV7163318PDPQT Active Production X2SON (DPQ) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CZ TLV7163318PDPQT.B Active Production X2SON (DPQ) | 6 250 | SMALL T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 CZ V716120275PDPQRG4 Active Production X2SON (DPQ) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 EI V716120275PDPQRG4.B Active Production X2SON (DPQ) | 6 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 EI (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. Addendum-Page 1

www.ti.com 7-Oct-2025 (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2020 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV7162818PDPQR X2SON DPQ 6 3000 184.0 184.0 19.0 TLV7162818PDPQT X2SON DPQ 6 250 184.0 184.0 19.0 TLV7162828PDPQR X2SON DPQ 6 3000 184.0 184.0 19.0 TLV7162828PDPQT X2SON DPQ 6 250 184.0 184.0 19.0 TLV7163030PDPQR X2SON DPQ 6 3000 184.0 184.0 19.0 TLV7163030PDPQT X2SON DPQ 6 250 184.0 184.0 19.0 TLV7163318PDPQR X2SON DPQ 6 3000 184.0 184.0 19.0 TLV7163318PDPQT X2SON DPQ 6 250 184.0 184.0 19.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2020 Pack Materials-Page 2

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