V62C2802048LL-85T

V62C2802048L MOSEL | Alldatasheet

Document overview

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Technical content

Features

• Low-power consumption - Active: 35mA at 55ns - Stand-by: 10 µA (CMOS input/output) 2 µA CMOS input/output, L version
• Single +2.2 to 2.7V Power Supply_ Typical
• Extented V oltage from 2.2 to 3.6 V .
• Equal access and cycle time
• 55/70/85/100 ns access time
• Easy memory expansion with CE1 , CE2 and OE inputs
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
• Package available: 32L TSOP(I)/ STSOP(I)
• 48 Ball CSP_BGA Functional Description The V62C2802048L is a low power CMOS Static RAM organized as 262,144 words by 8 bits. Easy memory exp- ansion is provided by an active LOW CE1 , an active HIGH CE2, an active LOW OE , and Tri-state I/O’s. This device has an automatic power-down mode feature when deselected. Writing to the device is accomplished by taking Chip Enable 1 ( CE1 ) with Write Enable ( WE ) LOW, and Chip Enable 2 (CE2) HIGH. Reading from the device is per- formed by taking Chip Enable 1 ( CE1 ) with Output Enable ( OE ) LOW while Write Enable ( WE ) and Chip Enable 2 (CE2) is HIGH. The I/O pins are placed in a high-impedance state when the device is deselected: the outputs are disabled during a write cycle. TheV62C2802048LL comes with a 1V data retention fe- ature and Lower Standby Powe r . The V62C2802048L is avalable in a 32-pin 8 x 20 mm TSOP1 / STSOP 8x13.4 mm and CSP type 48-fpBGA packages. 32-Pin TSOP1 / STSOP ( CSP_BGA See next page) Logic Block Diagram Cell Array ROW DECODER SENSE AMP INPUT BUFFER COLUMN DECODER CONTROL CIRCUIT I/O8 I/O1 OE WE CE1 CE2 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A A 9 A 11 A 13 WE CE 2 A 15 Vcc A17 A 16 A 14 A 12 A 7 A 6 A 5 A 4 CE 1 A 10 OE I/O 8 I/O 7 I/O 6 I/O 5 I/O 4 GND I/O 3 I/O 2 I/O 1 A 0 A 1 A 2 A 3 REV. 1.2 May 2001 V62C2 8020 48 L(L)

V62C2802048L(L) 1 2 3 4 5 6 MOSEL VITELIC V62C2802048L(L)B 1 2 3 4 5 6 A B C D E F G H I/O5 I/O6 VSS VCC I/O7 I/O8 NC NC NC NC OE A10 CS2 WE NC NC NC NC CS1 A11 NC NC A17 A16 A12 NC NC NC NC A15 A13 I/O1 I/O2 VCC VSS I/O3 I/O4 A14 Top View Note: NC means no Ball. Top View SIDE VIEW BOTTOM VIEW 48 Ball - 9x12 fpBGA (Ultra Low Power) PACKAGE OUTLINE DWG. SYMBOL UNIT:MM A D e E C A B C D E F G H aaa b SOLDER BALL A 1.05 + 0.15 A1 0.25 + 0.05 0.35 + .05 0.30(TYP) 12.00 + 0.10 5.25 9.00 + 0.10 b c D E e aaa 3.75 0.75TYP 0.10 REV. 1.2 May 2001 V62C2 8020 48 L(L)

V62C2802048L(L) Absolute Maximum Ratings * * Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress ra t- ing only and functional operation of the device at these or any conditions outside those indicated in the operational sections o f this specifica- tion is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Parameter Symbol Minimum Maximum Unit Voltage on Any Pin Relative to Gnd Vt -0.5 3.6 V Power Dissipation PT − 1.0 W Storage Temperature (Plastic) Tstg -55 +150 0C Temperature Under Bias Tbias -40 +85 0C Truth Table * Key: X = Don’t Care, L = Low, H = High CE1 CE2 WE OE Data Mode H X X X High-Z Standby X L X X High-Z Standby L H H L Data Out Active, Read L H H H High-Z Active, Output Disable L H L X Data In Active, Write Recommended Operating Conditions (T A = 0 0 C to +70 0 C / -40 0 C to 85 0 C ** ) * V IL min = -1.0V for pulse width less than t RC /2. ** For Industrial Temperature Parameter Symbol Min Typ Max Unit VCC 2.2 2.5 2.7 V Gnd 0.0 0.0 0.0 V VIH 2.0 - VCC + 0.2 V VIL -0.5* - 0.6 V Supply Voltage Input Voltage REV. 1.2 May 2001 V62C2 8020 48 L(L)

Input Pulse Level 0.6V to 2.2V Input Rise and Fall Tim e 5ns Input and Output Timing Reference Level 1.4V Output Load Condition 70ns/85 ns C L = 30pf + 1TTL Load Load 100ns/120 n s C L = 100pf + 1TTL Load CL* Figure A. * Including Scope and Jig Capacitance TTL V62C2802048L(L) DC Operating Characteristics (V cc = 2.2~2.7 V , Gnd = 0 V , T A = 0 0 C to +70 0 C / -40 0 C to 85 0 C) Input Leakage Current IILII Vcc = Max, Vin = Gnd to Vcc - 1 - 1 - 1 - 1 µA Output Leakage Current IILOI CE1 = VIH or CE2 = VIL Vcc= Max, VOUT = Gnd to Vcc - 1 - 1 - 1 - 1 µA Operating Power Supply Current I CC CE1 = VIL , CE2 = VIH VIN = VIH or VIL , IOUT = 0 mA - 3 - 3 - 3 - 3 mA Average Operating Current I CC1 CE1 = VIL , CE2 = VIH IOUT = 0mA, Min Cycle, 100% Duty - 35 - 30 - 25 - 20 mA ICC2 CE1 = 0.2V, CE2 = Vcc - 0.2V IOUT = 0mA, Cycle Time=1µs, 100% Duty - 3 - 3 - 3 - 3 mA Standby Power Supply Current (TTL Level) ISB CE1 = VIH or CE2 = VIL - 0.5 - 0.5 - 0.5 - 0.5 mA Standby Power Supply Current (CMOS Level) I SB1 CE1 > Vcc - 0.2V or CE2 < 0.2V, f = 0 VIN < 0.2V or VIN > Vcc- 0.2V L µA µA Output Low V oltage VOL IOL = 2 mA - 0.4 - 0.4 - 0.4 - 0.4 V Output High V oltage VOH IOH = -2 mA 2.0 - 2.0 - 2.0 - 2.0 - V -55 -85 -100 Unit Parameter Sym Test Conditions Min Max Min Max Min Max Min Max -70 Capacitance (f = 1MHz, T A = 25 0 C) Parameter* Symbol Test Condition Max Unit Input Capacitance Cin Vin = 0V 7 pF I/O Capacitance CI/O Vin = Vout = 0V 8 pF * This parameter is guaranteed by device characterization and is not production tested. REV. 1.2 May 2001 V62C2 8020 48 L(L)

V62C2802048L(L) Parameter Symbol Unit Note Read Cycle Time tRC 55 - 70 - 85 - 100 - ns Address Access Time tAA - 55 - 70 - 85 - 100 ns Chip Enable Access Time tACE - 55 - 70 - 85 - 100 ns Output Enable Access Time tOE - 35 - 40 - 40 - 50 ns Output Hold from Address Change tOH 10 - 10 - 10 - 10 - ns Chip Enable to Output in Low-Z tCLZ 10 - 10 - 10 - 10 - ns 4,5 Chip Disable to Output in High-Z tCHZ - 25 - 30 - 35 - 40 ns 4,5 Output Enable to Output in Low-Z tOLZ 5 - 5 - 5 - 5 - ns 4,5 Output Disable to Output in High-Z tOHZ - 25 - 25 - 30 - 35 ns 4,5 Power-Up Time tPU 0 - 0 - 0 - 0 - ns 5 Power-Down Time tPD - 55 - 70 - 85 - 100 ns 5 Read Cycle (3,9) (V cc = 2.2~2.7 V , Gnd = 0 V , T A = 0 0 C to +70 0 C / -40 0 C to +85 0 C) Write Cycle (3,11) (V cc = 2.2~2.7 V , Gnd = 0 V , T A = 0 0 C to +70 0 C / -40 0 C to +85 0 C) Parameter Symbol Unit Note Write Cycle Time tWC 55 - 70 - 85 - 100 - ns Chip Enable to Write End tCW 45 - 60 - 70 - 80 - ns Address Setup to Write End tAW 45 - 60 - 70 - 80 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 45 - 50 - 60 - 70 - ns Write Recovering Time tWR 0 - 0 - 0 - 0 - ns Data Valid to Write End tDW 25 - 30 - 35 - 40 - ns Data Hold Time tDH 0 - 0 - 0 - 0 - ns Write Enable to Output in High-Z tWZ - 25 - 30 - 35 - 40 ns 4,5 Output Active from Write End tOW 5 - 5 - 5 - 5 - ns 4,5 Min Max Min Max Min Max Min Max -55 -70 -85 -100 Min Max Min Max Min Max Min Max -55 -70 -85 -100 REV. 1.2 May 2001 V62C2 8020 48 L(L)

Timing Waveform of Read Cycle 1 (Address Controlled) (3,6,7,9) t RC t AA t O H Data Valid Address D OUT Timing Waveform of Read Cycle 2 (CE1 Controlled)(5,6,8,9) 50% 50% I CC I SB t PD t CHZ t OHZ t RC t OE t OLZ t ACE t CLZ t PU CE1 OE D OUT Supply Current Data Valid Timing Waveform of Read Cycle 3 (CE2 Controlled) (3,6,8,9) 50% 50% I CC I SB t PD t CHZ t OHZ t RC t OE t OLZ t ACE t CLZ t PU CE2 OE D OUT Supply Current Data Valid V62C2802048L(L) REV. 1.2 May 2001 V62C2 8020 48 L(L)

V62C2802048L(L) Timing Waveform of Write Cycle 1 (WE Controlled)(10,11) Data Valid Address D OUT Timing Waveform of Write Cycle 2 (CE1 Controlled) (10,11) Timing Waveform of Write Cycle 3 (CE2 Controlled) (10,11) D IN WE t DW t DH t OW t WZ t AS t WP t WR t WC t AW D OUT D IN WE Address CE1 Data Valid t WZ t DW t DH t WP t WC t CW t AW t WR t AS D OUT D IN WE Address CE2 Data Valid t WZ t DW t DH t WP t WC t CW t AW t WR t AS REV. 1.2 May 2001 V62C2 8020 48 L(L)

V62C2802048L(L) Data Retention Characteristics (L V ersion Only) (1) Parameter Symbol Test Condition Min Max Unit VCC for Data Retention VDR CE1 > VCC - 0.2V or 1.0 - V Data Retention Current ICCDR CE2 < + 0.2V - 1 µA Chip Deselect to Data Retention Time tCDR VIN > VCC - 0.2V or 0 - ns Operation Recovery Time (2) tR VIN < 0.2V tRC - ns Data Retention Mode VDR > 1.0VVcc Typ VIHVIH VDR VCC CE tRtCDR Vcc Typ Data Retention Waveform (L V ersion Only) (T A = 0 0 C to +70 0 C / -40 0 C to +85 0 C) Notes 1. L-version includes this feature. 2. This Parameter is samples and not 100% tested. 3. For test conditions, see AC Test Condition , Figure A. 4. This parameter is tested with CL = 5 pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage. 5. This parameter is guaranteed, but is not tested. 6. WE is HIGH for read cycle. 7. CE1 and OE are LOW and CE2 is HIGH for read cycle. 8. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH. 9. All read cycle timings are referenced from the last valid address to the first transtion address. 10. CE1 or WE must be HIGH or CE2 must be LOW during address transition. 11. All write cycle timings are referenced from the last valid address to the first transition address. REV. 1.2 May 2001 V62C2 8020 48 L(L)

V62C2802048L(L)

Ordering Information

Device Type* Speed Package V62C2802048L-55T 55 ns 8 x 20 mm 32-pin Plastic TSOP1 V62C2802048L-70T 70 ns V62C2802048L-85T 85 ns V62C2802048L-100T 100 ns V62C2802048LL-55T 55 ns V62C2802048LL-70T 70 ns V62C2802048LL-85T 85 ns V62C2802048LL-100T 100 ns V62C2802048L(L)-55V 55 ns 8 x 13.4 mm 32-pin Plastic STSOP V62C2802048L(L)-70V 70 ns V62C2802048L(L)-85V 85 ns V62C2802048L(L)-100V 100 ns V62C2802048L(L)-55B 55 ns 48-fpBGA V62C2802048L(L)-70B 70 ns V62C2802048L(L)-85B 85 ns V62C2802048L(L)-100B 100 ns * For Industrial Temperature tested devices, an “I” designator will be added to the end of the Device numbe r . REV. 1.2 May 2001 V62C2 8020 48 L(L)

© Copyright 2001, MOSEL VITELIC Inc. 5/01 Printed in U.S.A. MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461 The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep cur- rent the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. U.S. SALES OFFICES U.S.A.

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