V62C2801024L MOSEL | Alldatasheet

Document overview

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Technical content

Features

  • Ultra Low-power consumption - Active: 25mA at 70ns - Stand-by: 5 µA (CMOS input/output) 1 µA CMOS input/output, L version
  • Single +2.2V to 2.7V Power Supply
  • Equal access and cycle time
  • 70/85/100/150 ns access time
  • Easy memory expansion with CE1 , CE2 and OE inputs
  • 1.0V data retention mode
  • TTL compatible, Tri-state input/output
  • Automatic power-down when deselected Functional Description TheV62C2801024L is a low power CMOS Static RAM org- anized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW CE1 , an active HIGH CE2, an active LOW OE , and Tri-state I/O’s. This device has an a- utomatic power-down mode feature when deselected. Writing to the device is accomplished by taking Chip E- nable 1 (CE1 ) with Write Enable (WE ) LOW , and Chip En- able 2 (CE2) HIGH. Reading from the device is performed by taking Chip Enable 1 (CE1 ) with Output Enable (OE ) LOW while Write Enable (WE ) and Chip Enable 2 (CE2) is HIGH. The I/O pins are placed in a high-imped- ance state when the device is deselected: the outputs are d- isabled during a write cycle. TheV62C2801024LL comes with a 1V data retention feature and Lower Standby Power. The V62C2801024L is available in a 32pin 8 x 20 mm TSOP1 / STSOP / 48-fpBGA packages. 32-Pin TSOP1 / STSOP / 48-fpBGA (See nest page) Logic Block Diagram 1024 X 1024 ROW DECODER SENSE AMP INPUT BUFFER COLUMN DECODER CONTROL CIRCUIT I/O8 I/O1 OE WE CE1 CE2 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 A 9 REV. 1.1 April 2001 V62C2801024L(L)

V62C2801024L(L) Top V iew 48-CSP Ba ll- Gr id Array package (shad ing indicates no ball) 1 2 3 4 5 6 A A 0 A 1 CE2 A 3 A 6 A 8 B I/O 4 A 2 WE A 4 A 7 I/O 0 C I/O 5 NC NC A 5 NC I/O 1 D V SS NC NC NC NC V DD E V DD NC NC NC NC V SS F I/O 6 NC NC NC NC I/O 2 G I/O 7 OE CE 1 A 16 A 15 I/O 3 H A 9 A 10 A 11 A 12 A 13 A 14 MOSEL VITELIC V62C2801024L(L)B TOP VIEW A B C D E F G H REV. 1.1 April 2001 V62C2801024L(L)

V62C2801024L(L) Absolute Maximum Ratings * * Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress ra t- ing only and functional operation of the device at these or any conditions outside those indicated in the operational sections o f this specifica- tion is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect reliabilit y . Parameter Symbol Minimum Maximum Unit Voltage on Any Pin Relative to Gnd Vt -0.5 4.6 V Power Dissipation PT − 1.0 W Storage Temperature (Plastic) Tstg -55 +150 0C Temperature Under Bias Tbias -40 +85 0C Truth Table * Key: X = Don’t Care, L = Lo w , H = High CE1 CE2 WE OE Data Mode H X X X High-Z Standby X L X X High-Z Standby L H H L Data Out Active, Read L H H H High-Z Active, Output Disable L H L X Data In Active, Write Recommended Operating Conditions (TA = 00C to +700C / -400C to 850C ** ) * V IL min = -1.0V for pulse width less than t RC /2. ** For Industrial Temperature. Parameter Symbol Min Typ Max Unit VCC 2.2 2.5 2.7 V Gnd 0.0 0.0 0.0 V VIH 2.0 - VCC + 0.2 V VIL -0.5* - 0.6 V Supply Voltage Input Voltage REV. 1.1 April 2001 V62C2801024L(L)

Input Pulse Level 0.6V to 2.0V Input Rise and Fall Time5ns Input and Output Timing Reference Level 50% of input level IL + VIH)/2 Output Load Condition 70ns/85 ns C L = 30pf + 1TTL Load Load 100ns/150 ns C L = 100pf + 1TTL Load CL* Figure A. * Including Scope and Jig Capacitance TTL V62C2801024L(L) DC Operating Characteristics (Vcc = 2.2 to 2.7V, Gnd = 0V, TA = 00C to +700C / -400C to 850C) Input Leakage CurrentIILI Vcc = Max, Vin = Gnd to Vcc - 1 - 1 - 1 - 1 µA Output Leakage Current IILO CE1 = VIH or CE2 = VIL Vcc= Max, VOUT = Gnd to Vcc - 1 - 1 - 1 - 1 µA Operating Power Supply Current ICC CE1 = VIL , CE2 = VIH VIN = VIH or VIL , IOUT = 0 mA - 3 - 3 - 3 - 3 mA Average Operating Current ICC1 CE1 = VIL , CE2 = VIH IOUT = 0mA, Min Cycle, 100% Duty - 25 - 20 - 15 - 15 mA ICC2 CE1 = 0.2V, CE2 = Vcc - 0.2V IOUT = 0mA, Cycle Time=1µs, 100% Duty - 3 - 3 - 3 - 3 mA Standby Power Supply Current (TTL Level) ISB CE1 = VIH or CE2 = VIL - 0.5 - 0.5 - 0.5 - 0.5 mA Standby Power Supply Current (CMOS Level) ISB1 CE1 > Vcc - 0.2V or L CE2 < 0.2V, f = 0 VIN < 0.2V or VIN > Vcc- 0.2V LL µA µA Output Low Voltage VOL IOL = 2 mA - 0.4 - 0.4 - 0.4 - 0.4 V Output High Voltage VOH IOH = -2 mA 2.0 - 2.0 - 2.0 - 2.0 - V -70 -100 -150 Unit Parameter Sym Test Conditions Min Max Min Max Min Max Min Max -85 Capacitance (f = 1MHz, TA = 250C) Parameter* Symbol Test Condition Max Unit Input Capacitance Cin Vin = 0V 7 pF I/O Capacitance CI/O Vin = Vout = 0V 8 pF * This parameter is guaranteed by device characterization and is not production tested. REV. 1.1 April 2001 V62C2801024L(L)

V62C2801024L(L) Parameter Symbol Unit Note Read Cycle Time tRC 70 - 85 - 100 - 150 - ns Address Access Time tAA - 70 - 85 - 100 - 150 ns Chip Enable Access Time tACE - 70 - 85 - 100 - 150 ns Output Enable Access Time tOE - 40 - 40 - 50 - 70 ns Output Hold from Address Change tOH 10 - 10 - 10 - 10 - ns Chip Enable to Output in Low-Z tCLZ 10 - 10 - 10 - 10 - ns 4,5 Chip Disable to Output in High-Z tCHZ - 30 - 35 - 40 - 50 ns 4,5 Output Enable to Output in Low-Z tOLZ 5 - 5 - 5 - 5 - ns 4,5 Output Disable to Output in High-Z tOHZ - 25 - 30 - 35 - 40 ns 4,5 Power-Up Time tPU 0 - 0 - 0 - 0 - ns 5 Power-Down Time tPD - 70 - 85 - 100 - 150 ns 5 Read Cycle (3,9) (Vcc = 2.2 to 2.7V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Write Cycle (3,11) (Vcc = 2.2 to 2.7V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Symbol Unit Note Write Cycle Time tWC 70 - 85 - 100 - 150 - ns Chip Enable to Write End tCW 60 - 70 - 80 - 120 - ns Address Setup to Write End tAW 60 - 70 - 80 - 120 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 50 - 60 - 70 - 100 - ns Write Recovering Time tWR 0 - 0 - 0 - 0 - ns Data Valid to Write End tDW 30 - 35 - 40 - 60 - ns Data Hold Time tDH 0 - 0 - 0 - 0 - ns Write Enable to Output in High-Z tWZ - 30 - 35 - 40 - 50 ns 4,5 Output Active from Write End tOW 5 - 5 - 5 - 5 - ns 4,5 Min Max Min Max Min Max Min Max -70 -85 -100 Min Max Min Max Min Max Min Max -70 -85 -100 -150 -150 REV. 1.1 April 2001 V62C2801024L(L)

Timing Waveform of Read Cycle 1 (3,6,7,9) (Address Controlled) tRC tAA tOH Data Valid Address D OUT Timing Waveform of Read Cycle 2 (5,6,8,9) (CE1 Controlled) 50% 50% ICC ISB tPD tCHZ tOHZ tRC tOE tOLZ tACE tCLZ tPU CE1 OE DOUT Supply Current Data Valid Timing Waveform of Read Cycle 3 (3,6,8,9) (CE2 Controlled) 50% 50% ICC ISB tPD tCHZ tOHZ tRC tOE tOLZ tACE tCLZ tPU CE2 OE D OUT Supply Current Data Valid V62C2801024L(L) REV. 1.1 April 2001 V62C2801024L(L)

V62C2801024L(L) Timing Waveform of Write Cycle 1 (10,11) (WE Controlled) Data Valid Address D OUT Timing Waveform of Write Cycle 2 (10,11) (CE1 Controlled) Timing Waveform of Write Cycle 3 (10,11) (CE2 Controlled) D IN WE tDW tDH tOW tWZ tAS tWP tWR tWC tAW D OUT D IN WE Address CE1 Data Valid tWZ tDW tDH tWP tWC tCW tAW tWR tAS D OUT D IN WE Address CE2 Data Valid tWZ tDW tDH tWP tWC tCW tAW tWR tAS REV. 1.1 April 2001 V62C2801024L(L)

V62C2801024L(L) Data Retention Characteristics (L Version Only)(1) Parameter Symbol Test Condition Min Max Unit VCC for Data Retention VDR CE1 > VCC - 0.2V or 1.0 - V Data Retention Current ICCDR CE2 < + 0.2V - 1 µA Chip Deselect to Data Retention Time tCDR VIN > VCC - 0.2V or 0 - ns Operation Recovery Time(2) tR VIN < 0.2V tRC - ns Data Retention Mode VDR > 1.0VVcc_typ VIHVIH VDR VCC CE tRtCDR Vcc_typ Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C) Notes 1.L-version includes this feature. 2. This Parameter is sampled and not 100% tested. 3.For test conditions, see AC Test Condition, Figure A. 4.This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage. 5.This parameter is guaranteed, but is not tested. 6.WE is HIGH for read cycle. 7.CE1 and OE are LOW and CE2 is HIGH for read cycle. 8.Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH. 9.All read cycle timings are referenced from the last valid address to the first transtion address. 10.CE1 or WE must be HIGH or CE2 must be LOW during address transition. 11.All write cycle timings are referenced from the last valid address to the first transition address. REV. 1.1 April 2001 V62C2801024L(L)

V62C2801024L(L)

Ordering Information

Device Type* Speed Package V62C2801024L-70T 70 ns 8 x 20 mm 32-pin Plastic TSOP1 V62C2801024L-85T 85 ns V62C2801024L-100T 100 ns V62C2801024L-150T 150 ns V62C2801024LL-70T 70 ns V62C2801024LL-85T 85 ns V62C2801024LL-100T 100 ns V62C2801024LL-150T 150 ns V62C2801024L-70V 70 ns 8 x13.4 mm 32-pin Plastic STSOP V62C2801024L-85V 85 ns V62C2801024L-100V 100 ns V62C2801024L-150V 150 ns V62C2801024LL-70V 70 ns V62C2801024LL-85V 85 ns V62C2801024LL-100V 100 ns V62C2801024LL-150V 150 ns V62C2801024L(L)-70B 70 ns 48-fpBGA V62C2801024L(L)-85B 85 ns V62C2801024L(L)-100B 100 ns V62C2801024L(L)-150B 150 ns * For Industrial Temperature tested devices, an “I” designator will be added to the end of the device number. REV. 1.1 April 2001 V62C2801024L(L)

© Copyright 2001, MOSEL VITELIC Inc. 4/01 Printed in U.S.A. MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461 The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep cur- rent the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. U.S. SALES OFFICES U.S.A.

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