V62C18164096L

V62C18164096 MOSEL | Alldatasheet

Document overview

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Technical content

Features

I High-speed: 85, 100 ns I Ultra low CMOS standby current of 2 µ A (max.) I Fully static operation I All inputs and outputs directly TTL compatible I Three state outputs I Ultra low data retention current (V CC = 1.0V) I Operating voltage: 1.8V – 2.3V I Packages – 48-Ball CSP BGA (8mm x 10mm)

Description

The V62C18164096 is a 4,194,304-bit static random-access memory organized as 262,144 words by 16 bits. Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. Device Usage Chart Operating Temperature Range Package Outline Access Time (ns) Power Temperature MarkB 85 100 L LL C to 70 –40 C to +85 C• • • • I Functional Block Diagram Row Decoder 1024 x 4096 Memory Array Input Data Circuit Column I/O Column Decoder Control Circuit VCC GND I/O1 I/O16 LBE OE WE UBE A10 A17 CE 1 CE 2

V62C18164096 Rev. 1.2 June 2000 MOSEL VITELIC V62C18164096 Pin Descriptions A Address Inputs These 18 address inputs select one of the 256K x 16 bit segments in the RAM. CE , CE Chip Enable Inputs CE is active LOW and CE is active HIGH. Both chip enables must be active to read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The I/O pins will be in the high-impedance state when deselected. OE Output Enable Input The output enable input is active LOW. With the chip enabled, when OE is Low and WE High, data will be presented on the I/O pins. The I/O pins will be in the high impedance state when OE is High. UBE , LBE Byte Enable Active low inputs. These inputs are used to enable the upper or lower data byte. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip enabled, when WE is HIGH and OE is LOW, output data will be present at the I/O pins; when WE is LOW and OE is HIGH, the data present on the I/O pins will be written into the selected memory locations. I/O –I/O Data Input and Data Output Ports These 16 bidirectional ports are used to read data from and write data into the RAM. V CC Power Supply GND Ground Pin Configurations (Top View)

48 BGA

A 123456 1 Note: NC means no connect. 23 4 5 6 B C D E F G H TOP VIEW TOP VIEW A BLE I/O9 I/O10 B C D E F G H VSS VCC I/O15 I/O16 NC OE BHE I/O11 I/O12 I/O13 I/O14 NC A17 NC A14 A12 A16 A15 A13 A10 CE 1 I/O2 I/O4 I/O5 I/O6 WE A11 CE 2 I/O1 I/O3 VCC VSS I/O7 I/O8 NC

V62C18164096 Rev. 1.2 June 2000 Part Number Information Absolute Maximum Ratings (1) NOTE: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol Parameter Commercial Industrial Units V CC Supply Voltage -0.5 to V CC + 0.5 -0.5 to V CC + 0.5 V V N Input Voltage -0.5 to V CC + 0.5 -0.5 to V CC + 0.5 V V DQ Input/Output Voltage Applied V CC + 0.3 V CC + 0.3 V T BIAS Temperature Under Bias -10 to +125 -65 to +135 C T STG Storage Temperature -55 to +125 -65 to +150 C SRAM FAMILY C = CMOS PROCESS 62 = STANDARD 18 = 1.8V – 2.3V OPERATING VOLTAGE 4096K ORGANIZATION PKGSPEED

62 C 16 18 4096 –

V 16 = 16-bit 85 ns 100 ns TEMP. BLANK = 0°C to 70°C I = -40°C to +85°C B = BGA DENSITY PWR. L = LOW POWER LL = DOUBLE LOW POWER Capacitance* T A = 25 C, f = 1.0MHz NOTE: 1. This parameter is guaranteed and not tested. Symbol Parameter Conditions Max. Unit C IN Input Capacitance V IN = 0V 6 pF C OUT Output Capacitance V I/O = 0V 8 pF Truth Table NOTE: X = Don’t Care, L = LOW, H = HIGH Mode CE CE OE WE UBE LBE I/O 9-16 Operation I/O 1-8 Operation Standby H X X X X X High Z High Z Standby X L X X X X High Z High Z Output Disable L H X X H H High Z High Z Output Disable L H H H X X High Z High Z Read LHLHL L D OUT D OUT Read LHLHL H D OUT High Z Read LHLHH L High Z D OUT Write L H X L L L D IN D IN Write L H X L L H D IN High Z Write L H X L H L High Z D IN

V62C18164096 Rev. 1.2 June 2000 MOSEL VITELIC V62C18164096 (over all temperature ranges, V CC = 1.8V – 2.3V) NOTES: 1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included. 2. V IL (Min.) = -3.0V for pulse width < 20ns. 3. Maximum values. Symbol Parameter Test Conditions Min. Typ. Max. Units V IL Input LOW Voltage (1,2) -0.3 — 0.4 V V IH Input HIGH Voltage (1) 1.6 — V CC + 0.3 V I IL Input Leakage Current V CC = Max, V IN = 0V to V CC -1 — 1 µ A I OL Output Leakage Current V CC = Max, CE = V IH , V OUT = 0V to V CC -1 — 1 µ A V OL Output LOW Voltage V CC = Min, I OL = 2.1mA —— 0.4 V V OH Output HIGH Voltage V CC = Min, I OH = -0. 1mA V CC – 0.4 —— V Symbol Parameter Power Com. (3) Ind. (3) Units I CC1 Average Operating Current, CE = V IL , CE = VCC – 0.2V, Output Open, V CC = Max. f = fmax 25 30 mA f = 1 MHz 2 3 I SB TTL Standby Current CE V IH , V CC = Max., f = 0 L 0.4 0.5 mA LL 0.3 0.3 I SB1 CMOS Standby Current, CE ≥ VCC – 0.2V, CE2 < 0.2V VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, VCC = Max., f = 0 L57 µA LL 2 3 AC Test Conditions AC Test Loads and Waveforms Key to Switching Waveforms Input Pulse Levels 0 to 1.6V Input Rise and Fall Times 5 ns Timing Reference Levels 0.9V Output Load see below * Includes scope and jig capacitance C L* TTL C L = 30 pF + 1 TTL Load WAVEFORM INPUTS OUTPUTS MUST BE STEADY WILL BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGING FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGING FROM L TO H DON'T CARE: ANY CHANGE PERMITTED CHANGING: STATE UNKNOWN DOES NOT APPL Y CENTER LINE IS HIGH IMPEDANCE “OFF ” STATE

MOSEL VITELIC V62C18164096 5V62C18164096 Rev. 1.2 June 2000 Data Retention Characteristics NOTES: 1. t RC = Read Cycle Time 2. T A = +25°C. Low V CC Data Retention Waveform (CE Controlled) Symbol Parameter Power Min. Typ. (2) Max. Units VDR VCC for Data Retention CE 1 ≥ VCC – 0.2V, CE2 < 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V 1.0 — 2.3 V ICCDR Data Retention Current CE 1 ≥ VDR – 0.2V, CE2 < 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, VDR = 1.0V Com ’lL — 13 µA LL — 0.5 1.5 Ind. L —— 5 LL —— 2 tCDR Chip Deselect to Data Retention Time 0 —— ns tR Operation Recovery Time (see Retention Waveform) t RC (1) —— ns VCC Data Retention Mode CE 1 ≥ VCC – 0.2V CE 1 1.6V 1.6V 1.8V tCDR tR VDR ≥ 1V 1.8V

6V62C18164096 Rev. 1.2 June 2000 MOSEL VITELIC V62C18164096 (over all temperature ranges) Read Cycle Write Cycle Parameter Name Parameter 85 100 UnitMin. Max. Min. Max. tRC Read Cycle Time 85 — 70 — ns tAA Address Access Time — 85 — 100 ns tACS Chip Enable Access Time — 85 — 100 ns tBA UBE , LBE Access Time — 85 — 100 ns tOE Output Enable to Output Valid — 35 — 40 ns tCLZ Chip Enable to Output in Low Z 10 — 15 — ns tBLZ UBE , LBE to Output in Low Z 10 — 15 — ns tOLZ Output Enable to Output in Low Z 10 — 10 — ns tCHZ Chip Disable to Output in High Z 0 30 0 35 ns tOHZ Output Disable to Output in High Z 0 30 0 35 ns tBHZ UBE , LBE to Output in High Z 0 30 0 35 ns tOH Output Hold from Address Change 10 — 10 — ns Parameter Name Parameter 85 100 UnitMin. Max. Min. Max. tWC Write Cycle Time 85 — 100 — ns tCW Chip Enable to End of Write 70 — 80 — ns tAS Address Setup Time 0 — 0 — ns tAW Address Valid to End of Write 70 — 80 — ns tWP Write Pulse Width 60 — 70 — ns tWR Write Recovery Time 0 — 0 — ns tWHZ Write to Output High-Z 0 25 0 35 ns tDW Data Setup to End of Write 40 — 45 — ns tDH Data Hold from End of Write 0 — 0 — ns tBW UBE , LBE to End of Write 70 — 80 — ns

MOSEL VITELIC V62C18164096 7V62C18164096 Rev. 1.2 June 2000 Switching Waveforms (Read Cycle) Read Cycle 1(1, 2) Read Cycle 2(1, 2, 4, 6) Read Cycle 3(1, 3, 4, 6) NOTES: 1. WE = VIH. 2. CE 1 = VIL. CE2 = VIH. 3. Address valid prior to or coincident with CE transition LOW. 4. OE = VIL. 5. Transition is measured ±500mV from steady state with CL = 5pF. This parameter is guaranteed and not 100% tested. 6. UBE = VIL, LBE = VIL. ADDRESS OE I/O UBE, LBE tRC tAA tOE tBHZ tOLZ tBLZ tBA tOHZ (5) ADDRESS I/O tRC tAAtOH tOH ADDRESS I/O CE 1 tACS tCLZ (5) tCHZ (5) CE 2

8V62C18164096 Rev. 1.2 June 2000 MOSEL VITELIC V62C18164096 Switching Waveforms (Write Cycle) Write Cycle 1 (WE Controlled)(4) Write Cycle 2 (CE Controlled)(4) NOTES: 1. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 2. t WR is measured from the earlier of CE1 or WE going high, or CE2 going LOW at the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention. 5. If CE1 is LOW and CE2 is HIGH during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 6. t CW is measured from CE1 going low or CE2 going HIGH to the end of write. ADDRESS OUTPUT INPUT CE 1 CE 2 WE tWC tCW (6) tCW (6) tDW tDH tAW tWR (2) tWHZ tWP (1) tAS ADDRESS OUTPUT High-Z INPUT CE 1 CE 2 WE tWC tDW tDH tAW tCW (6) tCW (6) tWR (2) tAS (4) (5)

MOSEL VITELIC V62C18164096 9V62C18164096 Rev. 1.2 June 2000 Package Diagrams

48 Ball— 8x10 BGA

E D AB C D E BOTTOM VIEW SIDE VIEW aaa FG H b SOLDER BALL e A C SYMBOL A b c D E e aaa UNIT.MM 1.05+0.15 0.25±0.05 0.35±.0.05 0.30(TYP) 10.00±0.10 5.25 8.00±0.10 3.75 0.75TYP 0.10

MOSEL VITELIC WORLDWIDE OFFICES V62C18164096 MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461 © Copyright 2000, MOSEL VITELIC Inc. 6/00 Printed in U.S.A. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep cur- rent the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. U.S. SALES OFFICES U.S.A.

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