V62C1162048L-85M

V62C1162048L MOSEL | Alldatasheet

Document overview

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Technical content

Features

• Low-power consumption - Active: 35mA I CC at 70ns - Stand-by: 10 µA (CMOS input/output) 2 µA (CMOS input/output, L version)
• 70/85/100/120 ns access time
• Equal access and cycle time
• Single +1.8V to2.2V Power Supply
• Tri-state output
• Automatic power-down when deselected
• Multiple center power and ground pins for improved noise immunity
• Individual byte controls for both Read and Write cycles
• Available in 44 pin TSOPII / 48-fpBGA / 48-µBGA Functional Description The V62C1162048L is a Low Power CMOS Static RAM organized as 131,072 words by 16 bits. Easy Memory expansion is provided by an active LOW (CE) and (OE) pin. This device has an automatic power-down mode feature when deselected. Separate Byte Enable controls (BLE and BHE ) allow individual bytes to be accessed. BLE controls the lower bits I/O1 - I/O8. BHE controls the upper bits I/O9 - I/O16. Writing to these devices is performed by taking Chip Enable (CE ) with Write Enable (WE ) and Byte Enable (BLE /BHE ) LOW . Reading from the device is performed by taking Chip Enable (CE ) with Output Enable (OE ) and Byte Enable (BLE /BHE ) LOW while Write Enable ( WE ) is held HIGH. TSOPII / 48-fpBGA / 48- µBGA (See nest page)Logic Block Diagram 23 22 A5 A4 WE I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 CE Vss Vcc A12 A16 A15 A14 A13 A11 A10 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 NC NC Vss Vcc BHE BLE OE REV. 1.2 May 2001 V62C116 2048 L(L)

V62C1162048L(L) SIDE VIE W BOTTOM VIE W 48 Ball - 6 x 8 µ µBGA (Ultra Low Power) PACKAGE OUTLINE DWG. SYMBOL UNIT:MM A D e E C A B C D E F G H aaa b SOLDER BALL A 1.10 + 0.10 A1 0.22 +0.05 0.35 0.36(TYP) 8.00 + 0.10 5.25 6.00 + 0.10 b c D E e aaa 3.75 0.75TYP 0.10 1 2 3 4 5 6 MOSEL VITELIC V62C1162048L(L)M 1 2 3 4 5 6 A B C D E F G H BLE I/O9 I/O10 VSS VCC I/O15 I/O16 NC OE BHE I/O11 I/O12 I/O13 I/O14 NC NC NC A14 A12 A16 A15 A13 A10 CE I/O2 I/O4 I/O5 I/O6 WE A11 NC I/O1 I/O3 VCC VSS I/O7 I/O8 NC Top View Note: NC means no Ball. Top View REV. 1.2 May 2001 V62C1162048 L(L)

V62C1162048L(L) Absolute Maximum Ratings * * Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to the device. This is a stress ra t- ing only and function operation of the device at these or any other conditions outside those indicated in the operational sectio ns of this spec- ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliabilit y . Parameter Symbol Minimum Maximum Unit Voltage on Any Pin Relative to Gnd Vt -0.5 +4.0 V Power Dissipation PT − 1.0 W Storage Temperature (Plastic) Tstg -55 +150 0C Temperature Under Bias Tbias -40 +85 0C Truth Table * Key: X = Don’t Care, L = Lo w , H = High CE OE WE BLE BHE I/O1-I/O8 I/O9-I/O16 Power Mode H X X X X High-Z High-Z Standby Standby L L H L H Data Out High-Z Active Low Byte Read L L H H L High-Z Data Out Active High Byte Read L L H L L Data Out Data Out Active Word Read L X L L L Data In Data In Active Word Write L X L L H Data In High-Z Active Low Byte Write L X L H L High-Z Data In Active High Byte Write L H H X X High-Z High-Z Active Output Disable L X X H H High-Z High-Z Active Output Disable Recommended Operating Conditions (TA = 0oC to +70oC / -40oC to 85oC**) * V IL min = -2.0V for pulse width less than t RC /2. ** For Industrial Temperature Parameter Symbol Min Typ Max Unit VCC 1.8 2.0 2.2 V Gnd 0.0 0.0 0.0 V VIH 1.6 - VCC + 0.2 V VIL -0.5* - 0.4 V Supply Voltage Input Voltage REV. 1.2 May 2001 V62C116 2048 L(L)

Input Pulse Level 0.4V to 1.6V Input Rise and Fall Time5ns Input and Output Timing Reference Level 1.0V Output Load Condition 70ns/85ns C L = 30pf + 1TTL Load Load for 100ns/120ns C L = 100pf + 1TTL Load CL* Figure A. * Including Scope and Jig Capacitance TTL V62C1162048L(L) DC Operating Characteristics (Vcc =1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to 850C) Input Leakage CurrentIILII Vcc = Max, Vin = Gnd to Vcc - 1 - 1 - 1 - 1 µA Output Leakage Current IILOI CE = VIH or Vcc= Max, VOUT = Gnd to Vcc - 1 - 1 - 1 - 1 µA Operating Power Supply Current ICC CE = VIL , VIN = VIH or VIL , IOUT = 0 - 5 - 5 - 5 - 5 mA Average Operating Current ICC1 IOUT = 0mA, Min Cycle, 100% Duty - 35 - 35 - 30 - 30 mA ICC2 CE < 0.2V IOUT = 0mA, Cycle Time=1µs, Duty=100% - 3 - 3 - 3 - 3 mA Standby Power Supply Current (TTL Level) ISB CE = VIH - 0.5 - 0.5 - 0.5 - 0.5 mA Standby Power Supply Current (CMOS Level) ISB1 CE > Vcc - 0.2V VIN < 0.2V or VIN > Vcc- 0.2V L µA µA Output Low Voltage VOL IOL = 2 mA - 0.4 - 0.4 - 0.4 - 0.4 V Output High Voltage VOH IOH = -1 mA 1.6 - 1.6 - 1.6 - 1.6 - V -70 -100 -120 Unit Parameter Sym Test Conditions Min Max Min Max Min Max Min Max -85 Capacitance (f = 1MHz, TA = 250C) Parameter* Symbol Test Condition Max Unit Input Capacitance Cin Vin = 0V 7 pF I/O Capacitance CI/O Vin = Vout = 0V 8 pF * This parameter is guaranteed by device characterization and is not production tested. REV. 1.2 May 2001 V62C116 2048 L(L)

V62C1162048L(L) Parameter Sym Unit Note Read Cycle Time tRC 70 - 85 - 100 - 120 - ns Address Access Time tAA - 70 - 85 - 100 - 120 ns Chip Enable Access Time tACE - 70 - 85 - 100 - 120 ns Output Enable Access Time tOE - 40 - 40 - 50 - 60 ns Output Hold from Address Change tOH 10 - 10 - 10 - 10 - ns Chip Enable to Output in Low-Z tLZ 10 - 10 - 10 - 10 - ns 4,5 Chip Disable to Output in High-Z tHZ - 30 - 35 - 40 - 45 ns 3,4,5 Output Enable to Output in Low-Z tOLZ 5 - 5 - 5 - 5 - ns Output Disable to Output in High-Z tOHZ - 25 - 30 - 35 - 40 ns BLE, BHE Enable to Output in Low-Z tBLZ 5 - 5 - 5 - 5 - ns 4,5 BLE, BHE Disable to Output in High-Z tBHZ - 25 - 30 - 35 - 40 ns 3,4,5 BLE, BHE Access Time tBA - 40 - 40 - 50 - 60 ns Read Cycle (9) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Write Cycle (11) (Vcc = 1.8 to 2.2V, Gnd = 0V, TA = 00C to +700C / -400C to +850C) Parameter Symbol Unit Note Write Cycle Time tWC 70 - 85 - 100 - 120 - ns Chip Enable to Write End tCW 60 - 70 - 80 - 90 - ns Address Setup to Write End tAW 60 - 70 - 80 - 90 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 50 - 60 - 70 - 80 - ns Write Recovery Time tWR 0 - 0 - 0 - 0 - ns Data Valid to Write End tDW 30 - 35 - 40 - 45 - ns Data Hold Time tDH 0 - 0 - 0 - 0 - ns Write Enable to Output in High-Z tWHZ - 30 - 35 - 40 - 45 ns Output Active from Write End tOW 5 - 5 - 5 - 5 - ns BLE, BHE Setup to Write End tBW 60 - 70 - 80 - 90 - ns Min Max Min Max Min Max Min Max -70 -85 -100 -120 Min Max Min Max Min Max Min Max -70 -85 -100 -120 REV. 1.2 May 2001 V62C116 2048 L(L)

Timing Waveform of Read Cycle 1 (Address Controlled) tRC tAA tOH Data Valid Address Data Out Timing Waveform of Read Cycle 2 tOHZ tRC tOLZ tACE tLZ(4,5) CE Previous Data Valid Address tOH tAA tOE tBA tBLZ(4,5) tBHZ(3,4,5) tHZ(3,4,5) (BLE/BHE) OE Data Out Data ValidHigh-Z V62C1162048L(L) Notes (Read Cycle) 1. WE are high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to V OH or V OL levels. 4. At any given temperature and voltage condition tHZ (max.) is less than tLZ (min.) both for a given device and from device to device. 5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. 6. Device is continuously selected with CE = V IL . 7. Address valid prior to coincident with CE transition Lo w . 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 9. For test conditions, see AC Test Condition , Figure A. REV. 1.2 May 2001 V62C116 2048 L(L)

V62C1162048L(L) Timing Waveform of Write Cycle 1 (Address Controlled) Timing Waveform of Write Cycle 2 (CE Controlled) Timing Waveform of Write Cycle 3 (BLE/BHE Controlled) Address High-Z tDW tDH tWP (2) tWC tCW (3) tAW tWR (5) tAS (4) Address Address Data In Data In Data In Data Out Data Out Data Out CE CE CE BLE/BHE BLE/BHE BLE/BHE WE WE WE tBW tLZ tBLZ tWHZ (6) High-Z (8) High-Z tWHZ (6) High-Z (8)High-Z High-Z tDW tDH tWP (2) tBW tAS (4) tWR (5) tCW (3) tAW tWC High-Z High-Z (8) tOW tOHZ (6) tDW tDH tWP (2) tBW tAS (4) tCW (3) tAW tWC tWR (5) REV. 1.2 May 2001 V62C116 2048 L(L)

V62C1162048L(L) Notes (Write Cycle) 1. All write timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CE and WE . A write begins at the latest transition among CE and WE going low: A write ends at the earliest transition among CE going high and WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CE going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. 6. If OE , CE and WE are in the Read Mode during this period, the I/O pins are in the output Low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occu r. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CE goes low simultaneously with WE going low or after WE going lo w , the outputs remain high impedance state. 9. D OUT is the read data of the new address. 10. When CE is low: I/O pins are in the outputs state. The input signals in the opposite phase leading to the output should not be applied. 11. For test conditions, see AC Test Condition , Figure A. REV. 1.2 May 2001 V62C116 2048 L(L)

V62C1162048L(L) Notes (Write Cycle) 1. L-version includes this feature. 2. This Parameter is samples and not 100% tested. 3. For test conditions, see AC Test Condition , Figure A. 4. This parameter is tested with CL = 5pF as shown in Figure B. Transition is measured + 500mV from steady-state voltage. 5. This parameter is guaranteed, but is not tested. 6. WE is High for read cycle. 7. CE and OE are LOW for read cycle. 8. Address valid prior to or coincident with CE transition LO W . 9. All read cycle timings are referenced from the last valid address to the first transtion address. 10. CE or WE must be HIGH during address transition. 11. All write cycle timings are referenced from the last valid address to the first transition address. Data Retention Mode VDR > 1.0VVcc_typ VIHVIH VDR VCC CE tRtCDR Vcc_typ Data Retention Waveform (L Version Only) (TA = 00C to +700C / -400C to +850C) Data Retention Characteristics (L Version Only)(1) Parameter Symbol Test Condition Min Max Unit VCC for Data Retention VDR CE > VCC - 0.2V 1.0 - V Data Retention Current ICCDR - 1 µA Chip Deselect to Data Retention Time tCDR VIN > VCC - 0.2V or 0 - ns Operation Recovery Time(2) tR VIN < 0.2V tRC - ns REV. 1.2 May 2001 V62C116 2048 L(L)

V62C1162048L(L)

Ordering Information

Device Type* Speed Package V62C1162048L-70T 70 ns 44-pin TSOP Type 2 V62C1162048L-85T 85 ns V62C1162048L-100T 100 ns V62C1162048L-120T 120 ns V62C1162048LL-70T 70 ns V62C1162048LL-85T 85 ns V62C1162048LL-100T 100 ns V62C1162048LL-120T 120 ns V62C1162048L(L)-70B 70 ns 48-fpBGA V62C1162048L(L)-85B 85 ns V62C1162048L(L)-100B 100 ns V62C1162048L(L)-120B 120 ns V62C1162048L(L)-70M 70 ns 48-µBGA V62C1162048L(L)-85M 85 ns V62C1162048L(L)-100M 100 ns V62C1162048L(L)-120M 120 ns * For Industrial temperature tested devices, an “I” designator will be added to the end of the device numbe r . REV. 1.2 May 2001 V62C116 2048 L(L)

© Copyright 2001, MOSEL VITELIC Inc. 5/01 Printed in U.S.A. MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461 The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep cur- rent the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. U.S. SALES OFFICES U.S.A.

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