V6212615-01XE

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Datasheet sections

• 1 INTRODUCTION
• 1.1 Features
• 1.2 Applications
• 1.3 SupportsDefense,Aerospace,and MedicalApplications
• 1.4 TypicalSystem Diagram
• 2 OVERVIEW
• 2.1 Description
• 2.2 OrderingInformation
• 2.3 DeviceInformation
• 2.4 TerminalDescriptions
• 3 ELECTRICAL SPECIFICATIONS
• 3.1 AbsoluteMaximum Ratings
• 3.2 Recommended OperatingConditions
• 3.3 ThermalInformation
• 3.4 DC Specifications
• 3.4.1 ElectricalCharacteristics
• 3.5 AC Specifications
• 3.5.1 Power Up Timing
• 3.5.2 Reset Timing
• 3.5.3 MIISerialManagement Timing
• 3.5.22 Auto-NegotiationFastLinkPulse(FLP)Timing
• 3.5.26 RMII TransmitTiming
• 3.5.27 RMII ReceiveTiming
• 3.5.28 IsolationTiming
• 4 CONFIGURATION
• 4.1 Auto-Negotiation
• 4.1.1 Auto-NegotiationPinControl
• 4.1.2 Auto-NegotiationRegisterControl
• 4.1.3 Auto-NegotiationParallelDetection
• 2 Contents Copyright© 2012–2013,Texas InstrumentsIncorporated

PHYTER ™ MILITARY TEMPERATURE SINGLE PORT 10/100MB/S ETHERNET PHYSICAL LAYER TRANSCEIVER Data Manual PRODUCTION DATA informationiscurrentas of publicationdate. Products conform to specificationsper the terms of the Texas Instrumentsstandard warranty.Productionprocessingdoes not necessarilyincludetestingofallparameters. LiteratureNumber: SLLSEC6D September 2012–RevisedJune 2013

www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Copyright© 2012–2013,Texas InstrumentsIncorporated Contents 3

SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com

4 Contents Copyright© 2012–2013,Texas InstrumentsIncorporated

www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 ListofFigures Copyright© 2012–2013,Texas InstrumentsIncorporated ListofFigures 5

SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com ListofTables

6 ListofTables Copyright© 2012–2013,Texas InstrumentsIncorporated

www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 PHYTER™ MILITARYTEMPERATURESINGLEPORT10/100MB/SETHERNETPHYSICAL LAYERTRANSCEIVER Check forSamples: DP83848-EP

1 INTRODUCTION

1.1 Features

12• Low-Power 3.3-V,0.18-μm CMOS Technology

• Low Power Consumption < 270 mW Typical
• 3.3-VMAC Interface
• Auto-MDIX for10/100Mb/s
• Energy DetectionMode
• 25-MHz Clock Out
• SNI Interface(Configurable)
• RMII Rev. 1.2Interface(Configurable)
• MIISerialManagement Interface(MDC and MDIO)
• IEEE 802.3uMII
• IEEE 802.3uAuto-Negotiationand ParallelDetection
• IEEE 802.3uENDEC, 10BASE-T Transceiversand Filters
• IEEE 802.3uPCS, 100BASE-TX Transceiversand Filters
• IEEE 1149.1JTAG
• IntegratedANSI X3.263Compliant TP-PMD PhysicalSublayerwithAdaptiveEqualizationand Baseline Wander Compensation
• Error-FreeOperationup to150 meters
• Programmable LED Support Link,10 /100Mb/s Mode, Activity,and CollisionDetect
• SingleRegisterAccess forComplete PHY Status
• 10/100Mb/s Packet BIST (BuiltinSelfTest)
• Lead Free 48-PinPQFP Package (7mm) x (7mm)

1.2 Applications

• Automotive and Transportation
• IndustrialControlsand FactoryAutomation
• GeneralEmbedded Applications

1.3 Supports Defense,Aerospace,and MedicalApplications

• ControlledBaseline
• One Assembly and TestSite
• One FabricationSite
• MilitaryTemperature Range (-55°C to125°C)
• Extended Product LifeCycle
• Extended Product-Change Notification
• Product Traceability Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2PHYTER isa trademarkofTexas Instruments. PRODUCTION DATA informationiscurrentas ofpublicationdate.Productsconformto Copyright© 2012–2013,Texas InstrumentsIncorporatedspecificationsper the terms of the Texas Instrumentsstandardwarranty.Production processingdoes notnecessarilyincludetestingofallparameters.

SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com

1.4 TypicalSystem Diagram

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2 OVERVIEW

2.1 Description

The number ofapplicationsrequiringethernetconnectivitycontinuestoincrease.Alongwiththisincreased market demand isa change inapplicationrequirements.The DP83848 was designedto allowethernet connectivityin the harshestenvironments.Our devicemeets IEEE 802.3u standardsover a military temperaturerange of -55°C to 125°C. Thisdeviceisideallysuitedforharsh environmentsforexample wirelessremotebase stations,automotive,transportationand industrialcontrolapplications. The DP83848 isa highlyreliable,featurerichrobustdevicewhichincludesenhanced ESD protection,MII and RMII formaximum flexibilityinMPU selectionallina 48 pinPQFP package. The DP83848 featuresintegratedsublayersto supportboth 10BASE-T and 100BASE-TX Ethernet protocols,which ensures compatibilityand interoperabilitywith allother standardsbased Ethernet solutions.

2.2 OrderingInformation(1)

TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING VID NUMBER DP83848MPHPREP Tape and Reel,1000 V62/12615-01XE–55°C to PQFP-PHP DP83848EP125°C DP83848MPHPEP Tray,1250 V62/12615-01XE-R (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI websiteatwww.ti.com. Copyright© 2012–2013,Texas InstrumentsIncorporated OVERVIEW 9 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

TX_CLKTXD[3:0]TX_EN MDIO MDC COL CRS/CRS_DVRX_ERRX_DVRXD[3:0]RX_CLK RX_DATARX_CLK REFERENCE CLOCKTD± RD± LEDs MII/RMII/SNI Interfaces Auto-MDIX DAC ADC JTAG MII/RMII/SNI Serial Management TX_DATA TX_CLK 10Base-T and 100Base-TX 10Base-T and 100Base-TX Transmit Block Receive Block MI Registers Auto-Negotiation State Machine Clock Generation Boundary Scan LED Drivers DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com

2.3 Device Information

Figure2-1.Device Block Diagram

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DGNDIOGNDX1 X2 IOVDD33MDCMDIORESET_NLED_LINK/AN0LED_SPEED/AN1LED_ACT/COL/AN_EN25MHz_OUT RBIAS PFBOUT AVDD33 RESERVED RESERVED AGND PFBIN1 TD + TD – AGND RD + RD – TX_CLKTX_ENTXD_0TXD_1TXD_2 TXD_3/SNI_MODEPWR_DOWN/INT TCKTDOTMSTRST TDI 1 2 3 4 5 6 7 8 9 10 11 35 34 33 32 31 30 29 28 27 26 25 PFBIN2 RX_CLK RX_DV/MII_MODE CRS/CRS_DV/LED_CFG RX_ER/MDIX_EN COL/PHYAD0 RXD_0/PHYAD1 RXD_1/PHYAD2 RXD_2/PHYAD3 RXD_3/PHYAD4 IOGND IOVDD33 2437 Thermal Pad DP83848-EP www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 PHP PACKAGE (TOP VIEW) Copyright© 2012–2013,Texas InstrumentsIncorporated OVERVIEW 11 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

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2.4 TerminalDescriptions

AllDP83848 signalpinsare I/Ocellsregardlessof the particularuse.The definitionsbelow definethe functionalityoftheI/Ocellsforeach pin. Type:I-Input Type:O -Output Type:I/O-Input/Output Type OD -Open Drain Type:PD, PU -InternalPulldown/Pullup Type:S -StrappingPin(Allstrappinshave weak internalpull-upsorpull-downs.Ifthedefaultstrapvalue isneeded tobe changed thenan external2.2kΩ resistorshouldbe used.) Table2-1.SerialManagement Interface TERMINAL I/O DESCRIPTION NAME NO. MANAGEMENT DATA CLOCK: SynchronousclocktotheMDIO management datainput/outputserialinterface MDC 31 I whichmay be asynchronoustotransmitand receiveclocks.The maximum clockrateis25 MHz withno minimum clockrate. MANAGEMENT DATA I/O:Bi-directionalmanagement instruction/datasignalthatmay be sourcedby thestationMDIO 30 I/O management entityorthePHY. Thispinrequiresa 1.5kΩ pullupresistor. Table2-2.MAC Data Interface TERMINAL I/O DESCRIPTION NAME NO. MIITRANSMIT CLOCK: 25 MHz Transmitclockoutputin100 Mb/s mode or2.5MHz in10 Mb/s mode derived fromthe25 MHz referenceclock. Unused inRMII mode. The deviceuses theX1 referenceclockinputas the50 MHz referenceforbothtransmitTX_CLK 1 O and receive. SNI TRANSMIT CLOCK: 10 MHz Transmitclockoutputin10 Mb SNI mode. The MAC shouldsourceTX_EN and TXD_0 usingthisclock. MIITRANSMIT ENABLE: Activehighinputindicatesthepresenceofvaliddatainputson TXD[3:0]. TX_EN 2 I,PD RMII TRANSMIT ENABLE: Activehighinputindicatesthepresenceofvaliddataon TXD[1:0]. SNI TRANSMIT ENABLE: Activehighinputindicatesthepresenceofvaliddataon TXD_0. MIITRANSMIT DATA: TransmitdataMIIinputpins,TXD[3:0],thatacceptdatasynchronoustotheTX_CLKTXD_0 3 I (2.5MHz in10 Mb/s mode or25 MHz in100 Mb/s mode). RMII TRANSMIT DATA: TransmitdataRMII inputpins,TXD[1:0],thatacceptdatasynchronoustothe50 MHzTXD_1 4 referenceclock. TXD_2 5 SNI TRANSMIT DATA: TransmitdataSNI inputpin,TXD_0, thatacceptdatasynchronoustotheTX_CLK (10MHz in10 Mb/s SNI mode).TXD_3 6 S,I,PD MIIRECEIVE CLOCK: Providesthe25 MHz recoveredreceiveclocksfor100 Mb/s mode and 2.5MHz for 10 Mb/s mode. RX_CLK 38 O Unused inRMII mode. The deviceuses theX1 referenceclockinputas the50 MHz referenceforbothtransmit and receive. SNI RECEIVE CLOCK: Providesthe10 MHz recoveredreceiveclocksfor10 Mb/s SNI mode. MIIRECEIVE DATA VALID:Assertedhightoindicatethatvaliddataispresenton thecorrespondingRXD[3:0]. MIImode by defaultwithinternalpulldown. RX_DV 39 S,O, PD RMII SynchronousReceiveData Valid:ThissignalprovidestheRMII ReceiveData Validindication independentofCarrierSense. Thispinisnotused inSNI mode.

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Table2-2.MAC Data Interface(continued) TERMINAL I/O DESCRIPTION NAME NO. MIIRECEIVE ERROR: AssertedhighsynchronouslytoRX_CLK toindicatethatan invalidsymbolhas been detectedwithina receivedpacketin100 Mb/s mode. RMII RECEIVE ERROR: AsserthighsynchronouslytoX1 whenever itdetectsa media errorand RXDV is assertedin100 Mb/s mode.RX_ER 41 S,O, PU Thispinisnotrequiredtobe used by a MAC, ineitherMIIorRMII mode, sincethePhy isrequiredtocorrupt dataon a receiveerror. Thispinisnotused inSNI mode. MIIRECEIVE DATA: NibblewidereceivedatasignalsdrivensynchronouslytotheRX_CLK, 25 MHz forRXD_0 43 S,O, PD 100 Mb/s mode, 2.5MHz for10 Mb/s mode).RXD[3:0]signalscontainvaliddatawhen RX_DV isasserted. RXD_1 44 RMII RECEIVE DATA: 2-bitsreceivedatasignals,RXD[1:0],drivensynchronouslytotheX1 clock,50 MHz. RXD_2 45 SNI RECEIVE DATA: Receivedatasignal,RXD_0, drivensynchronouslytotheRX_CLK. RXD_0 containsvalid datawhen CRS isasserted.RXD[3:1]arenotused inthismode.RXD_3 46 MIICARRIER SENSE: Assertedhightoindicatethereceivemedium isnon-idle. RMII CARRIER SENSE/RECEIVE DATA VALID:ThissignalcombinestheRMII Carrierand ReceiveData Valid CRS/CRS_DV 40 S,O, PU indications.Fora detaileddescriptionofthissignal,see theRMII Specification. SNI CARRIER SENSE: Assertedhightoindicatethereceivemedium isnon-idle.Itisused toframevalid receivedataon theRXD_0 signal. MIICOLLISION DETECT: Assertedhightoindicatedetectionofa collisioncondition(simultaneoustransmit and receiveactivity)in10 Mb/s and 100 Mb/s HalfDuplexModes. Whilein10BASE-T HalfDuplexmode withheartbeatenabledthispinisalsoassertedfora durationof approximately1μs attheend oftransmissiontoindicateheartbeat(SQE test). InFullDuplexMode, for10 Mb/s or100 Mb/s operation,thissignalisalwayslogic0.Thereisno heartbeatCOL 42 S,O, PU functionduring10 Mb/s fullduplexoperation. RMII COLLISION DETECT: Per theRMII Specification,no COL signalisrequired.The MAC willrecoverCRS fromtheCRS_DV signaland use thatalongwithitsTX_EN signaltodeterminecollision. SNI COLLISION DETECT: Assertedhightoindicatedetectionofa collisioncondition(simultaneoustransmit and receiveactivity)in10 Mb/s SNI mode. Table2-3.Clock Interface TERMINAL I/O DESCRIPTION NAME NO. CRYSTAL/OSCILLATOR INPUT: ThispinistheprimaryclockreferenceinputfortheDP83848 and must be connectedtoa 25 MHz 0.005% (±50 ppm) clocksource.The DP83848 supportseitheran externalcrystal resonatorconnectedacrosspinsX1 and X2,oran externalCMOS-leveloscillatorsourceconnectedtopinX1 X1 34 I only. RMII REFERENCE CLOCK: ThispinistheprimaryclockreferenceinputfortheRMII mode and must be connectedtoa 50 MHz 0.005% (±50 ppm) CMOS-leveloscillatorsource. CRYSTAL OUTPUT: Thispinistheprimaryclockreferenceoutputtoconnecttoan external25 MHz crystalX2 33 O resonatordevice.Thispinmust be leftunconnectedifan externalCMOS oscillatorclocksourceisused.

25 MHz CLOCK OUTPUT:

InMIImode, thispinprovidesa 25 MHz clockoutputtothesystem. 25MHz_OUT 25 O InRMII mode, thispinprovidesa 50 MHz clockoutputtothesystem. Thisallowsotherdevicestouse thereferenceclockfromtheDP83848 withoutrequiringadditionalclock sources. Copyright© 2012–2013,Texas InstrumentsIncorporated OVERVIEW 13 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com Table2-4.LED Interface TERMINAL I/O DESCRIPTION NAME NO. LINK LED: InMode 1,thispinindicatesthestatusoftheLINK.The LED willbe ON when Linkisgood. LED_LINK 28 S,O, PU LINK/ACT LED: InMode 2 and Mode 3,thispinindicatestransmitand receiveactivityinadditiontothestatusof theLink.The LED willbe ON when Linkisgood.Itwillblinkwhen thetransmitterorreceiverisactive. SPEED LED: The LED isON when deviceisin100 Mb/s and OFF when in10 Mb/s.FunctionalityofthisLED isLED_SPEED 27 S,O, PU independentofmode selected. ACTIVITY LED: InMode 1,thispinistheActivityLED whichisON when activityispresenton eitherTransmitor Receive. LED_ACT/COL 26 S,O, PU COLLISION/DUPLEX LED: InMode 2,thispinby defaultindicatesCollisiondetection.ForMode 3,thisLED outputmay be programmed toindicateFull-duplexstatusinsteadofCollision. Table2-5.JTAG Interface TERMINAL I/O DESCRIPTION NAME No. TCK 8 I,PU TEST CLOCK: Thispinhas a weak internalpullup TDI 12 I,PU TEST DATA INPUT: Thispinhas a weak internalpullup TDO 9 O TEST OUTPUT TMS 10 I,PU TEST MODE SELECT: Thispinhas a weak internalpullup TRST# 11 I,PU TEST RESET: Activelowasynchronoustestreset.Thispinhas a weak internalpullup. Table2-6.Reset and Power Down TERMINAL I/O DESCRIPTION NAME NO. RESET: ActiveLow inputthatinitializesorre-initializestheDP83848. Assertingthispinlowforatleast1 μs will RESET_N 29 I,PU forcea resetprocesstooccur.Allinternalregisterswillre-initializetotheirdefaultstatesas specifiedforeach bit intheRegisterBlocksection.Allstrapoptionsarere-initializedas well. The defaultfunctionofthispinisPOWER DOWN. POWER DOWN: The pinisan activelowinputinthismode and shouldbe assertedlowtoputthedeviceina Power Down mode. PWR_DOWN/INT 7 I,OD, PU INTERRUPT: The pinisan open drainoutputinthismode and willbe assertedlowwhen an interruptcondition occurs.Althoughthepinhas a weak internalpull-up,some applicationsmay requirean externalpull-upresister. Registeraccessisrequiredforthepintobe used as an interruptmechanism.See Section7.5.2formore details on theinterruptmechanisms.

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Table2-7.StrapOptions(1)(2) TERMINAL I/O DESCRIPTION NAME NO. PHY ADDRESS [4:0]:The DP83848 providesfivePHY addresspins,thestateofwhicharelatchedintothePHYAD0 (COL) 42 S,O, PU PHYCTRL registeratsystemHardware-Reset. The DP83848 supportsPHY Addressstrappingvalues0 (<00000>)through31 (<11111>).A PHY Addressof0 puts thepartintotheMIIIsolateMode. The MIIisolatemode must be selectedby strappingPhy Address0;changingtoPHYAD1 (RXD_0) 43 S,O, PD Address0 by registerwritewillnotputthePhy intheMIIisolatemode. Pleaserefertosection2.3foradditional information. PHYAD2 (RXD_1) 44 PHYAD0 pinhas weak internalpull-upresistor. PHYAD3 (RXD_2) 45 PHYAD[4:1]pinshave weak internalpull-downresistors. PHYAD4 (RXD_3) 46 AN_EN Auto-NegotiationEnable:When high,thisenablesAuto-Negotiationwiththecapabilitysetby ANO and AN1 pins.26 S,O, PU(LED_ACT/COL) When low,thisputsthepartintoForcedMode withthecapabilitysetby AN0 and AN1 pins. AN0 /AN1: These inputpinscontroltheforcedoradvertisedoperatingmode oftheDP83848 accordingtotheAN_1 27 followingtable.The valueon thesepinsissetby connectingtheinputpinstoGND (0)orVCC (1)through2.2kΩ(LED_SPEED) resistors.These pinsshouldNEVER be connecteddirectlytoGND orVCC. AN_0 (LED_LINK) 28 The valuesetatthisinputislatchedintotheDP83848 atHardware-Reset. The float/pull-downstatusofthesepinsarelatchedintotheBasicMode ControlRegisterand theAuto_Negotiation AdvertisementRegisterduringHardware-Reset. The defaultis111 sincethesepinshave internalpull-ups. AN_EN AN1 AN0 Forced Mode 0 0 0 10BASE-T, Half-Duplex 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 0 1 1 100BASE-TX, Full-Duplex AN_EN AN1 AN0 AdvertisedMode 1 0 0 10BASE-T, Half/Full-Duplex 1 0 1 100BASE-TX, Half/Full-Duplex 10BASE-T Half-Duplex 1 1 0 100BASE-TX, Half-Duplex 10BASE-T, Half/Full-Duplex 1 1 1 100BASE-TX, Half/Full-Duplex MIIMODE SELECT: Thisstrappingoptionpairdeterminestheoperatingmode oftheMAC Data Interface.Default MII_MODE operation(No pull-ups)willenablenormalMIIMode ofoperation.StrappingMII_MODE highwillcause thedeviceto39 S,O, PD(RX_DV) be inRMII orSNI mode ofoperation,determinedby thestatusoftheSNI_MODE strap.Sincethepinsinclude internalpull-downs,thedefaultvaluesare0. SNI_MODE 6 The followingtabledetailstheconfigurations:(TXD_3) MII_MODE SNI_MODE MAC InterfaceMode

0 X MIIMode

LED CONFIGURATION: Thisstrappingoptiondeterminesthemode ofoperationoftheLED pins.DefaultisMode 1. Mode 1 and Mode 2 can be controlledviathestrapoption.Allmodes areconfigurableviaregisteraccess.LED_CFG (CRS) 40 S,O, PU See Table4-3forLED Mode Selection. MDIX ENABLE: DefaultistoenableMDIX. ThisstrappingoptiondisablesAuto-MDIX.An externalpull-downwillMDIX_EN (RX_ER) 41 S,O, PU disableAuto-MDIX mode. (1) The DP83848 uses many ofthefunctionalpinsas strapoptions.The valuesofthesepinsaresampled duringresetand used tostrap thedeviceintospecificmodes ofoperation.The functionalpinname isindicatedinparentheses. (2) A 2.2kΩ resistorshouldbe used forpull-downorpull-uptochange thedefaultstrapoption.Ifthedefaultoptionisrequired,thenthereis no need forexternalpull-uporpulldown resistors.Sincethesepinsmay have alternatefunctionsafterresetisdeasserted,theyshould notbe connecteddirectlytoVCC orGND. Copyright© 2012–2013,Texas InstrumentsIncorporated OVERVIEW 15 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com Table2-8.10 Mb/s and 100 Mb/s PMD Interface TERMINAL I/O DESCRIPTION NAME NO. Differentialcommon drivertransmitoutput(PMD OutputPair).These differentialoutputsareautomatically configuredtoeither10BASE-T or100BASE-TX signaling. TD-,TD+ 16,17 I/O InAuto-MDIX mode ofoperation,thispaircan be used as theReceiveInputpair. These pinsrequire3.3Vbiasforoperation. Differentialreceiveinput(PMD InputPair).These differentialinputsareautomaticallyconfiguredtoaccepteither 100BASE-TX or10BASE-T signaling. RD-,RD+ 13,14 I/O InAuto-MDIX mode ofoperation,thispaircan be used as theTransmitOutputpair. These pinsrequire3.3Vbiasforoperation. Table2-9.SpecialConnections TERMINAL I/O DESCRIPTION NAME NO. RBIAS 24 I BiasResistorConnection.A 4.87kΩ 1% resistorshouldbe connectedfromRBIAS toGND. Power Feedback Input.These pinsarefedwithpower fromPFBOUT pin.A smallcapacitorof0.1μF shouldbePFBIN1 18 I connectedclosetoeach pin. PFBIN2 37 Note:Do notsupplypower tothesepinsotherthanfromPFBOUT. RESERVED 20,21 I/O RESERVED: These pinsmust be pulled-upthrough2.2kΩ resistorstoAVDD33 supply. Table2-10.Power Supply Pins TERMINAL

DESCRIPTION

NAME NO. IOVDD33 32,48 I/O3.3VSupply IOGND 35,47 I/OGround DGND 36 DigitalGround AVDD33 22 Analog3.3VSupply AGND 15,19 AnalogGround GNDPAD ThermalPad

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3 ELECTRICAL SPECIFICATIONS

3.1 AbsoluteMaximum Ratings

overoperatingfree-airtemperaturerange(unlessotherwisenoted) VALUE UNIT VCC Supplyvoltage -0.5to4.2 V VIN DC inputvoltage -0.5toVCC + 0.5 V VOUT DC outputvoltage -0.5toVCC + 0.5 V TSTG Storagetemperature -65to150 °C TJ Operatingjunctiontemperature -55to150 °C TL Lead temperature(soldering,10 seconds) 260 °C ESD rating(RZAP = 1.5kΩ,C ZAP = 100 pF) 4 kV

3.2 Recommended OperatingConditions(1)

overoperatingfree-airtemperaturerange(unlessotherwisenoted) MIN NOM MAX UNIT VCC Supplyvoltage 3 3.6 V TA Operatingfree-airtemperature(2) -55 125 °C PD Power dissipation 267 mW (1) Absolutemaximum ratingsarethosevaluesbeyond whichthesafetyofthedevicecannotbe guaranteed.They arenotmeant toimply thatthedeviceshouldbe operatedattheselimits. (2) ProvidedthatThermalPad issoldereddown.

3.3 Thermal Information

48 PINS

θJA Junction-to-ambientthermalresistance(1) 35.74 θJCtop Junction-to-case(top)thermalresistance(2) 21.8 θJB Junction-to-boardthermalresistance(3) 19.5 °C/W ψJT Junction-to-topcharacterizationparameter(4) 1.2 ψJB Junction-to-boardcharacterizationparameter(5) 19.4 θJCbot Junction-to-case(bottom)thermalresistance(6) 3.2 (1) The junction-to-ambientthermalresistanceundernaturalconvectionisobtainedina simulationon a JEDEC-standard,high-Kboard,as specifiedinJESD51-7,inan environmentdescribedinJESD51-2a. (2) The junction-to-case(top)thermalresistanceisobtainedby simulatinga coldplateteston thepackage top.No specificJEDEC- standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. (3) The junction-to-boardthermalresistanceisobtainedby simulatinginan environmentwitha ringcoldplatefixturetocontrolthePCB temperature,as describedinJESD51-8. (4) The junction-to-topcharacterizationparameter,ψJT,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingθJA,usinga proceduredescribedinJESD51-2a (sections6 and 7). (5) The junction-to-boardcharacterizationparameter,ψJB,estimatesthejunctiontemperatureofa deviceina realsystemand isextracted fromthesimulationdataforobtainingθJA ,usinga proceduredescribedinJESD51-2a (sections6 and 7). (6) The junction-to-case(bottom)thermalresistanceisobtainedby simulatinga coldplateteston theexposed (power)pad.No specific JEDEC standardtestexists,buta closedescriptioncan be foundintheANSI SEMI standardG30-88. Spacer Copyright© 2012–2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 17 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

1000.00 10000.00 100000.00 1000000.00 80 90 100 1 10 120 130 140 150 160 Estimated Life (Hours) Continuous TJ (°C) DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com

3.4 DC Specifications

3.4.1 ElectricalCharacteristics

overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIH InputHighVoltage NominalVCC 2 V VIL InputLow Voltage 0.8 V IIH InputHighCurrent VIN = VCC 10 µA IIL InputLow Current VIN = GND 10 µA VOL OutputLow Voltage IOL = 4 mA 0.4 V VOH OutputHighVoltage IOH = -4mA VCC -0.5 V VOUT = VCCIOZ TRI-STATE Leakage ±10 µAVOUT = GND VTPTD_100 100M TransmitVoltage 0.89 1 1.15 V VTPTDsym 100M TransmitVoltageSymmetry ±2 % VT PTD_10 10M TransmitVoltage 2.17 2.5 2.8 V C IN1 CMOS InputCapacitance 5 pF C OUT1 CMOS OutputCapacitance 5 pF 100BASE-TX SignaldetectturnonSD THon 1000 mV diffpk-pkthreshold 100BASE-TX SignaldetectturnoffSD THoff 200 mV diffpk-pkthreshold VTH1 10BASE-T ReceiveThreshold 585 mV Idd100 100BASE-TX (FullDuplex) 81 mA Idd10 10BASE-T (FullDuplex) 92 mA Idd Power Down Mode 14 mA (1) See datasheetforabsolutemaximum and minimum recommended operatingconditions. (2) Siliconoperatinglifedesigngoalis10 yearsat105°C junctiontemperature(doesnotincludepackage interconnectlife). (3) Enhanced plasticproductdisclaimerapplies. Figure3-1.DP83848-EP OperatingLifeDeratingChart

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T2.1.1 32 clocks T2.1.2 T2.1.3 Input Output VCC X1 clock Hardware RESET_N MDC Latch-in of hardware configuration pins Dual function pins become enabled as outputs DP83848-EP www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013

3.5 AC Specifications

3.5.1 Power Up Timing

Figure3-2.Power Up Timing xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.1.1 PostPower Up Stabilizationtimeprior MDIO ispulledhighfor32-bitserial 167 ms toMDC preambleforregister management initialization accesses X1 Clockmust be stablefora min.of167ms atpower up. T2.1.2 Hardware ConfigurationLatchinTime Hardware ConfigurationPinsaredescribed 167 ms frompower up inthePinDescriptionsection X1 Clockmust be stablefora min.of167ms atpower up. T2.1.3 Hardware Configurationpins 50 ns transitiontooutputdrivers Copyright© 2012–2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 19 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

T2.2.4 T2.2.1 32 clocks T2.2.2 T2.2.3 Input Output VCC X1 clock Hardware RESET_N MDC Latch-in of hardware configuration pins Dual function pins become enabled as outputs DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com

3.5.2 Reset Timing

Figure3-3.Reset Timing xxx PARAMETER DESCRIPTION NOTES (1) MIN TYP MAX UNIT T2.2.1 PostRESET Stabilizationtimepriorto MDIO ispulledhighfor32-bitserial 3 µs MDC preambleforregisteraccesses management initialization T2.2.2 Hardware ConfigurationLatchinTime Hardware ConfigurationPinsaredescribed 3 µs fromtheDeassertionofRESET (either inthePinDescriptionsection softorhard) T2.2.3 Hardware Configurationpinstransition 50 ns tooutputdrivers T2.2.4 RESET pulsewidth X1 Clockmust be stableforatmin.of1µs 1 µs duringRESET pulselowtime (1) Itisimportanttochoose pull-upand/orpull-downresistorsforeach ofthehardwareconfigurationpinsthatprovidefastRC time constantsinordertolatch-inthepropervaluepriortothepintransitioningtoan outputdriver.

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TX_CLK TXD[3:0] TX_EN V alid data T2.4.1 T2.4.1 T2.4.2 T2.4.3 MDC MDC MDIO (output) MDIO (input) V alid data T2.3.1 T2.3.4 T2.3.2 T2.3.3 DP83848-EP www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013

3.5.3 MIISerialManagement Timing

Figure3-4.MIISerialManagement Timing xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.3.1 MDC toMDIO (Output)DelayTime 0 30 ns T2.3.2 MDIO (Input)toMDC SetupTime 10 ns T2.3.3 MDIO (Input)toMDC HoldTime 10 ns T2.3.4 MDC Frequency 2.5 25 MHz 3.5.4 100 Mb/s MIITransmitTiming Figure3-5.100 Mb/s MIITransmitTiming xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.4.1 TX_CLK High/LowTime 100 Mb/s Normal mode 16 20 24 ns T2.4.2 TXD[3:0],TX_EN Data Setupto 100 Mb/s Normal mode 9.70 ns TX_CLK T2.4.3 TXD[3:0],TX_EN Data Holdfrom 100 Mb/s Normal mode 0 ns TX_CLK Copyright© 2012–2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 21 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

TX_CLK TX_EN TXD PMD output pair (J/K) T2.6.1 IDLE DA T A RX_CLK RXD[3:0] RX_DV RX_ER V alid data T2.5.2 T2.5.1 T2.5.1 DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com 3.5.5 100 Mb/s MIIReceive Timing Figure3-6.100 Mb/s MIIReceive Timing xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.5.1 RX_CLK High/LowTime 100 Mb/s Normal mode 16 20 24 ns T2.5.2 RX_CLK toRXD[3:0],RX_DV, 100 Mb/s Normal mode 10 30 ns RX_ER Delay 3.5.6 100BASE-TX TransmitPacket Latency Timing Figure3-7.100BASE-TX TransmitPacket Latency Timing xxx PARAMETER DESCRIPTION NOTES (1) MIN TYP MAX UNIT T2.6.1 TX_CLK toPMD OutputPair 100 Mb/s Normal mode 6 bits Latency (1) ForNormal mode, latencyisdeterminedby measuringthetimefromthefirstrisingedge ofTX_CLK occurringaftertheassertionof TX_EN tothefirstbitofthe“J”code groupas outputfromthePMD OutputPair.1 bittime= 10 ns in100 Mb/s mode.

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TX_CLK TX_EN TXD PMD output pair (T/R) T2.7.1 IDLEDA T A DP83848-EP www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 3.5.7 100BASE-TX TransmitPacket DeassertionTiming Figure3-8.100BASE-TX TransmitPacket DeassertionTiming xxx PARAMETER DESCRIPTION NOTES (1) MIN TYP MAX UNIT T2.7.1 TX_CLK toPMD OutputPair 100 Mb/s Normal mode 6 bits Deassertion (1) ForNormal mode, latencyisdeterminedby measuringthetimefromthefirstrisingedge ofTX_CLK occurringaftertheassertionof TX_EN tothefirstbitofthe“J”code groupas outputfromthePMD OutputPair.1 bittime= 10 ns in100 Mb/s mode. Copyright© 2012–2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 23 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

T2.8.1 T2.8.1T2.8.1 T2.8.1 +1 rise +1 fall –1 fall –1 rise eye pattern T2.8.2 T2.8.2 90% 10% 10% 90% PMD output pair DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com 3.5.8 100BASE-TX TransmitTiming (tR/F & Jitter) Figure3-9.100BASE-TX TransmitTiming (tR/F & Jitter) xxx PARAMETER DESCRIPTION NOTES (1)(2) MIN TYP MAX UNIT T2.8.1 100 Mb/s PMD OutputPairtR and tF 2.6 4 5.5 ns

100 Mb/s tR and tF Mismatch 500 ps

T2.8.2(3) 100 Mb/s PMD OutputPairTransmit 1.4 ns Jitter (1) Normal Mismatchisthedifferencebetween themaximum and minimum ofallriseand falltimes. (2) Riseand falltimestakenat10% and 90% ofthe+1 or-1amplitude. (3) Specifiedfrom-40°C to125°C.

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(T/R) IDLEDA T APMD input pair CRS T2.10.1 (J/K)IDLE DA T APMD input pair CRS RXD[3:0] RX_DV RX_ER T2.9.1 T2.9.2 DP83848-EP www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 3.5.9 100BASE-TX Receive Packet Latency Timing Figure3-10.100BASE-TX Receive Packet Latency Timing xxx PARAMETER DESCRIPTION (1) NOTES (2)(3) MIN TYP MAX UNIT T2.9.1 CarrierSense ON Delay 100 Mb/s Normal mode 20 bits T2.9.2 ReceiveData Latency 100 Mb/s Normal mode 24 bits (1) CarrierSense On Delayisdeterminedby measuringthetimefromthefirstbitofthe“J”code grouptotheassertionofCarrierSense. (2) 1 bittime= 10 ns in100 Mb/s mode. (3) PMD InputPairvoltageamplitudeisgreaterthantheSignalDetectTurn-OnThresholdValue. 3.5.10 100BASE-TX Receive Packet DeassertionTiming Figure3-11.100BASE-TX Receive Packet DeassertionTiming xxx PARAMETER DESCRIPTION NOTES (1)(2) MIN TYP MAX UNIT T2.10.1 CarrierSense OFF Delay 100 Mb/s Normal mode 24 bits (1) CarrierSense OffDelayisdeterminedby measuringthetimefromthefirstbitofthe“T”code grouptothedeassertionofCarrierSense. (2) 1 bittime= 10 ns in100 Mb/s mode Copyright© 2012–2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 25 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

RX_CLK RXD[3:0] RX_DV V alid data T2.12.2 T2.12.3 T2.12.1 T2.12.1 TX_CLK TXD[3:0] TX_EN V alid data T2.1 1.1 T2.1 1.1 T2.1 1.2 T21 1.3 DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com 3.5.11 10 Mb/s MIITransmitTiming Figure3-12.10 Mb/s MIITransmitTiming xxx PARAMETER DESCRIPTION NOTES (1) MIN TYP MAX UNIT T2.11.1 TX_CLK High/LowTime 10 Mb/s MIImode 190 200 210 ns T2.11.2 TXD[3:0],TX_EN Data Setupto 10 Mb/s MIImode 24.70 ns TX_CLK fall T2.11.3 TXD[3:0],TX_EN Data Holdfrom 10 Mb/s MIImode 0 ns TX_CLK rise (1) An attachedMac shoulddrivethetransmitsignalsusingthepositiveedge ofTX_CLK. As shown above,theMIIsignalsaresampled on thefallingedge ofTX_CLK. 3.5.12 10 Mb/s MIIReceive Timing Figure3-13.10 Mb/s MIIReceive Timing xxx PARAMETER DESCRIPTION NOTES (1) MIN TYP MAX UNIT T2.12.1 RX_CLK High/LowTime 160 200 240 ns T2.12.2 RX_CLK toRXD[3:0],RX_DV 10 Mb/s MIImode 100 ns Delay T2.12.3 RX_CLK risingedge delayfrom 10 Mb/s MIImode 100 ns RXD[3:0],RX_DV Valid (1) RX_CLK may be heldlowfora longerperiodoftimeduringtransitionbetween referenceand recoveredclocks.Minimum highand low timeswillnotbe violated.

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RX_CLK RXD[0] RX_DV V alid data T2.14.2 T2.14.1 T2.14.1 TX_CLK TXD[0] TX_EN V alid data T2.13.1 T2.13.2 T2.13.3 T2.13.4 DP83848-EP www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 3.5.13 10 Mb/s SerialMode TransmitTiming Figure3-14.10 Mb/s SerialMode TransmitTiming xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.13.1 TX_CLK HighTime 10 Mb/s Serialmode 20 25 30 ns T2.13.2 TX_CLK Low Time 10 Mb/s Serialmode 70 75 80 ns T2.13.3 TXD_0, TX_EN Data Setupto 10 Mb/s Serialmode 24.70 ns TX_CLK rise T2.13.4 TXD_0, TX_EN Data Holdfrom 10 Mb/s Serialmode 0 ns TX_CLK rise 3.5.14 10 Mb/s SerialMode Receive Timing Figure3-15.10 Mb/s SerialMode Receive Timing xxx PARAMETER DESCRIPTION NOTES (1) MIN TYP MAX UNIT T2.14.1 RX_CLK High/LowTime 35 50 65 ns T2.14.2 RX_CLK falltoRXD_0, RX_DV 10 Mb/s Serialmode -10 10 ns Delay (1) RX_CLK may be heldhighfora longerperiodoftimeduringtransitionbetween referenceand recoveredclocks.Minimum highand low timeswillnotbe violated. Copyright© 2012–2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 27 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

TX_CLK TX_EN PWD output pair PMD output pair 0 0 T2.16.1 T2.16.2 1 1 TX_CLK TX_EN TXD PMD output pair T2.15.2 T2.15.1 DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com 3.5.15 10BASE-T TransmitTiming (StartofPacket) Figure3-16.10BASE-T TransmitTiming (StartofPacket) xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.15.1 TransmitOutputDelayfromthe 10 Mb/s MIImode 3.5 bits FallingEdge ofTX_CLK T2.15.2 TransmitOutputDelayfromthe 10 Mb/s Serialmode 3.5 bits RisingEdge ofTX_CLK 3.5.16 10BASE-T TransmitTiming (End ofPacket) Figure3-17.10BASE-T TransmitTiming (End ofPacket) xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.16.1 End ofPacketHighTime (with‘0’ 250 300 ns endingbit) T2.16.2 End ofPacketHighTime (with‘1’ 250 300 ns endingbit)

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RX_CLK CRS IDLE T2.18.1 First SFD bit decoded 1 0 1 0 1 0 101011 TPRD± CRS T2.17.1 T2.17.2 0000 T2.17.3 Preamble SFD Data RX_CLK RX_DV RXD[3:0] DP83848-EP www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 3.5.17 10BASE-T Receive Timing (StartofPacket) Figure3-18.10BASE-T Receive Timing (StartofPacket) xxx PARAMETER DESCRIPTION NOTES (1)(2) MIN TYP MAX UNIT T2.17.1 CarrierSense TurnOn Delay(PMD 630 1000 ns InputPairtoCRS) T2.17.2 RX_DV Latency 10 bits T2.17.3 ReceiveData Latency Measurement shown fromSFD 8 bits (1) 10BASE-T RX_DV Latencyismeasured fromfirstbitofpreambleon thewiretotheassertionofRX_DV (2) 1 bittime= 100 ns in10 Mb/s mode. 3.5.18 10BASE-T Receive Timing (End ofPacket) Figure3-19.10BASE-T Receive Timing (End ofPacket) xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.18.1 CarrierSense TurnOffDelay 1 µs Copyright© 2012–2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 29 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

T2.21.1 T2.21.2 TXE PMD output pair COL T2.20.1 T2.20.2 TX_CLK TX_EN COL T2.19.1 T2.19.2 DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com 3.5.19 10 Mb/s HeartbeatTiming Figure3-20.10 Mb/s HeartbeatTiming xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.19.1 CD HeartbeatDelay All10 Mb/s modes 1200 ns T2.19.2 CD HeartbeatDuration All10 Mb/s modes 1000 ns 3.5.20 10 Mb/s Jabber Timing Figure3-21.10 Mb/s Jabber Timing xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.20.1 JabberActivationTime 85 ms T2.20.2 JabberDeactivationTime 500 ms 3.5.21 10BASE-T Normal LinkPulse Timing Figure3-22.10BASE-T Normal LinkPulse Timing xxx PARAMETER DESCRIPTION NOTES (1) MIN TYP MAX UNIT T2.21.1 PulseWidth 100 ns T2.21.2 PulsePeriod 16 ms (1) These specificationsrepresenttransmittimings.

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T2.23.1 T2.23.2 Fast link pulses T2.22.1 T2.22.3 T2.22.2 T2.22.1 T2.22.5 T2.22.4 clock pulse clock pulse data pulse FLP burst FLP burst DP83848-EP www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013

3.5.22 Auto-NegotiationFastLinkPulse (FLP)Timing

Figure3-23.Auto-NegotiationFastLinkPulse (FLP)Timing xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.22.1 Clock,Data PulseWidth 100 ns T2.22.2 ClockPulsetoClockPulsePeriod 125 μs T2.22.3 ClockPulsetoData PulsePeriod Data = 1 62 μs T2.22.4 BurstWidth 2 ms T2.22.5 FLP BursttoFLP BurstPeriod 16 ms 3.5.23 100BASE-TX SignalDetectTiming Figure3-24.100BASE-TX SignalDetectTiming xxx PARAMETER DESCRIPTION NOTES (1) MIN TYP MAX UNIT T2.23.1 SD InternalTurn-onTime 1 ms T2.23.2 SD InternalTurn-offTime 350 µs (1) The signalamplitudeon PMD InputPairmust be TP-PMD compliant. Copyright© 2012–2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 31 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

TX_CLK TX_EN TXD[3:0] CRS RX_CLK RXD[3:0] RX_DV T2.24.1 DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com 3.5.24 100 Mb/s InternalLoopback Timing Figure3-25.100 Mb/s InternalLoopback Timing xxx PARAMETER DESCRIPTION NOTES (1)(2) MIN TYP MAX UNIT T2.24.1 TX_EN toRX_DV Loopback 100 Mb/s internalloopbackmode 240 ns (1) Due tothenatureofthedescramblerfunction,all100BASE-TX Loopback modes willcause an initial“dead-time”ofup to550 μs during whichtimeno datawillbe presentatthereceiveMIIoutputs.The 100BASE-TX timingspecifiedisbased on devicedelaysafterthe initial550μs “dead-time”. (2) Measurement ismade fromthefirstrisingedge ofTX_CLK afterassertionofTX_EN.

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TX_CLK TX_EN TXD[3:0] CRS RX_CLK RXD[3:0] RX_DV T2.25.1 DP83848-EP www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 3.5.25 10 Mb/s InternalLoopback Timing Figure3-26.10 Mb/s InternalLoopback Timing xxx PARAMETER DESCRIPTION NOTES (1) MIN TYP MAX UNIT T2.25.1 TX_EN toRX_DV Loopback 10 Mb/s internalloopbackmode 2 µs (1) Measurement ismade fromthefirstrisingedge ofTX_CLK afterassertionofTX_EN. Copyright© 2012–2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 33 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

TXD[1:0] TX_EN V alid data PMD output pair Symbol T2.26.1 T2.26.4 T2.26.2 T2.26.3 DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com

3.5.26 RMII TransmitTiming

Figure3-27.RMII TransmitTiming xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.26.1 X1 ClockPeriod 50 MHz ReferenceClock 20 ns T2.26.2 TXD[1:0],TX_EN, Data Setupto 3.70 ns X1 rising T2.26.3 TXD[1:0],TX_EN, Data Holdfrom 1.70 ns X1 rising T2.26.4 X1 ClocktoPMD OutputPair From X1 Risingedge tofirstbitof 17 bits Latency symbol

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CRS_DV RXD[1:0] RX_ER T2.27.2 T2.27.1 T2.27.2 PMD Input Pair T2.27.3 T2.27.5 RX_DV T2.27.2 T2.27.2 IDLE (J/K) Data (TR) Data T2.27.4 DP83848-EP www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013

3.5.27 RMII Receive Timing

Figure3-28.RMII Receive Timing xxx PARAMETER DESCRIPTION NOTES (1)(2)(3) MIN TYP MAX UNIT T2.27.1 X1 ClockPeriod 50 MHz ReferenceClock 20 ns T2.27.2 RXD[1:0],CRS_DV, RX_DV and 2 14 ns RX_ER outputdelayfromX1 rising T2.27.3 CRS ON delay From JK symbolon PMD 18.5 bits ReceivePairtoinitialassertion ofCRS_DV T2.27.4 CRS OFF delay From TR symbolon PMD 27 bits ReceivePairtoinitial deassertionofCRS_DV T2.27.5 RXD[1:0]and RX_ER latency From symbolon ReceivePair. 38 bits Elasticitybuffersettodefault value(01). (1) Per theRMII Specification,outputdelaysassume a 25pF load. (2) CRS_DV isassertedasynchronouslyinordertominimizelatencyofcontrolsignalsthroughthewhy.CRS_DV may toggle synchronouslyattheend ofthepackettoindicateCRS deassertion. (3) RX_DV issynchronoustoX1.WhilenotpartoftheRMII specification,thissignalisprovidedtosimplifyrecoveryofreceivedata. Copyright© 2012–2013,Texas InstrumentsIncorporated ELECTRICAL SPECIFICATIONS 35 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

25 MHz_OUT

T2.29.2 T2.29.1T2.29.1 Clear bit 10 of BMCR (return to normal operation from Isolate mode) Hardware or Software Reset (with PHYAD 00000)/c185 MODE T2.28.1 T2.28.2 ISOLATE NORMAL DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com

3.5.28 IsolationTiming

Figure3-29.IsolationTiming xxx PARAMETER DESCRIPTION NOTES MIN TYP MAX UNIT T2.28.1 From softwareclearofbit10 inthe 100 µs BMCR registertothetransitionfrom IsolatetoNormal Mode T2.28.2 From DeassertionofS/W orH/W Reset 500 µs totransitionfromIsolatetoNormal mode 3.5.29 25 MHz_OUT Timing Figure3-30.25 MHz_OUT Timing xxx PARAMETER DESCRIPTION NOTES (1) MIN TYP MAX UNIT MIImode 20 T2.29.1 25 MHz_OUT High/LowTime ns RMII mode 10 T2.29.2 25 MHz_OUT propagationdelay RelativetoX1 8 ns (1) 25 MHz_OUT characteristicsaredependentupon theX1 inputcharacteristics.

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013

4 CONFIGURATION

4.1 Auto-Negotiation

The auto-negotiationfunctionprovidesa mechanism forexchangingconfigurationinformationbetween two ends of a linksegment and automaticallyselectingthe highestperformancemode of operation supportedby bothdevices.Fastlinkpulse(FLP)burstsprovidethesignallingused tocommunicate auto- negotiationabilitiesbetween two devicesateach end ofa linksegment.For furtherdetailregardingauto- negotiation,referto Clause 28 of the IEEE 802.3u specification.The DP83848 supportsfourdifferent ethernetprotocols(10 Mb/s halfduplex,10 Mb/s fullduplex,100 Mb/s halfduplex,and 100 Mb/s full duplex),so theinclusionofauto-negotiationensuresthatthehighestperformanceprotocolwillbe selected based on theadvertisedabilityofthelinkpartner.The auto-negotiationfunctionwithintheDP83848 can be controlledeitherby internalregisteraccessorby theuse oftheAN_EN, AN1 and AN0 pins.

4.1.1 Auto-NegotiationPin Control

The stateofAN_EN, AN0 and AN1 determineswhethertheDP83848 isforcedintoa specificmode or auto-negotiationwilladvertisea specificability(orsetofabilities)as giveninTable4-1.These pinsallow configurationoptionstobe selectedwithoutrequiringinternalregisteraccess. The stateofAN_EN, AN0 and AN1, upon power-up/reset,determinesthestateofbits[8:5]oftheANAR register. The auto-negotiationfunctionselectedatpower-uporresetcan be changed atany timeby writingtothe basicmode controlregister(BMCR) ataddress0x00h. Table4-1.Auto-NegotiationModes AN_EN AN1 AN0 Forced Mode 0 0 0 10BASE-T, HalfDuplex 0 0 1 10BASE-T, FullDuplex 0 1 0 100BASE-TX, HalfDuplex 0 1 1 100BASE-TX, FullDuplex AN_EN AN1 AN0 AdvertisedMode 1 0 0 10BASE-T, HalforFullDuplex 1 0 1 100BASE-TX, HalforFullDuplex 10BASE-T HalfDuplex1 1 0 100BASE-TX, HalfDuplex 10BASE-T, Half/FullDuplex1 1 1 100BASE-TX, Half/FullDuplex

4.1.2 Auto-NegotiationRegisterControl

When auto-negotiationis enabled,the DP83848 transmitsthe abilitiesprogrammed intothe auto- negotiationadvertisementregister(ANAR) ataddress04h viaFLP Bursts.Any combinationof10 Mb/s, 100 Mb/s,halfduplex,and fullduplexmodes may be selected. Auto-negotiationpriorityresolution: 1. 100BASE-TX FullDuplex(HighestPriority) 2. 100BASE-TX HalfDuplex 3. 10BASE-T FullDuplex 4. 10BASE-T HalfDuplex(LowestPriority) Copyright© 2012–2013,Texas InstrumentsIncorporated CONFIGURATION 37 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com The basicmode controlregister(BMCR) at address 00h providescontrolforenabling,disabling,and restartingtheauto-negotiationprocess.When auto-negotiationisdisabled,thespeed selectionbitinthe BMCR controlsswitchingbetween 10 Mb/s or 100 Mb/s operation,and the duplexmode bitcontrols switchingbetween fullduplexoperationand halfduplexoperation.The speed selectionand duplexmode bitshave no effecton themode ofoperationwhen theauto-negotiationenablebitisset. The linkspeed can be examined throughthePHY statusregister(PHYSTS) ataddress10h aftera Linkis achieved. The BMSR indicatesthe set of availableabilitiesfortechnologytypes,auto-negotiationability,and extended registercapability.These bitsare permanentlyset to indicatethe fullfunctionalityof the DP83848 (onlythe100BASE-T4 bitisnotsetsincetheDP83848 does notsupportthatfunction). The BMSR alsoprovidesstatuson:

• Whether ornotauto-negotiationiscomplete
• Whether ornottheLinkPartnerisadvertisingthata remotefaulthas occurred
• Whether ornotvalidlinkhas been established
• Supportformanagement framepreamblesuppression The ANAR indicatestheauto-negotiationabilitiestobe advertisedby theDP83848. Allavailableabilities aretransmittedby default,butany abilitycan be suppressedby writingtotheANAR. UpdatingtheANAR tosuppressan abilityisone way fora management agenttochange (restrict)thetechnologythatisused. The auto-negotiationlinkpartnerabilityregister(ANLPAR) ataddress05h isused toreceivethebase link code word as wellas allnextpage code words duringthenegotiation.Furthermore,theANLPAR willbe updatedtoeither0081h or0021h forparalleldetectiontoeither100 Mb/s or10 Mb/s respectively. The auto-negotiationexpansionregister(ANER) indicatesadditionalauto-negotiationstatus.The ANER providesstatuson:
• Whether ornota paralleldetectfaulthas occurred
• Whether ornotthelinkpartnersupportsthenextpage function
• Whether ornottheDP83848 supportsthenextpage function
• Whether ornotthecurrentpage beingexchanged by auto-negotiationhas been received
• Whether ornotthelinkpartnersupportsautonegotiation

4.1.3 Auto-NegotiationParallelDetection

The DP83848 supportstheparalleldetectionfunctionas definedintheIEEE 802.3uspecification.Parallel detectionrequiresboththe10 Mb/s and 100 Mb/s receiverstomonitorthereceivesignaland reportlink statusto the auto-negotiationfunction.Auto-negotiationuses thisinformationto configurethe correct technologyin the event thatthe linkpartnerdoes not supportauto-negotiationbut istransmittinglink signalsthatthe100BASE-TX or10BASET PMAs recognizeas validlinksignals. Ifthe DP83848 completesauto-negotiationas a resultof paralleldetection,bits5 and 7 withinthe ANLPAR registerwillbe settoreflectthemode ofoperationpresentinthelinkpartner.Note thatbits4:0 oftheANLPAR willalsobe setto00001 based on a successfulparalleldetectiontoindicatea valid802.3 selectorfield.Softwaremay determinethatnegotiationcompletedviaparalleldetectionby readinga zero inthelinkpartnerauto-negotiationablebitonce theauto-negotiationcompletebitisset.Ifconfiguredfor paralleldetectmode and any conditionotherthana singlegood linkoccursthentheparalleldetectfault bitwillbe set.

4.1.4 Auto-NegotiationRestart

Once auto-negotiationhas completed,itmay be restartedat any time by settingbit9 (restartauto- negotiation)oftheBMCR toone.Ifthemode configuredby a successfulauto-negotiationlosesa valid link,thentheauto-negotiationprocesswillresume and attempttodeterminetheconfigurationforthelink. Thisfunctionensuresthata validconfigurationismaintainedifthecablebecomes disconnected.

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 A renegotiationrequestfromany entity,such as a management agent,willcause theDP83848 tohaltany transmitdataand linkpulseactivityuntilthebreak_link_timerexpires(~1500 ms).Consequently,thelink partnerwillgo intolinkfailand normal auto-negotiationresumes. The DP83848 willresume auto- negotiationafterthebreak_link_timerhas expiredby issuingFLP bursts.

4.1.5 EnablingAuto-NegotiationviaSoftware

ItisimportanttonotethatiftheDP83848 has been initializedupon power-upas a non-auto-negotiating device(forcedtechnology),and itisthenrequiredthatauto-negotiationorre-auto-negotiationbe initiated viasoftware,bit12 (auto-negotiationenable)oftheBMCR must firstbe clearedand thensetforany auto- negotiationfunctiontotakeeffect.

4.1.6 Auto-NegotiationComplete Time

Paralleldetectionand auto-negotiationtake approximately2-3 seconds to complete.In addition,auto- negotiationwithnextpage shouldtakeapproximately2-3seconds tocomplete,dependingon thenumber ofnextpages sent. Referto Clause 28 of the IEEE 802.3u standardfora fulldescriptionof the individualtimersrelatedto auto-negotiation.

4.2 Auto-MDIX

When enabled,thisfunctionutilizesauto-negotiationtodeterminetheproperconfigurationfortransmission and receptionof data and subsequentlyselectsthe appropriateMDI pairforMDI/MDIX operation.The functionuses a random seed tocontrolswitchingofthecrossovercircuitry.Thisimplementationcomplies withthecorrespondingIEEE 802.3auto-negotiationand crossoverspecifications. Auto-MDIX isenabledby defaultand can be configuredviastrapor viaPHYCR (0x19h)register,bits [15:14]. Neitherauto-negotiationnor auto-MDIX isrequiredtobe enabledinforcingcrossoveroftheMDI pairs. Forcedcrossovercan be achievedthroughtheFORCE_MDIX bit,bit14 ofPHYCR (0x19h)register. NOTE Auto-MDIX willnotwork ina forcedmode ofoperation.

4.3 PHY Address

The 5 PHY addressinputspinsaresharedwiththeRXD[3:0]pinsand COL pinas shown below. Table4-2.PHY Address Mapping PIN NUMBER PHYAD FUNCTION RXD FUNCTION

42 PHYAD0 COL

43 PHYAD1 RXD_0

44 PHYAD2 RXD_1

45 PHYAD3 RXD_2

46 PHYAD4 RXD_3

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COLRXD_0RXD_1RXD_2RXD_3 VCC 2.2 k Ω PHYAD0 = 1PHYAD1 = 1PHYAD2 = 0PHY AD3 = 0PHYAD4 = 0 DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com The DP83848 can be settorespondtoany of32 possiblePHY addressesviastrappins.The information islatchedintothe PHYCR (address19h, bits[4:0])at devicepower-up and hardware reset.The PHY addresspinsare sharedwiththeRXD and COL pins.Each DP83848 or portsharingan MDIO bus ina systemmust have a uniquephysicaladdress. The DP83848 supportsPHY addressstrappingvalues0 (<00000>)through31 (<11111>).StrappingPHY address0 putsthepartintoisolatemode. Itshouldalsobe notedthatselectingPHY address0 viaan MDIO writetoPHYCR willnotputthedeviceinisolatemode. For furtherdetailrelatingtothelatch-intimingrequirementsofthePHY addresspins,as wellas theother hardwareconfigurationpins,refertotheResetsummary inSection8. SincethePHYAD[0] pinhas weak internalpull-upresistorand PHYAD[4:1] pinshave weak internalpull- down resistors,thedefaultsettingforthePHY addressis00001 (01h). RefertoFigure4-1foran example ofa PHYAD connectiontoexternalcomponents.Inthisexample,the PHYAD strappingresultsinaddress00011 (03h). Figure4-1.PHYAD StrappingExample

4.3.1 MIIIsolateMode

The DP83848 can be putintoMIIisolatemode by writingtobit10 oftheBMCR registerorby strappingin physicaladdress0.Itshouldbe notedthatselectingphysicaladdress0 viaan MDIO writetoPHYCR will notputthedeviceintheMIIisolatemode. When intheMIIisolatemode, theDP83848 does notrespondtopacketdatapresentatTXD[3:0],TX_EN inputsand presentsa highimpedance on theTX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0],COL, and CRS outputs.When in Isolatemode, the DP83848 willcontinueto respond to allmanagement transactions. While in Isolatemode, the PMD outputpairwillnot transmitpacketdata but willcontinueto source 100BASE-TX scrambledidlesor10BASE-T normallinkpulses. The DP83848 can auto-negotiateor paralleldetectto a specifictechnologydependingon the receive signalatthePMD inputpair.A validlinkcan be establishedforthereceivereven when theDP83848 isin Isolatemode.

4.4 LED Interface

The DP83848 supportsthreeconfigurablelightemittingdiode(LED) pins.The devicesupportsthreeLED configurations:Link,Speed, Activityand Collision.Functionsare multiplexedamong the LEDs. The PHYCR fortheLEDs can alsobe selectedthroughaddress19h,bits[6:5].

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Table4-3.LED Mode Select LED_CFG[0]LED_CGF[1]MODE (BIT5) LED_LINK LED_SPEED LED_ACT/COL(BIT6) or (PIN40) ON forGood Link ON in100 Mb/s ON forActivity1 don'tcare 1 OFF forNo Link OFF in10 Mb/s OFF forNo Activity ON forGood Link ON in100 Mb/s ON forCollision2 0 0 BLINK forActivity OFF in10 Mb/s OFF forNo Collision ON forGood Link ON in100 Mb/s ON forFullDuplex3 1 0 BLINK forActivity OFF in10 Mb/s OFF forHalfDuplex The LED_LINK pininMode 1 indicatesthelinkstatusoftheport.In100BASE-T mode, linkisestablished as a resultofinputreceiveamplitudecompliantwiththeTPPMD specificationswhichwillresultininternal generationofsignaldetect.A 10 Mb/s Linkisestablishedas a resultofthereceptionofatleastseven consecutivenormallinkpulsesorthereceptionofa valid10BASE-T packet.Thiswillcause theassertion ofLED_LINK. LED_LINK willdeassertinaccordancewiththeLinkLoss Timer as specifiedintheIEEE 802.3specification. The LED_LINK pininMode 1 willbe OFF when no LINK ispresent. The LED_LINK pininMode 2 and Mode 3 willbe ON to indicateLinkisgood and BLINK to indicate activityispresenton eithertransmitorreceiveactivity. The LED_SPEED pinindicates10 or100 Mb/s datarateoftheport.The standardCMOS drivergoes high when operatingin100 Mb/s operation.The functionalityofthisLED isindependentofmode selected. The LED_ACT/COL pininMode 1 indicatesthepresenceofeithertransmitor receiveactivity.The LED willbe ON forActivityand OFF forNo Activity.InMode 2,thispinindicatestheCollisionstatusoftheport. The LED willbe ON forCollisionand OFF forNo Collision. The LED_ACT/COL pin in Mode 3 indicatesthe presence of duplexstatusfor10 Mb/s or 100 Mb/s operation.The LED willbe ON forfullduplexand OFF forhalfduplex. In10 Mb/s halfduplexmode, thecollisionLED isbased on theCOL signal. SincetheseLED pinsarealsoused as strapoptions,thepolarityoftheLED isdependenton whetherthe pinispulledup ordown.

4.4.1 LEDs

Since the auto-negotiation(AN) strapoptionsshare the LED outputpins,the externalcomponents requiredforstrappingand LED usage must be consideredinordertoavoidcontention. Specifically,when theLED outputsareused todriveLEDs directly,theactivestateofeach outputdriveris dependenton thelogiclevelsampled by thecorrespondingAN inputupon power-up/reset.For example,if a givenAN inputisresistivelypulledlow then the correspondingoutputwillbe configuredas an active highdriver.Conversely,ifa givenAN inputisresistivelypulledhigh,thenthecorrespondingoutputwillbe configuredas an activelowdriver. RefertoFigure4-2 foran example ofAN connectionstoexternalcomponents.Inthisexample,theAN strappingresultsinauto-negotiationwith10/100halforfullduplexadvertised. The adaptivenatureof the LED outputshelpsto simplifypotentialimplementationissuesof thesedual purposepins. Copyright© 2012–2013,Texas InstrumentsIncorporated CONFIGURATION 41 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

LED_LINKLED_SPEEDLED_ACT/COL VCC 2.2 k Ω 1 10 Ω 1 10 Ω2.2 k Ω 1 10 Ω AN0 = 1AN1 = 1AN_EN = 1 2.2 k Ω DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com Figure4-2.AN Strappingand LED Loading Example

4.4.2 LED DirectControl

The DP83848 providesanotheroptiontodirectlycontrolany or allLED outputsthroughtheLED direct controlregister(LEDCR), address18h.The registerdoes notprovidereadaccesstoLEDs.

4.5 HalfDuplex vs FullDuplex

The DP83848 supportsbothhalfand fullduplexoperationatboth10 Mb/s and 100 Mb/s speeds. Halfduplexrelieson theCSMA/CD protocoltohandlecollisionsand networkaccess.Inhalfduplexmode, CRS respondstobothtransmitand receiveactivityinordertomaintaincompliancewiththeIEEE 802.3 specification. Since the DP83848 isdesignedto supportsimultaneoustransmitand receiveactivityitiscapableof supportingfullduplexswitchedapplicationswitha throughputofup to200 Mb/s perportwhen operatingin 100BASE-TX mode. Because theCSMA/CD protocoldoes notapplytofullduplexoperation,theDP83848 disablesitsown internalcollisionsensingand reportingfunctionsand modifiesthe behaviorof carrier sense (CRS) such thatitindicatesonlyreceiveactivity.Thisallowsa fullduplexcapableMAC tooperate properly. Allmodes of operation(100BASE-TX and 10BASE-T) can run eitherhalfduplex or fullduplex. Additionally,otherthan CRS and collisionreporting,allremainingMII signalingremains the same regardlessoftheselectedduplexmode. Itisimportantto understandthatwhileauto-negotiationwiththe use of fastlinkpulsecode words can interpretand configuretofullduplexoperation,paralleldetectioncan notrecognizethedifferencebetween fulland halfduplexfrom a fixed10 Mb/s or 100 Mb/s linkpartnerovertwistedpair.As specifiedinthe 802.3uspecification,ifa far-endlinkpartnerisconfiguredtoa forcedfullduplex100BASE-TX ability,the paralleldetectionstatemachine inthepartnerwould be unabletodetectthefullduplexcapabilityofthe far-endlinkpartner.Thislinksegment would negotiatetoa halfduplex100BASE-TX configuration(same scenariofor10 Mb/s).

4.6 InternalLoopback

The DP83848 includesa loopbacktestmode forfacilitatingsystem diagnostics.The loopbackmode is selectedthroughbit14 (loopback)oftheBMCR. Writing1 tothisbitenablesMIItransmitdatatobe routed totheMIIreceiveoutputs.Loopback statusmay be checked inbit3 ofPHYSTS. WhileinLoopback mode thedatawillnotbe transmittedontothemedia.To ensurethatthedesiredoperatingmode ismaintained, Auto-Negotiationshouldbe disabledbeforeselectingtheloopbackmode.

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4.7 BIST

The DP83848 incorporatesan internalbuilt-inselftest(BIST)circuittoaccommodate in-circuittestingor diagnostics.The BIST circuitcan be utilizedtotesttheintegrityofthetransmitand receivedatapaths. BIST testingcan be performedwiththepartintheinternalloopbackmode orexternallyloopedback using a loopbackcablefixture. The BIST isimplementedwithindependenttransmitand receivepaths,withthetransmitblockgenerating a continuousstreamofa pseudo random sequence.The usercan selecta 9 bitor15 bitpseudo random sequence from thePSR_15 bitinthePHYCR. The receiveddataiscompared tothegeneratedpseudo- random databy theBIST linearfeedbackshiftregister(LFSR) todeterminetheBIST pass orfailstatus. The pass or failstatusoftheBIST isstoredintheBIST statusbitinthePHYCR register.The statusbit defaultsto0 (BIST fail)and willtransitionon a successfulcomparison.Ifan error(mis-compare)occurs, thestatusbitislatchedand isclearedupon a subsequentwritetotheStart/Stopbit. For transmitVOD testing,the packet BIST continuousmode can be used to allowcontinuousdata transmission,settingBIST_CONT_MODE, bit5,ofCDCTRL1 (0x1Bh). The number ofBIST errorscan be monitoredthroughtheBIST errorcountintheCDCTRL1 (0x1Bh),bits [15:8]. Copyright© 2012–2013,Texas InstrumentsIncorporated CONFIGURATION 43 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

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5 FUNCTIONAL DESCRIPTION

The DP83848 supportsseveralmodes ofoperationusingtheMIIinterfacepins.The optionsaredefinedin thefollowingsectionsand include:

• MIImode
• RMII mode
• 10 Mb serialnetworkinterface(SNI) The modes ofoperationcan be selectedby strapoptionsorregistercontrol.For RMII mode, itisrequired touse thestrapoption,sinceitrequiresa 50 MHz clockinsteadofthenormal25 MHz. In each of these modes, the IEEE 802.3 serialmanagement interfaceis operationalfor device configurationand status.The serialmanagement interfaceof the MII allowsforthe configurationand controlofmultiplePHY devices,gatheringofstatus,errorinformation,and thedeterminationofthetype and capabilitiesoftheattachedPHY(s).

5.1 MIIInterface

The DP83848 incorporatesthemedia independentinterface(MII)as specifiedinClause 22 oftheIEEE 802.3ustandard.Thisinterfacemay be used toconnectPHY devicestoa MAC in10/100Mb/s systems. ThissectiondescribesthenibblewideMIIdatainterface. The nibblewide MIIdatainterfaceconsistsofa receivebus and a transmitbus each withcontrolsignals tofacilitatedatatransferbetween thePHY and theupperlayer(MAC).

5.1.1 Nibble-WideMIIData Interface

Clause 22 of the IEEE 802.3u specificationdefinesthe media independentInterface.This interface includesa dedicatedreceivebus and a dedicatedtransmitbus.These two databuses,alongwithvarious controland statussignals,allowforthe simultaneousexchange of data between the DP83848 and the upperlayeragent(MAC). The receiveinterfaceconsistsofa nibblewidedatabus RXD[3:0],a receiveerrorsignalRX_ER, a receive data validflagRX_DV, and a receiveclockRX_CLK forsynchronoustransferof the data.The receive clockoperatesateither2.5MHz tosupport10 Mb/s operationmodes orat25 MHz tosupport100 Mb/s operationalmodes. The transmitinterfaceconsistsof a nibblewide data bus TXD[3:0],a transmitenable controlsignal TX_EN, and a transmitclockTX_CLK whichrunsateither2.5MHz or25 MHz. Additionally,theMIIincludesthecarriersense signalCRS, as wellas a collisiondetectsignalCOL. The CRS signalassertstoindicatethereceptionofdatafromthenetworkoras a functionoftransmitdatain halfduplexmode. The COL signalassertsas an indicationof a collisionwhich can occurduringhalf duplexoperationwhen botha transmitand receiveoperationoccursimultaneously.

5.1.2 CollisionDetect

Forhalfduplex,a 10BASE-T or100BASE-TX collisionisdetectedwhen thereceiveand transmitchannels areactivesimultaneously.Collisionsarereportedby theCOL signalon theMII. IftheDP83848 istransmittingin10 Mb/s mode when a collisionisdetected,thecollisionisnotreported untilseven bitshave been receivedwhileinthecollisionstate.Thispreventsa collisionbeingreported incorrectlydue tonoiseon thenetwork.The COL signalremainssetforthedurationofthecollision. Ifa collisionoccursduringa receiveoperation,itisimmediatelyreportedby theCOL signal. When heartbeatis enabled (onlyapplicableto 10 Mb/s operation),approximately1μs afterthe transmissionofeach packet,a signalqualityerror(SQE) signalofapproximately10 bittimesisgenerated (internally)toindicatesuccessfultransmission.SQE isreportedas a pulseon theCOL signaloftheMII.

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5.1.3 CarrierSense

Carriersense (CRS) isasserteddue to receiveactivity,once validdata isdetectedviathe squelch functionduring10 Mb/s operation.During100 Mb/s operationCRS isassertedwhen a validlink(SD) and two non-contiguouszerosaredetectedon theline. For10 or100 Mb/s halfduplexoperation,CRS isassertedduringeitherpackettransmissionorreception. For10 or100 Mb/s fullduplexoperation,CRS isassertedonlydue toreceiveactivity. CRS isdeassertedfollowingan end ofpacket.

5.2 Reduced MIIInterface

The DP83848 incorporatesthe reduced media independentinterface(RMII)as specifiedin the RMII specification(rev1.2)fromtheRMII Consortium.Thisinterfacemay be used toconnectPHY devicestoa MAC in10/100Mb/s systemsusinga reducednumber ofpins.Inthismode, dataistransferred2-bitsata timeusingthe50 MHz RMII_REF clockforbothtransmitand receive.The followingpinsareused inRMII mode:

• TX_EN
• TXD[1:0]
• RX_ER (optionalforMac)
• CRS_DV
• RXD[1:0]
• X1 (RMIIReferenceclockis50 MHz) In addition,the RMII mode suppliesan RX_DV signalwhich allowsfora simplermethod of recovering receivedatawithouthavingtoseparateRX_DV fromtheCRS_DV indication.Thisisespeciallyusefulfor systemswhichdo notrequireCRS, such as systemsthatonlysupportfullduplexoperation.Thissignalis alsousefulfordiagnostictestingwhere itmay be desirableto loop Receive RMII data directlyto the transmitter. Since the referenceclockoperatesat 10 timesthe data ratefor10 Mb/s operation,transmitdata is sampled every10 clocks.Likewise,receivedatawillbe generatedevery10thclockso thatan attached devicecan sample thedataevery10 clocks. RMII mode requiresa 50 MHz oscillatorbe connectedto the deviceX1 pin.A 50 MHz crystalisnot supported. To toleratepotentialfrequencydifferencesbetween the50 MHz referenceclockand therecoveredreceive clock,the receiveRMII functionincludesa programmable elasticitybuffer.The elasticitybufferis programmable to minimizepropagationdelaybased on expectedpacketsizeand clockaccuracy.This allowsforsupportinga rangeofpacketsizesincludingjumbo frames. The elasticitybufferwillforceframe check sequence errorsforpacketswhich overrunor underrunthe FIFO. Underrun and Overrun conditionscan be reportedin the RMII and bypass register(RBR). The followingtableindicateshow toprogram theelasticitybufferfifo(in4-bitincrements)based on expected max packetsizeand clockaccuracy.Itassumes bothclocks(RMIIreferenceclockand far-endtransmitter clock)have thesame accuracy. Table5-1.Supported Packet Sizesat±50ppm and ±100ppm forEach Clock START THRESHOLD RECOMMENDED PACKET SIZE RECOMMENDED PACKET SIZELATENCY TOLERANCERBR[1:0] at±50ppm at±100ppm 1 (4-bits) 2 bits 2400 bytes 1200 bytes 2 (8-bits) 6 bits 7200 bytes 3600 bytes 3 (12-bits) 10 bits 12000 bytes 6000 bytes 0 (16-bits) 14 bits 16800 bytes 8400 bytes Copyright© 2012–2013,Texas InstrumentsIncorporated FUNCTIONAL DESCRIPTION 45 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com 5.3 10 Mb SerialNetwork Interface(SNI) The DP83848 incorporatesa 10 Mb serialnetworkinterface(SNI)which allowsa simpleserialdata interfacefor10 Mb onlydevices.Thisisalsoreferredtoas a 7-wireinterface.Whilethereisno defined standardforthisinterface,itisbased on early10 Mb physicallayerdevices.Data isclockedseriallyat 10 MHz usingseparatetransmitand receivepaths.The followingpinsareused inSNI mode:

• TX_CLK
• TX_EN
• TXD[0]
• RX_CLK
• RXD[0]
• CRS
• COL 5.4 802.3uMIISerialManagement Interface

5.4.1 SerialManagement RegisterAccess

The serialmanagement MIIspecificationdefinesa setofthirty-two16-bitstatusand controlregistersthat areaccessiblethroughthemanagement interfacepinsMDC and MDIO. The DP83848 implementsallthe requiredMIIregistersas wellas severaloptionalregisters.A descriptionoftheserialmanagement access protocolfollows.

5.4.2 SerialManagement Access Protocol

The serialcontrolinterfaceconsistsof two pins,management data clock(MDC) and management data input/output(MDIO).MDC has a maximum clockrateof25 MHz and no minimum rate.The MDIO lineis bi-directionaland may be shared by up to 32 devices.The MDIO frame formatis shown below in Table5-2. The MDIO pinrequiresa pull-upresistor(1.5kΩ)which,duringIDLE and turnaround,willpullMDIO high. InordertoinitializetheMDIO interface,thestationmanagement entitysends a sequence of32 contiguous logicones on MDIO to providethe DP83848 with a sequence that can be used to establish synchronization.Thispreamblemay be generatedeitherby drivingMDIO highfor32 consecutiveMDC clockcycles,orby simplyallowingtheMDIO pull-upresistortopulltheMDIO pinhighduringwhichtime 32 MDC clockcyclesareprovided.Inaddition32 MDC clockcyclesshouldbe used tore-syncthedevice ifan invalidstart,opcode,orturnaroundbitisdetected. The DP83848 waitsuntilithas receivedthispreamble sequence beforerespondingto any other transaction.Once the DP83848 serialmanagement port has been initializedno furtherpreamble sequencingisrequireduntilaftera power-on/reset,invalidstart,invalidopcode,or invalidturnaroundbit has occurred. The startcode isindicatedby a <01> pattern.ThisassurestheMDIO linetransitionsfromthedefaultidle linestate. Turnaroundisdefinedas an idlebittimeinsertedbetween theregisteraddressfieldand thedatafield.To avoidcontentionduringa read transaction,no deviceshallactivelydrivetheMDIO signalduringthefirst bitofturnaround.The addressedDP83848 drivestheMDIO witha zeroforthesecond bitofturnaround and followsthiswiththerequireddata.Figure5-1 shows thetimingrelationshipbetween MDC and the MDIO as drivenor receivedby the station(STA) and the DP83848 (PHY) fora typicalregisterread access. For writetransactions,the stationmanagement entitywritesdata to the addressed DP83848 thus eliminatingtherequirementforMDIO turnaround.The turnaroundtimeisfilledby themanagement entity by inserting<10>.Figure5-2shows thetimingrelationshipfora typicalMIIregisterwriteaccess.

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(STA) Idle Start Opcode (Write) PHY Address (PHYAD = 0Ch) Register Address (00h = BMCR) TA Register Data Idle z z 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 z z MDC MDIO (STA) Idle Start Opcode (Read) PHY Address (PHY AD = 0Ch) Register Address (00h = BMCR) T A Register Data z MDIO (PHY) z z Idle z z z z0 1 01 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 DP83848-EP www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Table5-2.TypicalMDIO Frame Format MIIMANAGEMENT SERIAL <idle><start><op code><deviceaddr><reg addr><turnaround><data><idle>PROTOCOL Figure5-1.TypicalMDC/MDIO Read Operation Figure5-2.TypicalMDC/MDIO WriteOperation

5.4.3 SerialManagement Preamble Suppression

The DP83848 supportsa preamblesuppressionmode as indicatedby a one inbit6 ofthebasicmode statusregister(BMSR, address01h.)Ifthe stationmanagement entity(i.e.MAC or othermanagement controller)determinesthatallPHYs inthesystem supportpreamblesuppressionby returninga one inthis bit,thenthestationmanagement entityneed notgeneratepreambleforeach management transaction. The DP83848 requiresa singleinitializationsequence of32 bitsofpreamblefollowinghardware/software reset. This requirementis generallymet by the mandatory pull-upresistoron MDIO in conjunctionwitha continuousMDC, or the management access made to determinewhether preamble suppressionis supported. WhiletheDP83848 requiresan initialpreamblesequence of32 bitsformanagement initialization,itdoes not requirea full32-bitsequence between each subsequent transaction.A minimum of one idlebit between management transactionsisrequiredas specifiedintheIEEE 802.3uspecification. Copyright© 2012–2013,Texas InstrumentsIncorporated FUNCTIONAL DESCRIPTION 47 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

TX_CLK 125-MHZ Clock BP_SCR MUX MLT[1:0] Divide by 5 4B5B Code Croup Encoder 5B Parallel to Serial NRZ to NRZI Encoder Binary to MLT-3 / Common Driver 100Base-TX Loopback TXD[3:0] / TX_EN DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com

6 ARCHITECTURE

6.1 100BASE-TX Transmitter The 100BASE-TX transmitterconsistsofseveralfunctionalblockswhichconvertsynchronous4-bitnibble data,as providedby theMII,toa scrambledMLT-3 125 Mb/s serialdatastream.Because the100BASE- TX TP-PMD isintegrated,the differentialoutputpins,PMD outputpair,can be directlyroutedto the magnetics. The blockdiagram inFigure6-1 providesan overviewof each functionalblockwithinthe 100BASE-TX transmitsection. The transmittersectionconsistsofthefollowingfunctionalblocks:

• Code-groupencoderand injectionblock
• Scramblerblock(bypassoption)
• NRZ toNRZI encoderblock
• BinarytoMLT-3 converterorcommon driver The bypass optionforthe functionalblockswithinthe 100BASE-TX transmitterprovidesflexibilityfor applicationswhere data conversionisnot always required.The DP83848 implementsthe 100BASE-TX transmitstatemachine diagramas specifiedintheIEEE 802.3uStandard,Clause24. Figure6-1.100BASE-TX TransmitBlock Diagram

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Table6-1.4B5B Code-Group Encoding or Decoding DATA CODES 0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010 B 10111 1011 C 11010 1100 D 11011 1101 E 11100 1110 F 11101 1111 IDLE AND CONTROL CODES H 00100 HALT code-group-Errorcode I 11111 Inter-PacketIDLE -0000(1) J 11000 FirstStartofPacket-0101(1) K 10001 Second StartofPacket-0101(1) T 01101 FirstEnd ofPacket-0000(1) R 00111 Second End ofPacket-0000(1) INVALID CODES V 00000 V 00001 V 00010 V 00011 V 00101 V 00110 V 01000 V 01100 (1) Controlcode-groupsI,J,K,T and R indatafieldswillbe mapped as invalidcodes,togetherwithRX_ER asserted.

6.1.1 Code-Group Encoding and Injection

The code-groupencoderconverts4-bit(4B)nibbledatageneratedby theMAC into5-bit(5B)code-groups fortransmission.Thisconversionisrequiredtoallowcontroldatatobe combined withpacketdatacode- groups. The code-groupencoder substitutesthe first8-bitsof the MAC preamble witha J/K code-grouppair (1100010001)upon transmission.The code-groupencodercontinuestoreplacesubsequent4B preamble and data nibbleswithcorresponding5B code-groups.At the end of the transmitpacket,upon the deassertionoftransmitenablesignalfrom theMAC, thecode-groupencoderinjectstheT/R code-group pair(0110100111)indicatingtheend oftheframe. AftertheT/R code-grouppair,thecode-groupencodercontinuouslyinjectsIDLEs intothetransmitdata streamuntilthenexttransmitpacketisdetected(reassertionoftransmitenable). Copyright© 2012–2013,Texas InstrumentsIncorporated ARCHITECTURE 49 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

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6.1.2 Scrambler

The scramblerisrequiredtocontroltheradiatedemissionsatthemedia connectorand on thetwistedpair cable(for100BASE-TX applications).By scramblingthedata,thetotalenergylaunchedontothecableis randomlydistributedovera wide frequencyrange.Withoutthescrambler,energylevelsatthePMD and on thecablecouldpeak beyond FCC limitationsatfrequenciesrelatedtorepeating5B sequences (i.e., continuoustransmissionofIDLEs). The scrambleris configuredas a closed loop linearfeedback shiftregister(LFSR) with an 11-bit polynomial.The outputoftheclosedloopLFSR isX-ORd withtheserialNRZ datafrom thecode-group encoder.The resultis a scrambled data stream with sufficientrandomizationto decrease radiated emissionsat certainfrequenciesby as much as 20 dB. The DP83848 uses the PHY_ID (pinsPHYAD [4:0])toseta uniqueseed value.

6.1.3 NRZ toNRZI Encoder

Afterthe transmitdata stream has been serializedand scrambled,the data must be NRZI encoded in orderto comply withthe TP-PMD standardfor100BASE-TX transmissionover Category-5Unshielded twistedpaircable.

6.1.4 BinarytoMLT-3 Convertor

The binarytoMLT-3 conversionisaccomplishedby convertingtheserialbinarydatastreamoutputfrom theNRZI encoderintotwo binarydatastreamswithalternatelyphased logicone events.These two binary streamsarethenfedtothetwistedpairoutputdriverwhichconvertsthevoltagetocurrentand alternately driveseithersideofthetransmittransformerprimarywinding,resultingina MLT-3 signal. The 100BASE-TX MLT-3 signalsourcedby thePMD outputpaircommon driverisslew ratecontrolled. Thisshouldbe consideredwhen selectingAC couplingmagneticstoensureTP-PMD standardcompliant transitiontimes(3ns < Tr< 5 ns). The 100BASE-TX transmitTP-PMD functionwithinthe DP83848 is capable of sourcingonly MLT-3 encoded data.BinaryoutputfromthePMD outputpairisnotpossiblein100 Mb/s mode. 6.2 100BASE-TX Receiver The 100BASE-TX receiverconsistsofseveralfunctionalblockswhich convertthescrambledMLT-3 125 Mb/s serialdata stream to synchronous4-bitnibbledata thatis providedto the MII.Because the 100BASE-TX TP-PMD isintegrated,thedifferentialinputpins,RD ±,can be directlyroutedfrom theAC couplingmagnetics. See Figure6-2 fora blockdiagram of the 100BASE-TX receivefunction.Thisprovidesan overviewof each functionalblockwithinthe100BASE-TX receivesection. The receivesectionconsistsofthefollowingfunctionalblocks:

• Analogfrontend
• Digitalsignalprocessor
• Signaldetect
• MLT-3 tobinarydecoder
• NRZI toNRZ decoder
• Serialtoparallel
• Descrambler
• Code groupalignment
• 4B/5B decoder
• Linkintegritymonitor
• Bad SSD detection

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RX_CLK RXD[3:0] / RX_ERRX_DV/CRS Serial to Parallel Code Group Alignment Descrambler NRZI-to-NRZ Decoder MLT-3 to Binary Decoder RX_DATA Valid SSD Detect Digital Signal Processor Analog Front End Link Integrity Monitor Signal Detect RD ± DP83848-EP www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013

6.2.1 Analog FrontEnd

Inadditiontothedigitalequalizationand gaincontrol,theDP83848 includesanalogequalizationand gain controlin the analog frontend. The analog equalizationreduces the amount of digitalequalization requiredintheDSP.

6.2.2 DigitalSignalProcessor

The digitalsignalprocessorincludesadaptiveequalizationwith gain controland base linewander compensation. Figure6-2.100BASE-TX Receive Block Diagram Copyright© 2012–2013,Texas InstrumentsIncorporated ARCHITECTURE 51 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

Attenuation versus Frequency Frequency (MHz) Attenuation (dB) 0 20 40 60 80 100 120 150m 130m 100m 50m DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com

6.2.2.1 DigitalAdaptiveEqualizationand Gain Control

When transmittingdataathighspeeds overcoppertwistedpaircable,frequencydependentattenuation becomes a concern.Inhigh-speedtwistedpairsignalling,thefrequencycontentofthetransmittedsignal can vary greatlyduringnormal operationbased primarilyon the randomness of the scrambled data stream.This variationin signalattenuationcaused by frequencyvariationsmust be compensated to ensuretheintegrityofthetransmission. Inordertoensurequalitytransmissionwhen employingMLT-3 encoding,thecompensationmust be able toadapttovariouscablelengthsand cabletypesdependingon theinstalledenvironment.The selectionof long cable lengthsfor a given implementation,requiressignificantcompensation which willover- compensate forshorter,lessattenuatinglengths.Conversely,theselectionofshortorintermediatecable lengthsrequiringlesscompensationwillcause seriousunder-compensationforlongerlengthcables.The compensationor equalizationmust be adaptiveto ensure properconditioningof the receivedsignal independentofthecablelength. The DP83848 utilizesan extremelyrobustequalizationscheme referredas ‘digitaladaptiveequalization’. The digitalequalizerremoves intersymbol interference(ISI)fromthereceivedatastreamby continuously adaptingtoprovidea filterwiththeinversefrequencyresponseofthechannel.Equalizationiscombined withan adaptivegaincontrolstage.Thisenablesthe receive'eyepattern'to be opened sufficientlyto allowveryreliabledatarecovery. The curvesgiveninFigure6-3illustrateattenuationatcertainfrequenciesforgivencablelengths.Thisis derivedfromtheworstcase frequencyvs.attenuationfiguresas specifiedintheEIA/TIABulletinTSB-36. These curvesindicatethesignificantvariationsinsignalattenuationthatmust be compensated forby the receiveadaptiveequalizationcircuit. Figure6-3.EIA/TIAAttenuationvs.Frequency for0,50,100,130 and 150 meters ofCAT 5 cable

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6.2.2.2 Base LineWander Compensation

Figure6-4.100BASE-TX BLW Event The DP83848 is completelyANSI TP-PMD compliantand includesbase line wander (BLW) compensation.The BLW compensationblockcan successfullyrecovertheTPPMD defined“killer”pattern. BLW can generallybe definedas thechange intheaverageDC content,relativelyshortperiodovertime, ofan AC coupleddigitaltransmissionovera giventransmissionmedium. (i.e.,copperwire). BLW resultsfrom theinteractionbetween thelow frequencycomponents ofa transmittedbitstreamand the frequencyresponse of the AC couplingcomponents withinthe transmissionsystem. Ifthe low frequencycontentof the digitalbitstream goes below the low frequencypole of the AC coupling transformersthen the droop characteristicsof the transformerswilldominate resultingin potentially seriousBLW. The digitaloscilloscopeplotprovidedin Figure6-4 illustratesthe severityof the BLW event thatcan theoreticallybe generatedduring100BASE-TX packettransmission.Thiseventconsistsofapproximately 800 mV ofDC offsetfora periodof120 μs.Leftuncompensated,eventssuch as thiscan cause packet loss.

6.2.3 SignalDetect

The signaldetectfunctionof the DP83848 isincorporatedto meet the specificationsmandated by the ANSI FDDI TP-PMD Standard as wellas the IEEE 802.3 100BASE-TX Standard forboth voltage thresholdsand timingparameters. Note thatthe receptionof normal 10BASE-T linkpulsesand fastlinkpulsesper IEEE 802.3u auto- negotiationby the100BASE-TX receiverdo notcause theDP83848 toassertsignaldetect.

6.2.4 MLT-3 toNRZI Decoder

The DP83848 decodes the MLT-3 informationfrom the DigitalAdaptiveEqualizerblockto binaryNRZI data.

6.2.5 NRZI toNRZ

Ina typicalapplication,theNRZI toNRZ decoderisrequiredinordertopresentNRZ formatteddatatothe descrambler. Copyright© 2012–2013,Texas InstrumentsIncorporated ARCHITECTURE 53 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

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6.2.6 SerialtoParallel

The 100BASE-TX receiverincludesa serialtoparallelconverterwhichsupplies5-bitwide datasymbolsto thePCS Rx statemachine.

6.2.7 Descrambler

A serialdescramblerisused tode-scramblethereceivedNRZ data.The descramblerhas togeneratean identicaldatascramblingsequence (N)inordertorecovertheoriginalunscrambleddata(UD) from the scrambleddata(SD)as representedintheequations: SD = (UD ⊕ N) (1) UD = (SD ⊕ N) (2) Synchronizationof the descramblerto the originalscramblingsequence (N) isachievedbased on the knowledge thatthe incoming scrambled data stream consistsof scrambled IDLE data.Afterthe descramblerhas recognized12 consecutiveIDLE code-groups,where an unscrambledIDLE code-group in5B NRZ isequaltofiveconsecutiveones (11111),itwillsynchronizetothereceivedatastreamand generateunscrambleddataintheformofunaligned5B code-groups. In order to maintainsynchronization,the descramblermust continuouslymonitorthe validityof the unscrambleddata thatitgenerates.To ensure this,a linestatemonitorand a holdtimerare used to constantlymonitorthe synchronizationstatus.Upon synchronizationof the descramblerthe holdtimer startsa 722 μs countdown.Upon detectionofsufficientIDLE code-groups(58bittimes)withinthe722 μs period,the hold timerwillresetand begin a new countdown.This monitoringoperationwillcontinue indefinitelygiven a properlyoperatingnetwork connectionwithgood signalintegrity.Ifthe linestate monitordoes notrecognizesufficientunscrambledIDLE code-groupswithinthe722 μs period,theentire descramblerwillbe forcedout of the currentstateof synchronizationand resetin orderto reacquire synchronization.

6.2.8 Code-Group Alignment

The code-groupalignmentmodule operateson unaligned5-bitdata from the descrambler(or,ifthe descramblerisbypassed,directlyfromtheNRZI/NRZ decoder)and convertsitinto5B code-groupdata(5 bits).Code-group alignmentoccursafterthe J/K code-grouppairisdetected.Once the J/K code-group pair(1100010001)isdetected,subsequentdataisalignedon a fixedboundary. 6.2.9 4B/5B Decoder The code-groupdecoder functionsas a lookup tablethattranslatesincoming5B code-groupsinto4B nibbles.The code-groupdecoderfirstdetectstheJ/Kcode-grouppairprecededby IDLE code-groupsand replacestheJ/KwithMAC preamble.Specifically,theJ/K10-bitcode-grouppairisreplacedby thenibble pair(0101 0101).Allsubsequent5B code-groupsare convertedtothecorresponding4B nibblesforthe durationof the entirepacket.This conversionceases upon the detectionof the T/R code-grouppair denotingtheend ofstreamdelimiter(ESD) orwiththereceptionofa minimum oftwo IDLE code-groups. 6.2.10 100BASE-TX LinkIntegrityMonitor The 100 Base TX Linkmonitorensuresthata validand stablelinkisestablishedbeforeenablingboththe transmitand receivePCS layer. Signaldetectmust be validfor395 µs toallowthelinkmonitortoenterthelinkup state,and enablethe transmitand receivefunctions.

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6.2.11 Bad SSD Detection

A bad startofstreamdelimiter(Bad SSD) isany transitionfromconsecutiveidlecode-groupstonon-idle code-groupswhichisnotprefixedby thecode-grouppair/J/K. Ifthisconditionisdetected,theDP83848 willassertRX_ER and presentRXD[3:0]= 1110 totheMIIfor thecyclesthatcorrespondtoreceived5B code-groupsuntilatleasttwo IDLE code groupsaredetected. Inaddition,thefalsecarriersense counterregister(FCSCR) willbe incrementedby one. Once atleasttwo IDLE code groupsaredetected,RX_ER and CRS become de-asserted. 6.3 10BASE-T TransceiverModule The 10BASE-T transceivermodule isIEEE 802.3compliant.Itincludesthereceiver,transmitter,collision, heartbeat,loopback,jabber,and linkintegrityfunctions,as definedinthestandard.An externalfilterisnot requiredon the10BASE-T interfacesincethisisintegratedinsidetheDP83848. Thissectionfocuseson thegeneral10BASET systemleveloperation.

6.3.1 OperationalModes

6.3.1.1 HalfDuplex Mode

Inhalfduplexmode theDP83848 functionsas a standardIEEE 802.310BASE-T transceiversupporting theCSMA/CD protocol.

6.3.1.2 FullDuplex Mode

Infullduplexmode theDP83848 iscapableofsimultaneouslytransmittingand receivingwithoutasserting thecollisionsignal.The DP83848's 10 Mb/s ENDEC isdesignedtoencode and decode simultaneously.

6.3.2 Smart Squelch

The smart squelchisresponsiblefordeterminingwhen validdata ispresenton the differentialreceive inputs.The DP83848 implementsan intelligentreceivesquelchto ensure thatimpulsenoise on the receiveinputswillnot be mistakenfora validsignal.Smart squelchoperationisindependentof the 10BASE-T operationalmode. The squelchcircuitryemploys a combinationofamplitudeand timingmeasurements (asspecifiedinthe IEEE 802.3 10BSE-T standard)to determinethe validityof data on the twistedpairinputs(referto Figure6-5). The signalat the startof a packetischecked by the smart squelchand any pulsesnot exceedingthe squelchlevel(eitherpositiveornegative,dependingupon polarity)willbe rejected.Once thisfirstsquelch levelisovercome correctly,theoppositesquelchlevelmust thenbe exceeded within150 ns.Finallythe signalmust againexceed theoriginalsquelchlevelwithina 150 ns toensurethattheinputwaveform will not be rejected.This checkingprocedureresultsin the lossof typicallythreepreamble bitsat the beginningofeach packet. Only afteralltheseconditionshave been satisfiedwilla controlsignalbe generatedto indicateto the remainderofthecircuitrythatvaliddataispresent.Atthistime,thesmartsquelchcircuitryisreset. Validdataisconsideredtobe presentuntilthesquelchlevelhas notbeen generatedfora timelonger than 150 ns,indicatingthe end of packet.Once good data has been detected,the squelchlevelsare reducedtominimizetheeffectofnoisecausingprematureend ofpacketdetection. Copyright© 2012–2013,Texas InstrumentsIncorporated ARCHITECTURE 55 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

<150 ns <150 ns >150 ns Start of packet End of packet VSQ+ VSQ+(reduced) VSQ–(reduced) VSQ– DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com Figure6-5.10BASE-T TwistedPairSmart Squelch Operation

6.3.3 CollisionDetectionand SQE

When inhalfduplex,a 10BASE-T collisionisdetectedwhen thereceiveand transmitchannelsareactive simultaneously.Collisionsarereportedby theCOL signalon theMII.Collisionsarealsoreportedwhen a jabberconditionisdetected. The COL signalremainssetforthedurationofthecollision.IfthePHY isreceivingwhen a collisionis detecteditisreportedimmediately(throughtheCOL pin). When heartbeatisenabled,approximately1 μs afterthe transmissionof each packet,a signalquality error(SQE) signalofapproximately10-bittimesisgeneratedtoindicatesuccessfultransmission.SQE is reportedas a pulseon theCOL signaloftheMII. The SQE testisinhibitedwhen thePHY issetinfullduplexmode. SQE can alsobe inhibitedby setting theHEARTBEAT_DIS bitinthe10BTSCR register.

6.3.4 CarrierSense

Carriersense (CRS) may be asserteddue toreceiveactivityonce validdataisdetectedviathesquelch function. For10 Mb/s halfDduplexoperation,CRS isassertedduringeitherpackettransmissionorreception. For10 Mb/s fullduplexoperation,CRS isassertedonlyduringreceiveactivity. CRS isdeassertedfollowingan end ofpacket.

6.3.5 Normal LinkPulse Detection/Generation

The linkpulsegeneratorproducespulsesas definedinthe IEEE 802.3 10BASE-T standard.Each link pulseisnominally100 ns indurationand transmittedevery16 ms intheabsence oftransmitdata. Linkpulsesareused tocheck theintegrityoftheconnectionwiththeremoteend.Ifvalidlinkpulsesare not received,the linkdetectordisablesthe 10BASE-T twistedpairtransmitter,receiverand collision detectionfunctions. When the linkintegrityfunctionisdisabled(FORCE_LINK_10 of the 10BTSCR register),a good linkis forcedand the10BASE-T transceiverwilloperateregardlessofthepresenceoflinkpulses.

6.3.6 Jabber Function

The jabberfunctionmonitorstheDP83848's outputand disablesthetransmitterifitattemptstotransmita packetoflongerthanlegalsize.A jabbertimermonitorsthetransmitterand disablesthetransmissionif thetransmitterisactiveforapproximately85 ms.

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Once disabledby theJabberfunction,thetransmitterstaysdisabledfortheentiretimethattheENDEC module'sinternaltransmitenableisasserted.Thissignalhas tobe deassertedforapproximately500 ms (the“unjab”time)beforetheJabberfunctionre-enablesthetransmitoutputs. The Jabberfunctionisonlyrelevantin10BASE-T mode.

6.3.7 Automatic LinkPolarityDetectionand Correction

The DP83848's 10BASE-T transceivermodule incorporatesan automaticlinkpolaritydetectioncircuit. When threeconsecutiveinvertedlinkpulsesarereceived,bad polarityisreported. A polarityreversalcan be caused by a wiringerrorat eitherend of the cable,usuallyat the main distributionframe(MDF) orpatchpanelinthewiringcloset. The bad polarityconditionislatchedin the 10BTSCR register.The DP83848's 10BASE-T transceiver module correctsforthiserrorinternallyand willcontinuetodecode receiveddatacorrectly.Thiseliminates theneed tocorrectthewiringerrorimmediately.

6.3.8 Transmitand Receive Filtering

External10BASE-T filtersarenotrequiredwhen usingtheDP83848, as therequiredsignalconditioningis integratedintothedevice. Only isolationtransformersand impedance matchingresistorsarerequiredforthe10BASE-T transmitand receiveinterface.The internaltransmitfilteringensuresthatalltheharmonicsinthetransmitsignalare attenuatedby atleast30 dB.

6.3.9 Transmitter

The encoderbeginsoperationwhen thetransmitenableinput(TX_EN) goes highand convertsNRZ data topreemphasizedManchesterdataforthetransceiver.For thedurationofTX_EN, theserializedtransmit data (TXD) isencoded forthe transmit-driverpair(PMD OutputPair).TXD must be validon the rising edge oftransmitclock(TX_CLK).Transmissionends when TX_EN deasserts.The lasttransitionisalways positive;itoccursatthecenterofthebitcellifthelastbitisa one,orattheend ofthebitcellifthelastbit isa zero.

6.3.10 Receiver

The decoderdetectstheend ofa frame when no additionalmid-bittransitionsare detected.Withinone and a halfbittimesafterthelastbit,carriersense isde-asserted.Receiveclockstaysactiveforfivemore bittimesafterCRS goes low,toguaranteethereceivetimingsofthecontroller. Copyright© 2012–2013,Texas InstrumentsIncorporated ARCHITECTURE 57 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

RD– RD+ TD– TD+ RD- RD+ TD- TD+ 1:1 0.1μF* 1:1 49.9Ω 49.9Ω 0.1μF* Vdd NOTE: Center tap is pulled to VDD. 0.1µF All values are typical and are +/- 1% Vdd 49.9Ω 49.9Ω 0.1µF Vdd *Place capacitors close to the transformer center taps. Place resistors and capacitors close to the device. Common mode chokes may be required. DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com

7 DESIGN GUIDELINES

7.1 TPI Network Circuit

Figure7-1shows therecommended circuitfora 10/100Mb/s twistedpairinterface.To therightisa partial listof recommended transformers.Itis importantthatthe user realizethatvariationswithPCB and component characteristicsrequiresthatthe applicationbe testedto ensure thatthe circuitmeets the requirementsoftheintendedapplication. Figure7-1.10/100Mb/s TwistedPairInterface

7.2 ESD Protection

Typically,ESD precautionsare predominantlyineffectwhen handlingthedevicesor board beforebeing installedin a system. In those cases, stricthandlingproceduresneed be implemented duringthe manufacturingprocesstogreatlyreducetheoccurrencesofcatastrophicESD events.Afterthesystem is assembled,internalcomponents arelesssensitivefromESD events. See forESD rating.

7.3 Clock In(X1)Requirements

The DP83848 supportsan externalCMOS leveloscillatorsourceora crystalresonatordevice.

7.3.1 Oscillator

Ifan externalclocksourceisused,X1 shouldbe tiedtotheclocksourceand X2 shouldbe leftfloating. SpecificationsforCMOS oscillators:25 MHz inMIIMode and 50 MHz inRMII Mode arelistedinTable7-1 and Table7-2.

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7.3.2 Crystal

A 25 MHz, parallel,20 pF loadcrystalresonatorshouldbe used ifa crystalsourceisdesired.Figure7-2 shows a typicalconnectionfora crystalresonatorcircuit.The loadcapacitorvalueswillvarywiththe crystalvendors;checkwiththevendorfortherecommended loads. The oscillatorcircuitisdesignedtodrivea parallelresonanceatcutcrystalwitha minimum drivelevelof 100 μW and a maximum of 500 μW. Ifa crystalisspecifiedfora lowerdrivelevel,a currentlimiting resistorshouldbe placedinseriesbetween X2 and thecrystal. As a startingpointforevaluatingan oscillatorcircuit,iftherequirementsforthecrystalarenotknown,CL1 and CL2 shouldbe setat33 pF,and R1 shouldbe setat0 Ω. Specificationfor25 MHz crystalarelistedinTable7-3. Figure7-2.CrystalOscillatorCircuit Table7-1.25 MHz OscillatorSpecification PARAMETER MIN TYP MAX UNIT CONDITION Frequency 25 MHz Frequencytolerance ±50 ppm Operationaltemperature Frequencystability ±50 ppm 1 yearaging Rise/Falltime 6 ns 20% -80% Jitter 800(1) ps Shortterm Jitter 800(1) ps Long term Symmetry 40% 60% Dutycycle (1) Thislimitisprovidedas a guidelineforcomponent selectionand toguaranteedby productiontesting.RefertoAN-1548,“PHYTER 100 Base-TX ReferenceClockJitterTolerance,“fordetailson jitterperformance. Table7-2.50 MHz OscillatorSpecification PARAMETER MIN TYP MAX UNIT CONDITION Frequency 50 MHz Frequencytolerance ±50 ppm Operationaltemperature Frequencystability ±50 ppm Operationaltemperature Rise/Falltime 6 ns 20% -80% Jitter 800(1) ps Shortterm Jitter 800(1) ps Long term Symmetry 40% 60% Dutycycle (1) Thislimitisprovidedas a guidelineforcomponent selectionand toguaranteedby productiontesting.RefertoAN-1548,“PHYTER 100 Base-TX ReferenceClockJitterTolerance,“fordetailson jitterperformance. Copyright© 2012–2013,Texas InstrumentsIncorporated DESIGN GUIDELINES 59 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

.1 µF10 µF Pin 23 (PFBOUT) .1 µF .1 µF Pin 18 (PFBIN1) Pin 37 (PFBIN2) DP83848-EP SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com Table7-3.25 MHz CrystalSpecification PARAMETER MIN TYP MAX UNIT CONDITION Frequency 25 MHz Frequencytolerance ±50 ppm Operationaltemperature Frequencystability ±50 ppm 1 yearaging Load capacitance 25 40 pF

7.4 Power Feedback Circuit

To ensurecorrectoperationfortheDP83848, parallelcaps withvaluesof10 μF (Tantalum)and 0.1μF shouldbe placedclosetopin23 (PFBOUT) ofthedevice. Pin18 (PFBIN1)and pin37 (PFBIN2)must be connectedtopin23 (PFBOUT), each pinrequiresa small capacitor(.1μF).See Figure7-3forproperconnections. Figure7-3.Power Feedback Connection

7.5 Power Down and Interrupt

The power down and interruptfunctionsare multiplexedon pin 7 of the device.By default,thispin functionsas a power down inputand the interruptfunctionisdisabled.Settingbit0 (INT_OE) of MICR (0x11h)willconfigurethepinas an activelowinterruptoutput.

7.5.1 Power Down ControlMode

The PWR_DOWN/INT pincan be assertedlowtoputthedeviceina power down mode. Thisisequivalent to settingbit11 (power down) inthe basicmode controlregister,BMCR (0x00h).An externalcontrol signalcan be used todrivethepinlow,overcomingtheweak internalpull-upresistor.Alternatively,the devicecan be configuredtoinitializeintoa power down stateby use ofan externalpulldownresistoron thePWR_DOWN/INT pin.Sincethedevicewillstillrespondtomanagement registeraccesses,settingthe INT_OE bitintheMICR registerwilldisablethePWR_DOWN/INT input,allowingthedevicetoexitthe power down state.

7.5.2 InterruptMechanisms

The interruptfunctioniscontrolledviaregisteraccess.Allinterruptsourcesaredisabledby default.Setting bit1 (INTEN)ofMICR (0x11h)willenableinterruptstobe output,dependenton theinterruptmask setin thelowerbyteoftheMISR (0x12h).The PWR_DOWN/INT pinisasynchronouslyassertedlow when an interruptconditionoccurs.The sourceoftheinterruptcan be determinedby readingtheupperbyteofthe MISR. One ormore bitsintheMISR willbe set,denotingallcurrentlypendinginterrupts.Reading ofthe MISR clearsALL pendinginterrupts.

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Example:To generatean interrupton a change oflinkstatusoron a change ofenergydetectpower state, thestepswouldbe:

• Write0003h toMICR tosetINTEN and INT_OE
• Write0060h toMISR tosetED_INT_EN and LINK_INT_EN
• MonitorPWR_DOWN/INT pin When PWR_DOWN/INT pin assertslow,user would read the MISR registerto see ifthe ED_INT or LINK_INT bitsare set,i.e.which sourcecaused theinterrupt.AfterreadingtheMISR, theinterruptbits shouldclearand thePWR_DOWN/INT pinwilldeassert.

7.6 Energy DetectMode

When energydetectisenabledand thereisno activityon thecable,theDP83848 willremainina low power mode whilemonitoringthe transmissionline.Activityon the linewillcause the DP83848 to go througha normalpower up sequence.Regardlessofcableactivity,theDP83848 willoccasionallywake up thetransmittertoputED pulseson theline,butwillotherwisedraw as littlepower as possible.Energy detectfunctionalityiscontrolledviaregisterenergydetectcontrol(EDCR), address0x1Dh.

7.7 Thermal ViasRecommendation

The followingthermalviaguidelinesapplytoGNDPAD, pin49: 1. Thermalviasize= 0.2mm 2. Recommend 4 vias 3. Viashave a centertocenterseparationof2 mm Adherencetothisguidelineisrequiredtoachievetheintendedoperatingtemperaturerangeofthedevice. Figure7-4illustratesan example layout. Figure7-4.Top View,Thermal ViasforGNDPAD, Pin 49 Copyright© 2012–2013,Texas InstrumentsIncorporated DESIGN GUIDELINES 61 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

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8 RESET OPERATION

The DP83848 includesan internalpower-onreset(POR) functionand does notneed tobe explicitlyreset fornormal operationafterpower up. Ifrequiredduringnormal operation,the devicecan be resetby a hardwareorsoftwarereset.

8.1 Hardware Reset

A hardwareresetisaccomplishedby applyinga low pulse(TTL level),witha durationofatleast1 μs,to theRESET_N. Thiswillresetthedevicesuch thatallregisterswillbe reinitializedtodefaultvaluesand the hardwareconfigurationvalueswillbe re-latchedintothedevice(similartothepower-up/resetoperation).

8.2 SoftwareReset

A softwareresetisaccomplishedby settingthe resetbit(bit15) of the basicmode controlregister (BMCR). The periodfrom the pointintimewhen the resetbitissetto the pointintimewhen software resethas concludedisapproximately1 μs. The softwareresetwillresetthe devicesuch thatallregisterswillbe resetto defaultvaluesand the hardwareconfigurationvalueswillbe maintained.Softwaredrivercode must wait3 μs followinga software resetbeforeallowingfurtherserialMIIoperationswiththeDP83848. Copyright© 2012–2013,Texas InstrumentsIncorporated RESET OPERATION 63 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

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9 REGISTER BLOCK

9.1 Table9-1.RegisterMap OFFSET ACCESS TAG DESCRIPTION HEX DECIMAL 00h 0 RW BMCR BasicMode ControlRegister 01h 1 RO BMSR BasicMode StatusRegister 02h 2 RO PHYIDR1 PHY IdentifierRegister#1 03h 3 RO PHYIDR2 PHY IdentifierRegister#2 04h 4 RW ANAR Auto-NegotiationAdvertisementRegister Auto-NegotiationLinkPartnerAbilityRegister(Base05h 5 RW ANLPAR Page) Auto-NegotiationLinkPartnerAbilityRegister(Next05h 5 RW ANLPARNP Page) 06h 6 RW ANER Auto-NegotiationExpansionRegister 07h 7 RW ANNPTR Auto-NegotiationNextPage TX 08h-Fh 15-Aug RW RESERVED RESERVED EXTENDED REGISTERS 10h 16 RO PHYSTS PHY StatusRegister 11h 17 RW MICR MIIInterruptControlRegister 12h 18 RO MISR MIIInterruptStatusRegister 13h 19 RW RESERVED RESERVED 14h 20 RO FCSCR FalseCarrierSense CounterRegister 15h 21 RO RECR ReceiveErrorCounterRegister 16h 22 RW PCSR PCS Sub-LayerConfigurationand StatusRegister 17h 23 RW RBR RMII and Bypass Register 18h 24 RW LEDCR LED DirectControlRegister 19h 25 RW PHYCR PHY ControlRegister 1Ah 26 RW 10BTSCR 10Base-T Status/ControlRegister CD TestControlRegisterand BIST Extensions1Bh 27 RW CDCTRL1 Register 1Ch 28 RW RESERVED RESERVED 1Dh 29 RW EDCR EnergyDetectControlRegister 1Eh-1Fh 30-31 RW RESERVED RESERVED

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Table9-2.RegisterTable REGISTER ADDRESS TAG BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT0NAME BasicMode Auto- RestartLoop- Speed Power Duplex CollisionRe- Re- Re- Re- Re- Re- Re-Control 00h BMCR Reset Neg Isolate Auto-back Selection Down Mode Test served served served served served served servedRegister Enable Neg MF Pre- Auto- Extend-BasicMode Auto-100Base 100Base 100Base 10Base- 10Base- Re- Re- Re- Re- amble Neg Remote Link Jabber edStatus 01h BMSR Neg-T4 -TX FDX -TX HDX T FDX T HDX served served served served Sup- Com- Fault Status Detect Capa-Register Abilitypress plete bility PHY PHYIDR OUI OUI OUI OUI OUI OUI OUI OUI OUI OUI OUI OUI OUI OUI OUI OUIIdentifier 02h 1 MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSB MSBRegister1 PHY PHYIDR VNDR_ VNDR_ VNDR_ VNDR_ VNDR_ VNDR_ MDL_ MDL_ MDL_ MDL_Identifier 03h OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB OUI LSB2 MDL MDL MDL MDL MDL MDL REV REV REV REVRegister2 Auto- Negotiation Next Re- Remote Re- ASM_ Protocol Protocol Protocol Protocol ProtocolAdvertise- 04h ANAR PAUSE T4 TX_FD TX 10_FD 10Page Ind served Fault served DIR SelectionSelectionSelectionSelectionSelectionment Register Auto- Negotiation LinkPartner Next Remote Re- ASM_ Protocol Protocol Protocol Protocol Protocol05h ANLPAR ACK PAUSE T4 TX_FD TX 10_FD 10Ability Page Ind Fault served DIR SelectionSelectionSelectionSelectionSelection Register (BasePage) Auto- Negotiation Mes-LinkPartner AN- Next05h ACK sage ACK2 Toggle Code Code Code Code Code Code Code Code Code Code CodeAbility LPARNP Page Ind PageRegisterNext Page Auto- Negotiation Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- LP_NP_ NP_ PAGE_ LP_AN_06h ANER PDFExpansion served served served served served served served served served served served ABLE ABLE RX ABLE Register Auto- Negotiation Next Re- Message07h ANNPTR ACK2 TOG_TX CODE CODE CODE CODE CODE CODE CODE CODE CODE CODE CODENextPage Page Ind served Page TX Register Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re-Reserved 08-0fh served served served served served served served served served served served served served served served served served Copyright© 2012–2013,Texas InstrumentsIncorporated REGISTER BLOCK 65 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com Table9-2.RegisterTable(continued) REGISTER ADDRESS TAG BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT0NAME EXTENDED REGISTERS Auto-False Loop-PHY Status Re- MDI-X Rx Err Polarity Signal Descram Page MIIInter-Remote Jabber Neg Duplex Speed Link10h PHYSTS Carrier backRegister served mode Latch Status Detect Lock Receive rupt Fault Detect Com- Status Status StatusSense Statusplete MIIInterrupt Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re-Control 11h MICR TINT INTEN INT_OEserved served served served served served served served served served served served servedRegister MIIInterrupt Statusand Re- LINK_ SPD_ DUP_ ANC_ FHF_ RHF_ Re- UNMSK UNMSK UNMSK UNMSK UNMSK UNMSK UNMSK12h MISR ED_INTMisc.Control served INT INT INT INT INT INT served _ ED _ LINK _ JAB _ RF _ ANC _ FHF _ RHF Register Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re-Reserved 13h served served served served served served served served served served served served served served served served served FalseCarrier Sense Re- Re- Re- Re- Re- Re- Re- Re-14h FCSCR FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNT FCSCNTCounter served served served served served served served served Register Receive Re- Re- Re- Re- Re- Re- Re- Re- RXER- RXER- RXER- RXER- RXER- RXER- RXER- RXER-ErrorCounter 15h RECR served served served served served served served served CNT CNT CNT CNT CNT CNT CNT CNTRegister PCS Sub- Layer DESCRAMConfigura- Re- Re- Re- BYP_4B Re- SD_FOR SD_ DESC_ Re- FORCE_ Re- Re- NRZI_ SCRAM16h PCSR TQ_EN _tionand served served served 5B served CE_PMA OPTION TIME served 100_OK served served BYPASS _BYPASSStatus BYPASS Register RMII and Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- RMII_ RMII_ RX_OVF RX_UNF RX_RD_ RX_RD_Bypass 17h RBR served served served served served served served served served served MODE REV1_0 _STS _STS PTR[1] PTR[0]Register LED Direct Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- DRV_SP DRV_LN DRV_ACControl 18h LEDCR SPDLED LNKLED ACTLEDserved served served served served served served served served served DLED KLED TLEDRegister BP_PHY Control MDIX_E FORCE_ PAUSE_ PAUSE_ BIST_ BIST_ LED_ LED_ PHY PHY PHY PHY PHY19h PHYCR BIST_fe PSR_15 STRE-Register N MDIX RX TX STATUS START CNFG[1] CNFG[0] ADDR ADDR ADDR ADDR ADDRTCH 10Base-T REJECT LOOPBAStatus/ 10BT_S 10BT_S ERROR ERROR SQUE- SQUE- SQUE- FORC_ Re- POLARI- Re- Re- HEART_ JABBER1Ah 100 CK_10_ LP_DISControl ERIAL ERIAL RANGE RANGE LCH LCH LCH LINK_10 served TY served served DIS _DISBASE T DISRegister CD Test Controland BIST_ BIST_ BIST_ BIST_ BIST_ BIST_ BIST_ BIST_ BIST_ 10Meg_CDCTRL Re- Re- CDPattE Re- CDPatt- CDPatt-BIST 1Bh ERROR ERROR ERROR ERROR ERROR ERROR ERROR ERROR CONT_ Patt_1 served served N_10 served Sel SelExtensions _COUNT _COUNT _COUNT _COUNT _COUNT _COUNT _COUNT _COUNT MODE Gap Register Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re-Reserved 1Ch served served served served served served served served served served served served served served served served served

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Table9-2.RegisterTable(continued) REGISTER ADDRESS TAG BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT0NAME Energy ED_ ED_ ED_ ED_ ED_ ED_ ED_ ED_ ED_Detect ED_ ED_ERR ED_ERR ED_ERR ED_ERR ED_ERR1Dh EDCR ED_EN AUTO_ AUTO_ BURST_ PWR_ DATA_ DATA_ DATA_ DATA_ DATA_Control MAN _MET _COUNT _COUNT _COUNT _COUNTUP DOWN DIS STATE MET COUNT COUNT COUNT COUNTRegister Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re- Re-Reserved 1Eh-1Fh served served served served served served served served served served served served served served served served served Copyright© 2012–2013,Texas InstrumentsIncorporated REGISTER BLOCK 67 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

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9.2 RegisterDefinition

Intheregisterdefinitionsunderthe‘Default’heading,thefollowingdefinitionsholdtrue:

• RW = Read Writeaccess
• SC = Registersetson eventoccurrenceand Self-Clearswhen eventends
• RW/SC = Read Writeaccess/SelfClearingbit
• RO = Read Onlyaccess
• COR = Clearon Read
• RO/COR = Read Only,Clearon Read
• RO/P = Read Only,Permanentlysettoa defaultvalue
• LL = LatchedLow and helduntilread,based upon theoccurrenceofthecorrespondingevent
• LH = LatchedHighand helduntilread,based upon theoccurrenceofthecorrespondingevent

9.2.1 Basic Mode ControlRegister(BMCR)

Table9-3.Basic Mode ControlRegister(BMCR), Address 0x00 BIT BIT NAME DEFAULT DESCRIPTION Reset: 1 = InitiatesoftwareReset/ResetinProcess

15 Reset 0,RW/SC 0 = Normal operation

Thisbit,whichisself-clearing,returnsa valueofone untilthereset processiscomplete.The configurationisre-strapped. Loopback: 1 = Loopback enabled 0 = Normal operation The loopbackfunctionenablesMIItransmitdatatobe routedtotheMII14 Loopback 0,RW receivedatapath. Settingthisbitmay cause thedescramblertolosesynchronizationand producea 500 μs “dead time”beforeany validdatawillappearattheMII receiveoutputs. Speed Select: When auto-negotiationisdisabledwritingtothisbitallowstheportspeed tobe selected.13 Speed Selection Strap,RW 1 = 100 Mb/s 0 = 10 Mb/s Auto-NegotiationEnable: Strapcontrolsinitialvalueatreset 1 = Auto-NegotiationEnabled-bits8 and 13 ofthisregisterareignored12 Auto-NegotiationEnable Strap,RW when thisbitisset. 0 = Auto-NegotiationDisabled-bits8 and 13 determinetheportspeed and duplexmode. Power Down: 1 = Power down 0 = Normal opeation. 11 Power Down 0,RW Settingthisbitpowers down thePHY. Onlytheregisterblockisenabled duringa power down condition.ThisbitisOR ’d withtheinputfromthe PWR_DOWN/INT pin.When theactivelowPWR_DOWN/INT pinis asserted,thisbitwillbe set. Isolate: 1 = IsolatesthePortfromtheMIIwiththeexceptionoftheserialman-10 Isolate 0,RW agement. 0 = Normal operation

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Table9-3.Basic Mode ControlRegister(BMCR), Address 0x00 (continued) BIT BIT NAME DEFAULT DESCRIPTION RestartAuto-Negotiation: 1 = RestartAuto-Negotiation.Re-initiatestheAuto-Negotiationpro-cess. IfAuto-Negotiationisdisabled(bit12 = 0),thisbitisignored.Thisbitis 9 RestartAuto-Negotiation 0,RW/SC self-clearingand willreturna valueof1 untilAuto-Negotiationisinitiated, whereupon itwillself-clear.OperationoftheAuto-Negotiationprocessis notaffectedby themanagement entityclearingthisbit. 0 = Normal operation DuplexMode: When auto-negotiationisdisabledwritingtothisbitallowstheport Duplexcapabilitytobe selected.8 DuplexMode Strap,RW 1 = FullDuplexoperation 0 = HalfDuplexoperatio. CollisionTest: 1 = Collisiontestenabled 0 = Normal operation7 CollisionTest 0,RW When set,thisbitwillcause theCOL signaltobe assertedinresponse totheassertionofTX_EN within512-bittimes.The COL signalwillbe de-assertedwithin4-bittimesinresponsetothede-assertionofTX_EN. 6:00 RESERVED 0,RO RESERVED: Writeignored,readas 0

9.2.2 Basic Mode StatusRegister(BMSR)

Table9-4.Basic Mode StatusRegister(BMSR), Address 0x01 BIT BIT NAME DEFAULT DESCRIPTION 100BASE-T4 Capable: 15 100BASE-T4 0,RO/P 0 = Devicenotabletoperform100BASE-T4 mode 100BASE-TX FullDuplexCapable: 14 100BASE-T FullDuplex 1,RO/P 1 = Deviceabletoperform100BASE-TX infullduplexmode 100BASE-TX HalfDuplexCapable: 13 100BASE-T HalfDuplex 1,RO/P 1 = Deviceabletoperform100BASE-TX inhalfduplexmode 10BASE-T FullDuplexCapable: 12 10BASE-T FullDuplex 1,RO/P 1 = Deviceabletoperform10BASE-T infullduplexmode 10BASE-T HalfDuplexCapable: 11 10BASE-T HalfDuplex 1,RO/P 1 = Deviceabletoperform10BASE-T inhalfduplexmode 10:07 RESERVED 0,RO RESERVED: Writeas 0,readas 0 PreamblesuppressionCapable: 1 = Deviceabletoperformmanagement transactionwithpreamble

6 MF PreambleSuppression 1,RO/P suppressed,32-bitsofpreambleneeded onlyonce afterreset,invalid

opcode orinvalidturnaround. 0 = Normal management operation Auto-NegotiationComplete:

5 Auto-NegotiationCom- plete 0,RO 1 = Auto-Negotiationprocesscomplete

0 = Auto-Negotiationprocessnotcomplete Remote Fault: 1 = Remote Faultconditiondetected(clearedon readorby reset).Fault

4 Remote Fault 0,RO/LH criteria:FarEnd FaultIndicationornotificationfromLinkPartnerof

Remote Fault. 0 = No remotefaultconditiondetected Copyright© 2012–2013,Texas InstrumentsIncorporated REGISTER BLOCK 69 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com Table9-4.Basic Mode StatusRegister(BMSR), Address 0x01 (continued) BIT BIT NAME DEFAULT DESCRIPTION AutoNegotiationAbility:

3 Auto-NegotiationAbility 1,RO/P 1 = DeviceisabletoperformAuto-Negotiation

0 = DeviceisnotabletoperformAuto-Negotiation LinkStatus: 1 = Validlinkestablished(foreither10 or100 Mb/s operation) 0 = Linknotestablished 2 LinkStatus 0,RO/LL The criteriaforlinkvalidityisimplementationspecific.The occurrenceof a linkfailureconditionwillcausestheLinkStatusbittoclear.Once cleared,thisbitmay onlybe setby establishinga good linkconditionand a readviathemanagement interface. JabberDetect:Thisbitonlyhas meaning in10 Mb/s mode 1 = Jabberconditiondetected 0 = No Jabber1 JabberDetect 0,RO/LH Thisbitisimplementedwitha latchingfunction,such thattheoccurrence ofa jabberconditioncausesittosetuntilitisclearedby a readtothis registerby themanagement interfaceorby a reset. ExtendedCapability:

0 ExtendedCapability 1,RO/P 1 = Extendedregistercapabilities

0 = Basicregistersetcapabilitiesonly

9.2.3 PHY IdentifierRegister#1 (PHYIDR1)

The PHY IdentifierRegisters#1 and #2 togetherform a uniqueidentifierfortheDP83848. The Identifier consistsof a concatenationof the OrganizationallyUnique Identifier(OUI),the vendor'smodel number and the model revisionnumber. A PHY may returna valueof zero ineach of the 32 bitsof the PHY Identifierifdesired.The PHY Identifieris intendedto supportnetwork management. National'sIEEE assignedOUI is080017h. Table9-5.PHY IdentifierRegister#1 (PHYIDR1),Address 0x02 BIT BIT NAME DEFAULT DESCRIPTION OUI Most SignificantBits:Bits3 to18 oftheOUI (080017h)arestored<0010 0000 0000 0000>,15:0 OUI_MSB inbits15 to0 ofthisregister.The most significanttwo bitsoftheOUIRO/P areignored(theIEEE standardreferstotheseas bits1 and 2).

9.2.4 PHY IdentifierRegister#2 (PHYIDR2)

Table9-6.PHY IdentifierRegister#2 (PHYIDR2),Address 0x03 BIT BIT NAME DEFAULT DESCRIPTION OUI LeastSignificantBits: 15:10 OUI_LSB <0101 11>,RO/P Bits19 to24 oftheOUI (080017h)aremapped frombits15 to10 of thisregisterrespectively. Vendor Model Number: 9:4 VNDR_MDL <00 1001 >,RO/P The sixbitsofvendormodel number aremapped frombits9 to4 (mostsignificantbittobit9). Model RevisionNumber: Fourbitsofthevendormodel revisionnumber aremapped frombits33:0 MDL_REV <0000>,RO/P to0 (mostsignificantbittobit3).Thisfieldwillbe incrementedforall majordevicechanges.

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9.2.5 Auto-NegotiationAdvertisementRegister(ANAR)

Thisregistercontainstheadvertisedabilitiesofthisdeviceas theywillbe transmittedtoitslinkpartner duringAuto-Negotiation. Table9-7.NegotiationAdvertisementRegister(ANAR), Address 0x04 BIT BIT NAME DEFAULT DESCRIPTION NextPage Indication:

15 NP 0,RW 0 = NextPage Transfernotdesired

1 = NextPage Transferdesired

14 RESERVED 0,RO/P RESERVED by IEEE:Writesignored,Read as 0

Remote Fault:

13 RF 0,RW 1 = Advertisesthatthisdevicehas detecteda Remote Fault

0 = No Remote Faultdetected

12 RESERVED 0,RW RESERVED forFutureIEEE use:Writeas 0,Read as 0

AsymmetricPAUSE SupportforFullDuplexLinks: The ASM_DIR bitindicatesthatasymmetricPAUSE issupported. Encodingand resolutionofPAUSE bitsisdefinedinIEEE 802.3 Annex 28B,Tables28B-2 and 28B-3,respectively.Pause resolution 11 ASM_DIR 0,RW statusisreportedinPHYCR[13:12]. 1 = AdvertisethattheDTE (MAC) has implementedboththeoptional MAC controlsublayerand thepause functionas specifiedinclause31 and annex 31B of802.3u. 0 = No MAC based fullduplexflowcontrol PAUSE SupportforFullDuplexLinks: The PAUSE bitindicatesthatthedeviceiscapableofprovidingthe symmetricPAUSE functionsas definedinAnnex 31B. Encodingand resolutionofPAUSE bitsisdefinedinIEEE 802.3 Annex 28B,Tables28B-2 and 28B-3,respectively.Pause resolution10 PAUSE 0,RW statusisreportedinPHYCR[13:12]. 1 = AdvertisethattheDTE (MAC) has implementedboththeoptional MAC controlsublayerand thepause functionas specifiedinclause31 and annex 31B of802.3u. 0= No MAC based fullduplexflowcontrol 100BASE-T4 Support:

9 T4 0,RO/P 1 = 100BASE-T4 issupportedby thelocaldevice

0 = 100BASE-T4 notsupported 100BASE-TX FullDuplexSupport:

8 TX_FD Strap,RW 1 = 100BASE-TX FullDuplexissupportedby thelocaldevice

0 = 100BASE-TX FullDuplexnotsupported 100BASE-TX Support:

7 TX Strap,RW 1 = 100BASE-TX issupportedby thelocaldevice

0 = 100BASE-TX notsupported 10BASE-T FullDuplexSupport: 6 10_FD Strap,RW 1 = 10BASE-T FullDuplexissupportedby thelocaldevice 0 = 10BASE-T FullDuplexnotsupported 10BASE-T Support: 5 10 Strap,RW 1 = 10BASE-T issupportedby thelocaldevice 0 = 10BASE-T notsupported ProtocolSelectionBits: 4:0 Selector <00001>,RW These bitscontainthebinaryencoded protocolselectorsupportedby thisport.<00001> indicatesthatthisdevicesupportsIEEE 802.3u. Copyright© 2012–2013,Texas InstrumentsIncorporated REGISTER BLOCK 71 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

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9.2.6 Auto-NegotiationLinkPartnerAbilityRegister(ANLPAR) (BASE Page)

Thisregistercontainstheadvertisedabilitiesofthelinkpartneras receivedduringauto-negotiation.The contentchanges afterthesuccessfulauto-negotiationifnext-pagesaresupported. Table9-8.Auto-NegotiationLinkPartnerAbilityRegister(ANLPAR) (BASE Page),Address 0x05 BIT BIT NAME DEFAULT DESCRIPTION NextPage Indication:

15 NP 0,RO 0 = LinkPartnerdoes notdesireNextPage Transfer

1 = LinkPartnerdesiresNextPage Transfer Acknowledge: 1 = LinkPartneracknowledgesreceptionoftheabilitydataword

14 ACK 0,RO 0 = Not acknowledged

The Auto-Negotiationstatemachine willautomaticallycontrolthethis bitbased on theincomingFLP bursts. Remote Fault:

13 RF 0,RO 1 = Remote Faultindicatedby LinkPartner

0 = No Remote Faultindicatedby LinkPartner

12 RESERVED 0,RO RESERVED forFutureIEEE use:Writeas 0,readas 0

ASYMMETRIC PAUSE:

11 ASM_DIR 0,RO 1 = Asymmetricpause issupportedby theLinkPartner

0 = Asymmetricpause isnotsupportedby theLinkPartner PAUSE:

10 PAUSE 0,RO 1 = Pause functionissupportedby theLinkPartner

0 = Pause functionisnotsupportedby theLinkPartner 100BASE-T4 Support:

9 T4 0,RO 1 = 100BASE-T4 issupportedby theLinkPartner

0 = 100BASE-T4 notsupportedby theLinkPartner 100BASE-TX FullDuplexSupport:

8 TX_FD 0,RO 1 = 100BASE-TX FullDuplexissupportedby theLinkPartner

0 = 100BASE-TX FullDuplexnotsupportedby theLinkPartner 100BASE-TX Support:

7 TX 0,RO 1 = 100BASE-TX issupportedby theLinkPartner

0 = 100BASE-TX notsupportedby theLinkPartner 10BASE-T FullDuplexSupport: 6 10_FD 0,RO 1 = 10BASE-T FullDuplexissupportedby theLinkPartner 0 = 10BASE-T FullDuplexnotsupportedby theLinkPartner 10BASE-T Support: 5 10 0,RO 1 = 10BASE-T issupportedby theLinkPartner 0 = 10BASE-T notsupportedby theLinkPartner ProtocolSelectionBits: 4:0 Selector <0 0000>,RO LinkPartner’s binaryencoded protocolselector

9.2.7 Auto-NegotiationLinkPartnerAbilityRegister(ANLPAR) (NextPage)

Table9-9.Auto-NegotiationLinkPartnerAbilityRegister(ANLPAR) (NextPage),Address 0x05 BIT BIT NAME DEFAULT DESCRIPTION NextPage Indication:

15 NP 0,RO 1 = LinkPartnerdesiresNextPage Transfer

0 = LinkPartnerdoes notdesireNextPage Transfer

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Table9-9.Auto-NegotiationLinkPartnerAbilityRegister(ANLPAR) (NextPage),Address 0x05 (continued) BIT BIT NAME DEFAULT DESCRIPTION Acknowledge: 1 = LinkPartneracknowledgesreceptionoftheabilitydataword 0 = Not acknowledged14 ACK 0,RO The Auto-Negotiationstatemachine willautomaticallycontrolthethis bitbased on theincomingFLP bursts.Softwareshouldnotattemptto writetothisbit. Message Page:

13 MP 0,RO 1 = Message Page

0 = UnformattedPage Acknowledge2: 1 = LinkPartnerdoes have theabilitytocomplytonextpage

12 ACK2 0,RO message

0 = LinkPartnerdoes nothave theabilitytocomplytonextpage message Toggle:

11 Toggle 0,RO 1 = PreviousvalueofthetransmittedLinkCode word equalled0

0 = PreviousvalueofthetransmittedLinkCode word equalled1 Code: Thisfieldrepresentsthecode fieldofthenextpage transmission.If theMP bitisset(bit13 ofthisregister),thenthecode shallbe10:0 CODE <000 0000 0000>,RO interpretedas a “Message Page,”as definedinannex 28C ofClause 28.Otherwise,thecode shallbe interpretedas an “Unformatted Page,”and theinterpretationisapplicationspecific.

9.2.8 Auto-NegotiateExpansion Register(ANER)

Thisregistercontainsadditionallocaldeviceand linkpartnerstatusinformation. Table9-10.Auto-NegotiateExpansion Register(ANER), Address 0x06 BIT BIT NAME DEFAULT DESCRIPTION 15:5 RESERVED 0,RO RESERVED: Writesignored,Read as 0 ParallelDetectionFault:

4 PDF 0,RO 1 = A faulthas been detectedviatheParallelDetectionfunction

0 = A faulthas notbeen detected LinkPartnerNextPage Able:

3 LP_NP_ABLE 0,RO 1 = LinkPartnerdoes supportNextPage

0 = LinkPartnerdoes notsupportNextPage NextPage Able:

2 NP_ABLE 1,RO/P

1 = Indicateslocaldeviceisabletosend additional“NextPages” LinkCode Word Page Received:

1 PAGE_RX 0,RO/COR 1 = LinkCode Word has been received,clearedon a read

0 = LinkCode Word has notbeen received LinkPartnerAuto-NegotiationAble:

0 LP_AN_ABLE 0,RO 1 = indicatesthattheLinkPartnersupportsAuto-Negotiation

0 = indicatesthattheLinkPartnerdoes notsupportAuto-Negotiation Copyright© 2012–2013,Texas InstrumentsIncorporated REGISTER BLOCK 73 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

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9.2.9 Auto-NegotiationNext Page TransmitRegister(ANNPTR)

This registercontainsthe next page informationsent by thisdeviceto itslinkpartnerduringauto- negotiation. Table9-11.Auto-NegotiationNext Page TransmitRegister(ANNPTR), Address 0x07 BIT BIT NAME DEFAULT DESCRIPTION NextPage Indication:

15 NP 0,RW 0 = No otherNextPage Transferdesired

1 = AnotherNextPage desired

14 RESERVED 0,RO RESERVED: Writesignored,readas 0

Message Page:

13 MP 1,RW 1 = Message Page

0 = UnformattedPage Acknowledge2: 1 = Willcomplywithmessage

12 ACK2 0,RW 0 = Cannot complywithmessage

Acknowledge2isused by thenextpage functiontoindicatethatLocal Devicehas theabilitytocomplywiththemessage received. Toggle: 1 = ValueoftogglebitinpreviouslytransmittedLinkCode Word was 0 0 = ValueoftogglebitinpreviouslytransmittedLinkCode Word was 1

11 TOG_TX 0,RO Toggleisused by theArbitrationfunctionwithinAuto-Negotiationto

ensuresynchronizationwiththeLinkPartnerduringNextPage exchange.ThisbitshallalwaystaketheoppositevalueoftheToggle bitinthepreviouslyexchanged LinkCode Word. Thisfieldrepresentsthecode fieldofthenextpage transmission.Ifthe MP bitisset(bit13 ofthisregister),thenthecode shallbe interpreted as a "Message Page”,as definedinannex 28C ofIEEE 802.3u. Otherwise,thecode shallbe interpretedas an "UnformattedPage”,and10:0 CODE <000 0000 0001>,RW theinterpretationisapplicationspecific. The defaultvalueoftheCODE representsa NullPage as definedin Annex 28C ofIEEE 802.3u.

9.3 Extended Registers

9.3.1 PHY StatusRegister(PHYSTS)

Thisregisterprovidesa singlelocationwithinthe registersetforquickaccess to commonly accessed information. Table9-12.PHY StatusRegister(PHYSTS), Address 0x10 BIT BIT NAME DEFAULT DESCRIPTION

15 RESERVED 0,RO RESERVED: Writeignored,readas 0

MDI-X mode as reportedby theAuto-Negotiationlogic: Thisbitwillbe affectedby thesettingsoftheMDIX_EN and FORCE_MDIX bitsinthePHYCR register.When MDIX isenabled, butnotforced,thisbitwillupdatedynamicallyas theAuto-MDIX algorithmswaps between MDI and MDI-X configurations.14 MDI-X Mode 0,RO 1 = MDI pairsswapped (Receiveon TPTD pair,Transmiton TPRD pair) 0 = MDI pairsnormal (Receiveon TRD pair,Transmiton TPTD pair)

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Table9-12.PHY StatusRegister(PHYSTS), Address 0x10 (continued) BIT BIT NAME DEFAULT DESCRIPTION ReceiveErrorLatch: Thisbitwillbe clearedupon a readoftheRECR register.

13 ReceiveErrorLatch 0,RO/LH 1 = Receiveerroreventhas occurredsincelastreadofRXERCNT

(address0x15,Page 0) 0 = No receiveerroreventhas occurred PolarityStatus: Thisbitisa duplicationofbit4 inthe10BTSCR register.Thisbitwill be clearedupon a readofthe10BTSCR register,butnotupon a read 12 PolarityStatus 0,RO ofthePHYSTS register. 1 = InvertedPolaritydetected 0 = CorrectPolaritydetected FalseCarrierSense Latch: Thisbitwillbe clearedupon a readoftheFCSR register. FalseCarrierSense11 0,RO/LH 1 = FalseCarriereventhas occurredsincelastreadofFCSCRLatch (address0x14) 0 = No FalseCarriereventhas occurred

10 SignalDetect 0,RO/LL 100Base-TX unconditionalSignalDetectfromPMD

9 DescramblerLock 0,RO/LL 100Base-TX DescramblerLock fromPMD

LinkCode Word Page Received: Thisisa duplicateofthePage ReceivedbitintheANER register,but thisbitwillnotbe clearedupon a readofthePHYSTS register.

8 Page Received 0,RO

1 = A new LinkCode Word Page has been received.Clearedon read oftheANER (address0x06,bit1) 0 = LinkCode Word Page has notbeen received MIIInterruptPending: 1 = Indicatesthatan internalinterruptispending.Interruptsourcecan 7 MIIInterrupt 0,RO be determinedby readingtheMISR Register(0x12h).Readingthe MISR willcleartheInterrupt. 0= No interruptpending Remote Fault: 1 = Remote Faultconditiondetected(clearedon readofBMSR 6 Remote Fault 0,RO (address01h)registerorby reset).Faultcriteria:notificationfromLink PartnerofRemote FaultviaAuto-Negotiation. 0 = No remotefaultconditiondetected JabberDetect:Thisbitonlyhas meaning in10 Mb/s mode Thisbitisa duplicateoftheJabberDetectbitintheBMSR register, exceptthatitisnotclearedupon a readofthePHYSTS register.5 JabberDetect 0,RO 1 = Jabberconditiondetected 0 = No Jabber Auto-NegotiationComplete:

4 Auto-NegComplete 0,RO 1 = Auto-Negotiationcomplete

0 = Auto-Negotiationnotcomplete Loopback:

3 Loopback Status 0,RO 1 = Loopback enabled

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SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com Table9-12.PHY StatusRegister(PHYSTS), Address 0x10 (continued) BIT BIT NAME DEFAULT DESCRIPTION Duplex: Thisbitindicatesduplexstatusand isdeterminedfromAuto- NegotiationorForcedModes. 1 = Fullduplexmode2 DuplexStatus 0,RO 0 = Halfduplexmode Note:ThisbitisonlyvalidifAuto-Negotiationisenabledand complete and thereisa validlinkorifAuto-Negotiationisdisabledand thereis a validlink. Speed10: Thisbitindicatesthestatusofthespeed and isdeterminedfromAuto- NegotiationorForcedModes. 1 = 10 Mb/s mode1 Speed Status 0,RO 0 = 100 Mb/s mode Note:ThisbitisonlyvalidifAuto-Negotiationisenabledand complete and thereisa validlinkorifAuto-Negotiationisdisabledand thereis a validlink. LinkStatus: Thisbitisa duplicateoftheLinkStatusbitintheBMSR register, exceptthatitwillnotbe clearedupon a readofthePHYSTS register.0 LinkStatus 0,RO 1 = Validlinkestablished(foreither10 or100 Mb/s operation) 0 = Linknotestablished

9.3.2 MIIInterruptControlRegister(MICR)

ThisregisterimplementstheMIIinterruptPHY specificcontrolregister.Sources forinterruptgeneration include:energydetectstatechange,linkstatechange,speed statuschange,duplexstatuschange,auto- negotiationcompleteor any of the countersbecoming half-full.The individualinterrupteventsmust be enabledby settingbitsintheMIIinterruptstatusand eventcontrolregister(MISR). Table9-13.MIIInterruptControlRegister(MICR),Address 0x11 BIT BIT NAME DEFAULT DESCRIPTION 15:3 RESERVED 0,RO Reserved:Writeignored,Read as 0 TestInterrupt: ForcesthePHY togeneratean interrupttofacilitateinterrupttesting. Interruptswillcontinuetobe generatedas longas thisbitremainsset.2 TINT 0,RW 1 = Generatean interrupt 0 = Do notgenerateinterrupt InterruptEnable: Enableinterruptdependenton theeventenablesintheMISR register.

1 INTEN 0,RW

1 = Enableeventbased interrupts 0 = Disableeventbased interrupts InterruptOutputEnable: EnableinterrupteventstosignalviathePWR_DOWN/INT pinby configuringthePWR_DOWN/INT pinas an output.0 INT_OE 0,RW 1 = PWR_DOWN/INT isan InterruptOutput 0 = PWR_DOWN/INT isa Power Down Input

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9.3.3 MIIInterruptStatusand MiscellaneousControlRegister(MISR)

Thisregistercontainseventstatusand enablesfortheinterruptfunction.Ifan eventhas occurredsince thelastreadofthisregister,thecorrespondingstatusbitwillbe set.Ifthecorrespondingenablebitinthe registerisset,an interruptwillbe generatediftheeventoccurs.The MICR registercontrolsmust alsobe settoallowinterrupts.The statusindicationsinthisregisterwillbe seteven iftheinterruptisnotenabled. Table9-14.MIIInterruptStatusand MiscellaneousControlRegister(MISR),Address 0x12 BIT BIT NAME DEFAULT DESCRIPTION

15 RESERVED 0,RO RESERVED: Writesignored,Read as 0

EnergyDetectinterrupt: 1 = Energydetectinterruptispendingand isclearedby thecurrent14 ED_INT 0,RO/COR read 0 = No energydetectinterruptpending Change ofLinkStatusinterrupt: 1 = Change oflinkstatusinterruptispendingand isclearedby the13 LINK_INT 0,RO/COR currentread 0 = No change oflinkstatusinterruptpending Change ofspeed statusinterrupt: 1 = Speed statuschange interruptispendingand isclearedby the12 SPD_INT 0,RO/COR currentread 0 = No speed statuschange interruptpending Change ofduplexstatusinterrupt: 1 = Duplexstatuschange interruptispendingand isclearedby the11 DUP_INT 0,RO/COR currentread 0 = No duplexstatuschange interruptpending Auto-NegotiationCompleteinterrupt: 1 = Auto-negotiationcompleteinterruptispendingand isclearedby10 ANC_INT 0,RO/COR thecurrentread 0 = No Auto-negotiationcompleteinterruptpending FalseCarrierCounterhalf-fullinterrupt: 1 = Falsecarriercounterhalf-fullinterruptispendingand isclearedby9 FHF_INT 0,RO/COR thecurrentread 0 = No falsecarriercounterhalf-fullinterruptpending ReceiveErrorCounterhalf-fullinterrupt: 1 = Receiveerrorcounterhalf-fullinterruptispendingand iscleared8 RHF_INT 0,RO/COR by thecurrentread 0 = No receiveerrorcarriercounterhalf-fullinterruptpending

7 RESERVED 0,RO RESERVED: Writesignored,Read as 0

6 ED_INT_EN 0,RW EnableInterrupton energydetectevent

5 LINK_INT_EN 0,RW EnableInterrupton change oflinkstatus

4 SPD_INT_EN 0,RW EnableInterrupton change ofspeed status

3 DUP_INT_EN 0,RW EnableInterrupton change ofduplexstatus

2 ANC_INT_EN 0,RW EnableInterrupton Auto-negotiationcompleteevent

1 FHF_INT_EN 0,RW EnableInterrupton FalseCarrierCounterRegisterhalf-fullevent

0 RHF_INT_EN 0,RW EnableInterrupton ReceiveErrorCounterRegisterhalf-fullevent

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9.3.4 FalseCarrierSense Counter Register(FCSCR)

This counterprovidesinformationrequiredto implementthe “False Carriers” attributewithinthe MAU managed objectclassofClause30 oftheIEEE 802.3uspecification. Table9-15.FalseCarrierSense Counter Register(FCSCR), Address 0x14 BIT BIT NAME DEFAULT DESCRIPTION 15:8 RESERVED 0,RO RESERVED: Writesignored,Read as 0 FalseCarrierEventCounter: 7:0 FCSCNT[7:0] 0,RO/COR This8-bitcounterincrementson everyfalsecarrierevent.This counterstickswhen itreachesitsmax count(FFh).

9.3.5 ReceiverErrorCounter Register(RECR)

Thiscounterprovidesinformationrequiredtoimplementthe“Symbol ErrorDuringCarrier”attributewithin thePHY managed objectclassofClause30 oftheIEEE 802.3uspecification. Table9-16.ReceiverErrorCounter Register(RECR), Address 0x15 BIT BIT NAME DEFAULT DESCRIPTION 15:8 RESERVED 0,RO RESERVED: Writesignored,Read as 0 RX_ER Counter: When a validcarrierispresentand thereisatleastone occurrenceof an invaliddatasymbol,this8-bitcounterincrementsforeach receive7:0 RXERCNT[7:0] 0,RO/COR errordetected.Thiseventcan incrementonlyonce pervalidcarrier event.Ifa collisionispresent,theattributewillnotincrement.The counterstickswhen itreachesitsmax count. 9.3.6 100 Mb/s PCS Configurationand StatusRegister(PCSR) Thisregistercontainseventstatusand enablesfortheinterruptfunction.Ifan eventhas occurredsince thelastreadofthisregister,thecorrespondingstatusbitwillbe set.Ifthecorrespondingenablebitinthe registerisset,an interruptwillbe generatediftheeventoccurs.The MICR registercontrolsmust alsobe settoallowinterrupts.The statusindicationsinthisregisterwillbe seteven iftheinterruptisnotenabled. Table9-17.100 Mb/s PCS Configurationand StatusRegister(PCSR),Address 0x16 BIT BIT NAME DEFAULT DESCRIPTION 15:13 RESERVED <00>,RO RESERVED: Writesignored,Read as 0

12 RESERVED 0 RESERVED: Must be zero

11 RESERVED 0 RESERVED: Must be zero

100Mbs TrueQuietMode Enable:

10 TQ_EN 0,RW 1 = TransmitTrueQuietMode

0 = Normal TransmitMode SignalDetectForcePMA:

9 SD FORCE PMA 0,RW 1 = ForcesSignalDetectioninPMA

0 = Normal SD operation SignalDetectOption:

8 SD_OPTION 1,RW 1 = Enhanced signaldetectalgorithm

0 = Reduced signaldetectalgorithm

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Table9-17.100 Mb/s PCS Configurationand StatusRegister(PCSR),Address 0x16 (continued) BIT BIT NAME DEFAULT DESCRIPTION DescramblerTimeout: Increasethedescramblertimeout.When setthisshouldallowthe devicetoreceivelargerpackets(>9k bytes)withoutlossof 7 DESC_TIME 0,RW synchronization. 1 = 2 ms 0 = 722 µs (perANSI X3.263:1995 (TP-PMD) 7.2.3.3e)

6 RESERVED 0 RESERVED: Must be zero

Force100Mb/s Good Link:

5 FORCE_100_OK 0,RW 1 = Forces100Mb/s Good Link

0 = Normal 100Mb/s operation

4 RESERVED 0 RESERVED: Must be zero

3 RESERVED 0 RESERVED: Must be zero

NRZI Bypass Enable:

2 NRZI_BYPASS 0,RW 1 = NRZI Bypass Enabled

0 = NRZI Bypass Disabled

1 RESERVED 0 RESERVED: Must be zero

0 RESERVED 0 RESERVED: Must be zero

9.3.7 RMII and Bypass Register(RBR)

ThisregisterconfigurestheRMII Mode ofoperation.When RMII mode isdisabled,theRMII functionalityis bypassed. Table9-18.RMII and Bypass Register(RBR),Addresses 0x17 BIT BIT NAME DEFAULT DESCRIPTION 15:6 RESERVED 0,RO Reserved:Writesignored,Read as 0 Reduced MIIMode:

5 RMII_MODE Strap,RW 0 = StandardMIIMode

1 = Reduced MIIMode Reduce MIIRevision1.0: 0 = (RMIIrevision1.2)CRS_DV willtoggleattheend ofa packetto 4 RMII_REV1_0 0,RW indicatedeassertionofCRS. 1 = (RMIIrevision1.0)CRS_DV willremainasserteduntilfinaldatais transferred.CRS_DV willnottoggleattheend ofa packet. RX FIFO Over Flow Status:

3 RX_OVF_STS 0,RO 0 = Normal

1 = Overflowdetected RX FIFO Under Flow Status:

2 RX_UNF_STS 0,RO 0 = Normal

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SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com Table9-18.RMII and Bypass Register(RBR),Addresses 0x17 (continued) BIT BIT NAME DEFAULT DESCRIPTION ReceiveElasticityBuffer: ThisfieldcontrolstheReceiveElasticityBufferwhichallowsfor frequencyvariationtolerancebetween the50MHz RMII clockand the recovereddata.The followingvaluesindicatethetoleranceinbitsfor a singlepacket.The minimum settingallowsforstandardEthernet framesizesat±50ppm accuracyforbothRMII and Receiveclocks. Forgreaterfrequencytolerancethepacketlengthsmay be scaled(i.e.1:0 ELAST_BUF[1:0] 01,RW for±100ppm, thepacketlengthsneed tobe dividedby 2). 00 = 14 bittolerance(upto16800 bytepackets) 01 = 2 bittolerance(upto2400 bytepackets) 10 = 6 bittolerance(upto7200 bytepackets) 11 = 10 bittolerance(upto12000 bytepackets)

9.3.8 LED DirectControlRegister(LEDCR)

Thisregisterprovidestheabilitytodirectlycontrolany orallLED outputs.Itdoes notprovidereadaccess toLEDs. Table9-19.LED DirectControlRegister(LEDCR), Address 0x18 BIT BIT NAME DEFAULT DESCRIPTION 15:6 RESERVED 0,RO Reserved:Writesignored,Read as 0 1 = DrivevalueofSPDLED bitontoLED_SPD output

5 DRV_SPDLED 0,RW

0 = Normal operation 1 = DrivevalueofLNKLED bitontoLED_LNK output

4 DRV_LNKLED 0,RW

0 = Normal operation 1 = DrivevalueofACTLED bitontoLED_ACT/COL output

3 DRV_ACTLED 0,RW

0 = Normal operation

2 SPDLED 0,RW Valuetoforceon LED_SPD output

1 LNKLED 0,RW Valuetoforceon LED_LNK output

0 ACTLED 0,RW Valuetoforceon LED_ACT/COL output

9.3.9 PHY ControlRegister(PHYCR)

Table9-20.PHY ControlRegister(PHYCR), Address 0x19 BIT BIT NAME DEFAULT DESCRIPTION Auto-MDIX Enable: 1 = EnableAuto-negAuto-MDIX capability 0 = DisableAuto-negAuto-MDIX capability15 MDIX_EN Strap,RW The Auto-MDIX algorithmrequiresthattheAuto-NegotiationEnablebit intheBMCR registertobe set.IfAuto-Negotiationisnotenabled,Auto- MDIX shouldbe disabledas well. ForceMDIX: 1 = ForceMDI pairstocross

14 FORCE_MDIX 0,RW

(Receiveon TPTD pair,Transmiton TPRD pair) 0 = Normal operation Pause ReceiveNegotiated: Indicatesthatpause receiveshouldbe enabledintheMAC. Based on ANAR[11:10]and ANLPAR[11:10]settings.13 PAUSE_RX 0,RO Thisfunctionshallbe enabledaccordingtoIEEE 802.3Annex 28B Table28B-3,“Pause Resolution”,onlyiftheAuto-NegotiatedHighest Common Denominatorisa fullduplextechnology.

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www.ti.com SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 Table9-20.PHY ControlRegister(PHYCR), Address 0x19 (continued) BIT BIT NAME DEFAULT DESCRIPTION Pause TransmitNegotiated: Indicatesthatpause transmitshouldbe enabledintheMAC. Based on ANAR[11:10]and ANLPAR[11:10]settings.12 PAUSE_TX 0,RO Thisfunctionshallbe enabledaccordingtoIEEE 802.3Annex 28B Table28B-3,“Pause Resolution”,onlyiftheAuto-NegotiatedHighest Common Denominatorisa fullduplextechnology. BIST ForceError: 1 = ForceBIST Error

11 BIST_FE 0,RW/SC

0 = Normal operation Thisbitforcesa singleerror,and isselfclearing BIST Sequence select:

10 PSR_15 0,RW 1 = PSR15 selected

0 = PSR9 selected BIST TestStatus: 1 = BIST pass 9 BIST_STATUS 0,LL/RO 0 = BIST fail.Latched,clearedwhen BIST isstopped Fora countnumber ofBIST errors,see theBIST ErrorCount inthe CDCTRL1 register. BIST Start:

8 BIST_START 0,RW 1 = BIST start

0 = BIST stop Bypass LED Stretching: ThiswillbypasstheLED stretchingand theLEDs willreflecttheinternal value.7 BP_STRETCH 0,RW 1 = Bypass LED stretching 0 = Normal operation

6 LED_CNFG[1] 0,RW LEDs Configuration:

LED_CNFG LED_ Mode5 LED_CNFG[0] Strap,RW [1] CNFG[0] Description Don ’tcare 1 Mode 1 0 0 Mode 2 1 0 Mode 3 InMode 1,LEDs areconfiguredas follows: LED_LINK = ON forGood Link,OFF forNo Link LED_SPEED = ON in100 Mb/s,OFF in10 Mb/s LED_ACT/COL = ON forActivity,OFF forNo Activity InMode 2,LEDs areconfiguredas follows: LED_LINK = ON forgood Link,BLINK forActivity LED_SPEED = ON in100 Mb/s,OFF in10 Mb/s LED_ACT/COL = ON forCollision,OFF forNo Collision FullDuplex,OFF forHalfDuplex InMode 3,LEDs areconfiguredas follows: LED_LINK = ON forGood Link,BLINK forActivity LED_SPEED = ON in100 Mb/s,OFF in10 Mb/s LED_ACT/COL = ON forFullDuplex,OFF forHalfDuplex 4:0 PHYADDR[4:0] Strap,RW PHY Address:PHY addressforport Copyright© 2012–2013,Texas InstrumentsIncorporated REGISTER BLOCK 81 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com 9.3.10 10Base-T Status/ControlRegister(10BTSCR) Table9-21.10Base-T Status/ControlRegister(10BTSCR), Address 0x1A BIT BIT NAME DEFAULT DESCRIPTION 10Base-T SerialMode (SNI): 1 = Enables10Base-T SerialMode 0 = Normal Operation15 10BT_SERIAL Strap,RW Places10 Mb/s transmitand receivefunctionsinSerialNetwork Interface(SNI)Mode ofoperation.Has no effecton 100 Mb/s operation. 14:12 RESERVED 0,RW RESERVED: Must be zero SquelchConfiguration: 11:9 SQUELCH 100,RW Used tosettheSquelch‘ON ’thresholdforthereceiver DefaultSquelchON is330mV peak Inhalf-duplexmode, default10BASE-T operationloopsTransmitdata totheReceivedatainadditiontotransmittingthedataon thephysical medium. Thisisforconsistencywithearlier10BASE2 and 10BASE5 8 LOOPBACK_10_D IS 0,RW implementationswhichused a sharedmedium. Settingthisbit disablestheloopbackfunction. Thisbitdoes notaffectloopbackdue tosettingBMCR[14]. Normal LinkPulseDisable:

7 LP_DIS 0,RW 1 = TransmissionofNLPs isdisabled

0 = TransmissionofNLPs isenabled Force10Mb Good Link:

6 FORCE_LINK_10 0,RW 1 = ForcedGood 10Mb Link

0 = Normal LinkStatus

5 RESERVED 0,RW RESERVED: Must be zero

10Mb PolarityStatus: Thisbitisa duplicationofbit12 inthePHYSTS register.Bothbitswill be clearedupon a readof10BTSCR register,butnotupon a readof 4 POLARITY RO/LH thePHYSTS register. 1 = InvertedPolaritydetected 0 = CorrectPolaritydetected

3 RESERVED 0,RW RESERVED: Must be zero

2 RESERVED 1,RW RESERVED: Must be zero

HeartbeatDisable:Thisbitonlyhas influenceinhalf-duplex10Mb mode. 1 = Heartbeatfunctiondisabled

1 HEARTBEAT_DIS 0,RW

0 = Heartbeatfunctionenabled When thedeviceisoperatingat100Mb orconfiguredforfullduplex operation,thisbitwillbe ignored-theheartbeatfunctionisdisabled. JabberDisable: Applicableonlyin10BASE-T.

0 JABBER_DIS 0,RW

1 = Jabberfunctiondisabled 0 = Jabberfunctionenabled

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9.3.11 CD Testand BIST ExtensionsRegister(CDCTRL1)

Table9-22.CD Testand BIST ExtensionsRegister(CDCTRL1), Address 0x1B BIT BIT NAME DEFAULT DESCRIPTION BIST ERROR Counter: BIST_ERROR_CO Countsnumber oferroreddatanibblesduringPacketBIST.Thisvalue15:8 0,ROUNT willresetwhen PacketBIST isrestarted.The counterstickswhen it reachesitsmax count. 7:6 RESERVED 0,RW RESERVED: Must be zero PacketBIST ContinuousMode: Allowscontinuouspseudo random datatransmissionwithoutany breakintransmission.Thiscan be used fortransmitVOD testing.This5 BIST_CONT_MOD E 0,RW isused inconjunctionwiththeBIST controlsinthePHYCR Register (0x19h).For10Mb operation,jabberfunctionmust be disabled,bit0 ofthe10BTSCR (0x1Ah),JABBER_DIS = 1. CD PatternEnablefor10Mb:

4 CDPATTEN_10 0,RW 1 = Enabled

0 = Disabled Definesgap between dataorNLP testsequences: 2 10MEG_PATT_GA P 0,RW 1 = 15 μs 0 = 10 μs CD PatternSelect[1:0]: IfCDPATTEN_10 = 1: 00 = Data,EOP0 sequence 1:0 CDPATTSEL[1:0] 00,RW 01 = Data,EOP1 sequence 10 = NLPs 11 = ConstantManchester1s (10MHz sinewave) forharmonic distortiontesting

9.3.12 Energy DetectControl(EDCR)

Table9-23.Energy DetectControl(EDCR), Address 0x1D BIT BIT NAME DEFAULT DESCRIPTION EnergyDetectEnable: AllowEnergyDetectMode.

15 ED_EN 0,RW When EnergyDetectisenabledand Auto-Negotiationisdisabledvia

theBMCR register,Auto-MDIX shouldbe disabledviathePHYCR register. EnergyDetectAutomaticPower Up: Automaticallybeginpower up sequence when EnergyDetectData14 ED_AUTO_UP 1,RW Thresholdvalue(EDCR[3:0])isreached.Alternatively,devicecould be powered up manuallyusingtheED_MAN bit(ECDR[12]). EnergyDetectAutomaticPower Down: Automaticallybeginpower down sequence when no energyis13 ED_AUTO_DOWN 1,RW detected.Alternatively,devicecouldbe powered down usingthe ED_MAN bit(EDCR[12]). EnergyDetectManual Power Up/Down: Beginpower up/down sequence when thisbitisasserted.When set, theEnergyDetectalgorithmwillinitiatea change ofEnergyDetect12 ED_MAN 0,RW/SC stateregardlessofthreshold(errorordata)and timervalues.In managed applications,thisbitcan be setafterclearingtheEnergy Detectinterrupttocontrolthetimingofchangingthepower state. Copyright© 2012–2013,Texas InstrumentsIncorporated REGISTER BLOCK 83 SubmitDocumentationFeedback ProductFolderLinks:DP83848-EP

SLLSEC6D –SEPTEMBER 2012–REVISED JUNE 2013 www.ti.com Table9-23.Energy DetectControl(EDCR), Address 0x1D (continued) BIT BIT NAME DEFAULT DESCRIPTION EnergyDetectBustDisable: Disableburstingofenergydetectdatapulses.By default,Energy

11 ED_BURST_DIS 0,RW Detect(ED)transmitsa burstof4 ED datapulseseach timetheCD is

powered up.When burstingisdisabled,onlya singleED datapulse willbe send each timetheCD ispowered up. EnergyDetectPower State: IndicatescurrentEnergyDetectPower state.When set,Energy 10 ED_PWR_STATE 0,RO Detectisinthepowered up state.When cleared,EnergyDetectisin thepowered down state.Thisbitisinvalidwhen EnergyDetectisnot enabled. EnergyDetectErrorThresholdMet: 9 ED_ERR_MET 0,RO/COR No actionisautomaticallytakenupon receiptoferrorevents.Thisbit isinformationalonlyand wouldbe clearedon a read. EnergyDetectData ThresholdMet:

8 ED_DATA_MET 0,RO/COR The number ofdataeventsthatoccurredmet orsurpassedthe

EnergyDetectData Threshold.Thisbitisclearedon a read. EnergyDetectErrorThreshold: Thresholdtodeterminethenumber ofenergydetecterroreventsthat 7:4 ED_ERR_COUNT 0001,RW shouldcause thedevicetotakeaction.Intendedtoallowaveragingof noisethatmay be on theline.Counterwillresetafterapproximately2 secondswithoutany energydetectdataevents. EnergyDetectData Threshold: Thresholdtodeterminethenumber ofenergydetecteventsthat 3:0 ED_DATA_COUNT 0001,RW shouldcause thedevicetotakeactions.Intendedtoallowaveraging ofnoisethatmay be on theline.Counterwillresetafterapproximately 2 secondswithoutany energydetectdataevents.

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www.ti.com 3-May-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples DP83848MPHPEP ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR -55 to 125 DP83848EP DP83848MPHPREP ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR -55 to 125 DP83848EP V62/12615-01XE ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR -55 to 125 DP83848EP V62/12615-01XE-R ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-4-260C-72 HR -55 to 125 DP83848EP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 3-May-2013 Addendum-Page 2

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 13-Jul-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DP83848MPHPREP HTQFP PHP 48 1000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jul-2013 Pack Materials-Page 2

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