THS4524-EP NSC | Alldatasheet

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THS4524 ADS1278 (CH 1)49.9 /c87 1 k/c87 49.9 /c87 VOCM VIN+ VIN/c45 5 V VCOM 1 k/c87 1 k/c87 2.2 nF AINN1 AINP1 0.1 mF0.1 mF OPA2350 1.5 nF 1.5 nF 1 k/c87 100 120 140 -160 Magnitude (dBFS) 0 4 8 12 16 20 24 26 Frequency (kHz) 1-kHz FFT G = 1 R = R = 1 kW C = 1.5 nF V = 5 V Load = 2 x 49.9 W + 2.2 nF F G F S THS4524 and ADS1278 Combined Performance Tone (Hz) 1 k Signal (dBFS) 0.50/c45 SNR (dBc) 109.1 THD (dBc) 107.9/c45 SINAD (dBc) 105.5 SFDR (dBc) 113.7 THS4524-EP www.ti.com SBOS609A –JUNE 2012–REVISED AUGUST 2013 VERYLOWPOWER,NEGATIVERAILINPUT,RAIL-TO-RAILOUTPUT, FULLYDIFFERENTIALAMPLIFIER Check for Samples: THS4524-EP 1FEATURES 23• Fully Differential Architecture SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS• Bandwidth: 145 MHz

  • Controlled Baseline• Slew Rate: 490 V/μs
  • One Assembly/Test Site• HD2: –133 dBc at 10 kHz (1 VRMS, RL = 1 kΩ)
  • One Fabrication Site• HD3: –140 dBc at 10 kHz (1 VRMS, RL = 1 kΩ)
  • Available in Military (–55°C/125°C)• Input Voltage Noise: 4.6 nV/√Hz (f = 100 kHz) Temperature Range (1)
  • THD+N: –112dBc (0.00025%) at 1 kHz
  • Extended Product Life Cycle(22-kHz BW, G = 1, 5 VPP)
  • Extended Product-Change Notification• Open-Loop Gain: 119 dB
  • Product Traceability• NRI— Negative Rail Input
  • RRO— Rail-to-Rail Output
  • Output Common-Mode Control (With Low Offset and Drift)
  • Power Supply: – Voltage: +2.5 V (±1.25 V) to +5.5 V (±2.75 V) – Current: 1.14 mA/ch
  • Power-Down Capability: 20 μA (Typical)

APPLICATIONS

  • Low-Power SAR and ΔΣ ADC Drivers
  • Low-Power Differential Drivers
  • Low-Power Differential Signal Conditioning
  • Low-Power, High-Performance Differential Audio Amplifiers (1) Additional temperature ranges available - contact factory

DESCRIPTION

The THS4524 is a very low-power, fully differential operational amplifier with rail-to-rail output and an input common-mode range that includes the negative rail. This amplifier is designed for low-power data acquisition systems and high-density applications where power dissipation is a critical parameter, and provide exceptional performance in audio applications. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2I2S is a trademark of NXP Semiconductor. 3All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2012–2013, Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SBOS609A –JUNE 2012–REVISED AUGUST 2013 www.ti.com This fully differential op amp features accurate output common-mode control that allows for dc-coupling when driving analog-to-digital converters (ADCs). This control, coupled with an input common-mode range below the negative rail as well as rail-to-rail output, allows for easy interfacing between single-ended, ground-referenced signal sources. Additionally, the THS4524 is ideally suited for driving both successive-approximation register (SAR) and delta-sigma (ΔΣ) ADCs using only a single +2.5-V to +5-V and ground power supply. The THS4524 fully differential op amp is characterized for operation over the full industrial temperature range from –55°C to 125°C. RELATED PRODUCTS THD (dBc) DEVICE BW (MHz) IQ (mA) at 100 kHz VN (nV/√Hz) RAIL-TO-RAIL THS4520 570 15.3 –114 2 Out THS4121 100 16 –79 5.4 In/Out THS4130 150 16 –107 1.3 No

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www.ti.com SBOS609A –JUNE 2012–REVISED AUGUST 2013 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION(1) ORDERABLE PARTTA PACKAGE-LEAD PACKAGE DESIGNATOR TOP-SIDE MARKING VID NUMBERNUMBER Tape and reel, THS4524MDBTREP THS4524EP V62/12612-01XE2000-55°C to 125°C TSSOP - 38 DBT Rails, 50 THS4524MDBTEP THS4524EP V62/12612-01XE-T (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at www.ti.com. ABSOLUTE MAXIMUM RATINGS(1) Over operating free-air temperature range (unless otherwise noted). THS4524 UNIT Supply Voltage, VS– to VS+ 5.5 V Input/Output Voltage, VI (VIN±, VOUT±, VOCM pins) (VS–) – 0.7 to (VS+) + 0.7V V Differential Input Voltage, VID 1 V Output Current, IO 100 mA Input Current, II (VIN±, VOCM pins) 10 mA Continuous Power Dissipation See Thermal Characteristic Specifications Maximum Junction Temperature, TJ +150 °C Maximum Junction Temperature, TJ (continuous operation, long-term reliability) +125 °C Operating Free-air Temperature Range, TA –55 to 125 °C Storage Temperature Range, TSTG –65 to +150 °C Human Body Model (HBM) 1300 V ESD Charge Device Model (CDM) 1000 VRating: Machine Model (MM) 50 V (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links :THS4524-EP

SBOS609A –JUNE 2012–REVISED AUGUST 2013 www.ti.com THERMAL INFORMATION THS4524 THERMAL METRIC(1) DBT UNITS

38 PINS

θJA Junction-to-ambient thermal resistance(2) 106.9 θJCtop Junction-to-case (top) thermal resistance(3) 59.8 θJB Junction-to-board thermal resistance(4) 66.5 °C/W ψJT Junction-to-top characterization parameter(5) 17.1 ψJB Junction-to-board characterization parameter(6) 66.1 θJCbot Junction-to-case (bottom) thermal resistance(7) N/A (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. (3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC- standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. (4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. (5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). (6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). (7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer ELECTRICAL CHARACTERISTICS: VS+ – VS– = 3.3 V At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RL = 1 kΩ differential, G = 1 V/V, single-ended input, differential output, and input and output referenced to midsupply, unless otherwise noted. TA = -55°C to 125°C TEST PARAMETER CONDITIONS MIN TYP MAX UNIT LEVEL(1) AC PERFORMANCE Small-Signal Bandwidth VOUT = 100 mVPP, G = 1 135 MHz C VOUT = 100 mVPP, G = 2 49 MHz C VOUT = 100 mVPP, G = 5 18.6 MHz C VOUT = 100 mVPP, G = 10 9.3 MHz C Gain Bandwidth Product VOUT = 100 mVPP, G = 10 93 MHz C Large-Signal Bandwidth VOUT = 2 VPP, G = 1 95 MHz C Bandwidth for 0.1-dB Flatness VOUT = 2 VPP, G = 1 20 MHz C Rising Slew Rate (Differential) VOUT = 2-V Step, G = 1, RL = 200 Ω 420 V/μs C Falling Slew Rate (Differential) VOUT = 2-V Step, G = 1, RL = 200 Ω 460 V/μs C Overshoot VOUT = 2-V Step, G = 1, RL = 200 Ω 1.2 % C Undershoot VOUT = 2-V Step, G = 1, RL = 200 Ω 2.1 % C Rise Time VOUT = 2-V Step, G = 1, RL = 200 Ω 4 ns C Fall Time VOUT = 2-V Step, G = 1, RL = 200 Ω 3.5 ns C Settling Time to 1% VOUT = 2-V Step, G = 1, RL = 200 Ω 13 ns C Harmonic Distortion f = 1 kHz, VOUT = 1 VRMS, G = 1(2),2nd harmonic –122 dBc Cdifferential input f = 1 MHz, VOUT = 2 VPP, G = 1 –85 dBc C f = 1 kHz, VOUT = 1 VRMS, G = 1(2),3rd harmonic –141 dBc Cdifferential input f = 1 MHz, VOUT = 2 VPP, G = 1 –90 dBc C Two-tone, f1 = 2 MHz, f2 = 2.2 MHz,Second-Order Intermodulation Distortion –83 dBc CVOUT = 2-VPP envelope (1) Test levels: (A) 100% tested. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Not directly measureable; calculated using noise gain of 101 as described in the Applications section, Audio Performance.

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www.ti.com SBOS609A –JUNE 2012–REVISED AUGUST 2013 ELECTRICAL CHARACTERISTICS: VS+ – VS– = 3.3 V (continued) At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RL = 1 kΩ differential, G = 1 V/V, single-ended input, differential output, and input and output referenced to midsupply, unless otherwise noted. TA = -55°C to 125°C TEST PARAMETER CONDITIONS MIN TYP MAX UNIT LEVEL(1) Two-tone, f1 = 2 MHz, f2 = 2.2 MHz,Third-Order Intermodulation Distortion –90 dBc CVOUT = 2-VPP envelope Input Voltage Noise f > 10 kHz 4.6 nV/√Hz C Input Current Noise f > 100 kHz 0.6 pA/√Hz C Overdrive Recovery Time Overdrive = ±0.5 V 80 ns C Output Balance Error VOUT = 100 mV, f ≤ 2 MHz (differential input) –57 dB C Closed-Loop Output Impedance f = 1 MHz (differential) 0.3 Ω C Channel-to-Channel Crosstalk f = 10 kHz, measured differentially –125 dB C DC PERFORMANCE Open-Loop Voltage Gain (AOL) 80 116 dB A Input-Referred Offset Voltage ±0.5 ±7 mV A Input offset voltage drift(3) ±2 μV/°C C Input Bias Current 0.75 3.8 μA A Input bias current drift(3) ±1.75 nA/°C C Input Offset Current ±0.03 ±2.0 uA A Input offset current drift(3) ±0.1 nA/°C C (3) Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at –55°C and +125°C, computing the difference, and dividing by 180. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links :THS4524-EP

SBOS609A –JUNE 2012–REVISED AUGUST 2013 www.ti.com ELECTRICAL CHARACTERISTICS: VS+ – VS– = 3.3 V (continued) At VS+ = +3.3 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RL = 1 kΩ differential, G = 1 V/V, single-ended input, differential output, and input and output referenced to midsupply, unless otherwise noted. TA = -55°C to 125°C TEST PARAMETER CONDITIONS MIN TYP MAX UNIT LEVEL(1) INPUT Common-Mode Input Voltage Low -0.1 0 V A Common-Mode Input Voltage High 1.8 1.9 V A Common-Mode Rejection Ratio (CMRR) 73.8 100 dB A Input Resistance 110∥1.5 kΩ∥pF C OUTPUT Output Voltage Low 0.09 0.2 V A Output Voltage High 2.95 3.05 V A Output Current Drive (for linear operation) RL = 50 Ω ±35 mA C POWER SUPPLY Specified Operating Voltage 2.5 5.5 V A Quiescent Operating Current, per channel 0.85 1.0 1.25 mA A Power-Supply Rejection Ratio (±PSRR) 65 100 dB A POWER DOWN Enable Voltage Threshold Assured on above 2.1 V 1.6 2.1 V A Disable Voltage Threshold Assured off below 0.7 V 0.7 1.6 V A Disable Pin Bias Current 1 μA C Power Down Quiescent Current 10 μA C Time to VOUT = 90% of final value,Turn-On Time Delay 108 ns CVIN= 2 V, RL = 200 Ω Time to VOUT = 10% of original value,Turn-Off Time Delay 88 ns CVIN= 2 V, RL = 200 Ω VOCM VOLTAGE CONTROL Small-Signal Bandwidth 23 MHz C Slew Rate 55 V/μs C Gain 0.98 0.99 1.021 V/V A Common-Mode Offset Voltage from VOCM Measured at VOUT with VOCM input driven, ±2.5 ±7 mV AInput VOCM = 1.65 V ±0.5 V Input Bias Current VOCM = 1.65 V ±0.5 V ±5 ±8 μA A VOCM Voltage Range 0.8 to 2.5 V C Input Impedance 72∥1.5 kΩ∥pF C Default Output Common-Mode Voltage Measured at VOUT with VOCM input open ±1.5 ±5 mV AOffset from (VS+– VS–)/2

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www.ti.com SBOS609A –JUNE 2012–REVISED AUGUST 2013 ELECTRICAL CHARACTERISTICS: VS+ – VS– = 5 V At VS+ = +5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended input, differential output, input and output referenced to midsupply, unless otherwise noted. TA = -55°C to 125°C TEST PARAMETER CONDITIONS MIN TYP MAX UNIT LEVEL(1) AC PERFORMANCE Small-Signal Bandwidth VOUT = 100 mVPP, G = 1 145 MHz C VOUT = 100 mVPP, G = 2 50 MHz C VOUT = 100 mVPP, G = 5 20 MHz C VOUT = 100 mVPP, G = 10 9.5 MHz C Gain Bandwidth Product VOUT = 100 mVPP, G = 10 95 MHz C Large-Signal Bandwidth VOUT = 2 VPP, G = 1 145 MHz C Bandwidth for 0.1-dB Flatness VOUT = 2 VPP, G = 1 30 MHz C Rising Slew Rate (Differential) VOUT = 2-V Step, G = 1, RL = 200 Ω 490 V/μs C Falling Slew Rate (Differential) VOUT = 2-V Step, G = 1, RL = 200 Ω 600 V/μs C Overshoot VOUT = 2-V Step, G = 1, RL = 200 Ω 1 % C Undershoot VOUT = 2-V Step, G = 1, RL = 200 Ω 2.6 % C Rise Time VOUT = 2-V Step, G = 1, RL = 200 Ω 3.4 ns C Fall Time VOUT = 2-V Step, G = 1, RL = 200 Ω 3 ns C Settling Time to 1% VOUT = 2-V Step, G = 1, RL = 200 Ω 10 ns C Harmonic Distortion f = 1 kHz, VOUT = 1 VRMS, G = 1(2),2nd harmonic –122 dBc Cdifferential input f = 1 MHz, VOUT = 2 VPP, G = 1 –85 dBc C f = 1 kHz, VOUT = 1 VRMS, G = 1(2),3rd harmonic –141 dBc Cdifferential input f = 1 MHz, VOUT = 2 VPP, G = 1 –91 dBc C Two-tone, f1 = 2 MHz, f2 = 2.2 MHz,Second-Order Intermodulation Distortion –86 dBc CVOUT = 2-VPP envelope Two-tone, f1 = 2 MHz, f2 = 2.2 MHz,Third-Order Intermodulation Distortion –93 dBc CVOUT = 2-VPP envelope Input Voltage Noise f > 10 kHz 4.6 nV/√Hz C Input Current Noise f > 100 kHz 0.6 pA/√Hz C VOUT = 5 VPP, 20 Hz to 22 kHz BW,SNR 114 dBc Cdifferential input f = 1 kHz , VOUT = 5 VPP, 20 Hz to 22 kHz BW,THD+N 112 dBc Cdifferential input Overdrive Recovery Time Overdrive = ±0.5 V 75 ns C Output Balance Error VOUT = 100 mV, f < 2 MHz, VIN differential –57 dB C Closed-Loop Output Impedance f = 1 MHz (differential) 0.3 Ω C Channel-to-Channel Crosstalk f = 10 kHz, measured differentially –125 dB C DC PERFORMANCE Open-Loop Voltage Gain (AOL) 83 119 dB A Input-Referred Offset Voltage ±0.5 ±8 mV A Input offset voltage drift(3) ±2 μV/°C C Input Bias Current 0.9 5.5 μA A Input bias current drift(3) ±1.8 nA/°C C (1) Test levels: (A) 100% tested. (B) Limits set by characterization and simulation. (C) Typical value only for information. (2) Not directly measureable; calculated using noise gain of 101 as described in the Applications section, Audio Performance. (3) Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at –55°C and +125°C, computing the difference, and dividing by 180. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links :THS4524-EP

SBOS609A –JUNE 2012–REVISED AUGUST 2013 www.ti.com ELECTRICAL CHARACTERISTICS: VS+ – VS– = 5 V (continued) At VS+ = +5 V, VS– = 0 V, VOCM = open, VOUT = 2 VPP (differential), RF = 1 kΩ, RL = 1 kΩ differential, G = 1 V/V, single-ended input, differential output, input and output referenced to midsupply, unless otherwise noted. TA = -55°C to 125°C TEST PARAMETER CONDITIONS MIN TYP MAX UNIT LEVEL(1) Input Offset Current ±0.03 ±1.7 uA A Input offset current drift(4) ±0.1 nA/°C C INPUT Common-Mode Input Voltage Low –0.1 0 V A Common-Mode Input Voltage High 3.5 3.6 V A Common-Mode Rejection Ratio (CMRR) 80 102 dB A Input Impedance 100∥0.7 kΩ∥pF C OUTPUT Output Voltage Low 0.115 0.2 V A Output Voltage High 4.65 4.7 V A Output Current Drive (for linear operation) RL = 50 Ω ±55 mA C POWER SUPPLY Specified Operating Voltage 2.5 5.5 V A Quiescent Operating Current, per channel 0.9 1.15 1.4 mA A Power-Supply Rejection Ratio (±PSRR) 62 100 dB A POWER DOWN Enable Voltage Threshold Ensured on above 2.1 V 1.6 2.1 V A Disable Voltage Threshold Ensured off below 0.7 V 0.7 1.6 V A Disable Pin Bias Current 1 μA C Power Down Quiescent Current 20 μA C Time to VOUT = 90% of final value,Turn-On Time Delay 70 ns CVIN= 2 V, RL = 200 Ω Time to VOUT = 10% of original value,Turn-Off Time Delay 60 ns CVIN= 2 V, RL = 200 Ω VOCM VOLTAGE CONTROL Small-Signal Bandwidth 23 MHz C Slew Rate 55 V/μs C Gain 0.98 0.99 1.021 V/V A Measured at VOUT with VOCM input driven,Common-Mode Offset Voltage from VOCM Input ±5 ±12.5 mV AVOCM = 2.5V ±1 V Input Bias Current VOCM = 2.5V ±1 V ±20 ±25 μA A VOCM Voltage Range 0.8 to 4.2 V C Input Impedance 46∥1.5 kΩ∥pF C Default Output Common-Mode Voltage Offset Measured at VOUT with VOCM input open ±1 ±8 mV Afrom (VS+– VS–)/2 (4) Input Offset Voltage Drift, Input Bias Current Drift, and Input Offset Current Drift are average values calculated by taking data at –55°C and +125°C, computing the difference, and dividing by 180.

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A. See datasheet for absolute maximum and minimum recommended operating conditions. Figure 1. Electromigration Fail Mode/Wirebond Life Derating Chart

SBOS609A –JUNE 2012–REVISED AUGUST 2013 www.ti.com DEVICE INFORMATION TSSOP-38 (DBT PACKAGE) (TOP VIEW)

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www.ti.com SBOS609A –JUNE 2012–REVISED AUGUST 2013 TERMINAL FUNCTIONS TSSOP-38 PIN NO. NAME DESCRIPTION Power down 1. PD = logic low puts channel into low-power mode. PD = logic high or open for1 PD 1 normal operation.

2 VIN1+ Noninverting amplifier 1 input

3 VIN1– Inverting amplifier 1 input

4 VOCM1 Common-mode voltage input 1

5 VS– Negative power-supply input. Note that VS– is tied together on multi-channel devices. Power down 2. PD = logic low puts channel into low-power mode. PD = logic high or open for6 PD 2 normal operation.

7 VIN2+ Noninverting amplifier 2 input

8 VIN2– Inverting amplifier 2 input

9 VOCM2 Common-mode voltage input 2

10 VS– Negative power-supply input. Note that VS– is tied together on multi-channel devices. Power down 3. PD = logic low puts channel into low-power mode. PD = logic high or open for11 PD 3 normal operation.

12 VIN3+ Noninverting amplifier 3 input

13 VIN3– Inverting amplifier 3 input

14 VOCM3 Common-mode voltage input 3

15 VS– Negative power-supply input. Note that VS– is tied together on multi-channel devices. Power down 4. PD = logic low puts channel into low-power mode. PD = logic high or open for16 PD 4 normal operation.

17 VIN4+ Noninverting amplifier 4 input

18 VIN4– Inverting amplifier 4 input

19 VOCM4 Common-mode voltage input 4

20 VS4+ Amplifier 4 positive power-supply input

21 VOUT4+ Noninverting amplifier 4 output

22 VOUT4– Inverting amplifier 4 output

23 VS– Negative power-supply input. Note that VS– is tied together on multi-channel devices. 24 VS– Negative power-supply input. Note that VS– is tied together on multi-channel devices.

25 VS3+ Amplifier 3 positive power-supply input

26 VOUT3+ Noninverting amplifier3 output

27 VOUT3– Inverting amplifier3 output

28 VS– Negative power-supply input. Note that VS– is tied together on multi-channel devices. 29 VS– Negative power-supply input. Note that VS– is tied together on multi-channel devices.

30 VS2+ Amplifier 2 positive power-supply input

31 VOUT2+ Noninverting amplifier 2 output

32 VOUT2– Inverting amplifier 2 output

33 VS– Negative power-supply input. Note that VS– is tied together on multi-channel devices. 34 VS– Negative power-supply input. Note that VS– is tied together on multi-channel devices.

35 VS1+ Amplifier 1 positive power-supply input

36 VOUT1+ Noninverting amplifier 1 output

37 VOUT1– Inverting amplifier 1 output

38 VS– Negative power-supply input. Note that VS– is tied together on multi-channel devices. Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links :THS4524-EP

SBOS609A –JUNE 2012–REVISED AUGUST 2013 www.ti.com TYPICAL CHARACTERISTICS Table of Graphs: VS+ – VS– = 3.3 V TITLE FIGURE Small-Signal Frequency Response Figure 2 Large-Signal Frequency Response Figure 3 Large- and Small-Signal Pulse Response Figure 4 Slew Rate vs VOUT Step Figure 5 Overdrive Recovery Figure 6 10-kHz Output Spectrum on AP Analyzer Figure 7 Harmonic Distortion vs Frequency Figure 8 Harmonic Distortion vs Output Voltage at 1 MHz Figure 9 Harmonic Distortion vs Gain at 1 MHz Figure 10 Harmonic Distortion vs Load at 1 MHz Figure 11 Harmonic Distortion vs VOCM at 1 MHz Figure 12 Two-Tone, Second- and Third-Order Intermodulation Distortion vs Frequency Figure 13 Single-Ended Output Voltage Swing vs Load Resistance Figure 14 Main Amplifier Differential Output Impedance vs Frequency Figure 15 Frequency Response vs CLOAD (RLOAD = 1 kΩ) Figure 16 RO vs CLOAD (RLOAD = 1 kΩ) Figure 17 Rejection Ratio vs Frequency Figure 18 Crosstalk (Measured Differentially) Figure 19 Turn-on Time Figure 20 Turn-off Time Figure 21 Input-Referred Voltage Noise and Current Noise Spectral Density Figure 22 Main Amplifier Differential Open-Loop Gain and Phase Figure 23 Output Balance Error vs Frequency Figure 24 VOCM Small-Signal Frequency Response Figure 25 VOCM Large-Signal Frequency Response Figure 26 VOCM Input Impedance vs Frequency Figure 27

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www.ti.com SBOS609A –JUNE 2012–REVISED AUGUST 2013 Table of Graphs: VS+ – VS– = 5 V TITLE FIGURE Small-Signal Frequency Response Figure 28 Large-Signal Frequency Response Figure 29 Large- and Small-Signal Pulse Response Figure 30 Slew Rate vs VOUT Step Figure 31 Overdrive Recovery Figure 32 10-kHz Output Spectrum on AP Analyzer Figure 33 Harmonic Distortion vs Frequency Figure 34 Harmonic Distortion vs Output Voltage at 1 MHz Figure 35 Harmonic Distortion vs Gain at 1 MHz Figure 36 Harmonic Distortion vs Load at 1 MHz Figure 37 Harmonic Distortion vs VOCM at 1 MHz Figure 38 Two-Tone, Second- and Third-Order Intermodulation Distortion vs Frequency Figure 39 Single-Ended Output Voltage Swing vs Load Resistance Figure 40 Main Amplifier Differential Output Impedance vs Frequency Figure 41 Frequency Response vs CLOAD (RLOAD = 1 kΩ) Figure 42 RO vs CLOAD (RLOAD = 1 kΩ) Figure 43 Rejection Ratio vs Frequency Figure 44 Crosstalk (Measured Differentially) Figure 45 Turn-on Time Figure 46 Turn-off Time Figure 47 Input-Referred Voltage Noise and Current Noise Spectral Density Figure 48 Main Amplifier Differential Open-Loop Gain and Phase Figure 49 Output Balance Error vs Frequency Figure 50 VOCM Small-Signal Frequency Response Figure 51 VOCM Large-Signal Frequency Response Figure 52 VOCM Input Impedance vs Frequency Figure 53 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links :THS4524-EP

differential output, and input and output referenced to midsupply, unless otherwise noted. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7.

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differential output, and input and output referenced to midsupply, unless otherwise noted. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19.

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differential output, and input and output referenced to midsupply, unless otherwise noted. Figure 26. Figure 27.

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input, differential output, and input and output referenced to midsupply, unless otherwise noted. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39.

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input, differential output, and input and output referenced to midsupply, unless otherwise noted. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51.

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input, differential output, and input and output referenced to midsupply, unless otherwise noted. Figure 52. Figure 53.

0.22 F/c109

Table 2. Load Component Values For 1:1The THS4524 is tested with the test circuits shown in Differential to Single-Ended Output Transformer(1) 200 Ω 86.6 Ω 69.8 Ω 16.8 dBin the Applications section for recommendations.

  1. Total load includes 50-Ω termination by the testgenerators used are ac-coupled and in others they

An HP network analyzer is used as the signal sourceApplications section with no impact on performance. amplifier, a 49.9-Ω resistor to ground is insertedequipment has single-ended inputs and outputs. Table 1. Gain Component Values for

  1. Gain setting includes 50-Ω source impedance. Figure 54. Frequency Response Test CircuitComponents are chosen to achieve gain and 50-

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reduce harmonics generated at the signal source. input of the spectrum analyzer. Figure 56. Slew Rate, Transient Response, Figure 55. Distortion Test Circuit

best results. the amplifier VOCM input. back to the amplifier output. Figure 57. CMRR Test Circuit Figure 59. VOCM Input Test Circuit Figure 58. PSRR Test Circuit Figure 60. VOCM Transient Response and Slew

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applied to differential input sources.

  • VOCM is the voltage applied to the VOCM pin (2)

Figure 63. VOCM Input Circuit the input impedance of the amplifier circuit, RITperformance parameters. Table 3. Typical Performance Variation versus Power-Supply Voltage

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recommended values of RO versus capacitive loads Figure 68. Frequency Response for Various RO(CL), and Figure 68 shows an illustration of the and CL Values, with RLOAD = 1 kΩfrequency response with various values. (generator) together with the THS4524. Figure 67. Recommended Series Output Resistor Figure 69. THS4524 AP Analyzer Test Circuit

30 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated

Figure 75. THS4524 PD Pin Enable Pop Figure 73. THS4524 Power-Supply Turn-On Pop Figure 76. THS4524 PD Pin Disable Pop

32 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated

Figure 79. THS4524 and PCM4204 Test Circuit Table 4. 1-kHz AC Analysis: Test Circuit versus PCM4204 Data Sheet Typical Specifications

34 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated

Frequency (Hz) -80 -82 -84 -86 -88 -90 -92 -94 -96 -98 -100 THD+N (dB) 100 1 k 10 k 20 k THS4524 and PCM3168 THD+N vs FREQUENCY (No Weighting) Frequency (Hz) -95 -97 -99 -101 -103 -105 -107 -109 -111 -113 -115 THD+N (dB) 100 1 k 10 k 20 k G = 5 G = 1 G = 2 THS4524 and PCM4204 THD+N vs FREQUENCY (No Weighting, at Higher Gains) THS4524-EP www.ti.com SBOS609A –JUNE 2012–REVISED AUGUST 2013 Figure 80 shows the THS4524 and PCM4204 THD+N EVM is configured for both differential inputs as versus frequency with no weighting at higher gains. shown in Figure 61 and for single-ended input as shown in Figure 62 with 1-kΩ resistors for RF and RG, and 24.9-Ω resistors in series with each output to isolate the outputs from the reactive load of the coaxial cables. To limit the noise from the external EVM and cables, a 2.7-nF capacitor is placed differentially across the PCM3168A inputs. The THS4524 is operated with a single-supply +5-V supply so the output common-mode of the THS4524 defaults to +2.5 V as required at the input of the PCM3168A. The PCM3168A EVM is configured and operated as described in the PCM3168AEVM User Guide. The ADC was tested with an external THS4524 EVM with both single-ended input and differential inputs. In both configurations, the results are the same. Figure 81 shows the THD+N versus frequency and Table 5 compares the result to the PCM3168 data sheet typical specification at 1 kHz. Both graphs show that it makes an excellent drive amplifier for this ADC. Note: a 2700 series AudioFigure 80. THS4524 and PCM4204: THD+N versus Analyzer from Audio Precision is used to generateFrequency with No Weighting at Higher Gains the input signals to the THS4524 and to analyze the digital data from the PCM3168. Audio ADC Driver Performance: THS4524 and PCM3168 Combined Performance The THS4524 is also tested as the drive amplifier for the PCM3168A ADC input. The PCM3168A is a high- performance, single-chip, 24-bit, 6-in/8-out, audio coder/decoder (codec) with single-ended and differential selectable analog inputs and differential outputs. The six-channel, 24-bit ADC employs a ΔΣ modulator and supports 8-kHz to 96-kHz sampling rates and a 16-bit/24-bit width digital audio output word on the audio interface. The eight-channel, 24-bit digital-to-analog converter (DAC) employs a ΔΣ modulator and supports 8-kHz to 192-kHz sampling rates and a 16-bit/24-bit width digital audio input word on the audio interface. Each audio interface supports I2S™ , left-/right-justified, and DSP formats with 16- bit/24-bit word width. In addition, the PCM3168A Figure 81. THS4524 and PCM3168: THD+N versussupports the time-division-multiplexed (TDM) format.. Frequency with No WeightingThe PCM3168A provides flexible serial port interface and many other advanced features. Refer to the PCM3168A product data sheet for more information. Table 5. 1-kHz AC Analysis: Test Circuit vs PCM3168 Data Sheet Typical SpecificationsThe PCM3168A EVM is used to test the audio (fS = 48 kSPS)performance of the THS4524 as a drive amplifier. The standard PCM3168A EVM is provided with Configuration Tone THD+N OPA2134 op amps that are used to convert single- THS4524 and 1 kHz –92.6 dBcended inputs to differential to drive the ADC. For PCM3168 testing, the op amp output series resistors are PCM3168 Data 1 kHz –93 dBcremoved from one of the channels and a THS4524, sheet (typ) mounted on its standard EVM, is connected to the ADC inputs via short coaxial cables. The THS4524 Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links :THS4524-EP

ac and dc performance, with four selectable operating data sheet typical performance specifications. Figure 82. THS4524 and ADS1278 (Ch 1) Test Circuit Figure 83. 1-kHz FFT Figure 84. 10-kHz FFT Table 6. AC Analysis

36 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated

0.1 F/c109

10 F/c109

  1. Signal routing should be direct and as short as possible into and out of the op amp circuit.
  2. The feedback path should be short and direct.
  3. Ground or power planes should be removed from directly under the amplifier input and output pins.
  4. An output resistor is recommended in each output lead, placed as near to the output pins as possible.
  5. Two 0.1-μF power-supply decoupling capacitors should be placed as near to the power-supply pins as
  6. Two 10-μF power-supply decoupling capacitors should be placed within 1 inch of the device and can be

shared among multple analog devices.

  1. A 0.22-μF capacitor should be placed between the VOCM input pin and ground near to the pin. This capacitor

limits noise coupled into the pin.

  1. The PD pin uses TTL logic levels; a bypass capacitor is not necessary if actively driven, but can be used for

robustness in noisy environments whether driven or not.

  1. If input termination resistors R10 and R11 are used, a single point connection to ground on L2 is

Figure 88. THS4524EVM: Schematic

38 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated

Figure 89. THS4524EVM: Layer 1 to Layer 4 Images

Table 8. THS4524EVM Parts List

4 Open 0603 C2, C13, C14, C15, C16 5

5 Open 0603 R1, R2, R3, R7, R8, R9, R18, 12

6 Resistor, 0 Ω 0603 R24, R25 2 (ROHM) MCR03EZPJ000

9 Resistor, 487 Ω, 1/10W, 1% 0603 R16, R17 2 (ROHM) MCR03EZPFX4870

10 Resistor, 1k Ω, 1/10W, 1% 0603 R12, R13, R14, R15 4 (ROHM) MCR03EZPFX1001

11 Resistor, 0 Ω 0805 R4, R5 2 (ROHM) MCR10EZPJ000

12 Open T1 1

13 Transformer, RF T2 1 (MINI-CIRCUITS) ADT1-1WT

15 Open J1, J3, J6, J7, J10, J11 6

16 Connector, edge, SMA PCB jack J2, J9 2 (JOHNSON) 142-0701-801

18 Shunts JP1 1 (SULLINS) SSC02SYAN

19 Test point, Red TP1 1 (KEYSTONE) 5000

20 Test point, Black TP2, TP3 2 (KEYSTONE) 5001

21 IC, THS4524 U1 1 (TI) THS4524D

24 Board, printed circuit 1 (TI) EDGE# 6494532

40 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated

www.ti.com SBOS609A –JUNE 2012–REVISED AUGUST 2013 Evaluation Board/Kit Important Notice Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling (WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives. Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES. TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This notice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/or safety programs, please contact the TI application engineer or visit www.ti.com/esh. No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or combination in which such TI products or services might be or are used. FCC Warning This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may be required to correct this interference. EVM Warnings and Restrictions It is important to operate this EVM within the input voltage range of 3 V to 5.5 V and the output voltage range of 3 V to 5.5 V. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, some circuit components may have case temperatures greater than 125°C. The EVM is designed to operate properly with certain components above 125°C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated Copyright © 2012–2013, Texas Instruments Incorporated Submit Documentation Feedback 41 Product Folder Links :THS4524-EP

www.ti.com 31-Jul-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples THS4524MDBTEP PREVIEW TSSOP DBT 38 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 THS4524EP THS4524MDBTREP ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 THS4524EP V62/12612-01XE ACTIVE TSSOP DBT 38 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -55 to 125 THS4524EP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 31-Jul-2013 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF THS4524-EP :

  • Catalog: THS4524 NOTE: Qualified Version Definitions:
  • Catalog - TI's standard catalog product

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS4524MDBTREP TSSOP DBT 38 2000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 31-Jul-2013 Pack Materials-Page 2

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