V6212605-01XE

Texas Instruments

OMAPL138B C6-Integra DSP ARM Processor

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 OMAPL138BC6-Integra™ DSP+ARM® Processor Check forSamples: OMAPL138B-EP

1 OMAPL138B C6-Integra™ DSP+ARM ® Processor

1.1 Features

Highlights • C674x Two LevelCache Memory Architecture – Dual Core SoC – 32K-Byte L1P Program RAM/Cache
345-MHz ARM926EJ-S ™ RISC MPU – 32K-Byte L1D Data RAM/Cache
345-MHz C674x Fixed/Floating-PointVLIW – 256K-Byte L2 UnifiedMapped RAM/Cache DSP – FlexibleRAM/Cache Partition(L1and L2) – Supports TI’s Basic Secure Boot • Enhanced Direct-Memory-AccessController3 – Enhanced Direct-Memory-AccessController (EDMA3): (EDMA3) – 2 Channel Controllers – SerialATA (SATA) Controller – 3 TransferControllers – DDR2/Mobile DDR Memory Controller – 64 IndependentDMA Channels – Two MultimediaCard (MMC)/Secure Digital – 16 Quick DMA Channels (SD)Card Interface – Programmable TransferBurstSize – LCD Controller • TMS320C674x Floating-PointVLIW DSP Core – Video PortInterface(VPIF) – Load-StoreArchitectureWith Non-Aligned – 10/100Mb/s EthernetMAC (EMAC) Support – Programmable Real-TimeUnitSubsystem – 64 General-PurposeRegisters(32Bit) – Three ConfigurableUART Modules – SixALU (32-/40-Bit)FunctionalUnits – USB 1.1OHCI (Host)With IntegratedPHY • Supports 32-BitInteger,SP (IEEESingle – One MultichannelAudio SerialPort Precision/32-Bit)and DP (IEEEDouble Precision/64-Bit)FloatingPoint– Two MultichannelBufferedSerialPorts
Supports up toFour SP AdditionsPer• Dual Core SoC Clock,Four DP AdditionsEvery 2 Clocks– 345-MHz ARM926EJ-S ™ RISC MPU
Supports up toTwo FloatingPoint(SP or– 345-MHz C674x Fixed/Floating-PointVLIW DP) ReciprocalApproximation(RCPxP)DSP and Square-Root Reciprocal• ARM926EJ-S Core Approximation(RSQRxP) OperationsPer– 32-Bitand 16-Bit(Thumb ® )Instructions Cycle – DSP InstructionExtensions – Two MultiplyFunctionalUnits – SingleCycle MAC • Mixed-PrecisionIEEE FloatingPoint – ARM ® Jazelle® Technology MultiplySupported up to: – EmbeddedICE-RT ™ forReal-TimeDebug – 2 SP x SP → SP Per Clock
ARM9 Memory Architecture – 2 SP x SP → DP Every Two Clocks – 16K-Byte InstructionCache – 2 SP x DP → DP Every Three Clocks – 16K-Byte Data Cache – 2 DP x DP → DP Every Four Clocks – 8K-Byte RAM (VectorTable) • FixedPointMultiplySupports Two 32 x – 64K-Byte ROM 32-BitMultiplies,Four 16 x 16-Bit Multiplies,or Eight8 x 8-BitMultipliesper• C674x ™ InstructionSet Features Clock Cycle,and Complex Multiples– SupersetoftheC67x+ ™ and C64x+ ™ ISAs – InstructionPacking Reduces Code Size– Up to3648/2746C674x MIPS/MFLOPS – AllInstructionsConditional– Byte-Addressable(8-/16-/32-/64-BitData) – Hardware Support forModulo Loop– 8-BitOverflowProtection Operation– Bit-FieldExtract,Set,Clear – ProtectedMode Operation– Normalization,Saturation,Bit-Counting – ExceptionsSupport forErrorDetectionand– Compact 16-BitInstructions Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate.Productsconformto Copyright© 2011–2013,Texas InstrumentsIncorporatedspecificationsper the terms of the Texas Instrumentsstandardwarranty.Production processingdoes notnecessarilyincludetestingofallparameters.

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Program Redirection – USB 2.0High-/Full-SpeedClient

SoftwareSupport – USB 2.0High-/Full-/Low-SpeedHost – TIDSP/BIOS ™ – End Point0 (Control) – Chip Support Libraryand DSP Library – End Points1,2,3,4(Control,Bulk,Interruptor ISOC) Rx and Tx• 128K-Byte RAM Shared Memory
One MultichannelAudio SerialPort:• 1.8Vor 3.3VLVCMOS IOs (exceptforUSB and DDR2 interfaces) – Two Clock Zones and 16 SerialData Pins
Two ExternalMemory Interfaces: – Supports TDM, I2S,and SimilarFormats – EMIFA – DIT-Capable
NOR (8-/16-Bit-WideData) – FIFO buffersforTransmitand Receive
NAND (8-/16-Bit-WideData) • Two MultichannelBufferedSerialPorts:
16-BitSDRAM With 128 MB Address – Supports TDM, I2S,and SimilarFormats Space – AC97 Audio Codec Interface – DDR2/Mobile DDR Memory Controller – Telecom Interfaces(ST-Bus,H100)
16-BitDDR2 SDRAM With 512 MB – 128-channelTDM Address Space or – FIFO buffersforTransmitand Receive
16-BitmDDR SDRAM With 256 MB • 10/100Mb/s EthernetMAC (EMAC):Address Space – IEEE 802.3Compliant• Three Configurable16550 typeUART Modules: – MIIMedia IndependentInterface– With Modem ControlSignals – RMII Reduced Media IndependentInterface– 16-byteFIFO – Management Data I/O(MDIO) Module– 16x or 13x Oversampling Option • Video PortInterface(VPIF):• LCD Controller – Two 8-bitSD (BT.656),Single16-bitor Single• Two SerialPeripheralInterfaces(SPI)Each Raw (8-/10-/12-bit)Video Capture ChannelsWith MultipleChip-Selects – Two 8-bitSD (BT.656),Single16-bitVideo• Two MultimediaCard (MMC)/Secure Digital(SD) DisplayChannelsCard InterfacewithSecure Data I/O(SDIO) • UniversalParallelPort(uPP):Interfaces – High-Speed ParallelInterfacetoFPGAs and• Two Master/SlaveInter-IntegratedCircuit(I2C Data ConvertersBus ™ ) – Data Width on Each ofTwo Channels is8-to• One Host-PortInterface(HPI)With 16-Bit-Wide 16-bitInclusiveMuxed Address/DataBus For High Bandwidth – SingleData Rate or Dual Data Rate Transfers• Programmable Real-TimeUnitSubsystem – Supports MultipleInterfaceswithSTART,(PRUSS) ENABLE and WAIT Controls– Two IndependentProgrammable Realtime • SerialATA (SATA) Controller:Unit(PRU) Cores – Supports SATA I(1.5Gbps) and SATA II(3.0• 32-BitLoad/StoreRISC architecture Gbps)• 4K Byte instructionRAM per core – Supports allSATA Power Management• 512 Bytes dataRAM per core Features• PRU Subsystem (PRUSS) can be disabled – Hardware-AssistedNativeCommandviasoftwaretosave power Queueing (NCQ) forup to32 Entries• Register30 ofeach PRU isexportedfrom – Supports PortMultiplierand Command-thesubsystem inadditiontothenormal Based SwitchingR31 outputofthePRU cores. • Real-TimeClock With 32 KHz Oscillator(1)and– Standard power management mechanism SeparatePower Rail• Clock gating • Three 64-BitGeneral-PurposeTimers (Each• Entiresubsystem under a singlePSC Configurableas Two 32-BitTimers)clockgatingdomain • One 64-bitGeneral-Purpose/WatchdogTimer– Dedicatedinterruptcontroller (Configurableas Two 32-bitGeneral-Purpose – Dedicatedswitchedcentralresource Timers)
USB 1.1OHCI (Host)With IntegratedPHY • Two Enhanced Pulse Width Modulators (USB1) (eHRPWM):
USB 2.0OTG PortWith IntegratedPHY (USB0) (1) Crystaloscillatorcannotbe operatedbeyond 105°C.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 – Dedicated16-BitTime-Base Counter With – Configurableas 3 Capture Inputsor 3 PeriodAnd Frequency Control AuxiliaryPulse Width Modulator(APWM) outputs– 6 SingleEdge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs – SingleShot Capture ofup toFour Event Time-Stamps– Dead-Band Generation

361-BallSnPb PlasticBallGridArray(PBGA)– PWM Chopping by High-FrequencyCarrier [GWT Suffix],0.80-mm BallPitch– TripZone Input
AvailableinMilitary(-55°C to125°C)• Three 32-BitEnhanced Capture Modules Temperature Range(eCAP):

1.2 SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS

ControlledBaseline
One Assembly/TestSite
One FabricationSite
AvailableinExtended (–55°C/125°C) Temperature Range
Extended Product LifeCycle
Extended Product-Change Notification
Product Traceability Copyright© 2011–2013,Texas InstrumentsIncorporated OMAPL138B C6-Integra™ DSP+ARM ® Processor 3 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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1.3 Description

The OMAPL138B C6-Integra™ DSP+ARM ® processorisa low-powerapplicationsprocessorbased on an ARM926EJ-S ™ and a C674x DSP core.Itprovidessignificantlylowerpower thanothermembers ofthe TMS320C6000 ™ platformofDSPs. The deviceenables OEMs and ODMs to quicklybringto market devicesfeaturingrobustoperating systems support,richuser interfaces,and high processingperformancelifethroughthe maximum flexibilityofa fullyintegratedmixed processorsolution. The dual-corearchitectureof the deviceprovidesbenefitsof both DSP and Reduced InstructionSet Computer (RISC) technologies,incorporatinga high-performanceTMS320C674x DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bitRISC processorcore thatperforms32-bitor 16-bitinstructionsand processes32-bit,16-bit,or 8-bitdata.The core uses pipeliningso thatallpartsof the processorand memory systemcan operatecontinuously. The ARM core has a coprocessor15 (CP15), protectionmodule, and Data and program Memory Management Units(MMUs) withtablelook-asidebuffers.Ithas separate16K-byteinstructionand 16K- bytedatacaches.Both are four-wayassociativewithvirtualindexvirtualtag(VIVT).The ARM corealso has a 8KB RAM (VectorTable)and 64KB ROM. The deviceDSP coreuses a two-levelcache-basedarchitecture.The Level1 program cache (L1P)isa 32KB directmapped cache and theLevel1 datacache (L1D)isa 32KB 2-way set-associativecache.The Level2 program cache (L2P)consistsofa 256KB memory space thatissharedbetween program and data space. L2 memory can be configuredas mapped memory, cache, or combinationsof the two. Althoughthe DSP L2 isaccessibleby ARM and otherhostsinthe system,an additional128KB RAM sharedmemory isavailableforuse by otherhostswithoutaffectingDSP performance. For securityenabled devices,TI’s Basic Secure Boot allowsusers to protectproprietaryintellectual propertyand preventsexternalentitiesfrom modifyinguser-developedalgorithms.By startingfrom a hardware-based“root-of-trust”, the secure boot flowguaranteesa known good startingpointforcode execution.By default,theJTAG portislockeddown topreventemulationand debug attacksbutcan be enabledduringthe secureboot processduringapplicationdevelopment.The boot modules themselves areencryptedwhilesittinginexternalnon-volatilememory, such as flashorEEPROM, and aredecrypted and authenticatedwhen loaded duringsecure boot.This protectsthe users’ IP and enablesthem to securelyset up the system and begin deviceoperationwithknown, trustedcode. Basic Secure Boot utilizeseitherSHA-1 or SHA-256, and AES-128 forbootimage validation.Italsouses AES-128 forboot image encryption.The securebootflowemploys a multi-layerencryptionscheme whichnotonlyprotects thebootprocessbutofferstheabilitytosecurelyupgrade bootand applicationsoftwarecode.A 128-bit device-specificcipherkey,known onlytothedeviceand generatedusinga NIST-800-22certifiedrandom number generator,isused to protectuser encryptionkeys.When an update isneeded, the customer createsa new encryptedimage usingitsencryptionkeys.Then thedevicecan acquiretheimage viaan externalinterface,such as Ethernet,and overwritetheexistingcode.For more detailson thesupported securityfeaturesor TI’s BasicSecure Boot,referto the TMS320C674x/OMAP-L1x ProcessorSecurity User’s Guide (SPRUGQ9). The peripheralsetincludes:a 10/100Mb/s EthernetMAC (EMAC) witha Management Data Input/Output (MDIO) module;one USB2.0 OTG interface;one USB1.1 OHCI interface;two inter-integratedcircuit(I2C) Bus interfaces;one multichannelaudio serialport(McASP) with16 serializersand FIFO buffers;two multichannelbufferedserialports(McBSP) withFIFO buffers;two SPI interfaceswithmultiplechip selects;four 64-bitgeneral-purposetimerseach configurable(one configurableas watchdog);a configurable16-bithostportinterface(HPI); up to 9 banks of 16 pinsof general-purposeinput/output (GPIO) withprogrammable interrupt/eventgenerationmodes, multiplexedwithotherperipherals;three

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 UART interfaces(each with RTS and CTS); two enhanced high-resolutionpulse width modulator (eHRPWM) peripherals;3 32-bitenhanced capture(eCAP) module peripheralswhich can be configured as 3 captureinputsor 3 auxiliarypulse widthmodulator(APWM) outputs;and 2 externalmemory interfaces:an asynchronousand SDRAM externalmemory interface(EMIFA) forslowermemories or peripherals,and a higherspeed DDR2/MobileDDR controller. The EthernetMedia Access Controller(EMAC) providesan efficientinterfacebetween thedeviceand a network.The EMAC supportsboth10Base-T and 100Base-TX,or10 Mbits/second(Mbps)and 100 Mbps in eitherhalf-or full-duplexmode. Additionallyan Management Data Input/Output(MDIO) interfaceis availableforPHY configuration.The EMAC supportsbothMIIand RMII interfaces. The SATA controllerprovidesa high-speedinterfacetomass datastoragedevices.The SATA controller supportsbothSATA I(1.5Gbps) and SATA II(3.0Gbps). The UniversalParallelPort(uPP) providesa high-speedinterfaceto many typesof data converters, FPGAs or otherparalleldevices.The UPP supportsprogrammable datawidthsbetween 8- to16-bitson each oftwo channels.Single-datarateand double-dataratetransfersare supportedas wellas START, ENABLE and WAIT signalstoprovidecontrolfora varietyofdataconverters. A VideoPortInterface(VPIF)isincludedprovidinga flexiblevideoinput/outputport. The richperipheralsetprovidesthe abilityto controlexternalperipheraldevicesand communicate with externalprocessors.For detailson each oftheperipherals,see therelatedsectionslaterinthisdocument and theassociatedperipheralreferenceguides. The devicehas a completesetofdevelopmenttoolsfortheARM and DSP. These includeC compilers,a DSP assembly optimizertosimplifyprogramming and scheduling,and a Windows ™ debugger interface forvisibilityintosourcecode execution. Copyright© 2011–2013,Texas InstrumentsIncorporated OMAPL138B C6-Integra™ DSP+ARM ® Processor 5 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

Switched Central Resource (SCR) BOOT ROM 256KB L2 RAM 32KB L1 RAM 32KB L1 Pgm 16KB I-Cache 16KB D-Cache AET4KB ETB C674x™ DSP CPU ARM926EJ-S CPU With MMU DSP SubsystemARM SubsystemJTAG Interface System Control Input Clock(s) 64KB ROM 8KB RAM (Vector Table) Power/Sleep Controller Pin Multiplexing PLL/Clock Generator w/OSC General- Purpose Timer (x4) Serial InterfacesAudio Ports McASP w/FIFO DMA Peripherals Display Internal Memory LCD Ctlr 128KB RAM External Memory InterfacesConnectivity EDMA3 (x2) Control Timers ePWM (x2) eCAP (x3) EMIFA(8b/16B) NAND/Flash 16b SDRAM DDR2/MDDR Controller RTC/ 32-kHz OSC I C (x2)

2 SPI

(x2) UART (x3) McBSP (x2) Video VPIF Parallel Port uPP EMAC (MII/RMII) MDIO USB1.1 OHCI Ctlr PHY USB2.0 OTG Ctlr PHY HPI MMC/SD (8b) (x2) SATA Customizable Interface PRU Subsystem OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com

1.4 FunctionalBlock Diagram

(1) Note:Not allperipheralsareavailableatthesame timedue tomultiplexing. Figure1-1.FunctionalBlock Diagram

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SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Thisdata manual revisionhistoryhighlightsthe changes made to the SPRS586C device-specificdata manual tomake itan SPRS586D revision.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013

2 Device Overview

2.1 Device Characteristics

Table2-1providesan overviewofthedevice.The tableshows significantfeaturesofthedevice,including thecapacityofon-chipRAM, peripherals,and thepackage typewithpincount. Table2-1.CharacteristicsofOMAPL138 HARDWARE FEATURES OMAPL138 DDR2, 16-bitbus width,up to156 MHzDDR2/mDDR Controller MobileDDR, 16-bitbus width,up to150 MHz Asynchronous(8/16-bitbus width)RAM, Flash,EMIFA 16-bitSDRAM, NOR, NAND FlashCard Interface 2 MMC and SD cardssupported 64 independentchannels,16 QDMA channels,EDMA3 2 channelcontrollers,3 transfercontrollers 4 64-BitGeneralPurpose(eachconfigurableas 2 separateTimers 32-bittimers,one configurableas Watch Dog) UART 3 (eachwithRTS and CTS flowcontrol) SPI 2 (Eachwithone hardwarechipselect) I2C 2 (bothMaster/Slave) Peripherals MultichannelAudioSerialPort[McASP] 1 (eachwithtransmit/receive,FIFO buffer,16 serializers)Not allperipheralspins MultichannelBufferedSerialPort[McBSP] 2 (eachwithtransmit/receive,FIFO buffer,16)areavailableatthe same time(formore 10/100EthernetMAC withManagement Data I/O 1 (MIIorRMII Interface) detail,see theDevice 4 SingleEdge,4 DualEdge Symmetric,orConfigurationssection).eHRPWM 2 DualEdge AsymmetricOutputs eCAP 3 32-bitcaptureinputsor3 32-bitauxiliaryPWM outputs UHPI 1 (16-bitmultiplexedaddress/data) USB 2.0(USB0) High-SpeedOTG Controllerwithon-chipOTG PHY USB 1.1(USB1) Full-SpeedOHCI (ashost)withon-chipPHY General-PurposeInput/OutputPort 9 banks of16-bit LCD Controller 1 SATA Controller 1 (SupportsbothSATA Iand SATAII) UniversalParallelPort(uPP) 1 VideoPortInterface(VPIF) 1 (videoinand videoout) PRU Subsystem (PRUSS) 2 Programmable PRU Cores Size(Bytes) 488KB RAM DSP 32KB L1 Program (L1P)/Cache(upto32KB) 32KB L1 Data (L1D)/Cache(upto32KB) 256KB UnifiedMapped RAM/Cache (L2) DSP Memories can be made accessibletoARM, EDMA3, and otherperipherals.On-ChipMemory Organization ARM 16KB I-Cache 16KB D-Cache 8KB RAM (VectorTable) 64KB ROM ADDITIONAL SHARED MEMORY 128KB RAM Security SecureBoot TIBasicSecureBoot C674x CPU ID + CPU ControlStatusRegister(CSR.[31:16]) 0x1400Rev ID C674x Megamodule RevisionID Register(MM_REVID[15:0]) 0x0000Revision JTAG BSDL_ID DEVIDR0 Register 0x0B7D_102F Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 9 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-1.CharacteristicsofOMAPL138 (continued) HARDWARE FEATURES OMAPL138 674x DSP 345 MHz (1.2V) CPU Frequency MHz ARM926 345 MHz (1.2V) Core (V) Variable(1.2V-1.0V)for345 MHz version Voltage I/O(V) 1.8Vor3.3V Package 16 mm x 16 mm, 361-Ball0.80mm pitch,PBGA (GWT) ProductPreview(PP), ProductStatus(1) Advance Information(AI), 345 MHz versions-PD orProductionData (PD) (1) ADVANCE INFORMATION concernsnew productsinthesamplingorpreproductionphase ofdevelopment.Characteristicdataand otherspecificationsaresubjecttochange withoutnotice.PRODUCTION DATA informationiscurrentas ofpublicationdate.Products conformtospecificationsperthetermsoftheTexas Instrumentsstandardwarranty.Productionprocessingdoes notnecessarilyinclude testingofallparameters.

2.2 ORDERING INFORMATION (1)

PRODUCT ORDERABLE PART NUMBER PACKAGE PACKAGE DESIGNATOR PACKAGE MARKING VID NUMBER OMAPL138B OMAPL138BGWTMEP PBGA GWT OMAPL138BGWTMEP V62/12605-01XE (1) Forthemost currentpackage and orderinginformationsee thePackage OptionAddendum attheend ofthisdocument,orsee theTI web siteatwww.ti.com.

2.3 Device Compatibility

The ARM926EJ-S RISC CPU iscompatiblewithotherARM9 CPUs fromARM Holdingsplc. The C674x DSP coreiscode-compatiblewiththeC6000 ™ DSP platformand supportsfeaturesofboth theC64x+ and C67x+ DSP families.

2.4 ARM Subsystem

The ARM Subsystem includesthefollowingfeatures:

ARM926EJ-S RISC processor
ARMv5TEJ (32/16-bit)instructionset
Littleendian
System ControlCo-Processor15 (CP15)
MMU
16KB Instructioncache
16KB Data cache
WriteBuffer
Embedded TraceModule and Embedded TraceBuffer(ETM/ETB)
ARM Interruptcontroller

2.4.1 ARM926EJ-S RISC CPU

The ARM Subsystem integratestheARM926EJ-S processor.The ARM926EJ-S processorisa member of ARM9 familyofgeneral-purposemicroprocessors.Thisprocessoristargetedatmulti-taskingapplications where fullmemory management, highperformance,low diesize,and low power are allimportant.The ARM926EJ-S processorsupportsthe32-bitARM and 16 bitTHUMB instructionsets,enablingtheuserto tradeoffbetween high performanceand high code density.Specifically,the ARM926EJ-S processor supportstheARMv5TEJ instructionset,whichincludesfeaturesforefficientexecutionofJava bytecodes, providingJava performancesimilarto JustinTime (JIT)Java interpreter,but withoutassociatedcode overhead.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 The ARM926EJ-S processorsupportsthe ARM debug architectureand includeslogicto assistinboth hardware and softwaredebug. The ARM926EJ-S processorhas a Harvardarchitectureand providesa completehighperformancesubsystem,including:

ARM926EJ -S integercore
CP15 systemcontrolcoprocessor
Memory Management Unit(MMU)
Separateinstructionand datacaches
Writebuffer
Separateinstructionand data(internalRAM) interfaces
Separateinstructionand dataAHB bus interfaces
Embedded TraceModule and Embedded TraceBuffer(ETM/ETB) For more completedetailson theARM9, refertotheARM926EJ-S TechnicalReferenceManual,available athttp://www.arm.com

2.4.2 CP15

The ARM926EJ-S system controlcoprocessor(CP15) isused to configureand controlinstructionand datacaches,Memory Management Unit(MMU), and otherARM subsystemfunctions.The CP15 registers areprogrammed usingtheMRC and MCR ARM instructions,when theARM ina privilegedmode such as supervisororsystemmode.

2.4.3 MMU

A singlesetoftwo levelpage tablesstoredinmain memory isused tocontroltheaddresstranslation, permissionchecksand memory regionattributesforbothdataand instructionaccesses.The MMU uses a singleunifiedTranslationLookasideBuffer(TLB) to cache the informationheldinthe page tables.The MMU featuresare:

StandardARM architecturev4 and v5 MMU mapping sizes,domains and accessprotectionscheme.
Mapping sizesare: – 1MB (sections) – 64KB (largepages) – 4KB (smallpages) – 1KB (tinypages)
Access permissionsforlargepages and smallpages can be specifiedseparatelyforeach quarterof thepage (subpagepermissions)
Hardware page tablewalks
InvalidateentireTLB, usingCP15 register8
InvalidateTLB entry,selectedby MVA, usingCP15 register8
Lockdown ofTLB entries,usingCP15 register10

2.4.4 Caches and WriteBuffer

The sizeoftheInstructioncache is16KB, Data cache is16KB. Additionally,thecaches have thefollowing features:

Virtualindex,virtualtag,and addressedusingtheModifiedVirtualAddress(MVA)
Four-waysetassociative,witha cache linelengthofeightwords perline(32-bytesperline)and with two dirtybitsintheDcache
Dcache supportswrite-throughand write-back(orcopy back)cache operation,selectedby memory regionusingtheC and B bitsintheMMU translationtables
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Cache lockdownregistersenablecontroloverwhich cache ways are used forallocationon a linefill, providinga mechanism forbothlockdown,and controllingcache corruption
Dcache storesthePhysicalAddress TAG (PA TAG) correspondingtoeach Dcache entryintheTAG RAM foruse duringthe cache linewrite-backs,inadditionto the VirtualAddress TAG storedinthe TAG RAM. Thismeans thattheMMU isnotinvolvedinDcache write-backoperations,removingthe possibilityofTLB missesrelatedtothewrite-backaddress.
Cache maintenanceoperationsprovideefficientinvalidationof,theentireDcache orIcache,regionsof theDcache orIcache,and regionsofvirtualmemory. The writebufferisused forallwritestoa noncachablebufferableregion,write-throughregionand write misses toa write-backregion.A separatebufferisincorporatedintheDcache forholdingwrite-backfor cache lineevictionsorcleaningofdirtycache lines.The main writebufferhas 16-worddatabufferand a four-addressbuffer.The Dcache write-backhas eightdataword entriesand a singleaddressentry.

2.4.5 Advanced High-PerformanceBus (AHB)

The ARM Subsystem uses theAHB portoftheARM926EJ-S toconnecttheARM totheConfigbus and theexternalmemories.Arbitersareemployed toarbitrateaccesstotheseparateD-AHB and I-AHB by the ConfigBus and theexternalmemories bus.

2.4.6 Embedded Trace Macrocell(ETM) and Embedded Trace Buffer(ETB)

To supportreal-timetrace,theARM926EJ-S processorprovidesan interfacetoenableconnectionofan Embedded Trace Macrocell(ETM). The ARM926ES-J Subsystem in the device also includesthe Embedded TraceBuffer(ETB).The ETM consistsoftwo parts:

TracePortprovidesreal-timetracecapabilityfortheARM9.
Triggeringfacilitiesprovidetriggerresources,which includeaddressand data comparators,counter, and sequencers. The devicetraceportisnotpinnedoutand isinsteadonlyconnectedtotheEmbedded TraceBuffer.The ETB has a 4KB buffermemory. ETB enableddebug toolsarerequiredtoread/interpretthecapturedtrace data.

2.4.7 ARM Memory Mapping

By defaultthe ARM has access to most on and offchip memory areas,includingthe DSP Internal memories,EMIFA, DDR2, and theadditional128K byteon chipsharedSRAM. Likewisealmostallofthe on chipperipheralsareaccessibletotheARM by default. See Table2-4fora detailedtopleveldevicememory map thatincludestheARM memory space.

2.5 DSP Subsystem

The DSP Subsystem includesthefollowingfeatures:

C674x DSP CPU
32KB L1 Program (L1P)/Cache(upto32KB)
32KB L1 Data (L1D)/Cache(upto32KB)
256KB UnifiedMapped RAM/Cache (L2)
BootROM (cannotbe used forapplicationcode)
Littleendian

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure2-1.C674x Megamodule Block Diagram

2.5.1 C674x DSP CPU Description

The C674x CentralProcessingUnit(CPU) consistsof eightfunctionalunits,two registerfiles,and two datapathsas shown inFigure2-2.The two general-purposeregisterfiles(A and B) each contain32 32- bitregistersfora totalof64 registers.The general-purposeregisterscan be used fordataorcan be data addresspointers.The datatypessupportedincludepacked 8-bitdata,packed 16-bitdata,32-bitdata,40- bitdata,and 64-bitdata.Valueslargerthan32 bits,such as 40-bit-longor64-bit-longvaluesarestoredin registerpairs,withthe32 LSBs ofdataplacedinan even registerand theremaining8 or32 MSBs inthe nextupperregister(whichisalwaysan odd-numberedregister). performa generalsetofarithmetic,logical,and branchfunctions.The .D unitsprimarilyloaddata from memory totheregisterfileand storeresultsfromtheregisterfileintomemory. The C674x CPU combines theperformanceoftheC64x+ corewiththefloating-pointcapabilitiesofthe C67x+ core. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 13 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Each C674x .M unitcan performone ofthefollowingeach clockcycle:one 32 x 32 bitmultiply,one 16 x 32 bitmultiply,two 16 x 16 bitmultiplies,two 16 x 32 bitmultiplies,two 16 x 16 bitmultiplieswith add/subtractcapabilities,four8 x 8 bitmultiplies,four8 x 8 bitmultiplieswithadd operations,and four 16 x 16 multiplieswithadd/subtractcapabilities(includinga complex multiply).There isalsosupportfor Galoisfieldmultiplicationfor8-bitand 32-bitdata.Many communicationsalgorithmssuch as FFTs and modems requirecomplex multiplication.The complex multiply(CMPY) instructiontakesfor16-bitinputs and producesa 32-bitrealand a 32-bitimaginaryoutput.There arealsocomplex multiplieswithrounding capabilitythatproducesone 32-bitpacked outputthatcontain16-bitrealand 16-bitimaginaryvalues.The 32 x 32 bitmultiplyinstructionsprovidetheextendedprecisionnecessaryforhigh-precisionalgorithmson a varietyofsignedand unsigned32-bitdatatypes. The .Lor (ArithmeticLogicUnit)now incorporatestheabilitytodo paralleladd/subtractoperationson a pairofcommon inputs.Versionsofthisinstructionexisttowork on 32-bitdataor on pairsof16-bitdata performingdual16-bitadd and subtractsinparallel.Therearealsosaturatedformsoftheseinstructions. The C674x coreenhances the.S unitinseveralways.On thepreviouscores,dual16-bitMIN2 and MAX2 comparisonswere onlyavailableon the.Lunits.On theC674x coretheyarealsoavailableon the.S unit which increasesthe performanceof algorithmsthatdo searchingand sorting.Finally,to increasedata packingand unpackingthroughput,the.S unitallowssustainedhighperformanceforthequad 8-bit/16-bit and dual16-bitinstructions.Unpack instructionsprepare8-bitdata forparallel16-bitoperations.Pack instructionsreturnparallelresultstooutputprecisionincludingsaturationsupport. Othernew featuresinclude:

SPLOOP -A smallinstructionbufferintheCPU thataidsincreationofsoftwarepipeliningloopswhere multipleiterationsof a loop are executed in parallel.The SPLOOP bufferreduces the code size associatedwithsoftwarepipelining.Furthermore,loopsintheSPLOOP bufferarefullyinterruptible.
Compact Instructions- The nativeinstructionsizefortheC6000 devicesis32 bits.Many common instructionssuch as MPY, AND, OR, ADD, and SUB can be expressed as 16 bitsifthe C674x compilercan restrictthe code to use certainregistersin the registerfile.This compression is performedby thecode generationtools.
InstructionSet Enhancement - As noted above, there are new instructionssuch as 32-bit multiplications,complex multiplications,packing,sorting,bitmanipulation,and 32-bitGaloisfield multiplication.
Exceptions Handling - Intendedtoaidtheprogrammer inisolatingbugs.The C674x CPU isableto detectand respondtoexceptions,bothfrominternallydetectedsources(suchas illegalop-codes)and fromsystemevents(suchas a watchdogtimeexpiration).
Privilege- Definesuserand supervisormodes ofoperation,allowingtheoperatingsystem togivea basiclevelofprotectiontosensitiveresources.Localmemory isdividedintomultiplepages,each with read,write,and executepermissions.
Time-Stamp Counter -PrimarilytargetedforReal-TimeOperatingSystem (RTOS) robustness,a free- runningtime-stampcounterisimplementedintheCPU whichisnot sensitivetosystemstalls. For more detailson theC674x CPU and itsenhancements overtheC64x architecture,see thefollowing documents:
TMS320C64x/C64x+ DSP CPU and InstructionSetReferenceGuide (literaturenumber SPRUFE8 )
TMS320C64x TechnicalOverview(literaturenumber SPRU395 )

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Á Á Á Á Á Á Á .D1 .M1 Á Á Á Á Á Á Á Á Á Á Á Á Á .S1 Á Á Á Á Á Á Á Á Á Á .L1 long src odd dst src2 src1 Á Á Á Á Á Á Á Á Á Á Á Á Á Á ÁÁ Á Á Á Á Á src1 src1 src1 even dst even dst odd dst dst1 dst src2 src2 src2 long src DA1 ST1b LD1b LD1a ST1a Data path A Odd register file A (A1, A3, A5...A31) Á Á Á Odd register file B (B1, B3, B5...B31) Á Á Á .D2 Á Á Á Á src1 dst src2DA2 LD2a LD2b src2 .M2 src1 Á Á Á dst1 Á Á Á .S2 src1 Á Á Á Á even dst long src odd dst ST2a ST2b long src .L2 Á Á Á Á even dst odd dst Á Á Á src1 Data path B Control Register

32 MSB

32 LSB

dst2 (A) (B) (B) (A) (C) (C) Even register file A (A0, A2, A4...A30) Even register file B (B0, B2, B4...B30) (D) (D) (D) (D) A. On .M unit, dst2 is 32 MSB. B. On .M unit, dst1 is 32 LSB. C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits. D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files. OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure2-2.TMS320C674x CPU (DSP Core)Data Paths Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 15 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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2.5.2 DSP Memory Mapping

The DSP memory map isshown inSection2.6. By defaulttheDSP alsohas accesstomost on and offchipmemory areas,withtheexceptionoftheARM RAM, ROM, and AINTC interruptcontroller. Additionally,theDSP megamodule includesthecapabilitytolimitaccesstoitsinternalmemories through itsSDMA port;withoutneedingan externalMPU unit.

2.5.2.1 ARM InternalMemories

The DSP does nothave accesstotheARM internalmemory.

2.5.2.2 ExternalMemories

The DSP has accesstothefollowingExternalmemories:

AsynchronousEMIF /SDRAM /NAND /NOR Flash(EMIFA)
SDRAM (DDR2)

2.5.2.3 DSP InternalMemories

The DSP has accesstothefollowingDSP memories:

L2 RAM
L1P RAM
L1D RAM

2.5.2.4 C674x CPU

The C674x coreuses a two-levelcache-basedarchitecture.The Level1 Program cache (L1P)is32 KB directmapped cache and theLevel1 Data cache (L1D)is32 KB 2-way setassociatedcache.The Level2 memory/cache (L2)consistsofa 256 KB memory space thatissharedbetween program and dataspace. L2 memory can be configuredas mapped memory, cache,ora combinationofboth. Table2-2shows a memory map oftheC674x CPU cache registersforthedevice. Table2-2.C674x Cache Registers Byte Address RegisterName RegisterDescription 0x0184 0000 L2CFG L2 Cache configurationregister 0x0184 0020 L1PCFG L1P SizeCache configurationregister 0x0184 0024 L1PCC L1P FreezeMode Cache configurationregister 0x0184 0040 L1DCFG L1D SizeCache configurationregister 0x0184 0044 L1DCC L1D FreezeMode Cache configurationregister 0x0184 0048 -0x0184 0FFC - Reserved 0x0184 1000 EDMAWEIGHT L2 EDMA accesscontrolregister 0x0184 1004 -0x0184 1FFC - Reserved 0x0184 2000 L2ALLOC0 L2 allocationregister0 0x0184 2004 L2ALLOC1 L2 allocationregister1 0x0184 2008 L2ALLOC2 L2 allocationregister2 0x0184 200C L2ALLOC3 L2 allocationregister3 0x0184 2010 -0x0184 3FFF - Reserved 0x0184 4000 L2WBAR L2 writebackbase addressregister 0x0184 4004 L2WWC L2 writebackword countregister 0x0184 4010 L2WIBAR L2 writebackinvalidatebase addressregister 0x0184 4014 L2WIWC L2 writebackinvalidateword countregister 0x0184 4018 L2IBAR L2 invalidatebase addressregister

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table2-2.C674x Cache Registers(continued) Byte Address RegisterName RegisterDescription 0x0184 401C L2IWC L2 invalidateword countregister 0x0184 4020 L1PIBAR L1P invalidatebase addressregister 0x0184 4024 L1PIWC L1P invalidateword countregister 0x0184 4030 L1DWIBAR L1D writebackinvalidatebase addressregister 0x0184 4034 L1DWIWC L1D writebackinvalidateword countregister 0x0184 4038 - Reserved 0x0184 4040 L1DWBAR L1D BlockWriteback 0x0184 4044 L1DWWC L1D BlockWriteback 0x0184 4048 L1DIBAR L1D invalidatebase addressregister 0x0184 404C L1DIWC L1D invalidateword countregister 0x0184 4050 -0x0184 4FFF - Reserved 0x0184 5000 L2WB L2 writebackallregister 0x0184 5004 L2WBINV L2 writebackinvalidateallregister 0x0184 5008 L2INV L2 GlobalInvalidatewithoutwriteback 0x0184 500C -0x0184 5027 - Reserved 0x0184 5028 L1PINV L1P GlobalInvalidate 0x0184 502C -0x0184 5039 - Reserved 0x0184 5040 L1DWB L1D GlobalWriteback 0x0184 5044 L1DWBINV L1D GlobalWritebackwithInvalidate 0x0184 5048 L1DINV L1D GlobalInvalidatewithoutwriteback 0x0184 8000 – 0x0184 80FF MAR0 -MAR63 Reserved0x0000 0000 – 0x3FFF FFFF Memory AttributeRegistersforEMIFA SDRAM Data (CS0)0x0184 8100 – 0x0184 817F MAR64 – MAR95 Externalmemory addresses0x4000 0000 – 0x5FFF FFFF Memory AttributeRegistersforEMIFA Async Data (CS2)0x0184 8180 – 0x0184 8187 MAR96 -MAR97 Externalmemory addresses0x6000 0000 – 0x61FF FFFF Memory AttributeRegistersforEMIFA Async Data (CS3)0x0184 8188 – 0x0184 818F MAR98 – MAR99 Externalmemory addresses0x6200 0000 – 0x63FF FFFF Memory AttributeRegistersforEMIFA Async Data (CS4)0x0184 8190 – 0x0184 8197 MAR100 – MAR101 Externalmemory addresses0x6400 0000 – 0x65FF FFFF Memory AttributeRegistersforEMIFA Async Data (CS5)0x0184 8198 – 0x0184 819F MAR102 – MAR103 Externalmemory addresses0x6600 0000 – 0x67FF FFFF 0x0184 81A0 – 0x0184 81FF MAR104 – MAR127 Reserved0x6800 0000 – 0x7FFF FFFF Memory AttributeRegisterforShared RAM Externalmemory addresses0x8000 0000 – 0x8001 FFFF0x0184 8200 MAR128 Reserved0x8002 0000 – 0x81FF FFFF 0x0184 8204 – 0x0184 82FF MAR129 – MAR191 Reserved0x8200 0000 – 0xBFFF FFFF Memory AttributeRegistersforDDR2 Data (CS2)0x0184 8300 – 0x0184 837F MAR192 – MAR223 Externalmemory addresses0xC000 0000 – 0xDFFF FFFF 0x0184 8380 – 0x0184 83FF MAR224 – MAR255 Reserved0xE000 0000 – 0xFFFF FFFF Table2-3.C674x L1/L2Memory ProtectionRegisters HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x0184 A000 L2MPFAR L2 memory protectionfaultaddressregister 0x0184 A004 L2MPFSR L2 memory protectionfaultstatusregister 0x0184 A008 L2MPFCR L2 memory protectionfaultcommand register 0x0184 A00C -0x0184 A0FF - Reserved 0x0184 A100 L2MPLK0 L2 memory protectionlockkey bits[31:0] 0x0184 A104 L2MPLK1 L2 memory protectionlockkey bits[63:32] 0x0184 A108 L2MPLK2 L2 memory protectionlockkey bits[95:64] Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 17 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-3.C674x L1/L2Memory ProtectionRegisters(continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x0184 A10C L2MPLK3 L2 memory protectionlockkey bits[127:96] 0x0184 A110 L2MPLKCMD L2 memory protectionlockkey command register 0x0184 A114 L2MPLKSTAT L2 memory protectionlockkey statusregister 0x0184 A118 -0x0184 A1FF - Reserved L2 memory protectionpage attributeregister0 (controlsmemory address0x0184 A200 L2MPPA0 0x0080 0000 -0x0080 1FFF) L2 memory protectionpage attributeregister1 (controlsmemory address0x0184 A204 L2MPPA1 0x0080 2000 -0x0080 3FFF) L2 memory protectionpage attributeregister2 (controlsmemory address0x0184 A208 L2MPPA2 0x0080 4000 -0x0080 5FFF) L2 memory protectionpage attributeregister3 (controlsmemory address0x0184 A20C L2MPPA3 0x0080 6000 -0x0080 7FFF) L2 memory protectionpage attributeregister4 (controlsmemory address0x0184 A210 L2MPPA4 0x0080 8000 -0x0080 9FFF) L2 memory protectionpage attributeregister5 (controlsmemory address0x0184 A214 L2MPPA5 0x0080 A000 -0x0080 BFFF) L2 memory protectionpage attributeregister6 (controlsmemory address0x0184 A218 L2MPPA6 0x0080 C000 -0x0080 DFFF) L2 memory protectionpage attributeregister7 (controlsmemory address0x0184 A21C L2MPPA7 0x0080 E000 -0x0080 FFFF) L2 memory protectionpage attributeregister8 (controlsmemory address0x0184 A220 L2MPPA8 0x0081 0000 -0x0081 1FFF) L2 memory protectionpage attributeregister9 (controlsmemory address0x0184 A224 L2MPPA9 0x0081 2000 -0x0081 3FFF) L2 memory protectionpage attributeregister10 (controlsmemory address0x0184 A228 L2MPPA10 0x0081 4000 -0x0081 5FFF) L2 memory protectionpage attributeregister11 (controlsmemory address0x0184 A22C L2MPPA11 0x0081 6000 -0x0081 7FFF) L2 memory protectionpage attributeregister12 (controlsmemory address0x0184 A230 L2MPPA12 0x0081 8000 -0x0081 9FFF) L2 memory protectionpage attributeregister13 (controlsmemory address0x0184 A234 L2MPPA13 0x0081 A000 -0x0081 BFFF) L2 memory protectionpage attributeregister14 (controlsmemory address0x0184 A238 L2MPPA14 0x0081 C000 -0x0081 DFFF) L2 memory protectionpage attributeregister15 (controlsmemory address0x0184 A23C L2MPPA15 0x0081 E000 -0x0081 FFFF) L2 memory protectionpage attributeregister16 (controlsmemory address0x0184 A240 L2MPPA16 0x0082 0000 -0x0082 1FFF) L2 memory protectionpage attributeregister17 (controlsmemory address0x0184 A244 L2MPPA17 0x0082 2000 -0x0082 3FFF) L2 memory protectionpage attributeregister18 (controlsmemory address0x0184 A248 L2MPPA18 0x0082 4000 -0x0082 5FFF) L2 memory protectionpage attributeregister19 (controlsmemory address0x0184 A24C L2MPPA19 0x0082 6000 -0x0082 7FFF) L2 memory protectionpage attributeregister20 (controlsmemory address0x0184 A250 L2MPPA20 0x0082 8000 -0x0082 9FFF) L2 memory protectionpage attributeregister21 (controlsmemory address0x0184 A254 L2MPPA21 0x0082 A000 -0x0082 BFFF) L2 memory protectionpage attributeregister22 (controlsmemory address0x0184 A258 L2MPPA22 0x0082 C000 -0x0082 DFFF) L2 memory protectionpage attributeregister23 (controlsmemory address0x0184 A25C L2MPPA23 0x0082 E000 -0x0082 FFFF) L2 memory protectionpage attributeregister24 (controlsmemory address0x0184 A260 L2MPPA24 0x0083 0000 -0x0083 1FFF)

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table2-3.C674x L1/L2Memory ProtectionRegisters(continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION L2 memory protectionpage attributeregister25 (controlsmemory address0x0184 A264 L2MPPA25 0x0083 2000 -0x0083 3FFF) L2 memory protectionpage attributeregister26 (controlsmemory address0x0184 A268 L2MPPA26 0x0083 4000 -0x0083 5FFF) L2 memory protectionpage attributeregister27 (controlsmemory address0x0184 A26C L2MPPA27 0x0083 6000 -0x0083 7FFF) L2 memory protectionpage attributeregister28 (controlsmemory address0x0184 A270 L2MPPA28 0x0083 8000 -0x0083 9FFF) L2 memory protectionpage attributeregister29 (controlsmemory address0x0184 A274 L2MPPA29 0x0083 A000 -0x0083 BFFF) L2 memory protectionpage attributeregister30 (controlsmemory address0x0184 A278 L2MPPA30 0x0083 C000 -0x0083 DFFF) L2 memory protectionpage attributeregister31 (controlsmemory address0x0184 A27C L2MPPA31 0x0083 E000 -0x0083 FFFF) L2 memory protectionpage attributeregister32 (controlsmemory address0x0184 A280 L2MPPA32 0x0070 0000 -0x0070 7FFF) L2 memory protectionpage attributeregister33 (controlsmemory address0x0184 A284 L2MPPA33 0x0070 8000 -0x0070 FFFF) L2 memory protectionpage attributeregister34 (controlsmemory address0x0184 A288 L2MPPA34 0x0071 0000 -0x0071 7FFF) L2 memory protectionpage attributeregister35 (controlsmemory address0x0184 A28C L2MPPA35 0x0071 8000 -0x0071 FFFF) L2 memory protectionpage attributeregister36 (controlsmemory address0x0184 A290 L2MPPA36 0x0072 0000 -0x0072 7FFF) L2 memory protectionpage attributeregister37 (controlsmemory address0x0184 A294 L2MPPA37 0x0072 8000 -0x0072 FFFF) L2 memory protectionpage attributeregister38 (controlsmemory address0x0184 A298 L2MPPA38 0x0073 0000 -0x0073 7FFF) L2 memory protectionpage attributeregister39 (controlsmemory address0x0184 A29C L2MPPA39 0x0073 8000 -0x0073 FFFF) L2 memory protectionpage attributeregister40 (controlsmemory address0x0184 A2A0 L2MPPA40 0x0074 0000 -0x0074 7FFF) L2 memory protectionpage attributeregister41 (controlsmemory address0x0184 A2A4 L2MPPA41 0x0074 8000 -0x0074 FFFF) L2 memory protectionpage attributeregister42 (controlsmemory address0x0184 A2A8 L2MPPA42 0x0075 0000 -0x0075 7FFF) L2 memory protectionpage attributeregister43 (controlsmemory address0x0184 A2AC L2MPPA43 0x0075 8000 -0x0075 FFFF) L2 memory protectionpage attributeregister44 (controlsmemory address0x0184 A2B0 L2MPPA44 0x0076 0000 -0x0076 7FFF) L2 memory protectionpage attributeregister45 (controlsmemory address0x0184 A2B4 L2MPPA45 0x0076 8000 -0x0076 FFFF) L2 memory protectionpage attributeregister46 (controlsmemory address0x0184 A2B8 L2MPPA46 0x0077 0000 -0x0077 7FFF) L2 memory protectionpage attributeregister47 (controlsmemory address0x0184 A2BC L2MPPA47 0x0077 8000 -0x0077 FFFF) L2 memory protectionpage attributeregister48 (controlsmemory address0x0184 A2C0 L2MPPA48 0x0078 0000 -0x0078 7FFF) L2 memory protectionpage attributeregister49 (controlsmemory address0x0184 A2C4 L2MPPA49 0x0078 8000 -0x0078 FFFF) L2 memory protectionpage attributeregister50 (controlsmemory address0x0184 A2C8 L2MPPA50 0x0079 0000 -0x0079 7FFF) L2 memory protectionpage attributeregister51 (controlsmemory address0x0184 A2CC L2MPPA51 0x0079 8000 -0x0079 FFFF) L2 memory protectionpage attributeregister52 (controlsmemory address0x0184 A2D0 L2MPPA52 0x007A 0000 -0x007A 7FFF) Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 19 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-3.C674x L1/L2Memory ProtectionRegisters(continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION L2 memory protectionpage attributeregister53 (controlsmemory address0x0184 A2D4 L2MPPA53 0x007A 8000 -0x007A FFFF) L2 memory protectionpage attributeregister54 (controlsmemory address0x0184 A2D8 L2MPPA54 0x007B 0000 -0x007B 7FFF) L2 memory protectionpage attributeregister55 (controlsmemory address0x0184 A2DC L2MPPA55 0x007B 8000 -0x007B FFFF) L2 memory protectionpage attributeregister56 (controlsmemory address0x0184 A2E0 L2MPPA56 0x007C 0000 -0x007C 7FFF) L2 memory protectionpage attributeregister57 (controlsmemory address0x0184 A2E4 L2MPPA57 0x007C 8000 -0x007C FFFF) L2 memory protectionpage attributeregister58 (controlsmemory address0x0184 A2E8 L2MPPA58 0x007D 0000 -0x007D 7FFF) L2 memory protectionpage attributeregister59 (controlsmemory address0x0184 A2EC L2MPPA59 0x007D 8000 -0x007D FFFF) L2 memory protectionpage attributeregister60 (controlsmemory address0x0184 A2F0 L2MPPA60 0x007E 0000 -0x007E 7FFF) L2 memory protectionpage attributeregister61 (controlsmemory address0x0184 A2F4 L2MPPA61 0x007E 8000 -0x007E FFFF) L2 memory protectionpage attributeregister62 (controlsmemory address0x0184 A2F8 L2MPPA62 0x007F 0000 -0x007F 7FFF) L2 memory protectionpage attributeregister63 (controlsmemory address0x0184 A2FC L2MPPA63 0x007F 8000 -0x007F FFFF) 0x0184 A300 -0x0184 A3FF - Reserved 0x0184 A400 L1PMPFAR L1P memory protectionfaultaddressregister 0x0184 A404 L1PMPFSR L1P memory protectionfaultstatusregister 0x0184 A408 L1PMPFCR L1P memory protectionfaultcommand register 0x0184 A40C -0x0184 A4FF - Reserved 0x0184 A500 L1PMPLK0 L1P memory protectionlockkey bits[31:0] 0x0184 A504 L1PMPLK1 L1P memory protectionlockkey bits[63:32] 0x0184 A508 L1PMPLK2 L1P memory protectionlockkey bits[95:64] 0x0184 A50C L1PMPLK3 L1P memory protectionlockkey bits[127:96] 0x0184 A510 L1PMPLKCMD L1P memory protectionlockkey command register 0x0184 A514 L1PMPLKSTAT L1P memory protectionlockkey statusregister 0x0184 A518 -0x0184 A5FF - Reserved 0x0184 A600 -0x0184 A63F - Reserved (1) L1P memory protectionpage attributeregister16 (controlsmemory address0x0184 A640 L1PMPPA16 0x00E0 0000 -0x00E0 07FF) L1P memory protectionpage attributeregister17 (controlsmemory address0x0184 A644 L1PMPPA17 0x00E0 0800 -0x00E0 0FFF) L1P memory protectionpage attributeregister18 (controlsmemory address0x0184 A648 L1PMPPA18 0x00E0 1000 -0x00E0 17FF) L1P memory protectionpage attributeregister19 (controlsmemory address0x0184 A64C L1PMPPA19 0x00E0 1800 -0x00E0 1FFF) L1P memory protectionpage attributeregister20 (controlsmemory address0x0184 A650 L1PMPPA20 0x00E0 2000 -0x00E0 27FF) L1P memory protectionpage attributeregister21 (controlsmemory address0x0184 A654 L1PMPPA21 0x00E0 2800 -0x00E0 2FFF) L1P memory protectionpage attributeregister22 (controlsmemory address0x0184 A658 L1PMPPA22 0x00E0 3000 -0x00E0 37FF) L1P memory protectionpage attributeregister23 (controlsmemory address0x0184 A65C L1PMPPA23 0x00E0 3800 -0x00E0 3FFF) (1) These addressescorrespondtotheL1P memory protectionpage attributeregisters0-15(L1PMPPA0-L1PMPPA15) oftheC674x megamaodule. These registersarenotsupportedforthisdevice.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table2-3.C674x L1/L2Memory ProtectionRegisters(continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION L1P memory protectionpage attributeregister24 (controlsmemory address0x0184 A660 L1PMPPA24 0x00E0 4000 -0x00E0 47FF) L1P memory protectionpage attributeregister25 (controlsmemory address0x0184 A664 L1PMPPA25 0x00E0 4800 -0x00E0 4FFF) L1P memory protectionpage attributeregister26 (controlsmemory address0x0184 A668 L1PMPPA26 0x00E0 5000 -0x00E0 57FF) L1P memory protectionpage attributeregister27 (controlsmemory address0x0184 A66C L1PMPPA27 0x00E0 5800 -0x00E0 5FFF) L1P memory protectionpage attributeregister28 (controlsmemory address0x0184 A670 L1PMPPA28 0x00E0 6000 -0x00E0 67FF) L1P memory protectionpage attributeregister29 (controlsmemory address0x0184 A674 L1PMPPA29 0x00E0 6800 -0x00E0 6FFF) L1P memory protectionpage attributeregister30 (controlsmemory address0x0184 A678 L1PMPPA30 0x00E0 7000 -0x00E0 77FF) L1P memory protectionpage attributeregister31 (controlsmemory address0x0184 A67C L1PMPPA31 0x00E0 7800 -0x00E0 7FFF) 0x0184 A67F – 0x0184 ABFF - Reserved 0x0184 AC00 L1DMPFAR L1D memory protectionfaultaddressregister 0x0184 AC04 L1DMPFSR L1D memory protectionfaultstatusregister 0x0184 AC08 L1DMPFCR L1D memory protectionfaultcommand register 0x0184 AC0C -0x0184 ACFF - Reserved 0x0184 AD00 L1DMPLK0 L1D memory protectionlockkey bits[31:0] 0x0184 AD04 L1DMPLK1 L1D memory protectionlockkey bits[63:32] 0x0184 AD08 L1DMPLK2 L1D memory protectionlockkey bits[95:64] 0x0184 AD0C L1DMPLK3 L1D memory protectionlockkey bits[127:96] 0x0184 AD10 L1DMPLKCMD L1D memory protectionlockkey command register 0x0184 AD14 L1DMPLKSTAT L1D memory protectionlockkey statusregister 0x0184 AD18 -0x0184 ADFF - Reserved 0x0184 AE00 -0x0184 AE3F - Reserved (2) L1D memory protectionpage attributeregister16 (controlsmemory address0x0184 AE40 L1DMPPA16 0x00F0 0000 -0x00F0 07FF) L1D memory protectionpage attributeregister17 (controlsmemory address0x0184 AE44 L1DMPPA17 0x00F0 0800 -0x00F0 0FFF) L1D memory protectionpage attributeregister18 (controlsmemory address0x0184 AE48 L1DMPPA18 0x00F0 1000 -0x00F0 17FF) L1D memory protectionpage attributeregister19 (controlsmemory address0x0184 AE4C L1DMPPA19 0x00F0 1800 -0x00F0 1FFF) L1D memory protectionpage attributeregister20 (controlsmemory address0x0184 AE50 L1DMPPA20 0x00F0 2000 -0x00F0 27FF) L1D memory protectionpage attributeregister21 (controlsmemory address0x0184 AE54 L1DMPPA21 0x00F0 2800 -0x00F0 2FFF) L1D memory protectionpage attributeregister22 (controlsmemory address0x0184 AE58 L1DMPPA22 0x00F0 3000 -0x00F0 37FF) L1D memory protectionpage attributeregister23 (controlsmemory address0x0184 AE5C L1DMPPA23 0x00F0 3800 -0x00F0 3FFF) L1D memory protectionpage attributeregister24 (controlsmemory address0x0184 AE60 L1DMPPA24 0x00F0 4000 -0x00F0 47FF) L1D memory protectionpage attributeregister25 (controlsmemory address0x0184 AE64 L1DMPPA25 0x00F0 4800 -0x00F0 4FFF) L1D memory protectionpage attributeregister26 (controlsmemory address0x0184 AE68 L1DMPPA26 0x00F0 5000 -0x00F0 57FF) (2) These addressescorrespondtotheL1D memory protectionpage attributeregisters0-15(L1DMPPA0-L1DMPPA15) oftheC674x megamaodule. These registersarenotsupportedforthisdevice. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 21 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-3.C674x L1/L2Memory ProtectionRegisters(continued) HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION L1D memory protectionpage attributeregister27 (controlsmemory address0x0184 AE6C L1DMPPA27 0x00F0 5800 -0x00F0 5FFF) L1D memory protectionpage attributeregister28 (controlsmemory address0x0184 AE70 L1DMPPA28 0x00F0 6000 -0x00F0 67FF) L1D memory protectionpage attributeregister29 (controlsmemory address0x0184 AE74 L1DMPPA29 0x00F0 6800 -0x00F0 6FFF) L1D memory protectionpage attributeregister30 (controlsmemory address0x0184 AE78 L1DMPPA30 0x00F0 7000 -0x00F0 77FF) L1D memory protectionpage attributeregister31 (controlsmemory address0x0184 AE7C L1DMPPA31 0x00F0 7800 -0x00F0 7FFF) 0x0184 AE80 – 0x0185 FFFF - Reserved

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2.6 Memory Map Summary

Table2-4.Top LevelMemory Map StartAddress End Address Size ARM Mem DSP Mem Map EDMA Mem PRUSS Mem Master LCDC Map Map Map Peripheral Mem Mem Map Map 0x0000 0000 0x0000 0FFF 4K PRUSS Local AddressSpace 0x0000 1000 0x006F FFFF 0x0070 0000 0x007F FFFF 1024K DSP L2 ROM (1) 0x0080 0000 0x0083 FFFF 256K DSP L2 RAM 0x0084 0000 0x00DF FFFF 0x00E0 0000 0x00E0 7FFF 32K DSP L1P RAM 0x00E0 8000 0x00EF FFFF 0x00F0 0000 0x00F0 7FFF 32K DSP L1D RAM 0x00F0 8000 0x017F FFFF 0x0180 0000 0x0180 FFFF 64K DSP Interrupt Controller 0x0181 0000 0x0181 0FFF 4K DSP Powerdown Controller 0x0181 1000 0x0181 1FFF 4K DSP SecurityID 0x0181 2000 0x0181 2FFF 4K DSP RevisionID 0x0181 3000 0x0181 FFFF 52K - 0x0182 0000 0x0182 FFFF 64K DSP EMC 0x0183 0000 0x0183 FFFF 64K DSP Internal Reserved 0x0184 0000 0x0184 FFFF 64K DSP Memory System 0x0185 0000 0x01BB FFFF 0x01BC 0000 0x01BC 0FFF 4K ARM ETB memory 0x01BC 1000 0x01BC 17FF 2K ARM ETB reg 0x01BC 1800 0x01BC 18FF 256 ARM Ice Crusher 0x01BC 1900 0x01BF FFFF 0x01C0 0000 0x01C0 7FFF 32K EDMA3 CC 0x01C0 8000 0x01C0 83FF 1K EDMA3 TC0 0x01C0 8400 0x01C0 87FF 1K EDMA3 TC1 0x01C0 8800 0x01C0 FFFF 0x01C1 0000 0x01C1 0FFF 4K PSC 0 0x01C1 1000 0x01C1 1FFF 4K PLL Controller0 0x01C1 2000 0x01C1 3FFF 0x01C1 4000 0x01C1 4FFF 4K SYSCFG0 0x01C1 5000 0x01C1 FFFF 0x01C2 0000 0x01C2 0FFF 4K Timer0 0x01C2 1000 0x01C2 1FFF 4K Timer1 0x01C2 2000 0x01C2 2FFF 4K I2C 0 0x01C2 3000 0x01C2 3FFF 4K RTC 0x01C2 4000 0x01C3 FFFF 0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0 0x01C4 1000 0x01C4 1FFF 4K SPI 0 0x01C4 2000 0x01C4 2FFF 4K UART 0 (1) The DSP L2 ROM isused forbootpurposesand cannotbe programmed withapplicationcode Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 23 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-4.Top LevelMemory Map (continued) StartAddress End Address Size ARM Mem DSP Mem Map EDMA Mem PRUSS Mem Master LCDC Map Map Map Peripheral Mem Mem Map Map 0x01C4 3000 0x01CF FFFF 0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control 0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Ctrl 0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data 0x01D0 3000 0x01D0 BFFF 0x01D0 C000 0x01D0 CFFF 4K UART 1 0x01D0 D000 0x01D0 DFFF 4K UART 2 0x01D0 E000 0x01D0 FFFF 0x01D1 0000 0x01D1 07FF 2K McBSP0 0x01D1 0800 0x01D1 0FFF 2K McBSP0 FIFO Ctrl 0x01D1 1000 0x01D1 17FF 2K McBSP1 0x01D1 1800 0x01D1 1FFF 2K McBSP1 FIFO Ctrl 0x01D1 2000 0x01DF FFFF 0x01E0 0000 0x01E0 FFFF 64K USB0 0x01E1 0000 0x01E1 0FFF 4K UHPI 0x01E1 1000 0x01E1 2FFF 0x01E1 3000 0x01E1 3FFF 4K LCD Controller 0x01E1 4000 0x01E1 4FFF 4K Memory ProtectionUnit1 (MPU 1) 0x01E1 5000 0x01E1 5FFF 4K Memory ProtectionUnit2 (MPU 2) 0x01E1 6000 0x01E1 6FFF 4K UPP 0x01E1 7000 0x01E1 7FFF 4K VPIF 0x01E1 8000 0x01E1 9FFF 8K SATA 0x01E1 A000 0x01E1 AFFF 4K PLL Controller1 0x01E1 B000 0x01E1 BFFF 4K MMCSD1 0x01E1 C000 0x01E1 FFFF 0x01E2 0000 0x01E2 1FFF 8K EMAC ControlModule RAM 0x01E2 2000 0x01E2 2FFF 4K EMAC ControlModule Registers 0x01E2 3000 0x01E2 3FFF 4K EMAC ControlRegisters 0x01E2 4000 0x01E2 4FFF 4K EMAC MDIO port 0x01E2 5000 0x01E2 5FFF 4K USB1 0x01E2 6000 0x01E2 6FFF 4K GPIO 0x01E2 7000 0x01E2 7FFF 4K PSC 1 0x01E2 8000 0x01E2 8FFF 4K I2C 1 0x01E2 9000 0x01E2 BFFF 0x01E2 C000 0x01E2 CFFF 4K SYSCFG1 0x01E2 D000 0x01E2 FFFF 0x01E3 0000 0x01E3 7FFF 32K EDMA3 CC1 0x01E3 8000 0x01E3 83FF 1K EDMA3 TC2 0x01E3 8400 0x01EF FFFF 0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0 0x01F0 1000 0x01F0 1FFF 4K HRPWM 0 0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1 0x01F0 3000 0x01F0 3FFF 4K HRPWM 1 0x01F0 4000 0x01F0 5FFF 0x01F0 6000 0x01F0 6FFF 4K ECAP 0 0x01F0 7000 0x01F0 7FFF 4K ECAP 1

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table2-4.Top LevelMemory Map (continued) StartAddress End Address Size ARM Mem DSP Mem Map EDMA Mem PRUSS Mem Master LCDC Map Map Map Peripheral Mem Mem Map Map 0x01F0 8000 0x01F0 8FFF 4K ECAP 2 0x01F0 9000 0x01F0 BFFF 0x01F0 C000 0x01F0 CFFF 4K Timer2 0x01F0 D000 0x01F0 DFFF 4K Timer3 0x01F0 E000 0x01F0 EFFF 4K SPI1 0x01F0 F000 0x01F0 FFFF 0x01F1 0000 0x01F1 0FFF 4K McBSP0 FIFO Data 0x01F1 1000 0x01F1 1FFF 4K McBSP1 FIFO Data 0x01F1 2000 0x116F FFFF 0x1170 0000 0x117F FFFF 1024K DSP L2 ROM (2) 0x1180 0000 0x1183 FFFF 256K DSP L2 RAM 0x1184 0000 0x11DF FFFF 0x11E0 0000 0x11E0 7FFF 32K DSP L1P RAM 0x11E0 8000 0x11EF FFFF 0x11F0 0000 0x11F0 7FFF 32K DSP L1D RAM 0x11F0 8000 0x3FFF FFFF 0x4000 0000 0x5FFF FFFF 512M EMIFA SDRAM data(CS0) 0x6000 0000 0x61FF FFFF 32M EMIFA asyncdata(CS2) 0x6200 0000 0x63FF FFFF 32M EMIFA asyncdata(CS3) 0x6400 0000 0x65FF FFFF 32M EMIFA asyncdata(CS4) 0x6600 0000 0x67FF FFFF 32M EMIFA asyncdata(CS5) 0x6800 0000 0x6800 7FFF 32K EMIFA ControlRegs 0x6800 8000 0x7FFF FFFF 0x8000 0000 0x8001 FFFF 128K Shared RAM 0x8002 0000 0xAFFF FFFF 0xB000 0000 0xB000 7FFF 32K DDR2 ControlRegs 0xB000 8000 0xBFFF FFFF 0xC000 0000 0xDFFF FFFF 512M DDR2 Data 0xE000 0000 0xFFFC FFFF 0xFFFD 0000 0xFFFD FFFF 64K ARM local ROM 0xFFFE 0000 0xFFFE DFFF 0xFFFE E000 0xFFFE FFFF 8K ARM Interrupt Controller 0xFFFF 0000 0xFFFF 1FFF 8K ARM local ARM Local RAM RAM (PRU0 only) 0xFFFF 2000 0xFFFF FFFF (2) The DSP L2 ROM isused forbootpurposesand cannotbe programmed withapplicationcode Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 25 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

W V U T R P N M L K 10987654321 10987654321 DVDD3318_C VP_CLKOUT3/ PRU1_R30[0]/ GP6[1]/ PRU1_R31[1] SA T A_VSS SA T A_RXP VP_CLKOUT2/ MMCSD1_DA T[2]/ PRU1_R30[2]/ GP6[3]/ PRU1_R31[3] SA T A_RXN SA T A_VDD SA T A_REFCLKN SA T A_REGSA T A_REFCLKP SA T A_VDD SA T A_VDD SA T A_VDDRSA T A_VDD DVDD3318_C DDR_A[1 1] VP_DOUT[15]/ LCD_D[15]/ UPP_XD[7]/ GP7[7]/ BOOT[7] DVDD3318_C DVDD18 DDR_DVDD18 DDR_DVDD18 DDR_D[15]DDR_RASDDR_CLKPDDR_CLKNDDR_A[2]DDR_A[10] VSS LCD_AC_ENB_CS/ GP6[0]/ PRU1_R31[28] DDR_A[13] DDR_CAS DDR_A[5] DDR_CKE DDR_BA[0] VSS CVDDRVDD DDR_A[9] DDR_A[1] DDR_WE DDR_D[10] DDR_A[7] DDR_A[0] DDR_D[12] DDR_A[12] DDR_A[3] DDR_CS DDR_A[6] DDR_DQM[1] SA T A_VSS CVDD SA T A_VSS DDR_DVDD18 VP_DOUT[12]/ LCD_D[12]/ UPP_XD[4]/ GP7[4]/ BOOT[4] DDR_VREF DDR_BA[1] DDR_A[8] DDR_A[4] DDR_BA[2] SA T A_VSS W V U T R P N M L K DDR_D[13] VSS VSS VSS VSS DVDD18 VSS VSS VSS VSS NC VSS VSS VSS VSS CVDD CVDD VSS DDR_DVDD18DDR_DVDD18DDR_DVDD18DDR_DVDD18DVDD3318_C VP_DOUT[13]/ LCD_D[13]/ UPP_XD[5]/ GP7[5]/ BOOT[5] VP_DOUT[14]/ LCD_D[14]/ UPP_XD[6]/ GP7[6]/ BOOT[6] DDR_DVDD18 DDR_DVDD18 DDR_DVDD18 VP_DOUT[9]/ LCD_D[9]/ UPP_XD[1]/ GP7[1]/ BOOT[1] VP_DOUT[10]/ LCD_D[10]/ UPP_XD[2]/ GP7[2]/ BOOT[2] VP_DOUT[1 1]/ LCD_D[1 1]/ UPP_XD[3]/ GP7[3]/ BOOT[3] VP_DOUT[6]/ LCD_D[6]/ UPP_XD[14]/ GP7[14]/ PRU1_R31[14] VP_DOUT[7]/ LCD_D[7]/ UPP_XD[15]/ GP7[15]/ PRU1_R31[15] VP_DOUT[8]/ LCD_D[8]/ UPP_XD[0]/ GP7[0]/ BOOT[0] VP_DOUT[3]/ LCD_D[3]/ UPP_XD[1 1]/ GP7[1 1]/ PRU1_R31[1 1] VP_DOUT[4]/ LCD_D[4]/ UPP_XD[12]/ GP7[12]/ PRU1_R31[12] VP_DOUT[5]/ LCD_D[5]/ UPP_XD[13]/ GP7[13]/ PRU1_R31[13] VP_DOUT[0]/ LCD_D[0]/ UPP_XD[8]/ GP7[8]/ PRU1_R31[8] VP_DOUT[1]/ LCD_D[1]/ UPP_XD[9]/ GP7[9]/ PRU1_R31[9] VP_DOUT[2]/ LCD_D[2]/ UPP_XD[10]/ GP7[10]/ PRU1_R31[10] OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com

2.7 Pin Assignments

Extensiveuse ofpinmultiplexingisused toaccommodate thelargestnumber ofperipheralfunctionsin the smallestpossiblepackage. Pin multiplexingis controlledusing a combinationof hardware configurationatdeviceresetand softwareprogrammableregistersettings.

2.7.1 Pin Map (Bottom View)

The followinggraphicsshow thebottomviewoftheGWT package pinassignmentsinfourquadrants(A, B,C, and D).The pinassignmentsforbothpackagesareidentical. Figure2-3.Pin Map (Quad A)

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W V U T R P N M L K 191817161514131211 191817161514131211 USB1_VDDA33 DVDD3318_CCVDD USB_CVDD DVDD3318_C DDR_DQGATE0 DVDD18DDR_DQGATE1 DDR_D[9] DDR_D[8] DDR_D[11] DVDD18 RTC_CVDD RESET USB0_DM USB0_DP VP_DIN[11]/ UHPI_HD[3]/ UPP_D[3]/ PRU0_R30[11]/ PRU0_R31[11] USB0_VDDA33 USB0_VBUS USB1_DM VP_DIN[0]/ UHPI_HD[8]/ UPP_D[8]/ RMII_CRS_DV/ PRU1_R31[29] VP_DIN[1]/ UHPI_HD[9]/ UPP_D[9]/ RMII_MHZ_50 _CLK / PRU0_R31[23] VP_DIN[2]/ UHPI_HD[10]/ UPP_D[10]/ RMII_RXER / PRU0_R31[24] VP_DIN[4]/ UHPI_HD[12]/ UPP_D[12]/ RMII_RXD[1]/ PRU0_R31[26] PRU0_R30[28]/ UHPI_HCNTL1/ UPP_CHA_START/ GP6[10] USB1_DP PLL0_VDDA PRU0_R30[30] / PRU1_R30[11]/ GP6[12] UHPI_HINT USB0_VDDA18 VP_DIN[5]/ UHPI_HD[13]/ UPP_D[13]/ RMII_TXEN/ PRU0_R31[27] DDR_D[1] VP_DIN[7]/ UHPI_HD[15]/ UPP_D[15]/ RMII_TXD[1]/ PRU0_R31[29] OSCVSS DDR_D[2] VP_DIN[6]/ UHPI_HD[14]/ UPP_D[14]/ RMII_TXD[0]/ PRU0_R31[28] VP_DIN[3]/ UHPI_HD[11]/ UPP_D[11]/ RMII_RXD[0]/ PRU0_R31[25] VP_DIN[14]_ HSYNC/ UHPI_HD[6]/ UPP_D[6]/ PRU0_R30[14]/ PRU0_R31[14] EMU1 VP_DIN[8]/ UHPI_HD[0]/ UPP_D[0]/ GP6[5]/ PRU1_R31[0] USB0_VDDA12 TDI NC PRU0_R30[26]/ UHPI_HR / UPP_CHA_WAIT/ GP6[8]/ PRU1_R31[17] W VP_DIN[12]/ UHPI_HD[4]/ UPP_D[4]/ PRU0_R30[12]/ PRU0_R31[12] RESETOUT UHPI_HAS PRU1_R30[14]/ GP6[15] RSV2 RTCK/ GP8[0] OSCOUT DDR_D[0] PRU0_R30[27]/ UHPI_HHWIL/ UPP_CHA _ENABLE/ GP6[9] VP_DIN[13]_ FIELD/ UHPI_HD[5]/ UPP_D[5]/ PRU0_R30[13]/ PRU0_R31[13] TRST OSCIN VP_CLKIN1/ PRU1_R30[9]/ GP6[6]/ PRU1_R31[16] UHPI_HDS1 VP_DIN[15]_ VSYNC/ UHPI_HD[7]/ UPP_D[7]/ PRU0_R30[15]/ PRU0_R31[15] VP_CLKIN0/ PRU1_R30[10]/ GP6[7]/ UPP_2xTXCLK UHPI_HCS VP_DIN[10]/ UHPI_HD[2]/ UPP_D[2]/ PRU0_R30[10]/ PRU0_R31[10] VSS DVDD3318_B PLL0_VSSA TMS PRU0_R30[31]/ PRU1_R30[12] GP6[13] UHPI_HRDY NC PLL1_VSSA PLL1_VDDA USB1_VDDA18 USB0_ID VP_DIN[9]/ UHPI_HD[1]/ UPP_D[1]/ PRU0_R30[9]/ PRU0_R31[9] CLKOUT/ PRU1_R30[13]/ GP6[14] UHPI_HDS2 USB0_DRVVBUS DDR_DQS[0] PRU0_R30[29]/ UHPI_HCNTL0/ UPP_CHA_CLOCK/ GP6[11] W V U T R P N M L K DDR_DQM[0] DDR_D[3] DDR_D[4] DDR_D[6] DDR_ZP DDR_D[5] DDR_D[7] DDR_D[14] DDR_DQS[1] VSS VSS VSS VSS VSS CVDD DVDD3318_C DVDD3318_C DVDD3318_C OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure2-4.Pin Map (Quad B) Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 27 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

H G F E D C B A 191817161514131211 191817161514131211 CVDD EMA_A[8]/ PRU1_R30[16]/ GP5[8] EMA_A[14]/ MMCSD0_DAT[7]/ PRU1_R30[22]/ GP5[14]/ PRU1_R31[22] EMA_A[15]/ MMCSD0_DAT[6]/ PRU1_R30[23]/ GP5[15]/ PRU1_R31[23] EMA_A[10]/ PRU1_R30[18]/ GP5[10]/ PRU1_R31[18] EMA_A[9]/ PRU1_R30[17]/ GP5[9] EMA_A[13]/ PRU0_R30[21]/ PRU1_R30[21] / GP5[13]/ PRU1_R31[21] EMA_A[12]/ PRU1_R30[20]/ GP5[12]/ PRU1_R31[20] EMA_A[16]/ MMCSD0_DAT[5]/ PRU1_R30[24]/ GP4[0] EMA_A[18]/ MMCSD0_DAT[3]/ PRU1_R30[26]/ GP4[2] DVDD3318_B DVDD18 EMA_A[6]/ GP5[6] EMA_A[5]/ GP5[5] EMA_A[2]/ GP5[2] EMA_A[7]/ PRU1_R30[15]/ GP5[7] EMA_A[4]/ GP5[4] SPI0_SIMO/ EPWMSYNCO/ GP8[5]/ MII_CRS SPI0_SCS[5]/ UART0_RXD/ GP8[4]/ MII_RXD[3] SPI1_SCS[1]/ EPWM1A/ PRU0_R30[8]/ GP2[15]/ TM64P2_IN12 SPI0_SCS[4]/ UART0_TXD/ GP8[3]/ MII_RXD[2] SPI0_CLK/ EPWM0A/ GP1[8]/ MII_RXCLK SPI1_SCS[3]/ UART1_RXD/ SATA_LED/ GP1[1] SPI1_SCS[0]/ EPWM1B/ PRU0_R30[7]/ GP2[14]/ TM64P3_IN12 EMA_OE/ GP3[10] SPI1_SCS[4]/ UART2_TXD/ I2C1_SDA/ GP1[2] EMA_A[3]/ GP5[3] DVDD18 RTC_VSS EMA_WAIT[0]/ PRU0_R30[0]/ GP3[8]/ PRU0_R31[0] EMA_RAS/ PRU0_R30[3]/ GP2[5]/ PRU0_R31[3] SPI0_SCS[3] UART0_CTS GP8[2]/ MII_RXD[1]/ SATA_MP_SWITCH SPI0_SCS[0]/ TM64P1_OUT12/ GP1[6]/ MDIO_D/ TM64P1_IN12 SPI0_SOMI/ EPWMSYNCI/ GP8[6]/ MII_RXER SPI0_SCS[2] UART0_RTS GP8[1]/ MII_RXD[0]/ SATA_CP_DET SPI1_SCS[7]/ I2C0_SCL/ TM64P2_OUT12/ GP1[5] SPI1_SIMO/ GP2[10] SPI1_CLK/ GP2[13] EMA_CS[3]/ GP3[14] VSS VSS SPI1_ENA/ GP2[12] RTC_XO EMA_CS[2]/ GP3[15] EMA_WAIT[1]/ PRU0_R30[1]/ GP2[1]/ PRU0_R31[1] EMA_A[20]/ MMCSD0_DAT[1]/ PRU1_R30[28]/ GP4[4] EMA_BA[1]/ GP2[9] SPI0_ENA/ EPWM0B/ PRU0_R30[6]/ MII_RXDV EMA_CS[5]/ GP3[12] SPI1_SCS[5]/ UART2_RXD/ I2C1_SCL/ GP1[3] EMA_A[0]/ GP5[0] EMA_BA[0]/ GP2[8] EMA_A[1]/ GP5[1] DVDD3318_B SPI0_SCS[1]/ TM64P0_OUT12/ GP1[7]/ MDIO_CLK/ TM64P0_IN12 DVDD3318_A SPI1_SCS[6]/ I2C0_SDA/ TM64P3_OUT12/ GP1[4] EMA_CS[0]/ GP2[0] CVDD SPI1_SOMI/ GP2[11] H G F E D C B A J TDOTCK EMU0 RTC_XINMI J SPI1_SCS[2]/ UART1_TXD/ SATA_CP_POD/ GP1[0] EMA_A[11]/ PRU1_R30[19]/ GP5[11]/ PRU1_R31[19] EMA_A[17]/ MMCSD0_DAT[4]/ PRU1_R30[25] GP4[1] DVDD3318_BDVDD3318_B DVDD18 CVDD DVDD3318_A DVDD3318_A RVDDCVDDCVDD VSS CVDD DVDD18 DVDD3318_B OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure2-5.Pin Map (Quad C)

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J H G F E D C B A 10987654321 10987654321 EMA_D[15]/ GP3[7] AXR15/ EPWM0TZ[0]/ ECAP2_APWM2/ GP0[7] ACLKR/ PRU0_R30[20]/ GP0[15]/ PRU0_R31[22] ACLKX/ PRU0_R30[19]/ GP0[14]/ PRU0_R31[21] AHCLKX/ USB_REFCLKIN/ GP0[10]/ PRU0_R31[17] UART1_CTS AFSX/ GP0[12]/ PRU0_R31[19] AFSR/ GP0[13]/ PRU0_R31[20] AXR9/ DX1/ GP0[1] AXR4/ FSR0/ GP1[12]/ MII_COL AXR5/ CLKX0/ GP1[13]/ MII_TXCLK AXR7/ EPWM1TZ[0]/ PRU0_R30[17] GP1[15]/ PRU0_R31[7] AXR10/ DR1/ GP0[2] AXR1/ DX0/ GP1[9]/ MII_TXD[1] AXR3/ FSX0/ GP1[1 1]/ MII_TXD[3] AXR2/ DR0/ GP1[10]/ MII_TXD[2] MMCSD1_DA T[6]/ LCD_MCLK/ PRU1_R30[6]/ GP8[10]/ PRU1_R31[7] RTC_ALARM/ GP0[8]/ UART2_CTS DEEPSLEEP AXR0/ ECAP0_APWM0/ GP8[7]/ MII_TXD[0]/ CLKS0 PRU0_R30[24]/ MMCSD1_CLK/ UPP_CHB_ST ART/ GP8[14]/ PRU1_R31[26] MMCSD1_DA T[4]/ LCD_VSYNC/ PRU1_R30[4]/ GP8[8]/ PRU1_R31[5] SA T A_VSS PRU0_R30[22]/ PRU1_R30[8]/ UPP_CHB_WAIT/ GP8[12]/ PRU1_R31[24] AXR8/ CLKS1/ ECAP1_APWM1/ GP0[0]/ PRU0_R31[8] AXR12/ FSR1/ GP0[4] EMA_D[4]/ GP4[12] AXR14/ CLKR1/ GP0[6] EMA_WEN_DQM[1]/ GP2[2] EMA_D[0]/ GP4[8] EMA_A[19]/ MMCSD0_DA T[2]/ PRU1_R30[27]/ GP4[3] EMA_D[9]/ GP3[1] EMA_A_R / GP3[9] W MMCSD0_CLK/ PRU1_R30[31]/ GP4[7] EMA_D[8]/ GP3[0] EMA_D[13]/ GP3[5] VP_CLKIN2/ MMCSD1_DA T[3]/ PRU1_R30[3]/ GP6[4]/ PRU1_R31[4] VP_CLKIN3/ MMCSD1_DA T[1]/ PRU1_R30[1]/ GP6[2]/ PRU1_R31[2] AMUTE/ GP0[9]/ PRU0_R31[16] PRU0_R30[16]/ UART2_RTS/ DVDD3318_A DVDD3318_A EMA_WE/ GP3[1 1] EMA_D[10]/ GP3[2] EMA_D[3]/ GP4[1 1] EMA_SDCKE/ PRU0_R30[4]/ GP2[6]/ PRU0_R31[4] EMA_D[14]/ GP3[6] EMA_D[7]/ GP4[15] EMA_D[1]/ GP4[9] EMA_A[22]/ MMCSD0_CMD/ PRU1_R30[30]/ GP4[6] EMA_D[2]/ GP4[10] EMA_A[21]/ MMCSD0_DA T[0]/ PRU1_R30[29]/ GP4[5] PRU0_R30[23]/ MMCSD1_CMD/ UPP_CHB_ENABLE/ GP8[13]/ PRU1_R31[25] AHCLKR/ GP0[1 1]/ PRU0_R31[18] PRU0_R30[18]/ UART1_RTS EMA_D[12]/ GP3[4] EMA_WEN_DQM[0]/ GP2[3] EMA_CLK/ PRU0_R30[5]/ GP2[7]/ PRU0_R31[5] AXR6/ CLKR0/ GP1[14]/ MII_TXEN/ PRU0_R31[6] AXR1 1/ FSX1/ GP0[3] EMA_D[6]/ GP4[14] EMA_D[1 1]/ GP3[3] RVDD EMA_D[5]/ GP4[13] MMCSD1_DA T[7]/ LCD_PCLK/ PRU1_R30[7]/ GP8[1 1] MMCSD1_DA T[5]/ LCD_HSYNC/ PRU1_R30[5]/ GP8[9]/ PRU1_R31[6] PRU0_R30[25]/ MMCSD1_DA T[0]/ UPP_CHB_CLOCK/ GP8[15]/ PRU1_R31[27] AXR13/ CLKX1/ GP0[5] J H G F E D C B A EMA_CS[4]/ GP3[13] EMA_CAS/ PRU0_R30[2]/ GP2[4]/ PRU0_R31[2] DVDD3318_B DVDD3318_B DVDD3318_B DVDD3318_B DVDD18 CVDD CVDD DVDD3318_B DVDD18 SA T A_VSS DVDD3318_A VSS VSS CVDD CVDD VSS VSS CVDD SA T A_TXP SA T A_TXN DVDD3318_C CVDD VSS VSS OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure2-6.Pin Map (Quad D)

2.8 Pin MultiplexingControl

Devicelevelpinmultiplexingiscontrolledby registersPINMUX0 -PINMUX19 intheSYSCFG module. For thedevicefamily,pinmultiplexingcan be controlledon a pin-by-pinbasis.Each pinthatismultiplexed withseveraldifferentfunctionshas a corresponding4-bitfieldinone ofthePINMUX registers. Pin multiplexingselectswhich ofseveralperipheralpinfunctionscontrolsthepin'sIO bufferoutput data and outputenable valuesonly.The defaultpinmultiplexingcontrolforalmosteverypinistoselect'none' oftheperipheralfunctionsinwhichcase thepin'sIO bufferisheldtri-stated. Note thattheinputfromeach pinisalwaysroutedtoalloftheperipheralsthatsharethepin;thePINMUX registershave no effecton inputfroma pin. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 29 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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2.9 TerminalFunctions

Table2-5toTable2-31identifytheexternalsignalnames, theassociatedpin/ballnumbers alongwiththe mechanicalpackage designator,thepintype(I,O, IO,OZ, orPWR), whetherthepin/ballhas any internal pullup/pulldownresistors,whetherthepin/ballisconfigurableas an IO inGPIO mode, and a functionalpin description.

2.9.1 Device Reset,NMI and JTAG

Table2-5.Reset,NMI and JTAG TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. RESET RESET K14 I IPU B Deviceresetinput NMI J17 I IPU B Non-MaskableInterrupt RESETOUT /UHPI_HAS /PRU1_R30[14] / T17 O (4) CP[21] C ResetoutputGP6[15] JTAG TMS L16 I IPU B JTAG testmode select TDI M16 I IPU B JTAG testdatainput TDO J18 O IPU B JTAG testdataoutput TCK J15 I IPU B JTAG testclock TRST L17 I IPD B JTAG testreset EMU0 J16 I/O IPU B Emulationpin EMU1 K16 I/O IPU B Emulationpin RTCK /GP80 K17 I/O IPD B General-purposeinput/output (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:Formultiplexedpinswhere functionshave differenttypes(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionfor thatparticularperipheral. (2) IPD = InternalPulldownresistor,IPU = InternalPullupresistor.CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C. (4) Open drainmode forRESETOUT function. (5) GP8[0]isinitiallyconfiguredas a reservedfunctionafterresetand willnotbe ina predictablestate.Thissignalwillonlybe stableafter theGPIO configurationforthispinhas been completed.Usersshouldcarefullyconsiderthesystemimplicationsofthispinbeinginan unknown stateafterreset.

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2.9.2 High-FrequencyOscillatorand PLL

Table2-6.High-FrequencyOscillatorand PLL TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. CLKOUT /UHPI_HDS2 / T18 O CP[22] C PLL ObservationClockPRU1_R30[13] /GP6[14] 1.2-VOSCILLATOR OSCIN L19 I — — Oscillatorinput OSCOUT K19 O — — Oscillatoroutput OSCVSS L18 GND — — Oscillatorground 1.2-VPLL0 PLL0_VDDA L15 PWR — — PLL analogVDD (1.2-Vfilteredsupply) PLL0_VSSA M17 GND — — PLL analogVSS (forfilter) 1.2-VPLL1 PLL1_VDDA N15 PWR — — PLL analogVDD (1.2-Vfilteredsupply) PLL1_VSSA M15 GND — — PLL analogVSS (forfilter) (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:Formultiplexedpinswhere functionshave differenttypes(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionfor thatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 31 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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2.9.3 Real-TimeClock and 32-kHz Oscillator

Table2-7.Real-TimeClock (RTC) and 1.2-V,32-kHz OscillatorTerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. RTC_XI J19 I — — RTC 32-kHzoscillatorinput RTC_XO H19 O — — RTC 32-kHzoscillatoroutput RTC_ALARM /UART2_CTS /GP0[8]/DEEPSLEEP F4 O CP[0] A RTC Alarm RTC module corepowerRTC_CVDD L14 PWR — — (isolatedfromchipCV DD ) RTC_V ss H18 GND — — Oscillatorground (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:Formultiplexedpinswhere functionshave differenttypes(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionfor thatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C.

2.9.4 DEEPSLEEP Power Control

Table2-8.DEEPSLEEP Power ControlTerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. RTC_ALARM /UART2_CTS /GP0[8]/DEEPSLEEP F4 I CP[0] A DEEPSLEEP power controloutput (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:Formultiplexedpinswhere functionshave differenttypes(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionfor thatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C.

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2.9.5 ExternalMemory InterfaceA (EMIFA)

Table2-9.ExternalMemory InterfaceA (EMIFA) TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. EMA_D[15] /GP3[7] E6 I/O CP[17] B EMA_D[14] /GP3[6] C7 I/O CP[17] B EMA_D[13] /GP3[5] B6 I/O CP[17] B EMA_D[12] /GP3[4] A6 I/O CP[17] B EMA_D[11] /GP3[3] D6 I/O CP[17] B EMA_D[10] /GP3[2] A7 I/O CP[17] B EMA_D[9] /GP3[1] D9 I/O CP[17] B EMA_D[8] /GP3[0] E10 I/O CP[17] B EMIFA databus EMA_D[7] /GP4[15] D7 I/O CP[17] B EMA_D[6] /GP4[14] C6 I/O CP[17] B EMA_D[5] /GP4[13] E7 I/O CP[17] B EMA_D[4] /GP4[12] B5 I/O CP[17] B EMA_D[3] /GP4[11] E8 I/O CP[17] B EMA_D[2] /GP4[10] B8 I/O CP[17] B EMA_D[1] /GP4[9] A8 I/O CP[17] B EMA_D[0] /GP4[8] C9 I/O CP[17] B EMA_A[22] /MMCSD0_CMD / A10 O CP[18] BPRU1_R30[30] /GP4[6] EMA_A[21] /MMCSD0_DAT[0] / B10 O CP[18] BPRU1_R30[29] /GP4[5] EMA_A[20] /MMCSD0_DAT[1] / A11 O CP[18] BPRU1_R30[28] /GP4[4] EMA_A[19] /MMCSD0_DAT[2] / C10 O CP[18] BPRU1_R30[27] /GP4[3] EMA_A[18] /MMCSD0_DAT[3] / E11 O CP[18] BPRU1_R30[26] /GP4[2] EMA_A[17] /MMCSD0_DAT[4] / B11 O CP[18] B EMIFA addressbusPRU1_R30[25] /GP4[1] EMA_A[16] /MMCSD0_DAT[5] / E12 O CP[18] BPRU1_R30[24] /GP4[0] EMA_A[15] /MMCSD0_DAT[6] / C11 O CP[19] BPRU1_R30[23] /GP5[15]/PRU1_R31[23] EMA_A[14] /MMCSD0_DAT[7] / A12 O CP[19] BPRU1_R30[22] /GP5[14]/PRU1_R31[22] EMA_A[13] /PRU0_R30[21] /PRU1_R30[21] D11 O CP[19] B/GP5[13]/PRU1_R31[21] EMA_A[12] /PRU1_R30[20] /GP5[12]/ D13 O CP[19] BPRU1_R31[20] (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 33 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-9.ExternalMemory InterfaceA (EMIFA) TerminalFunctions(continued) SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. EMA_A[11] /PRU1_R30[19] /GP5[11]/ B12 O CP[19] BPRU1_R31[19] EMA_A[10] /PRU1_R30[18] /GP5[10]/ C12 O CP[19] BPRU1_R31[18] EMA_A[9] /PRU1_R30[17] /GP5[9] D12 O CP[19] B EMA_A[8] /PRU1_R30[16] /GP5[8] A13 O CP[19] B EMA_A[7] /PRU1_R30[15] /GP5[7] B13 O CP[20] B EMIFA addressbusEMA_A[6] /GP5[6] E13 O CP[20] B EMA_A[5] /GP5[5] C13 O CP[20] B EMA_A[4] /GP5[4] A14 O CP[20] B EMA_A[3] /GP5[3] D14 O CP[20] B EMA_A[2] /GP5[2] B14 O CP[20] B EMA_A[1] /GP5[1] D15 O CP[20] B EMA_A[0] /GP5[0] C14 O CP[20] B EMA_BA[0] /GP2[8] C15 O CP[16] B EMIFA bank address EMA_BA[1] /GP2[9] A15 O CP[16] B EMA_CLK /PRU0_R30[5] /GP2[7]/ B7 O CP[16] B EMIFA clockPRU0_R31[5] EMA_SDCKE /PRU0_R30[4] /GP2[6]/ D8 O CP[16] B EMIFA SDRAM clockenablePRU0_R31[4] EMA_RAS /PRU0_R30[3] /GP2[5]/ A16 O CP[16] B EMIFA SDRAM row addressstrobePRU0_R31[3] EMA_CAS /PRU0_R30[2] /GP2[4]/ A9 O CP[16] B EMIFA SDRAM column addressstrobePRU0_R31[2] EMA_CS[0] /GP2[0] A18 O CP[16] B EMIFA SDRAM ChipSelect EMA_CS[2] /GP3[15] B17 O CP[16] B EMA_CS[3] /GP3[14] A17 O CP[16] B EMIFA Async chipselect EMA_CS[4] /GP3[13] F9 O CP[16] B EMA_CS[5] /GP3[12] B16 O CP[16] B EMA_A_R W /GP3[9] D10 O CP[16] B EMIFA Async Read/Writecontrol EMA_WE /GP3[11] B9 O CP[16] B EMIFA SDRAM writeenable EMIFA writeenable/datamask forEMA_WEN_DQM[1] /GP2[2] A5 O CP[16] B EMA_D[15:8] EMA_WEN_DQM[0] /GP2[3] C8 O CP[16] B EMIFA writeenable/datamask forEMA_D[7:0] EMA_OE /GP3[10] B15 O CP[16] B EMIFA outputenable EMA_WAIT[0] /PRU0_R30[0] /GP3[8]/ B18 I CP[16] BPRU0_R31[0] EMIFA waitinput/interrupt EMA_WAIT[1] /PRU0_R30[1] /GP2[1]/ B19 I CP[16] BPRU0_R31[1]

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2.9.6 DDR2 Controller(DDR2)

Table2-10.DDR2 Controller(DDR2) TerminalFunctions SIGNAL TYPE (1) PULL (2) DESCRIPTION NAME NO. DDR_D[15] W10 I/O IPD DDR_D[14] U11 I/O IPD DDR_D[13] V10 I/O IPD DDR_D[12] U10 I/O IPD DDR_D[11] T12 I/O IPD DDR_D[10] T10 I/O IPD DDR_D[9] T11 I/O IPD DDR_D[8] T13 I/O IPD DDR2 SDRAM databus DDR_D[7] W11 I/O IPD DDR_D[6] W12 I/O IPD DDR_D[5] V12 I/O IPD DDR_D[4] V13 I/O IPD DDR_D[3] U13 I/O IPD DDR_D[2] V14 I/O IPD DDR_D[1] U14 I/O IPD DDR_D[0] U15 I/O IPD DDR_A[13] T5 O IPD DDR_A[12] V4 O IPD DDR_A[11] T4 O IPD DDR_A[10] W4 O IPD DDR_A[9] T6 O IPD DDR_A[8] U4 O IPD DDR_A[7] U6 O IPD DDR2 row/columnaddress DDR_A[6] W5 O IPD DDR_A[5] V5 O IPD DDR_A[4] U5 O IPD DDR_A[3] V6 O IPD DDR_A[2] W6 O IPD DDR_A[1] T7 O IPD DDR_A[0] U7 O IPD DDR_CLKP W8 O IPD DDR2 clock(positive) DDR_CLKN W7 O IPD DDR2 clock(negative) DDR_CKE V7 O IPD DDR2 clockenable DDR_WE T8 O IPD DDR2 writeenable DDR_RAS W9 O IPD DDR2 row addressstrobe DDR_CAS U9 O IPD DDR2 column addressstrobe DDR_CS V9 O IPD DDR2 chipselect DDR_DQM[0] W13 O IPD DDR2 datamask outputs DDR_DQM[1] R10 O IPD (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 35 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-10.DDR2 Controller(DDR2) TerminalFunctions(continued) SIGNAL TYPE (1) PULL (2) DESCRIPTION NAME NO. DDR_DQS[0] T14 I/O IPD DDR2 datastrobeinputs/outputs DDR_DQS[1] V11 I/O IPD DDR_BA[2] U8 O IPD DDR_BA[1] T9 O IPD DDR2 SDRAM bank address DDR_BA[0] V8 O IPD DDR2 loopbacksignalforexternalDQS gating. DDR_DQGATE0 R11 O IPD Route toDDR and back toDDR_DQGATE1 with same constraintsas used forDDR clockand data. DDR2 loopbacksignalforexternalDQS gating. DDR_DQGATE1 R12 I IPD Route toDDR and back toDDR_DQGATE0 with same constraintsas used forDDR clockand data. DDR2 referenceoutputfordrivestrengthcalibration DDR_ZP U12 O — ofN and P channeloutputs.Tietogroundvia50 ohm resistor@ 5% tolerance. DDR voltageinputfortheDDR2/mDDR I/Obuffers. DDR_VREF R6 I — Note even inthecase ofmDDR an externalresistor dividerconnectedtothispinisnecessary. N6, N9, N10, P7,P8,P9,DDR_DVDD18 PWR — DDR PHY 1.8Vpower supplypinsP10,R7, R8,

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2.9.7 SerialPeripheralInterfaceModules (SPI)

Table2-11.SerialPeripheralInterface(SPI)TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. SPI0 SPI0_CLK /EPWM0A /GP1[8]/MII_RXCLK D19 I/O CP[7] A SPI0 clock SPI0_ENA /EPWM0B /PRU0_R30[6] /MII_RXDV C17 I/O CP[7] A SPI0 enable SPI0_SCS[0] /TM64P1_OUT12 /GP1[6]/MDIO_D /TM64P1_IN12 D17 I/O CP[10] A SPI0_SCS[1] /TM64P0_OUT12 /GP1[7]/MDIO_CLK / E16 I/O CP[10] ATM64P0_IN12 SPI0_SCS[2] /UART0_RTS /GP8[1]/MII_RXD[0]/SATA_CP_DET D16 I/O CP[9] A SPI0 chipselects SPI0_SCS[3] /UART0_CTS /GP8[2]/MII_RXD[1]/ E17 I/O CP[9] ASATA_MP_SWITCH SPI0_SCS[4] /UART0_TXD /GP8[3]/MII_RXD[2] D18 I/O CP[8] A SPI0_SCS[5] /UART0_RXD /GP8[4]/MII_RXD[3] C19 I/O CP[8] A SPI0 dataslave-in-SPI0_SIMO /EPWMSYNCO /GP8[5]/MII_CRS C18 I/O CP[7] A master-out SPI0 dataslave-out-SPI0_SOMI /EPWMSYNCI /GP8[6]/MII_RXER C16 I/O CP[7] A master-in SPI1 SPI1_CLK /GP2[13] G19 I/O CP[15] A SPI1 clock SPI1_ENA /GP2[12] H16 I/O CP[15] A SPI1 enable SPI1_SCS[0] /EPWM1B /PRU0_R30[7] /GP2[14]/TM64P3_IN12 E19 I/O CP[14] A SPI1_SCS[1] /EPWM1A /PRU0_R30[8] /GP2[15]/TM64P2_IN12 F18 I/O CP[14] A SPI1_SCS[2] /UART1_TXD /SATA_CP_POD /GP1[0] F19 I/O CP[13] A SPI1_SCS[3] /UART1_RXD /SATA_LED /GP1[1] E18 I/O CP[13] A SPI1 chipselects SPI1_SCS[4] /UART2_TXD /I2C1_SDA /GP1[2] F16 I/O CP[12] A SPI1_SCS[5] /UART2_RXD /I2C1_SCL /GP1[3] F17 I/O CP[12] A SPI1_SCS[6] /I2C0_SDA /TM64P3_OUT12 /GP1[4] G18 I/O CP[11] A SPI1_SCS[7] /I2C0_SCL /TM64P2_OUT12 /GP1[5] G16 I/O CP[11] A SPI1 dataslave-in-SPI1_SIMO /GP2[10] G17 I/O CP[15] A master-out SPI1 dataslave-out-SPI1_SOMI /GP2[11] H17 I/O CP[15] A master-in (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 37 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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2.9.8 Programmable Real-TimeUnit(PRU)

Table2-12.Programmable Real-TimeUnit(PRU) TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. PRU0_R30[31] /UHPI_HRDY /PRU1_R30[12] /GP6[13] R17 O CP[23] C PRU0_R30[30] /UHPI_HINT /PRU1_R30[11] /GP6[12] R16 O CP[23] C PRU0_R30[29] /UHPI_HCNTL0 /UPP_CHA_CLOCK /GP6[11] U17 O CP[24] C PRU0_R30[28] /UHPI_HCNTL1 /UPP_CHA_START /GP6[10] W15 O CP[24] C PRU0_R30[27] /UHPI_HHWIL /UPP_CHA_ENABLE /GP6[9] U16 O CP[24] C PRU0_R30[26] /UHPI_HR W /UPP_CHA_WAIT /GP6[8]/ T15 O CP[24] CPRU1_R31[17] PRU0_R30[25] /MMCSD1_DAT[0] /UPP_CHB_CLOCK /GP8[15]/ G1 O CP30] CPRU1_R31[27] PRU0_R30[24] /MMCSD1_CLK /UPP_CHB_START /GP8[14]/ PRU0 OutputG2 O CP[30] CPRU1_R31[26] Signals PRU0_R30[23] /MMCSD1_CMD /UPP_CHB_ENABLE /GP8[13]/ J4 O CP[30] CPRU1_R31[25] PRU0_R30[22] /PRU1_R30[8] /UPP_CHB_WAIT /GP8[12]/ G3 O CP[30] CPRU1_R31[24] EMA_A[13] /PRU0_R30[21] /PRU1_R30[21] /GP5[13]/PRU1_R31[21] D11 O CP[19] B ACLKR /PRU0_R30[20] /GP0[15]/PRU0_R31[22] A1 O CP[0] A ACLKX /PRU0_R30[19] /GP0[14]/PRU0_R31[21] B1 O CP[0] A AHCLKR /PRU0_R30[18] /UART1_RTS /GP0[11]/PRU0_R31[18] A2 O CP[0] A AXR7 /EPWM1TZ[0] /PRU0_R30[17] /GP1[15]/PRU0_R31[7] D2 O CP[4] A (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table2-12.Programmable Real-TimeUnit(PRU) TerminalFunctions(continued) SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. AMUTE /PRU0_R30[16] /UART2_RTS /GP0[9]/PRU0_R31[16] D5 O CP[0] A VP_DIN[15]_VSYNC /UHPI_HD[7] /UPP_D[7] /PRU0_R30[15] / V18 O CP[27] CPRU0_R31[15] VP_DIN[14]_HSYNC /UHPI_HD[6] /UPP_D[6] /PRU0_R30[14] / V19 O CP[27] CPRU0_R31[14] VP_DIN[13]_FIELD/UHPI_HD[5] /UPP_D[5] /PRU0_R30[13] / U19 O CP[27] CPRU0_R31[13] VP_DIN[12]/UHPI_HD[4] /UPP_D[4] /PRU0_R30[12] /PRU0_R31[12] T16 O CP[27] C VP_DIN[11]/UHPI_HD[3] /UPP_D[3] /PRU0_R30[11] /PRU0_R31[11] R18 O CP[27] C VP_DIN[10]/UHPI_HD[2] /UPP_D[2] /PRU0_R30[10] /PRU0_R31[10] R19 O CP[27] C PRU0 OutputVP_DIN[9]/UHPI_HD[1] /UPP_D[1] /PRU0_R30[9] /PRU0_R31[9] R15 O CP[27] C Signals SPI1_SCS[1]/EPWM1A /PRU0_R30[8] /GP2[15]/TM64P2_IN12 F18 O CP[14] A SPI1_SCS[0]/EPWM1B /PRU0_R30[7] /GP2[14]/TM64P3_IN12 E19 O CP[14] A SPI0_ENA /EPWM0B /PRU0_R30[6] /MII_RXDV C17 O CP[7] A EMA_CLK /PRU0_R30[5] /GP2[7]/PRU0_R31[5] B7 O CP[16] B EMA_SDCKE /PRU0_R30[4] /GP2[6]/PRU0_R31[4] D8 O CP[16] B EMA_RAS /PRU0_R30[3] /GP2[5]/PRU0_R31[3] A16 O CP[16] B EMA_CAS /PRU0_R30[2] /GP2[4]/PRU0_R31[2] A9 O CP[16] B EMA_WAIT[1] /PRU0_R30[1] /GP2[1]/PRU0_R31[1] B19 O CP[16] B EMA_WAIT[0] /PRU0_R30[0] /GP3[8]/PRU0_R31[0] B18 O CP[16] B Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 39 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-12.Programmable Real-TimeUnit(PRU) TerminalFunctions(continued) SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. VP_DIN[7]/UHPI_HD[15] /UPP_D[15] /RMII_TXD[1]/PRU0_R31[29] U18 I CP[26] C VP_DIN[6]/UHPI_HD[14] /UPP_D[14] /RMII_TXD[0]/PRU0_R31[28] V16 I CP[26] C VP_DIN[5]/UHPI_HD[13] /UPP_D[13] /RMII_TXEN /PRU0_R31[27] R14 I CP[26] C VP_DIN[4]/UHPI_HD[11] /UPP_D[12] /RMII_RXD[1]/PRU0_R31[26] W16 I CP[26] C VP_DIN[3]/UHPI_HD[11] /UPP_D[11] /RMII_RXD[0]/PRU0_R31[25] V17 I CP[26] C VP_DIN[2]/UHPI_HD[10] /UPP_D[10] /RMII_RXER /PRU0_R31[24] W17 I CP[26] C VP_DIN[1]/UHPI_HD[9] /UPP_D[9] /RMII_MHZ_50_CLK / W18 I CP[26] CPRU0_R31[23] ACLKR /PRU0_R30[20] /GP0[15]/PRU0_R31[22] A1 I CP[0] A ACLKX /PRU0_R30[19] /GP0[14]/PRU0_R31[21] B1 I CP[0] A AFSR /GP0[13]/PRU0_R31[20] C2 I CP[0] A AFSX /GP0[12]/PRU0_R31[19] B2 I CP[0] A AHCLKR /PRU0_R30[18] /UART1_RTS /GP0[11]/PRU0_R31[18] A2 I CP[0] A AHCLKX /USB_REFCLKIN /UART1_CTS /GP0[10]/PRU0_R31[17] A3 I CP[0] A AMUTE /PRU0_R30[16] /UART2_RTS /GP0[9]/PRU0_R31[16] D5 I CP[0] A VP_DIN[15]_VSYNC /UHPI_HD[7] /UPP_D[7] /PRU0_R30[15] / V18 I CP[27] CPRU0_R31[15] PRU0 Input SignalsVP_DIN[14]_HSYNC /UHPI_HD[6] /UPP_D[6] /PRU0_R30[14] / V19 I CP[27] CPRU0_R31[14] VP_DIN[13]_FIELD/UHPI_HD[5] /UPP_D[5] /PRU0_R30[13] / U19 I CP[27] CPRU0_R31[13] VP_DIN[12]/UHPI_HD[4] /UPP_D[4] /PRU0_R30[12] /PRU0_R31[12] T16 I CP[27] C VP_DIN[11]/UHPI_HD[3] /UPP_D[3] /PRU0_R30[11] /PRU0_R31[11] R18 I CP[27] C VP_DIN[10]/UHPI_HD[2] /UPP_D[2] /PRU0_R30[10] /PRU0_R31[10] R19 I CP[27] C VP_DIN[9]/UHPI_HD[1] /UPP_D[1] /PRU0_R30[9] /PRU0_R31[9] R15 I CP[27] C AXR8 /CLKS1 /ECAP1_APWM1 /GP0[0]/PRU0_R31[8] E4 I CP[3] A AXR7 /EPWM1TZ[0] /PRU0_R30[17] /GP1[15]/PRU0_R31[7] D2 I CP[4] A AXR6 /CLKR0 /GP1[14]/MII_TXEN /PRU0_R31[6] C1 I CP[5] A EMA_CLK /PRU0_R30[5] /GP2[7]/PRU0_R31[5] B7 I CP[16] B EMA_SDCKE /PRU0_R30[4] /GP2[6]/PRU0_R31[4] D8 I CP[16] B EMA_RAS /PRU0_R30[3] /GP2[5]/PRU0_R31[3] A16 I CP[16] B EMA_CAS /PRU0_R30[2] /GP2[4]/PRU0_R31[2] A9 I CP[16] B EMA_WAIT[1] /PRU0_R30[1] /GP2[1]/PRU0_R31[1] B19 I CP[16] B EMA_WAIT[0] /PRU0_R30[0] /GP3[8]/PRU0_R31[0] B18 I CP[16] B

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table2-12.Programmable Real-TimeUnit(PRU) TerminalFunctions(continued) SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. MMCSD0_CLK /PRU1_R30[31] /GP4[7] E9 O CP[18] B EMA_A[22] /MMCSD0_CMD /PRU1_R30[30] /GP4[6] A10 O CP[18] B EMA_A[21] /MMCSD0_DAT[0] /PRU1_R30[29] /GP4[5] B10 O CP[18] B EMA_A[20] /MMCSD0_DAT[1] /PRU1_R30[28] /GP4[4] A11 O CP[18] B EMA_A[19] /MMCSD0_DAT[2] /PRU1_R30[27] /GP4[3] C10 O CP[18] B EMA_A[18] /MMCSD0_DAT[3] /PRU1_R30[26] /GP4[2] E11 O CP[18] B EMA_A[17] /MMCSD0_DAT[4] /PRU1_R30[25] /GP4[1] B11 O CP[18] B EMA_A[16] /MMCSD0_DAT[5] /PRU1_R30[24] /GP4[0] E12 O CP[18] B EMA_A[15] /MMCSD0_DAT[6] /PRU1_R30[23] /GP5[15]/ C11 O CP[19] BPRU1_R31[23] EMA_A[14] /MMCSD0_DAT[7] /PRU1_R30[22] /GP5[14]/ A12 O CP[19] BPRU1_R31[22] EMA_A[13] /PRU0_R30[21] /PRU1_R30[21] /GP5[13]/PRU1_R31[21] D11 O CP[19] B EMA_A[12] /PRU1_R30[20] /GP5[12]/PRU1_R31[20] D13 O CP[19] B EMA_A[11] /PRU1_R30[19] /GP5[11]/PRU1_R31[19] B12 O CP[19] B EMA_A[10] /PRU1_R30[18] /GP5[10]/PRU1_R31[18] C12 O CP[19] B EMA_A[9] /PRU1_R30[17] /GP5[9] D12 O CP[19] B EMA_A[8] /PRU1_R30[16] /GP5[8] A13 O CP[19] B PRU1 Output SignalsEMA_A[7] /PRU1_R30[15] /GP5[7] B13 O CP[20] B RESETOUT /UHPI_HAS /PRU1_R30[14] /GP6[15] T17 O CP[21] C CLKOUT /UHPI_HDS2 /PRU1_R30[13] /GP6[14] T18 O CP[22] C PRU0_R30[31] /UHPI_HRDY /PRU1_R30[12] /GP6[13] R17 O CP[23] C PRU0_R30[30] /UHPI_HINT /PRU1_R30[11] /GP6[12] R16 O CP[23] C VP_CLKIN0 /UHPI_HCS /PRU1_R30[10] /GP6[7]/UPP_2xTXCLK W14 O CP[25] C VP_CLKIN1 /UHPI_HDS1 /PRU1_R30[9] /GP6[6]/PRU1_R31[16] V15 O CP[25] C PRU0_R30[22] /PRU1_R30[8] /UPP_CHB_WAIT /GP8[12]/ G3 O CP[30] CPRU1_R31[24] MMCSD1_DAT[7] /LCD_PCLK /PRU1_R30[7] /GP8[11] F1 O CP[31] C MMCSD1_DAT[6] /LCD_MCLK /PRU1_R30[6] /GP8[10]/PRU1_R31[7] F2 O CP[31] C MMCSD1_DAT[5] /LCD_HSYNC /PRU1_R30[5] /GP8[9]/PRU1_R31[6] H4 O CP[31] C MMCSD1_DAT[4] /LCD_VSYNC /PRU1_R30[4] /GP8[8]/PRU1_R31[5] G4 O CP[31] C VP_CLKIN2 /MMCSD1_DAT[3] /PRU1_R30[3] /GP6[4]/PRU1_R31[4] H3 O CP[30] C VP_CLKOUT2 /MMCSD1_DAT[2] /PRU1_R30[2] /GP6[3]/ K3 O CP[30] CPRU1_R31[3] VP_CLKIN3 /MMCSD1_DAT[1] /PRU1_R30[1] /GP6[2]/PRU1_R31[2] J3 O CP[30] C VP_CLKOUT3 /PRU1_R30[0] /GP6[1]/PRU1_R31[1] K4 O CP[30] C Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 41 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-12.Programmable Real-TimeUnit(PRU) TerminalFunctions(continued) SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. VP_DIN[0]/UHPI_HD[8] /UPP_D[8] /RMII_CRS_DV /PRU1_R31[29] W19 I CP[26] C LCD_AC_ENB_CS /GP6[0]/PRU1_R31[28] R5 I CP[31] C PRU0_R30[25] /MMCSD1_DAT[0] /UPP_CHB_CLOCK /GP8[15]/ G1 I CP[30] CPRU1_R31[27] PRU0_R30[24] /MMCSD1_CLK /UPP_CHB_START /GP8[14]/ G2 I CP[30] CPRU1_R31[26] PRU0_R30[23] /MMCSD1_CMD /UPP_CHB_ENABLE /GP8[13]/ J4 I CP[30] CPRU1_R31[25] PRU0_R30[22] /PRU1_R30[8] /UPP_CHB_WAIT /GP8[12]/ G3 I CP[30] CPRU1_R31[24] EMA_A[15]/MMCSD0_DAT[6]/PRU1_R30[23]/GP5[15]/PRU1_R31[23] C11 I CP[19] B EMA_A[14]/MMCSD0_DAT[7]/PRU1_R30[22]/GP5[14]/PRU1_R31[22] A12 I CP[19] B EMA_A[13]/PRU0_R30[21]/PRU1_R30[21]/GP5[13]/PRU1_R31[21] D11 I CP[19] B EMA_A[12]/PRU1_R30[20]/GP5[12]/PRU1_R31[20] D13 I CP[19] B EMA_A[11]/PRU1_R30[19]/GP5[11]/PRU1_R31[19] B12 I CP[19] B EMA_A[10]/PRU1_R30[18]/GP5[10]/PRU1_R31[18] C12 I CP[19] B PRU0_R30[26] /UHPI_HR W /UPP_CHA_WAIT /GP6[8]/ T15 I CP[24] CPRU1_R31[17] PRU1 InputVP_CLKIN1 /UHPI_HDS1 /PRU1_R30[9] /GP6[6]/PRU1_R31[16] V15 I CP[25] C Signals VP_DOUT[7] /LCD_D[7] /UPP_XD[15] /GP7[15]/PRU1_R31[15] U2 I CP[28] C VP_DOUT[6] /LCD_D[6] /UPP_XD[14] /GP7[14]/PRU1_R31[14] U1 I CP[28] C VP_DOUT[5] /LCD_D[5] /UPP_XD[13] /GP7[13]/PRU1_R31[13] V3 I CP[28] C VP_DOUT[4] /LCD_D[4] /UPP_XD[12] /GP7[12]/PRU1_R31[12] V2 I CP[28] C VP_DOUT[3] /LCD_D[3] /UPP_XD[11] /GP7[11]/PRU1_R31[11] V1 I CP[28] C VP_DOUT[2] /LCD_D[2] /UPP_XD[10] /GP7[10]/PRU1_R31[10] W3 I CP[28] C VP_DOUT[1] /LCD_D[1] /UPP_XD[9] /GP7[9]/PRU1_R31[9] W2 I CP[28] C VP_DOUT[0] /LCD_D[0] /UPP_XD[8] /GP7[8]/PRU1_R31[8] W1 I CP[28] C MMCSD1_DAT[6] /LCD_MCLK /PRU1_R30[6] /GP8[10]/PRU1_R31[7] F2 I CP[31] C MMCSD1_DAT[5] /LCD_HSYNC /PRU1_R30[5] /GP8[9]/PRU1_R31[6] H4 I CP[31] C MMCSD1_DAT[4] /LCD_VSYNC /PRU1_R30[4] /GP8[8]/PRU1_R31[5] G4 I CP[31] C VP_CLKIN2 /MMCSD1_DAT[3] /PRU1_R30[3] /GP6[4]/PRU1_R31[4] H3 I CP[30] C VP_CLKOUT2 /MMCSD1_DAT[2] /PRU1_R30[2] /GP6[3]/ K3 I CP[30] CPRU1_R31[3] VP_CLKIN3 /MMCSD1_DAT[1] /PRU1_R30[1] /GP6[2]/PRU1_R31[2] J3 I CP[30] C VP_CLKOUT3 /PRU1_R30[0] /GP6[1]/PRU1_R31[1] K4 I CP[30] C VP_DIN[8]/UHPI_HD[0] /UPP_D[0] /GP6[5]/PRU1_R31[0] P17 I CP[27] C

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2.9.9 Enhanced Capture/AuxiliaryPWM Modules (eCAP0)

The eCAP Module pinsfunctionas eitherinputcapturesorauxiliaryPWM 32-bitoutputs,dependingupon how theeCAP module isprogrammed. Table2-13.Enhanced Capture Module (eCAP) TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. eCAP0 enhanced capture0 inputorAXR0 /ECAP0_APWM0 /GP8[7]/MII_TXD[0]/CLKS0 F3 I/O CP[6] A auxiliaryPWM 0 output eCAP1 enhanced capture1 inputorAXR8 /CLKS1 /ECAP1_APWM1 /GP0[0]/PRU0_R31[8] E4 I/O CP[3] A auxiliaryPWM 1 output eCAP2 enhanced capture2 inputorAXR15 /EPWM0TZ[0] /ECAP2_APWM2 /GP0[7] A4 I/O CP[1] A auxiliaryPWM 2 output (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 43 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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2.9.10 Enhanced Pulse Width Modulators(eHRPWM)

Table2-14.Enhanced Pulse Width Modulator(eHRPWM) TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. eHRPWM0 eHRPWM0 A outputSPI0_CLK /EPWM0A /GP1[8]/MII_RXCLK D19 I/O CP[7] A (withhigh-resolution) SPI0_ENA /EPWM0B /PRU0_R30[6] /MII_RXDV C17 I/O CP[7] A eHRPWM0 B output AXR15 /EPWM0TZ[0] /ECAP2_APWM2 /GP0[7] A4 I CP[1] A eHRPWM0 tripzone input SPI0_SOMI /EPWMSYNCI /GP8[6]/MII_RXER C16 I CP[7] A eHRPWM0 syncinput SPI0_SIMO /EPWMSYNCO /GP8[5]/MII_CRS C18 I/O CP[7] A eHRPWM0 syncoutput eHRPWM1 SPI1_SCS[1]/EPWM1A /PRU0_R30[8] /GP2[15]/ eHRPWM1 A outputF18 I/O CP[14] ATM64P2_IN12 (withhigh-resolution) SPI1_SCS[0]/EPWM1B /PRU0_R30[7] /GP2[14]/ E19 I/O CP[14] A eHRPWM1 B outputTM64P3_IN12 AXR7 /EPWM1TZ[0] /PRU0_R30[17] /GP1[15]/ D2 I CP[4] A eHRPWM1 tripzone inputPRU0_R31[7] (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C.

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2.9.11 Boot

Table2-15.Boot Mode SelectionTerminalFunctions(1) SIGNAL POWERTYPE (2) PULL (3) DESCRIPTIONGROUP (4) NAME NO. VP_DOUT[15] /LCD_D[15] /UPP_XD[7] /GP7[7]/BOOT[7] P4 I CP[29] C VP_DOUT[14] /LCD_D[14] /UPP_XD[6] /GP7[6]/BOOT[6] R3 I CP[29] C VP_DOUT[13] /LCD_D[13] /UPP_XD[5] /GP7[5]/BOOT[5] R2 I CP[29] C VP_DOUT[12] /LCD_D[12] /UPP_XD[4] /GP7[4]/BOOT[4] R1 I CP[29] C BootMode SelectionPins VP_DOUT[11] /LCD_D[11] /UPP_XD[3] /GP7[3]/BOOT[3] T3 I CP[29] C VP_DOUT[10] /LCD_D[10] /UPP_XD[2] /GP7[2]/BOOT[2] T2 I CP[29] C VP_DOUT[9] /LCD_D[9] /UPP_XD[1] /GP7[1]/BOOT[1] T1 I CP[29] C VP_DOUT[8] /LCD_D[8] /UPP_XD[0] /GP7[0]/BOOT[0] U3 I CP[29] C (1) Bootdecodingisdefinedinthebootloaderapplicationreport. (2) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (3) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (4) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 45 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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2.9.12 UniversalAsynchronous Receiver/Transmitters(UART0 ,UART1, UART2)

Table2-16.UniversalAsynchronous Receiver/Transmitter(UART) TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. UART0 SPI0_SCS[5]/UART0_RXD /GP8[4]/MII_RXD[3] C19 I CP[8] A UART0 receivedata SPI0_SCS[4]/UART0_TXD /GP8[3]/MII_RXD[2] D18 O CP[8] A UART0 transmitdata SPI0_SCS[2]/UART0_RTS /GP8[1]/MII_RXD[0]/ D16 O CP[9] A UART0 ready-to-sendoutputSATA_CP_DET SPI0_SCS[3]/UART0_CTS /GP8[2]/MII_RXD[1]/ E17 I CP[9] A UART0 clear-to-sendinputSATA_MP_SWITCH UART1 SPI1_SCS[3]/UART1_RXD /SATA_LED /GP1[1] E18 I CP[13] A UART1 receivedata SPI1_SCS[2]/UART1_TXD /SATA_CP_POD /GP1[0] F19 O CP[13] A UART1 transmitdata AHCLKR /PRU0_R30[18] /UART1_RTS /GP0[11]/ A2 O CP[0] A UART1 ready-to-sendoutputPRU0_R31[18] AHCLKX /USB_REFCLKIN /UART1_CTS /GP0[10]/ A3 I CP[0] A UART1 clear-to-sendinputPRU0_R31[17] UART2 SPI1_SCS[5]/UART2_RXD /I2C1_SCL /GP1[3] F17 I CP[12] A UART2 receivedata SPI1_SCS[4]/UART2_TXD /I2C1_SDA /GP1[2] F16 O CP[12] A UART2 transmitdata AMUTE /PRU0_R30[16] /UART2_RTS /GP0[9]/ D5 O CP[0] A UART2 ready-to-sendoutputPRU0_R31[16] RTC_ALARM /UART2_CTS /GP0[8]/DEEPSLEEP F4 I CP[0] A UART2 clear-to-sendinput (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.Thepull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C.

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2.9.13 Inter-IntegratedCircuitModules(I2C0,I2C1)

Table2-17.Inter-IntegratedCircuit(I2C)TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. I2C0 SPI1_SCS[6]/I2C0_SDA /TM64P3_OUT12 /GP1[4] G18 I/O CP[11] A I2C0 serialdata SPI1_SCS[7]/I2C0_SCL /TM64P2_OUT12 /GP1[5] G16 I/O CP[11] A I2C0 serialclock I2C1 SPI1_SCS[4]/UART2_TXD /I2C1_SDA /GP1[2] F16 I/O CP[12] A I2C1 serialdata SPI1_SCS[5]/UART2_RXD /I2C1_SCL /GP1[3] F17 I/O CP[12] A I2C1 serialclock (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.Thepull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 47 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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2.9.14 Timers

Table2-18.Timers TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. TIMER0 SPI0_SCS[1]/TM64P0_OUT12 /GP1[7]/MDIO_CLK /TM64P0_IN12 E16 I CP[10] A Timer0lowerinput Timer0lowerSPI0_SCS[1]/TM64P0_OUT12 /GP1[7]/MDIO_CLK /TM64P0_IN12 E16 O CP[10] A output TIMER1 (Watchdog) SPI0_SCS[0]/TM64P1_OUT12 /GP1[6]/MDIO_D /TM64P1_IN12 D17 I CP[10] A Timer1lowerinput Timer1lowerSPI0_SCS[0]/TM64P1_OUT12 /GP1[6]/MDIO_D /TM64P1_IN12 D17 O CP[10] A output TIMER2 SPI1_SCS[1]/EPWM1A /PRU0_R30[8] /GP2[15]/TM64P2_IN12 F18 I CP[14] A Timer2lowerinput Timer2lowerSPI1_SCS[7]/I2C0_SCL /TM64P2_OUT12 /GP1[5] G16 O CP[11] A output TIMER3 SPI1_SCS[0]/EPWM1B /PRU0_R30[7] /GP2[14]/TM64P3_IN12 E19 I CP[14] A Timer3lowerinput Timer3lowerSPI1_SCS[6]/I2C0_SDA /TM64P3_OUT12 /GP1[4] G18 O CP[11] A output (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C.

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2.9.15 MultichannelAudio SerialPorts(McASP)

Table2-19.MultichannelAudio SerialPortsTerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. McASP0 AXR15 /EPWM0TZ[0] /ECAP2_APWM2 /GP0[7] A4 I/O CP[1] A AXR14 /CLKR1 /GP0[6] B4 I/O CP[2] A AXR13 /CLKX1 /GP0[5] B3 I/O CP[2] A AXR12 /FSR1 /GP0[4] C4 I/O CP[2] A AXR11 /FSX1 /GP0[3] C5 I/O CP[2] A AXR10 /DR1 /GP0[2] D4 I/O CP[2] A AXR9 /DX1 /GP0[1] C3 I/O CP[2] A AXR8 /CLKS1 /ECAP1_APWM1 /GP0[0]/PRU0_R31[8] E4 I/O CP[3] A McASP0 serialdataAXR7 /EPWM1TZ[0] /PRU0_R30[17] /GP1[15]/ D2 I/O CP[4] APRU0_R31[7] AXR6 /CLKR0 /GP1[14]/MII_TXEN /PRU0_R31[6] C1 I/O CP[5] A AXR5 /CLKX0 /GP1[13]/MII_TXCLK D3 I/O CP[5] A AXR4 /FSR0 /GP1[12]/MII_COL D1 I/O CP[5] A AXR3 /FSX0 /GP1[11]/MII_TXD[3] E3 I/O CP[5] A AXR2 /DR0 /GP1[10]/MII_TXD[2] E2 I/O CP[5] A AXR1 /DX0 /GP1[9]/MII_TXD[1] E1 I/O CP[5] A AXR0 /ECAP0_APWM0 /GP8[7]/MII_TXD[0]/CLKS0 F3 I/O CP[6] A AHCLKX /USB_REFCLKIN /UART1_CTS /GP0[10]/ A3 I/O CP[0] A McASP0 transmitmasterclockPRU0_R31[17] ACLKX /PRU0_R30[19] /GP0[14]/PRU0_R31[21] B1 I/O CP[0] A McASP0 transmitbitclock AFSX /GP0[12]/PRU0_R31[19] B2 I/O CP[0] A McASP0 transmitframesync AHCLKR /PRU0_R30[18] /UART1_RTS /GP0[11]/ A2 I/O CP[0] A McASP0 receivemasterclockPRU0_R31[18] ACLKR /PRU0_R30[20] /GP0[15]/PRU0_R31[22] A1 I/O CP[0] A McASP0 receivebitclock AFSR /GP0[13]/PRU0_R31[20] C2 I/O CP[0] A McASP0 receiveframesync AMUTE /PRU0_R30[16] /UART2_RTS /GP0[9]/ D5 I/O CP[0] A McASP0 mute outputPRU0_R31[16] (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 49 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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2.9.16 MultichannelBufferedSerialPorts(McBSP)

Table2-20.MultichannelBufferedSerialPorts(McBSPs) TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. McBSP0 AXR0 /ECAP0_APWM0 /GP8[7]/MII_TXD[0] F3 I CP[6] A McBSP0 sample rategeneratorclockinput/CLKS0 AXR6 /CLKR0 /GP1[14]/MII_TXEN / C1 I/O CP[5] A McBSP0 receiveclockPRU0_R31[6] AXR4 /FSR0 /GP1[12]/MII_COL D1 I/O CP[5] A McBSP0 receiveframesync AXR2 /DR0 /GP1[10]/MII_TXD[2] E2 I CP[5] A McBSP0 receivedata AXR5 /CLKX0 /GP1[13]/MII_TXCLK D3 I/O CP[5] A McBSP0 transmitclock AXR3 /FSX0 /GP1[11]/MII_TXD[3] E3 I/O CP[5] A McBSP0 transmitframesync AXR1 /DX0 /GP1[9]/MII_TXD[1] E1 O CP[5] A McBSP0 transmitdata McBSP1 AXR8 /CLKS1 /ECAP1_APWM1 /GP0[0]/ E4 I CP[3] A McBSP1 sample rategeneratorclockinputPRU0_R31[8] AXR14 /CLKR1 /GP0[6] B4 I/O CP[2] A McBSP1 receiveclock AXR12 /FSR1 /GP0[4] C4 I/O CP[2] A McBSP1 receiveframesync AXR10 /DR1 /GP0[2] D4 I CP[2] A McBSP1 receivedata AXR13 /CLKX1 /GP0[5] B3 I/O CP[2] A McBSP1 transmitclock AXR11 /FSX1 /GP0[3] C5 I/O CP[2] A McBSP1 transmitframesync AXR9 /DX1 /GP0[1] C3 O CP[2] A McBSP1 transmitdata (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C.

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2.9.17 UniversalSerialBus Modules (USB0 ,USB1)

Table2-21.UniversalSerialBus (USB) TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. USB0 2.0OTG (USB0) USB0_DM M18 A IPD — USB0 PHY dataminus USB0_DP M19 A IPD — USB0 PHY dataplus USB0_VDDA33 N18 PWR — — USB0 PHY 3.3-Vsupply USB0 PHY identificationUSB0_ID P16 A — — (mini-Aormini-Bplug) USB0_VBUS N19 A — — USB0 bus voltage USB0_DRVVBUS K18 0 IPD B USB0 controllerVBUS controloutput. AHCLKX /USB_REFCLKIN /UART1_CTS / A3 I CP[0] A USB_REFCLKIN. OptionalclockinputGP0[10]/PRU0_R31[17] USB0_VDDA18 N14 PWR — — USB0 PHY 1.8-Vsupplyinput USB0_VDDA12 N17 A — — USB0 PHY 1.2-VLDO outputforbypasscap USB0 and USB1 corelogic1.2-VsupplyUSB_CVDD M12 PWR — — input USB1 1.1OHCI (USB1) USB1_DM l P18 A — — USB1 PHY dataminus USB1_DP P19 A — — USB1 PHY dataplus AHCLKX /USB_REFCLKIN /UART1_CTS / A3 I CP[0] A USB_REFCLKIN. OptionalclockinputGP0[10]/PRU0_R31[17] USB1_VDDA33 P15 PWR — — USB1 PHY 3.3-Vsupply USB1_VDDA18 P14 PWR — — USB1 PHY 1.8-Vsupply USB0 and USB1 corelogic1.2-VsupplyUSB_CVDD M12 PWR — — input (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 51 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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2.9.18 EthernetMedia Access Controller(EMAC)

Table2-22.EthernetMedia Access Controller(EMAC) TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. MII AXR6 /CLKR0 /GP1[14]/MII_TXEN /PRU0_R31[6] C1 O CP[5] A EMAC MIITransmitenableoutput AXR5 /CLKX0 /GP1[13]/MII_TXCLK D3 I CP[5] A EMAC MIITransmitclockinput AXR4 /FSR0 /GP1[12]/MII_COL D1 I CP[5] A EMAC MIICollisiondetectinput AXR3 /FSX0 /GP1[11]/MII_TXD[3] E3 O CP[5] A AXR2 /DR0 /GP1[10]/MII_TXD[2] E2 O CP[5] A EMAC MIItransmitdataAXR1 /DX0 /GP1[9]/MII_TXD[1] E1 O CP[5] A AXR0 /ECAP0_APWM0 /GP8[7]/MII_TXD[0]/ F3 O CP[6] ACLKS0 SPI0_SOMI /EPWMSYNCI /GP8[6]/MII_RXER C16 I CP[7] A EMAC MIIreceiveerrorinput SPI0_SIMO /EPWMSYNCO /GP8[5]/MII_CRS C18 I CP[7] A EMAC MIIcarriersense input SPI0_CLK /EPWM0A /GP1[8]/MII_RXCLK D19 I CP[7] A EMAC MIIreceiveclockinput SPI0_ENA /EPWM0B /PRU0_R30[6] /MII_RXDV C17 I CP[7] A EMAC MIIreceivedatavalidinput SPI0_SCS[5]/UART0_RXD /GP8[4]/MII_RXD[3] C19 I CP[8] A SPI0_SCS[4]/UART0_TXD /GP8[3]/MII_RXD[2] D18 I CP[8] A SPI0_SCS[3]/UART0_CTS /GP8[2]/MII_RXD[1]/ EMAC MIIreceivedataE17 I CP[9] ASATA_MP_SWITCH SPI0_SCS[2]/UART0_RTS /GP8[1]/MII_RXD[0]/ D16 I CP[9] ASATA_CP_DET (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table2-22.EthernetMedia Access Controller(EMAC) TerminalFunctions(continued) SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. RMII VP_DIN[1]/UHPI_HD[9] /UPP_D[9] / W18 I/O CP[26] C EMAC 50-MHz clockinputoroutputRMII_MHZ_50_CLK /PRU0_R31[23] VP_DIN[2]/UHPI_HD[10] /UPP_D[10] /RMII_RXER / W17 I CP[26] C EMAC RMII receivererrorPRU0_R31[24] VP_DIN[3]/UHPI_HD[11] /UPP_D[11] /RMII_RXD[0] V17 I CP[26] C/PRU0_R31[25] EMAC RMII receivedata VP_DIN[4]/UHPI_HD[12] /UPP_D[12] /RMII_RXD[1] W16 I CP[26] C/PRU0_R31[26] VP_DIN[0]/UHPI_HD[8] /UPP_D[8] /RMII_CRS_DV W19 I CP[26] C EMAC RMII carriersense datavalid/PRU1_R31[29] VP_DIN[5]/UHPI_HD[13] /UPP_D[13] /RMII_TXEN / R14 O CP[26] C EMAC RMII transmitenablePRU0_R31[27] VP_DIN[6]/UHPI_HD[14] /UPP_D[14] /RMII_TXD[0] V16 O CP[26] C/PRU0_R31[28] EMAC RMII transmitdata VP_DIN[7]/UHPI_HD[15] /UPP_D[15] /RMII_TXD[1] U18 O CP[26] C/PRU0_R31[29] MDIO SPI0_SCS[0]/TM64P1_OUT12 /GP1[6]/MDIO_D / D17 I/O CP[10] A MDIO serialdataTM64P1_IN12 SPI0_SCS[1]/TM64P0_OUT12 /GP1[7]/MDIO_CLK E16 O CP[10] A MDIO clock/TM64P0_IN12 Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 53 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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2.9.19 MultimediaCard/SecureDigital(MMC/SD)

Table2-23.MultimediaCard/SecureDigital(MMC/SD) TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. MMCSD0 MMCSD0_CLK /PRU1_R30[31] /GP4[7] E9 O CP[18] B MMCSD0 Clock EMA_A[22] /MMCSD0_CMD /PRU1_R30[30] /GP4[6] A10 I/O CP[18] B MMCSD0 Command EMA_A[14] /MMCSD0_DAT[7] /PRU1_R30[22] /GP5[14]/ A12 I/O CP[19] BPRU1_R31[22] EMA_A[15] /MMCSD0_DAT[6] /PRU1_R30[23] /GP5[15]/ C11 I/O CP[19] BPRU1_R31[23] EMA_A[16] /MMCSD0_DAT[5] /PRU1_R30[24] /GP4[0] E12 I/O CP[18] B MMC/SD0 dataEMA_A[17] /MMCSD0_DAT[4] /PRU1_R30[25] /GP4[1] B11 I/O CP[18] B EMA_A[18] /MMCSD0_DAT[3] /PRU1_R30[26] /GP4[2] E11 I/O CP[18] B EMA_A[19] /MMCSD0_DAT[2] /PRU1_R30[27] /GP4[3] C10 I/O CP[18] B EMA_A[20] /MMCSD0_DAT[1] /PRU1_R30[28] /GP4[4] A11 I/O CP[18] B EMA_A[21] /MMCSD0_DAT[0] /PRU1_R30[29] /GP4[5] B10 I/O CP[18] B MMCSD1 PRU0_R30[24] /MMCSD1_CLK /UPP_CHB_START /GP8[14]/ G2 O CP[30] C MMCSD1 ClockPRU1_R31[26]/ PRU0_R30[23] /MMCSD1_CMD /UPP_CHB_ENABLE /GP8[13]/ J4 I/O CP[30] C MMCSD1 CommandPRU1_R31[25] MMCSD1_DAT[7] /LCD_PCLK /PRU1_R30[7] /GP8[11] F1 I/O CP[31] C MMCSD1_DAT[6] /LCD_MCLK /PRU1_R30[6] /GP8[10]/ F2 I/O CP[31] CPRU1_R31[7] MMCSD1_DAT[5] /LCD_HSYNC /PRU1_R30[5] /GP8[9]/ H4 I/O CP[31] CPRU1_R31[6] MMCSD1_DAT[4] /LCD_VSYNC /PRU1_R30[4] /GP8[8]/ G4 I/O CP[31] CPRU1_R31[5] MMC/SD1 dataVP_CLKIN2 /MMCSD1_DAT[3] /PRU1_R30[3] /GP6[4]/ H3 I/O CP[30] CPRU1_R31[4] VP_CLKOUT2 /MMCSD1_DAT[2] /PRU1_R30[2] /GP6[3]/ K3 I/O CP[30] CPRU1_R31[3] VP_CLKIN3 /MMCSD1_DAT[1] /PRU1_R30[1] /GP6[2]/ J3 I/O CP[30] CPRU1_R31[2] PRU0_R30[25] /MMCSD1_DAT[0] /UPP_CHB_CLOCK /GP8[15]/ G1 I/O CP[30] CPRU1_R31[27] (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C.

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2.9.20 LiquidCrystalDisplayController(LCD)

Table2-24.LiquidCrystalDisplayController(LCD) TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. VP_DOUT[15] /LCD_D[15] /UPP_XD[7] /GP7[7]/BOOT[7] P4 I/O CP[29] C VP_DOUT[14] /LCD_D[14] /UPP_XD[6] /GP7[6]/BOOT[6] R3 I/O CP[29] C VP_DOUT[13] /LCD_D[13] /UPP_XD[5] /GP7[5]/BOOT[5] R2 I/O CP[29] C VP_DOUT[12] /LCD_D[12] /UPP_XD[4] /GP7[4]/BOOT[4] R1 I/O CP[29] C VP_DOUT[11] /LCD_D[11] /UPP_XD[3] /GP7[3]/BOOT[3] T3 I/O CP[29] C VP_DOUT[10] /LCD_D[10] /UPP_XD[2] /GP7[2]/BOOT[2] T2 I/O CP[29] C VP_DOUT[9] /LCD_D[9] /UPP_XD[1] /GP7[1]/BOOT[1] T1 I/O CP[29] C VP_DOUT[8] /LCD_D[8] /UPP_XD[0] /GP7[0]/BOOT[0] U3 I/O CP[29] C VP_DOUT[7] /LCD_D[7] /UPP_XD[15] /GP7[15]/ U2 I/O CP[28] CPRU1_R31[15] LCD databusVP_DOUT[6] /LCD_D[6] /UPP_XD[14] /GP7[14]/ U1 I/O CP[28] CPRU1_R31[14] VP_DOUT[5] /LCD_D[5] /UPP_XD[13] /GP7[13]/ V3 I/O CP[28] CPRU1_R31[13] VP_DOUT[4] /LCD_D[4] /UPP_XD[12] /GP7[12]/ V2 I/O CP[28] CPRU1_R31[12] VP_DOUT[3] /LCD_D[3] /UPP_XD[11] /GP7[11]/ V1 I/O CP[28] CPRU1_R31[11] VP_DOUT[2] /LCD_D[2] /UPP_XD[10] /GP7[10]/ W3 I/O CP[28] CPRU1_R31[10] VP_DOUT[1] /LCD_D[1] /UPP_XD[9] /GP7[9]/PRU1_R31[9] W2 I/O CP[28] C VP_DOUT[0] /LCD_D[0] /UPP_XD[8] /GP7[8]/PRU1_R31[8] W1 I/O CP[28] C MMCSD1_DAT[7] /LCD_PCLK /PRU1_R30[7] /GP8[11] F1 O CP[31] C LCD pixelclock MMCSD1_DAT[5] /LCD_HSYNC /PRU1_R30[5] /GP8[9]/ H4 O CP[31] C LCD horizontalsyncPRU1_R31[6] MMCSD1_DAT[4] /LCD_VSYNC /PRU1_R30[4] /GP8[8]/ G4 O CP[31] C LCD verticalsyncPRU1_R31[5] LCD AC biasenablechipLCD_AC_ENB_CS /GP6[0]/PRU1_R31[28] R5 O CP[31] C select MMCSD1_DAT[6] /LCD_MCLK /PRU1_R30[6] /GP8[10]/ F2 O CP[31] C LCD memory clockPRU1_R31[7] (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 55 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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2.9.21 SerialATA Controller(SATA)

Table2-25.SerialATA Controller(SATA) TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. SATA_RXP L1 I — — SATA receivedata(positive) SATA_RXN L2 I — — SATA receivedata(negative) SATA_TXP J1 O — — SATA transmitdata(positive) SATA_TXN J2 O — — SATA transmitdata(negative) SATA_REFCLKP N2 I — — SATA PHY referenceclock(positive) SATA_REFCLKN N1 I — — SATA PHY referenceclock(negative) SPI0_SCS[3]/UART0_CTS /GP8[2]/ E17 I CP[9] A SATA mechanicalpresenceswitchinputMII_RXD[1]/SATA_MP_SWITCH SPI0_SCS[2]/UART0_RTS /GP8[1]/ D16 I CP[9] A SATA coldpresencedetectinputMII_RXD[0]/SATA_CP_DET SPI1_SCS[2]/UART1_TXD / F19 O CP[13] A SATA coldpresencepower-onoutputSATA_CP_POD /GP1[0] SPI1_SCS[3]/UART1_RXD /SATA_LED / E18 O CP[13] A SATA LED controloutputGP1[1] SATA PHY PLL regulatoroutput.RequiresanSATA_REG N3 A — — external0.1uFfiltercapacitor. SATA_VDDR P3 PWR — — SATA PHY 1.8Vinternalregulatorsupply M2, P1,SATA_VDD PWR — — SATA PHY 1.2VlogicsupplyP2, H1, H2, K1,SATA_VSS GND — — SATA PHY groundreferenceK2, L3, (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C.

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2.9.22 UniversalHost-PortInterface(UHPI)

Table2-26.UniversalHost-PortInterface(UHPI)TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. VP_DIN[7]/UHPI_HD[15] /UPP_D[15] /RMII_TXD[1]/ U18 I/O CP[26] CPRU0_R31[29] VP_DIN[6]/UHPI_HD[14] /UPP_D[14] /RMII_TXD[0]/ V16 I/O CP[26] CPRU0_R31[28] VP_DIN[5]/UHPI_HD[13] /UPP_D[13] /RMII_TXEN / R14 I/O CP[26] CPRU0_R31[27] VP_DIN[4]/UHPI_HD[12] /UPP_D[12] /RMII_RXD[1]/ W16 I/O CP[26] CPRU0_R31[26] VP_DIN[3]/UHPI_HD[11] /UPP_D[11] /RMII_RXD[0]/ V17 I/O CP[26] CPRU0_R31[25] VP_DIN[2]/UHPI_HD[10] /UPP_D[10] /RMII_RXER / W17 I/O CP[26] CPRU0_R31[24] VP_DIN[1]/UHPI_HD[9] /UPP_D[9] /RMII_MHZ_50_CLK / W18 I/O CP[26] CPRU0_R31[23] VP_DIN[0]/UHPI_HD[8] /UPP_D[8] /RMII_CRS_DV / W19 I/O CP[26] C UHPI databusPRU1_R31[29] VP_DIN[15]_VSYNC /UHPI_HD[7] /UPP_D[7] /PRU0_R30[15] / V18 I/O CP[27] CPRU0_R31[15] VP_DIN[14]_HSYNC /UHPI_HD[6] /UPP_D[6] /PRU0_R30[14] / V19 I/O CP[27] CPRU0_R31[14] VP_DIN[13]_FIELD/UHPI_HD[5] /UPP_D[5] /PRU0_R30[13] / U19 I/O CP[27] CPRU0_R31[13] VP_DIN[12]/UHPI_HD[4] /UPP_D[4] /PRU0_R30[12] / T16 I/O CP[27] CPRU0_R31[12] VP_DIN[11]/UHPI_HD[3] /UPP_D[3] /PRU0_R30[11] / R18 I/O CP[27] CPRU0_R31[11] VP_DIN[10]/UHPI_HD[2] /UPP_D[2] /PRU0_R30[10] / R19 I/O CP[27] CPRU0_R31[10] VP_DIN[9]/UHPI_HD[1] /UPP_D[1] /PRU0_R30[9] /PRU0_R31[9] R15 I/O CP[27] C VP_DIN[8]/UHPI_HD[0] /UPP_D[0] /GP6[5]/PRU1_R31[0] P17 I/O CP[27] C PRU0_R30[29] /UHPI_HCNTL0 /UPP_CHA_CLOCK /GP6[11] U17 I CP[24] C UHPI accesscontrol PRU0_R30[28] /UHPI_HCNTL1 /UPP_CHA_START /GP6[10] W15 I CP[24] C UHPI half-wordPRU0_R30[27] /UHPI_HHWIL /UPP_CHA_ENABLE /GP6[9] U16 I CP[24] C identificationcontrol PRU0_R30[26] /UHPI_HR W /UPP_CHA_WAIT / T15 I CP[24] C UHPI read/writeGP6[8]/PRU1_R31[17] VP_CLKIN0 /UHPI_HCS /PRU1_R30[10] /GP6[7]/UPP_2xTXCLK W14 I CP[25] C UHPI chipselect VP_CLKIN1 /UHPI_HDS1 /PRU1_R30[9] /GP6[6]/PRU1_R31[16] V15 I CP[25] C UHPI datastrobe CLKOUT /UHPI_HDS2 /PRU1_R30[13] /GP6[14] T18 I CP[22] C PRU0_R30[30] /UHPI_HINT /PRU1_R30[11] /GP6[12] R16 O CP[23] C UHPI hostinterrupt (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 57 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-26.UniversalHost-PortInterface(UHPI)TerminalFunctions(continued) SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. PRU0_R30[31] /UHPI_HRDY /PRU1_R30[12] /GP6[13] R17 O CP[23] C UHPI ready RESETOUT /UHPI_HAS /PRU1_R30[14] /GP6[15] T17 I CP[21] C UHPI addressstrobe

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2.9.23 UniversalParallelPort(uPP)

Table2-27.UniversalParallelPort(uPP)TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. VP_CLKIN0 /UHPI_HCS /PRU1_R30[10]/GP6[7]/ uPP 2x transmitclockW14 I CP[25] CUPP_2xTXCLK input PRU0_R30[25] /MMCSD1_DAT[0] /UPP_CHB_CLOCK / G1 I/O CP[30] C uPP channelB clockGP8[15]/PRU1_R31[27] PRU0_R30[24]/MMCSD1_CLK /UPP_CHB_START /GP8[14]/ G2 I/O CP[30] C uPP channelB startPRU1_R31[26] PRU0_R30[23] /MMCSD1_CMD /UPP_CHB_ENABLE / J4 I/O CP[30] C uPP channelB enableGP8[13]/PRU1_R31[25] PRU0_R30[22] /PRU1_R30[8] /UPP_CHB_WAIT /GP8[12]/ G3 I/O CP[30] C uPP channelB waitPRU1_R31[24] PRU0_R30[29] /UHPI_HCNTL0 /UPP_CHA_CLOCK /GP6[11] U17 I/O CP[24] C uPP channelA clock PRU0_R30[28] /UHPI_HCNTL1 /UPP_CHA_START /GP6[10] W15 I/O CP[24] C uPP channelA start PRU0_R30[27] /UHPI_HHWIL /UPP_CHA_ENABLE /GP6[9] U16 I/O CP[24] C uPP channelA enable PRU0_R30[26] /UHPI_HR W /UPP_CHA_WAIT /GP6[8]/ T15 I/O CP[24] C uPP channelA waitPRU1_R31[17] (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 59 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-27.UniversalParallelPort(uPP)TerminalFunctions(continued) SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. VP_DOUT[7] /LCD_D[7] /UPP_XD[15] /GP7[15]/ U2 I/O CP[28] CPRU1_R31[15] VP_DOUT[6] /LCD_D[6] /UPP_XD[14] /GP7[14]/ U1 I/O CP[28] CPRU1_R31[14] VP_DOUT[5] /LCD_D[5] /UPP_XD[13] /GP7[13]/ V3 I/O CP[28] CPRU1_R31[13] VP_DOUT[4] /LCD_D[4] /UPP_XD[12] /GP7[12]/ V2 I/O CP[28] CPRU1_R31[12] VP_DOUT[3] /LCD_D[3] /UPP_XD[11] /GP7[11]/ V1 I/O CP[28] CPRU1_R31[11] VP_DOUT[2] /LCD_D[2] /UPP_XD[10] /GP7[10]/ W3 I/O CP[28] CPRU1_R31[10] VP_DOUT[1] /LCD_D[1] /UPP_XD[9] /GP7[9]/PRU1_R31[9] W2 I/O CP[28] C VP_DOUT[0] /LCD_D[0] /UPP_XD[8] /GP7[8]/PRU1_R31[8] W1 I/O CP[28] C VP_DOUT[15] /LCD_D[15] /UPP_XD[7] /GP7[7]/BOOT[7] P4 I/O CP[29] C VP_DOUT[14] /LCD_D[14] /UPP_XD[6] /GP7[6]/BOOT[6] R3 I/O CP[29] C VP_DOUT[13] /LCD_D[13] /UPP_XD[5] /GP7[5]/BOOT[5] R2 I/O CP[29] C VP_DOUT[12] /LCD_D[12] /UPP_XD[4] /GP7[4]/BOOT[4] R1 I/O CP[29] C VP_DOUT[11] /LCD_D[11] /UPP_XD[3] /GP7[3]/BOOT[3] T3 I/O CP[29] C VP_DOUT[10] /LCD_D[10] /UPP_XD[2] /GP7[2]/BOOT[2] T2 I/O CP[29] C VP_DOUT[9] /LCD_D[9] /UPP_XD[1] /GP7[1]/BOOT[1] T1 I/O CP[29] C VP_DOUT[8] /LCD_D[8] /UPP_XD[0] /GP7[0]/BOOT[0] U3 I/O CP[29] C VP_DIN[7]/UHPI_HD[15] /UPP_D[15] /RMII_TXD[1]/ U18 I/O CP[26] CPRU0_R31[29] VP_DIN[6]/UHPI_HD[14] /UPP_D[14] /RMII_TXD[0]/ V16 I/O CP[26] C uPP databusPRU0_R31[28] VP_DIN[5]/UHPI_HD[13] /UPP_D[13] /RMII_TXEN / R14 I/O CP[26] CPRU0_R31[27] VP_DIN[4]/UHPI_HD[12] /UPP_D[12] /RMII_RXD[1]/ W16 I/O CP[26] CPRU0_R31[26] VP_DIN[3]/UHPI_HD[11] /UPP_D[11] /RMII_RXD[0]/ V17 I/O CP[26] CPRU0_R31[25] VP_DIN[2]/UHPI_HD[10] /UPP_D[10] /RMII_RXER / W17 I/O CP[26] CPRU0_R31[24] VP_DIN[1]/UHPI_HD[9] /UPP_D[9] /RMII_MHZ_50_CLK / W18 I/O CP[26] CPRU0_R31[23] VP_DIN[0]/UHPI_HD[8] /UPP_D[8] /RMII_CRS_DV / W19 I/O CP[26] CPRU1_R31[29] VP_DIN[15]_VSYNC /UHPI_HD[7] /UPP_D[7]/PRU0_R30[15]/ V18 I/O CP[27] CPRU0_R31[15] VP_DIN[14]_HSYNC /UHPI_HD[6] /UPP_D[6]/PRU0_R30[14] / V19 I/O CP[27] CPRU0_R31[14] VP_DIN[13]_FIELD/UHPI_HD[5] /UPP_D[5] /PRU0_R30[13] / U19 I/O CP[27] CPRU0_R31[13] VP_DIN[12]/UHPI_HD[4] /UPP_D[4]/PRU0_R30[12] / T16 I/O CP[27] CPRU0_R31[12] VP_DIN[11]/UHPI_HD[3] /UPP_D[3]/PRU0_R30[11] / R18 I/O CP[27] CPRU0_R31[11] VP_DIN[10]/UHPI_HD[2] /UPP_D[2]/PRU0_R30[10] / R19 I/O CP[27] CPRU0_R31[10] VP_DIN[9]/UHPI_HD[1] /UPP_D[1]/PRU0_R30[9] / R15 I/O CP[27] CPRU0_R31[9] VP_DIN[8]/UHPI_HD[0] /UPP_D[0] /GP6[5]/PRU1_R31[0] P17 I/O CP[27] C

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2.9.24 Video PortInterface(VPIF)

Table2-28.Video PortInterface(VPIF)TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. VIDEO INPUT VP_CLKIN0 /UHPI_HCS /PRU1_R30[10] /GP6[7]/ VPIF capturechannel0W14 I CP[25] CUPP_2xTXCLK inputclock VPIF capturechannel1VP_CLKIN1 /UHPI_HDS1/PRU1_R30[9] /GP6[6]/PRU1_R31[16] V15 I CP[25] C inputclock VP_DIN[15]_VSYNC /UHPI_HD[7] /UPP_D[7] /PRU0_R30[15] / V18 I CP[27] CPRU0_R31[15] VP_DIN[14]_HSYNC /UHPI_HD[6] /UPP_D[6] /RU0_R30[14] / V19 I CP[27] CPRU0_R31[14] VP_DIN[13]_FIELD /UHPI_HD[5] /UPP_D[5] /PRU0_R30[13] / U19 I CP[27] CPRU0_R31[13] VP_DIN[12]/UHPI_HD[4] /UPP_D[4] /PRU0_R30[12] / T16 I CP[27] CPRU0_R31[12] VP_DIN[11]/UHPI_HD[3] /UPP_D[3] /PRU0_R30[11] / R18 I CP[27] CPRU0_R31[11] VP_DIN[10]/UHPI_HD[2] /UPP_D[2] /PRU0_R30[10] / R19 I CP[27] CPRU0_R31[10] VP_DIN[9]/UHPI_HD[1] /UPP_D[1] /PRU0_R30[9] / R15 I CP[27] CPRU0_R31[9] VP_DIN[8]/UHPI_HD[0] /UPP_D[0] /GP6[5]/PRU1_R31[0] P17 I CP[27] C VPIF capturedatabusVP_DIN[7]/UHPI_HD[15] /UPP_D[15] /RMII_TXD[1]/ U18 I CP[26] CPRU0_R31[29] VP_DIN[6]/UHPI_HD[14] /UPP_D[14] /RMII_TXD[0]/ V16 I CP[26] CPRU0_R31[28] VP_DIN[5]/UHPI_HD[13] /UPP_D[13] /RMII_TXEN / R14 I CP[26] CPRU0_R31[27] VP_DIN[4]/UHPI_HD[12] /UPP_D[12] /RMII_RXD[1]/ W16 I CP[26] CPRU0_R31[26] VP_DIN[3]/UHPI_HD[11] /UPP_D[11] /MII_RXD[0]/ V17 I CP[26] CPRU0_R31[25] VP_DIN[2]/UHPI_HD[10] /UPP_D[10] /RMII_RXER / W17 I CP[26] CPRU0_R31[24] VP_DIN[1]/UHPI_HD[9] /UPP_D[9] /RMII_MHZ_50_CLK / W18 I CP[26] CPRU0_R31[23] VP_DIN[0]/UHPI_HD[8] /UPP_D[8] /RMII_CRS_DV / W19 I CP[26] CPRU1_R31[29] (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 61 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-28.Video PortInterface(VPIF)TerminalFunctions(continued) SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. VIDEO OUTPUT VP_CLKIN2 /MMCSD1_DAT[3] /PRU1_R30[3] /GP6[4]/ VPIF displaychannel2H3 I CP[30] CPRU1_R31[4] inputclock VP_CLKOUT2 /MMCSD1_DAT[2] /PRU1_R30[2] /GP6[3]/ VPIF displaychannel2K3 O CP[30] CPRU1_R31[3] outputclock VP_CLKIN3 /MMCSD1_DAT[1] /PRU1_R30[1] /GP6[2]/ VPIF displaychannel3J3 I CP[30] CPRU1_R31[2] inputclock VPIF displaychannel3VP_CLKOUT3 /PRU1_R30[0] /GP6[1]/PRU1_R31[1] K4 O CP[30] C outputclock VP_DOUT[15] /LCD_D[15] /UPP_XD[7] /GP7[7]/BOOT[7] P4 O CP[29] C VP_DOUT[14] /LCD_D[14] /UPP_XD[6] /GP7[6]/BOOT[6] R3 O CP[29] C VP_DOUT[13] /LCD_D[13] /UPP_XD[5] /GP7[5]/BOOT[5] R2 O CP[29] C VP_DOUT[12] /LCD_D[12] /UPP_XD[4] /GP7[4]/BOOT[4] R1 O CP[29] C VP_DOUT[11] /LCD_D[11] /UPP_XD[3] /GP7[3]/BOOT[3] T3 O CP[29] C VP_DOUT[10] /LCD_D[10] /UPP_XD[2] /GP7[2]/BOOT[2] T2 O CP[29] C VP_DOUT[9] /LCD_D[9] /UPP_XD[1] /GP7[1]/BOOT[1] T1 O CP[29] C VP_DOUT[8] /LCD_D[8] /UPP_XD[0] /GP7[0]/BOOT[0] U3 O CP[29] C VPIF displaydatabus VP_DOUT[7] /LCD_D[7] /UPP_XD[15] /GP7[15]/PRU1_R31[15] U2 O CP[28] C VP_DOUT[6] /LCD_D[6] /UPP_XD[14] /GP7[14]/PRU1_R31[14] U1 O CP[28] C VP_DOUT[5] /LCD_D[5] /UPP_XD[13] /GP7[13]/PRU1_R31[13] V3 O CP[28] C VP_DOUT[4] /LCD_D[4] /UPP_XD[12] /GP7[12]/PRU1_R31[12] V2 O CP[28] C VP_DOUT[3] /LCD_D[3] /UPP_XD[11] /GP7[11]/PRU1_R31[11] V1 O CP[28] C VP_DOUT[2] /LCD_D[2] /UPP_XD[10] /GP7[10]/PRU1_R31[10] W3 O CP[28] C VP_DOUT[1] /LCD_D[1] /UPP_XD[9] /GP7[9]/PRU1_R31[9] W2 O CP[28] C VP_DOUT[0] /LCD_D[0] /UPP_XD[8] /GP7[8]/PRU1_R31[8] W1 O CP[28] C

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2.9.25 GeneralPurpose InputOutput

Table2-29.GeneralPurpose InputOutput TerminalFunctions SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. GP0 ACLKR /PRU0_R30[20] /GP0[15] /PRU0_R31[22] A1 I/O CP[0] A ACLKX /PRU0_R30[19] /GP0[14] /PRU0_R31[21] B1 I/O CP[0] A AFSR /GP0[13] /PRU0_R31[20] C2 I/O CP[0] A AFSX /GP0[12] /PRU0_R31[19] B2 I/O CP[0] A AHCLKR /PRU0_R30[18] /UART1_RTS /GP0[11] / A2 I/O CP[0] APRU0_R31[18] AHCLKX /USB_REFCLKIN /UART1_CTS /GP0[10] / A3 I/O CP[0] APRU0_R31[17] AMUTE /PRU0_R30[16] /UART2_RTS /GP0[9] /PRU0_R31[16] D5 I/O CP[0] A GPIO Bank 0RTC_ALARM /UART2_CTS /GP0[8] /DEEPSLEEP F4 I/O CP[0] A AXR15 /EPWM0TZ[0] /ECAP2_APWM2 /GP0[7] A4 I/O CP[1] A AXR14 /CLKR1 /GP0[6] B4 I/O CP[2] A AXR13 /CLKX1 /GP0[5] B3 I/O CP[2] A AXR12 /FSR1 /GP0[4] C4 I/O CP[2] A AXR11 /FSX1 /GP0[3] C5 I/O CP[2] A AXR10 /DR1 /GP0[2] D4 I/O CP[2] A AXR9 /DX1 /GP0[1] C3 I/O CP[2] A AXR8 /CLKS1 /ECAP1_APWM1 /GP0[0] /PRU0_R31[8] E4 I/O CP[3] A (1) I= Input,O = Output,I/O= Bidirectional,Z = Highimpedance,PWR = Supplyvoltage,GND = Ground,A = Analogsignal. Note:The pintypeshown referstotheinput,outputorhigh-impedancestateofthepinfunctionwhen configuredas thesignalname highlightedinbold.Allmultiplexedsignalsmay entera high-impedancestatewhen theconfiguredfunctionisinput-onlyortheconfigured functionsupportshigh-Zoperation.AllGPIO signalscan be used as inputoroutput.Formultiplexedpinswhere functionshave different types(ie.,inputversusoutput),thetablereflectsthepinfunctiondirectionforthatparticularperipheral. (2) IPD = InternalPulldownresistor;IPU = InternalPullupresistor;CP[n]= configurablepull-up/pull-down(wheren isthepingroup)using thePUPDENA and PUPDSEL registersintheSystem Module.The pull-upand pull-downcontrolofthesepinsisnotactiveuntilthe deviceisoutofreset.Duringreset,allofthepinsassociatedwiththeseregistersarepulleddown. Iftheapplicationrequiresa pull-up, an externalpull-upcan be used.Forelectricalspecificationson thepull-upand and internalpull-downcircuits,see theDeviceOperating Conditionssection. (3) Thissignalispartofa dual-voltageIO group(A,B orC).These groupscan be operatedat3.3Vor1.8Vnominal.The threegroupscan be operatedatindependentvoltagesbutallpinswithinagroupwilloperateatthesame voltage.Group A operatesatthevoltageof power supplyDVDD3318_A. Group B operatesatthevoltageofpower supplyDVDD3318_B. Group C operatesatthevoltageofpower supplyDVDD3318_C. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 63 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-29.GeneralPurpose InputOutput TerminalFunctions(continued) SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. GP1 AXR7 /EPWM1TZ[0] /PRU0_R30[17] /GP1[15] /PRU0_R31[7] D2 I/O CP[4] A AXR6 /CLKR0 /GP1[14] /MII_TXEN /PRU0_R31[6] C1 I/O CP[5] A AXR5 /CLKX0 /GP1[13] /MII_TXCLK D3 I/O CP[5] A AXR4 /FSR0 /GP1[12] /MII_COL D1 I/O CP[5] A AXR3 /FSX0 /GP1[11] /MII_TXD[3] E3 I/O CP[5] A AXR2 /DR0 /GP1[10] /MII_TXD[2] E2 I/O CP[5] A AXR1 /DX0 /GP1[9] /MII_TXD[1] E1 I/O CP[5] A SPI0_CLK /EPWM0A /GP1[8] /MII_RXCLK D19 I/O CP[7] A SPI0_SCS[1]/TM64P0_OUT12 /GP1[7] /MDIO_CLK / GPIO Bank 1E16 I/O CP[10] ATM64P0_IN12 SPI0_SCS[0]/TM64P1_OUT12 /GP1[6] /MDIO_D / D17 I/O CP[10] ATM64P1_IN12 SPI1_SCS[7]/I2C0_SCL /TM64P2_OUT12 /GP1[5] G16 I/O CP[11] A SPI1_SCS[6]/I2C0_SDA /TM64P3_OUT12 /GP1[4] G18 I/O CP[11] A SPI1_SCS[5]/UART2_RXD /I2C1_SCL /GP1[3] F17 I/O CP[12] A SPI1_SCS[4]/UART2_TXD /I2C1_SDA /GP1[2] F16 I/O CP[12] A SPI1_SCS[3]/UART1_RXD /SATA_LED /GP1[1] E18 I/O CP[13] A SPI1_SCS[2]/UART1_TXD /SATA_CP_POD /GP1[0] F19 I/O CP[13] A

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table2-29.GeneralPurpose InputOutput TerminalFunctions(continued) SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. GP2 SPI1_SCS[1]/EPWM1A /PRU0_R30[8] /GP2[15] /TM64P2_IN12 F18 I/O CP[14] A SPI1_SCS[0]/EPWM1B /PRU0_R30[7] /GP2[14] /TM64P3_IN12 E19 I/O CP[14] A SPI1_CLK /GP2[13] G19 I/O CP[15] A SPI1_ENA /GP2[12] H16 I/O CP[15] A SPI1_SOMI /GP2[11] H17 I/O CP[15] A SPI1_SIMO /GP2[10] G17 I/O CP[15] A EMA_BA[1] /GP2[9] A15 I/O CP[16] B EMA_BA[0] /GP2[8] C15 I/O CP[16] B GPIO Bank 2 EMA_CLK /PRU0_R30[5] /GP2[7] /PRU0_R31[5] B7 I/O CP[16] B EMA_SDCKE /PRU0_R30[4] /GP2[6] /PRU0_R31[4] D8 I/O CP[16] B EMA_RAS /PRU0_R30[3] /GP2[5] /PRU0_R31[3] A16 I/O CP[16] B EMA_CAS /PRU0_R30[2] /GP2[4] /PRU0_R31[2] A9 I/O CP[16] B EMA_WEN_DQM[0] /GP2[3] C8 I/O CP[16] B EMA_WEN_DQM[1] /GP2[2] A5 I/O CP[16] B EMA_WAIT[1] /PRU0_R30[1] /GP2[1] /PRU0_R31[1] B19 I/O CP[16] B EMA_CS[0] /GP2[0] A18 I/O CP[16] B GP3 EMA_CS[2] /GP3[15] B17 I/O CP[16] B EMA_CS[3] /GP3[14] A17 I/O CP[16] B EMA_CS[4] /GP3[13] F9 I/O CP[16] B EMA_CS[5] /GP3[12] B16 I/O CP[16] B EMA_WE /GP3[11] B9 I/O CP[16] B EMA_OE /GP3[10] B15 I/O CP[16] B EMA_A_R W /GP3[9] D10 I/O CP[16] B EMA_WAIT[0] /PRU0_R30[0] /GP3[8] /PRU0_R31[0] B18 I/O CP[16] B GPIO Bank 3 EMA_D[15] /GP3[7] E6 I/O CP[17] B EMA_D[14] /GP3[6] C7 I/O CP[17] B EMA_D[13] /GP3[5] B6 I/O CP[17] B EMA_D[12] /GP3[4] A6 I/O CP[17] B EMA_D[11] /GP3[3] D6 I/O CP[17] B EMA_D[10] /GP3[2] A7 I/O CP[17] B EMA_D[9] /GP3[1] D9 I/O CP[17] B EMA_D[8] /GP3[0] E10 I/O CP[17] B Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 65 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-29.GeneralPurpose InputOutput TerminalFunctions(continued) SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. GP4 EMA_D[7] /GP4[15] D7 I/O CP[17] B EMA_D[6] /GP4[14] C6 I/O CP[17] B EMA_D[5] /GP4[13] E7 I/O CP[17] B EMA_D[4] /GP4[12] B5 I/O CP[17] B EMA_D[3] /GP4[11] E8 I/O CP[17] B EMA_D[2] /GP4[10] B8 I/O CP[17] B EMA_D[1] /GP4[9] A8 I/O CP[17] B EMA_D[0] /GP4[8] C9 I/O CP[17] B GPIO Bank 4 MMCSD0_CLK /PRU1_R30[31] /GP4[7] E9 I/O CP[18] B EMA_A[22] /MMCSD0_CMD /PRU1_R30[30] /GP4[6] A10 I/O CP[18] B EMA_A[21] /MMCSD0_DAT[0] /PRU1_R30[29] /GP4[5] B10 I/O CP[18] B EMA_A[20] /MMCSD0_DAT[1] /PRU1_R30[28] /GP4[4] A11 I/O CP[18] B EMA_A[19] /MMCSD0_DAT[2] /PRU1_R30[27] /GP4[3] C10 I/O CP[18] B EMA_A[18] /MMCSD0_DAT[3] /PRU1_R30[26] /GP4[2] E11 I/O CP[18] B EMA_A[17] /MMCSD0_DAT[4] /PRU1_R30[25] /GP4[1] B11 I/O CP[18] B EMA_A[16] /MMCSD0_DAT[5] /PRU1_R30[24] /GP4[0] E12 I/O CP[18] B GP5 EMA_A[15] /MMCSD0_DAT[6] /PRU1_R30[23] /GP5[15] / C11 I/O CP[19] BPRU1_R31[23] EMA_A[14] /MMCSD0_DAT[7] /PRU1_R30[22] /GP5[14] / A12 I/O CP[19] BPRU1_R31[22] EMA_A[13] /PRU0_R30[21] /PRU1_R30[21] /GP5[13] / D11 I/O CP[19] BPRU1_R31[21] EMA_A[12] /PRU1_R30[20] /GP5[12] /PRU1_R31[20] D13 I/O CP[19] B EMA_A[11] /PRU1_R30[19] /GP5[11] /PRU1_R31[19] B12 I/O CP[19] B EMA_A[10] /PRU1_R30[18] /GP5[10] /PRU1_R31[18] C12 I/O CP[19] B EMA_A[9] /PRU1_R30[17] /GP5[9] D12 I/O CP[19] B GPIO Bank 5 EMA_A[8] /PRU1_R30[16] /GP5[8] A13 I/O CP[19] B EMA_A[7] /PRU1_R30[15] /GP5[7] B13 I/O CP[20] B EMA_A[6] /GP5[6] E13 I/O CP[20] B EMA_A[5] /GP5[5] C13 I/O CP[20] B EMA_A[4] /GP5[4] A14 I/O CP[20] B EMA_A[3] /GP5[3] D14 I/O CP[20] B EMA_A[2] /GP5[2] B14 I/O CP[20] B EMA_A[1] /GP5[1] D15 I/O CP[20] B EMA_A[0] /GP5[0] C14 I/O CP[20] B

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table2-29.GeneralPurpose InputOutput TerminalFunctions(continued) SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. GP6 RESETOUT /UHPI_HAS /PRU1_R30[14] /GP6[15] T17 I/O CP[21] C CLKOUT /UHPI_HDS2 /PRU1_R30[13] /GP6[14] T18 I/O CP[22] C PRU0_R30[31] /UHPI_HRDY /PRU1_R30[12] /GP6[13] R17 I/O CP[23] C PRU0_R30[30] /UHPI_HINT /PRU1_R30[11] /GP6[12] R16 I/O CP[23] C PRU0_R30[29] /UHPI_HCNTL0 /UPP_CHA_CLOCK /GP6[11] U17 I/O CP[24] C PRU0_R30[28] /UHPI_HCNTL1 /UPP_CHA_START /GP6[10] W15 I/O CP[24] C PRU0_R30[27] /UHPI_HHWIL /UPP_CHA_ENABLE /GP6[9] U16 I/O CP[24] C PRU0_R30[26] /UHPI_HR W /UPP_CHA_WAIT /GP6[8]/ T15 I/O CP[24] CPRU1_R31[17] VP_CLKIN0 /UHPI_HCS /PRU1_R30[10] GP6[7] / W14 I/O CP[25] CUPP_2xTXCLK GPIO Bank 6 VP_CLKIN1 /UHPI_HDS1 /PRU1_R30[9] /GP6[6] / V15 I/O CP[25] CPRU1_R31[16] VP_DIN[8]/UHPI_HD[0] /UPP_D[0] /GP6[5] /PRU1_R31[0] P17 I/O CP[27] C VP_CLKIN2 /MMCSD1_DAT[3] /PRU1_R30[3] /GP6[4] / H3 I/O CP[30] CPRU1_R31[4] VP_CLKOUT2 /MMCSD1_DAT[2] /PRU1_R30[2] /GP6[3] / K3 I/O CP[30] CPRU1_R31[3] VP_CLKIN3 /MMCSD1_DAT[1] /PRU1_R30[1] /GP6[2] / J3 I/O CP[30] CPRU1_R31[2] VP_CLKOUT3 /PRU1_R30[0] /GP6[1] /PRU1_R31[1] K4 I/O CP[30] C LCD_AC_ENB_CS /GP6[0] /PRU1_R31[28] R5 I/O CP[31] C GP7 VP_DOUT[7] /LCD_D[7] /UPP_XD[15] /GP7[15] /PRU1_R31[15] U2 I/O CP[28] C VP_DOUT[6] /LCD_D[6] /UPP_XD[14] /GP7[14] /PRU1_R31[14] U1 I/O CP[28] C VP_DOUT[5] /LCD_D[5] /UPP_XD[13] /GP7[13] /PRU1_R31[13] V3 I/O CP[28] C VP_DOUT[4] /LCD_D[4] /UPP_XD[12] /GP7[12] /PRU1_R31[12] V2 I/O CP[28] C VP_DOUT[3] /LCD_D[3] /UPP_XD[11] /GP7[11] /PRU1_R31[11] V1 I/O CP[28] C VP_DOUT[2] /LCD_D[2] /UPP_XD[10] /GP7[10] /PRU1_R31[10] W3 I/O CP[28] C VP_DOUT[1] /LCD_D[1] /UPP_XD[9] /GP7[9] /PRU1_R31[9] W2 I/O CP[28] C VP_DOUT[0] /LCD_D[0] /UPP_XD[8] /GP7[8] /PRU1_R31[8] W1 I/O CP[28] C GPIO Bank 7 VP_DOUT[15] /LCD_D[15] /UPP_XD[7] /GP7[7] /BOOT[7] P4 I/O CP[29] C VP_DOUT[14] /LCD_D[14] /UPP_XD[6] /GP7[6] /BOOT[6] R3 I/O CP[29] C VP_DOUT[13] /LCD_D[13] /UPP_XD[5] /GP7[5]/BOOT[5] R2 I/O CP[29] C VP_DOUT[12] /LCD_D[12] /UPP_XD[4] /GP7[4] /BOOT[4] R1 I/O CP[29] C VP_DOUT[11] /LCD_D[11] /UPP_XD[3] /GP7[3] /BOOT[3] T3 I/O CP[29] C VP_DOUT[10] /LCD_D[10] /UPP_XD[2] /GP7[2] /BOOT[2] T2 I/O CP[29] C VP_DOUT[9] /LCD_D[9] /UPP_XD[1] /GP7[1] /BOOT[1] T1 I/O CP[29] C VP_DOUT[8] /LCD_D[8] /UPP_XD[0] /GP7[0] /BOOT[0] U3 I/O CP[29] C Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 67 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-29.GeneralPurpose InputOutput TerminalFunctions(continued) SIGNAL POWERTYPE (1) PULL (2) DESCRIPTIONGROUP (3) NAME NO. GP8 PRU0_R30[25] /MMCSD1_DAT[0] /UPP_CHB_CLOCK /GP8[15] G1 I/O CP30] C/PRU1_R31[27] PRU0_R30[24] /MMCSD1_CLK /UPP_CHB_START /GP8[14] / G2 I/O CP[30] CPRU1_R31[26] PRU0_R30[23] /MMCSD1_CMD /UPP_CHB_ENABLE /GP8[13] / J4 I/O CP[30] CPRU1_R31[25] PRU0_R30[22] /PRU1_R30[8] /UPP_CHB_WAIT /GP8[12] / G3 I/O CP[30] CPRU1_R31[24] MMCSD1_DAT[7] /LCD_PCLK /PRU1_R30[7] /GP8[11] F1 I/O CP[31] C MMCSD1_DAT[6] /LCD_MCLK /PRU1_R30[6] /GP8[10] / F2 I/O CP[31] CPRU1_R31[7] MMCSD1_DAT[5] /LCD_HSYNC /PRU1_R30[5] /GP8[9] / H4 I/O CP[31] CPRU1_R31[6] GPIO Bank 8 MMCSD1_DAT[4] /LCD_VSYNC /PRU1_R30[4] /GP8[8] / G4 I/O CP[31] CPRU1_R31[5] AXR0 /ECAP0_APWM0 /GP8[7] /MII_TXD[0]/CLKS0 F3 I/O CP[6] A SPI0_SOMI /EPWMSYNCI /GP8[6] /MII_RXER C16 I/O CP[7] A SPI0_SIMO /EPWMSYNCO /GP8[5] /MII_CRS C18 I/O CP[7] A SPI0_SCS[5]/UART0_RXD /GP8[4] /MII_RXD[3] C19 I/O CP[8] A SPI0_SCS[4]/UART0_TXD /GP8[3] /MII_RXD[2] D18 I/O CP[8] A SPI0_SCS[3]/UART0_CTS /GP8[2] /MII_RXD[1]/ E17 I/O CP[9] ASATA_MP_SWITCH SPI0_SCS[2]/UART0_RTS /GP8[1] /MII_RXD[0]/ D16 I/O CP[9] ASATA_CP_DET RTCK /GP80 K17 I/O IPD B (1) GP8[0]isinitiallyconfiguredas a reservedfunctionafterresetand willnotbe ina predictablestate.Thissignalwillonlybe stableafter theGPIO configurationforthispinhas been completed.Usersshouldcarefullyconsiderthesystemimplicationsofthispinbeinginan unknown stateafterreset.

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2.9.26 Reserved and No Connect

Table2-30.Reserved and No Connect TerminalFunctions SIGNAL TYPE (1) DESCRIPTION NAME NO. Reserved.Forproperdeviceoperation,thispinmust be tiedeitherdirectlytoRSV2 T19 PWR CVDD orleftunconnected(donotconnecttoground). PinM3 shouldbe leftunconnected(do not connecttopower orground)NC M3, M14, N16 PinsM14 and N16 may be leftunconnectedorconnectedtoground(VSS) (1) PWR = Supplyvoltage. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 69 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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2.9.27 Supply and Ground

Table2-31.Supply and Ground TerminalFunctions SIGNAL TYPE (1) DESCRIPTION NAME NO. E15,G7, G8, G13, H6, H7, H10, H11, CVDD (Coresupply) H12, H13, J6, PWR Variable(1.3V-1.0V)coresupplyvoltagepins J12,K6,K12, L12,M8, M9, RVDD (InternalRAM supply) E5,H14, N7 PWR 1.2Vinternalram supplyvoltagepins(for345 MHz versions) F14,G6, G10, G11, G12, 1.8VI/Osupplyvoltagepins.DVDD18 must be powered even ifallofDVDD18 (I/Osupply) PWRJ13,K5,L6, theDVDD3318_x suppliesareoperatedat3.3V. P13,R13 F5,F15,G5,DVDD3318_A (I/Osupply) PWR 1.8Vor3.3-Vdual-voltageLVCMOS I/Osupplyvoltagepins,Group AG14, G15, H5 E14,F6,F7, F8,F10,F11,DVDD3318_B (I/Osupply) PWR 1.8Vor3.3-Vdual-voltageLVCMOS I/Osupplyvoltagepins,Group BF12,F13,G9, J14,K15 J5,K13,L4, L13,M13,DVDD3318_C (I/Osupply) PWR 1.8Vor3.3-Vdual-voltageLVCMOS I/Osupplyvoltagepins,Group CN13, P5,P6, P12,R4 A19,H8, H9, H15, J7,J8, J9,J10,J11, K7,K8,K9, K10,K11,L5,VSS (Ground) GND Ground pins.L7,L8,L9, L10,L11,M4, M5, M6, M7, M10, M11, N5, N11, N12, P11 USB0_VDDA33 N18 PWR USB0 PHY 3.3-Vsupply USB0_VDDA18 N14 PWR USB0 PHY 1.8-Vsupplyinput USB0_VDDA12 N17 A USB0 PHY 1.2-VLDO outputforbypasscap USB_CVDD M12 PWR USB0 corelogic1.2-Vsupplyinput USB1_VDDA33 P15 PWR USB1 PHY 3.3-Vsupply USB1_VDDA18 P14 PWR USB1 PHY 1.8-Vsupply M2, N4, P1,SATA_VDD PWR SATA PHY 1.2VlogicsupplyP2 H1, H2, K1,SATA_VSS GND SATA PHY groundreferenceK2,L3,M1 N6, N9, N10, P7,P8,P9,DDR_DVDD18 PWR DDR PHY 1.8Vpower supplypinsP10,R7, R8, (1) PWR = Supplyvoltage,GND -Ground.

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2.10 Unused Pin Configurations

Allsignalsmultiplexedwithmultiplefunctionsmay be used as an alternatefunctionifa givenperipheralis notused.Unused non-multiplexedsignalsand some otherspecificsignalsshouldbe handledas specified inthetablesbelow. IfNMI isunused,itshouldbe pulled-highexternallythrougha 10k-ohm resistortosupplyDVDD3318_B. Table2-32.Unused USB0 and USB1 SignalConfigurations Configuration(When USB0 and USB1 arenotSIGNAL NAME Configuration(When onlyUSB1 isnot used)used) USB0_DM No Connect Use as USB0 function USB0_DP No Connect Use as USB0 function USB0_ID No Connect Use as USB0 function USB0_VBUS No Connect Use as USB0 function USB0_DRVVBUS No Connect Use as USB0 function USB0_VDDA33 No Connect 3.3V USB0_VDDA18 No Connect 1.8V InternalUSB PHY outputconnectedtoan externalUSB0_VDDA12 No Connect filtercapacitor USB1_DM No Connect VSS orNo Connect USB1_DP No Connect VSS orNo Connect USB1_VDDA33 No Connect No Connect USB1_VDDA18 No Connect No Connect USB_REFCLKIN No Connectorotherperipheralfunction Use forUSB0 orotherperipheralfunction USB_CVDD 1.2V 1.2V Table2-33.Unused SATA SignalConfiguration SIGNAL NAME Configuration SATA_RXP No Connect SATA_RXN No Connect SATA_TXP No Connect SATA_TXN No Connect SATA_REFCLKP No Connect SATA_REFCLKN No Connect SATA_MP_SWITCH May be used as GPIO orotherperipheralfunction SATA_CP_DET May be used as GPIO orotherperipheralfunction SATA_CP_POD May be used as GPIO orotherperipheralfunction SATA_LED May be used as GPIO orotherperipheralfunction SATA_REG No Connect SATA_VDDR No Connect Priortosiliconrevision2.0,thissupplymust be connectedtoa static1.2Vnominalsupply. SATA_VDD Forsiliconrevision2.0and later,thissupplymay be leftunconnectedforadditionalpower conservation. SATA_VSS VSS Table2-34.Unused RTC SignalConfiguration SIGNAL NAME Configuration RTC_XI May be heldhigh(CVDD) orlow RTC_XO No Connect RTC_ALARM May be used as GPIO orotherperipheralfunction Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOverview 71 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table2-34.Unused RTC SignalConfiguration(continued) SIGNAL NAME Configuration RTC_CVDD ConnecttoCVDD RTC_VSS VSS Table2-35.Unused DDR2/mDDR ControllerSignalConfiguration SIGNAL NAME Configuration(1) DDR_D[15:0] No Connect DDR_A[13:0] No Connect DDR_CLKP No Connect DDR_CLKN No Connect DDR_CKE No Connect DDR_WE No Connect DDR_RAS No Connect DDR_CAS No Connect DDS_CS No Connect DDR_DQM[1:0] No Connect DDR_DQS[1:0] No Connect DDR_BA[2:0] No Connect DDR_DQGATE0 No Connect DDR_DQGATE1 No Connect DDR_ZP No Connect DDR_VREF No Connect DDR_DVDD18 No Connect (1) To minimizepower consumption,theDDR2/mDDR controllerinputreceiversshouldbe placedinpower-down mode by setting VTPIO[14]=1.

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3 Device Configuration

3.1 Boot Modes

Thisdevicesupportsa varietyofbootmodes throughan internalARM ROM bootloader.Thisdevicedoes notsupportdedicatedhardwarebootmodes; therefore,allbootmodes utilizetheinternalARM ROM. The inputstatesoftheBOOT pinsare sampled and latchedintotheBOOTCFG register,which ispartofthe system configuration(SYSCFG) module, when device resetis deasserted.Boot mode selectionis determinedby thevaluesoftheBOOT pins. See UsingtheOMAP-L132/L138 BootloaderApplicationReport(SPRAB41 )formore detailson theROM BootLoader. The followingbootmodes aresupported:

NAND Flashboot – 8-bitNAND – 16-bitNAND (supportedon ROM revisionsafterd800k002 -- see the bootloaderdocuments mentionedabove todeterminetheROM revision)
NOR Flashboot – NOR Directboot(8-bitor16-bit) – NOR Legacy boot(8-bitor16-bit) – NOR AIS boot(8-bitor16-bit)
HPI Boot
I2C0/I2C1Boot – EEPROM (MasterMode) – ExternalHost(SlaveMode)
SPI0/SPI1Boot – SerialFlash(MasterMode) – SERIAL EEPROM (MasterMode) – ExternalHost(SlaveMode)
UART0 /UART1/UART2 Boot – ExternalHost
MMC/SD0 Boot

3.2 SYSCFG Module

The followingsystemlevelfeaturesofthechiparecontrolledby theSYSCFG peripheral:

ReadableDevice,Die,and ChipRevisionID
ControlofPinMultiplexing
Priorityofbus accessesdifferentbus mastersinthesystem
Captureatpower on resetthechipBOOT pinvaluesand make them availabletosoftware
ControloftheDeepSleep power management function
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Specialcase settingsforperipherals: – LockingofPLL controllersettings – DefaultburstsizesforEDMA3 transfercontrollers – SelectionofthesourcefortheeCAP module inputcapture(includingon chipsources) – McASP AMUTEIN selectionand clearingofAMUTE statusfortheMcASP – Controlofthereferenceclocksourceand otherside-bandsignalsforbothoftheintegratedUSB PHYs – ClocksourceselectionforEMIFA – DDR2 ControllerPHY settings – SATA PHY power management controls
Selectsthe sourceof emulationsuspend signal(fromeitherARM or DSP) of peripheralssupporting thisfunction.
Controlofon-chipinter-processorinterruptsforsignalingbetween ARM and DSP Many registersare accessibleonlyby a host(ARM or DSP) when itisoperatinginitsprivilegedmode. (ex.fromthekernel,butnotfromuserspace code). Table3-1.System Configuration(SYSCFG) Module RegisterAccess BYTE ADDRESS ACRONYM REGISTER DESCRIPTION REGISTER ACCESS 0x01C1 4000 REVID RevisionIdentificationRegister — 0x01C1 4008 DIEIDR0 DeviceIdentificationRegister0 — 0x01C1 400C DIEIDR1 DeviceIdentificationRegister1 — 0x01C1 4010 DIEIDR2 DeviceIdentificationRegister2 — 0x01C1 4014 DIEIDR3 DeviceIdentificationRegister3 — 0x01C1 4020 BOOTCFG BootConfigurationRegister Privilegedmode 0x01C1 4038 KICK0R Kick0 Register Privilegedmode 0x01C1 403C KICK1R Kick1 Register Privilegedmode 0x01C1 4040 HOST0CFG Host0 ConfigurationRegister — 0x01C1 4044 HOST1CFG Host1 ConfigurationRegister — 0x01C1 40E0 IRAWSTAT InterruptRaw Status/SetRegister Privilegedmode 0x01C1 40E4 IENSTAT InterruptEnableStatus/ClearRegister Privilegedmode 0x01C1 40E8 IENSET InterruptEnableRegister Privilegedmode 0x01C1 40EC IENCLR InterruptEnableClearRegister Privilegedmode 0x01C1 40F0 EOI End ofInterruptRegister Privilegedmode 0x01C1 40F4 FLTADDRR FaultAddressRegister Privilegedmode 0x01C1 40F8 FLTSTAT FaultStatusRegister — 0x01C1 4110 MSTPRI0 MasterPriority0 Registers Privilegedmode 0x01C1 4114 MSTPRI1 MasterPriority1 Registers Privilegedmode 0x01C1 4118 MSTPRI2 MasterPriority2 Registers Privilegedmode 0x01C1 4120 PINMUX0 PinMultiplexingControl0 Register Privilegedmode 0x01C1 4124 PINMUX1 PinMultiplexingControl1 Register Privilegedmode 0x01C1 4128 PINMUX2 PinMultiplexingControl2 Register Privilegedmode 0x01C1 412C PINMUX3 PinMultiplexingControl3 Register Privilegedmode 0x01C1 4130 PINMUX4 PinMultiplexingControl4 Register Privilegedmode 0x01C1 4134 PINMUX5 PinMultiplexingControl5 Register Privilegedmode 0x01C1 4138 PINMUX6 PinMultiplexingControl6 Register Privilegedmode 0x01C1 413C PINMUX7 PinMultiplexingControl7 Register Privilegedmode 0x01C1 4140 PINMUX8 PinMultiplexingControl8 Register Privilegedmode 0x01C1 4144 PINMUX9 PinMultiplexingControl9 Register Privilegedmode 0x01C1 4148 PINMUX10 PinMultiplexingControl10 Register Privilegedmode

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table3-1.System Configuration(SYSCFG) Module RegisterAccess (continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION REGISTER ACCESS 0x01C1 414C PINMUX11 PinMultiplexingControl11 Register Privilegedmode 0x01C1 4150 PINMUX12 PinMultiplexingControl12 Register Privilegedmode 0x01C1 4154 PINMUX13 PinMultiplexingControl13 Register Privilegedmode 0x01C1 4158 PINMUX14 PinMultiplexingControl14 Register Privilegedmode 0x01C1 415C PINMUX15 PinMultiplexingControl15 Register Privilegedmode 0x01C1 4160 PINMUX16 PinMultiplexingControl16 Register Privilegedmode 0x01C1 4164 PINMUX17 PinMultiplexingControl17 Register Privilegedmode 0x01C1 4168 PINMUX18 PinMultiplexingControl18 Register Privilegedmode 0x01C1 416C PINMUX19 PinMultiplexingControl19 Register Privilegedmode 0x01C1 4170 SUSPSRC Suspend SourceRegister Privilegedmode 0x01C1 4174 CHIPSIG ChipSignalRegister — 0x01C1 4178 CHIPSIG_CLR ChipSignalClearRegister — 0x01C1 417C CFGCHIP0 ChipConfiguration0 Register Privilegedmode 0x01C1 4180 CFGCHIP1 ChipConfiguration1 Register Privilegedmode 0x01C1 4184 CFGCHIP2 ChipConfiguration2 Register Privilegedmode 0x01C1 4188 CFGCHIP3 ChipConfiguration3 Register Privilegedmode 0x01C1 418C CFGCHIP4 ChipConfiguration4 Register Privilegedmode 0x01E2 C000 VTPIO_CTL VTPIO COntrolRegister Privilegedmode 0x01E2 C004 DDR_SLEW DDR Slew Register Privilegedmode 0x01E2 C008 DeepSleep DeepSleep Register Privilegedmode 0x01E2 C00C PUPD_ENA Pullup/PulldownEnableRegister Privilegedmode 0x01E2 C010 PUPD_SEL Pullup/PulldownSelectionRegister Privilegedmode 0x01E2 C014 RXACTIVE RXACTIVE ControlRegister Privilegedmode 0x01E2 C018 PWRDN PWRDN ControlRegister Privilegedmode Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceConfiguration 75 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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3.3 Pullup/PulldownResistors

Properboard designshouldensurethatinputpinstothedevicealwaysbe ata validlogicleveland not floating.Thismay be achievedviapullup/pulldownresistors.The devicefeaturesinternalpullup(IPU)and internalpulldown(IPD)resistorson most pinstoeliminatetheneed,unlessotherwisenoted,forexternal pullup/pulldownresistors. An externalpullup/pulldownresistorneeds tobe used inthefollowingsituations:

Boot and ConfigurationPins:Ifthe pin is both routedout and 3-stated(notdriven),an external pullup/pulldownresistorisstronglyrecommended, even iftheIPU/IPDmatches thedesiredvalue/state.
Other Input Pins: If the IPU/IPD does not match the desired value/state,use an external pullup/pulldownresistortopullthesignaltotheoppositerail. For the boot and configurationpins,iftheyare both routedout and 3-stated(notdriven),itisstrongly recommended that an external pullup/pulldownresistorbe implemented. Although, internal pullup/pulldownresistorsexiston these pins and they may match the desiredconfigurationvalue, providingexternalconnectivitycan helpensurethatvalidlogiclevelsarelatchedon thesedevicebootand configurationpins.In addition,applyingexternalpullup/pulldownresistorson the boot and configuration pinsadds conveniencetotheuserindebuggingand flexibilityinswitchingoperatingmodes. Tipsforchoosingan externalpullup/pulldownresistor:
Considerthetotalamount ofcurrentthatmay pass throughthepulluporpulldownresistor.Make sure toincludetheleakagecurrentsofallthedevicesconnectedtothenet,as wellas any internalpullupor pulldownresistors.
Decidea targetvalueforthenet.For a pulldownresistor,thisshouldbe below thelowestVIL levelof allinputsconnectedtothenet.For a pullupresistor,thisshouldbe above thehighestVIH levelofall inputson thenet.A reasonablechoicewould be totargettheVOL orVOH levelsforthelogicfamilyof thelimitingdevice;which,by definition,have margintotheVIL and VIH levels.
Selecta pullup/pulldownresistorwiththelargestpossiblevalue;but,whichcan stillensurethatthenet willreachthetargetpulledvaluewhen maximum currentfromalldeviceson thenetisflowingthrough the resistor.The currentto be consideredincludesleakage currentplus,any otherinternaland externalpullup/pulldownresistorson thenet.
For bidirectionalnets,thereisan additionalconsiderationwhich setsa lowerlimiton the resistance valueoftheexternalresistor.Verifythattheresistanceissmallenough thattheweakestoutputbuffer can drivethenettotheoppositelogiclevel(includingmargin).
Remember toincludetoleranceswhen selectingtheresistorvalue.
Forpullupresistors,alsoremember toincludetoleranceson theIO supplyrail.
For most systems,a 1-kΩ resistorcan be used to oppose the IPU/IPD whilemeeting the above criteria.Usersshouldconfirmthisresistorvalueiscorrectfortheirspecificapplication.
For most systems,a 20-kΩ resistorcan be used to compliment the IPU/IPD on the boot and configurationpinswhilemeetingtheabove criteria.Users shouldconfirmthisresistorvalueiscorrect fortheirspecificapplication.
For more detailedinformationon inputcurrent(II),and thelow-/high-levelinputvoltages(VIL and VIH) forthedevice,see Section4.2,Recommended OperatingConditions.
For theinternalpullup/pulldownresistorsforalldevicepins,see theperipheral/system-specificterminal functionstable.

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4 Device OperatingConditions

4.1 AbsoluteMaximum RatingsOver OperatingJunctionTemperature Range

(UnlessOtherwiseNoted) (1) Core Logic,Variableand Fixed -0.5V to1.4V (CVDD, RVDD, RTC_CVDD, PLL0_VDDA ,PLL1_VDDA , SATA_VDD, USB_CVDD )(2) I/O,1.8V -0.5V to2 VSupplyvoltageranges (USB0_VDDA18, USB1_VDDA18, SATA_VDDR, DDR_DVDD18) (2) I/O,3.3V -0.5V to3.8V (DVDD3318_A, DVDD3318_B, DVDD3318_C, USB0_VDDA33 , USB1_VDDA33) (2) Oscillatorinputs(OSCIN, RTC_XI),1.2V -0.3V toCVDD + 0.3V Dual-voltageLVCMOS inputs,3.3Vor1.8V(SteadyState) -0.3VtoDVDD + 0.3V Dual-voltageLVCMOS inputs,operatedat3.3V(Transient) DVDD + 20% up to20% ofSignal Period Inputvoltage(VI)ranges Dual-voltageLVCMOS inputs,operatedat1.8V(Transient) DVDD + 30% up to30% ofSignal Period USB 5V TolerantIOs: 5.25V(3) (USB0_DM, USB0_DP, USB0_ID ,USB1_DM, USB1_DP) USB0 VBUS Pin 5.50V(3) Dual-voltageLVCMOS outputs,3.3Vor1.8V -0.5V toDVDD + 0.3V (SteadyState) Dual-voltageLVCMOS outputs,operatedat3.3V(Transient) DVDD + 20% (Transient) up to20% ofSignalOutputvoltage(VO )ranges Period Dual-voltageLVCMOS outputs,operatedat1.8V(Transient) DVDD + 30% (Transient) up to30% ofSignal Period InputorOutputVoltages0.3Vabove orbelowtheirrespectivepower ±20mA Clamp Current rails.Limitclamp currentthatflowsthroughtheI/O'sinternaldiode protectioncells. OperatingJunctionTemperatureranges, -55°C to125°C TJ Storagetemperaturerange,Tstg (default) -55°C to150°C Human Body Model (HBM) (5) >1000 V ESD StressVoltage,VESD (4) Charged DeviceModel (CDM) (6) >500 V (1) Stressesbeyond thoselistedunder"absolutemaximum ratings"may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) AllvoltagevaluesarewithrespecttoVSS, USB0_VSSA33, USB0_VSSA, PLL0_VSSA, OSCVSS, RTC_VSS (3) Up toa maximum of24 hours. (4) Electrostaticdischarge(ESD) tomeasure devicesensitivity/immunitytodamage caused by electrostaticdischargesintothedevice. (5) Levellistedabove isthepassinglevelperANSI/ESDA/JEDEC JS-001-2010.JEDEC document JEP 155 statesthat500V HBM allows safemanufacturingwitha standardESD controlprocess,and manufacturingwithlessthan500V HBM ispossibleifnecessary precautionsaretaken.Pinslistedas 1000V may actuallyhave higherperformance. (6) Levellistedabove isthepassinglevelperEIA-JEDEC JESD22-C101E. JEDEC document JEP 157 statesthat250V CDM allowssafe manufacturingwitha standardESD controlprocess.Pinslistedas 250V may actuallyhave higherperformance. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOperatingConditions 77 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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4.2 Recommended OperatingConditions

NAME DESCRIPTION CONDITION MIN NOM MAX UNIT 1.3Voperatingpoint 1.25 1.3 1.35 1.2Voperatingpoint 1.14 1.2 1.32 CVDD Core LogicSupplyVoltage(variable) V 1.1Voperatingpoint 1.05 1.1 1.16 1.0Voperatingpoint 0.95 1.0 1.05 RVDD InternalRAM SupplyVoltage 345 MHz versions 1.14 1.2 1.32 V RTC_CVDD (1) RTC Core LogicSupplyVoltage 0.9 1.2 1.32 V PLL0_VDDA PLL0 SupplyVoltage 1.14 1.2 1.32 V PLL1_VDDA PLL1 SupplyVoltage 1.14 1.2 1.32 V SATA_VDD SATA Core LogicSupplyVoltage 1.14 1.2 1.32 V USB_CVDD USB0, USB1 Core LogicSupplyVoltage 1.14 1.2 1.32 V USB0_VDDA18 USB0 PHY SupplyVoltage 1.71 1.8 1.89 V USB0_VDDA33 USB0 PHY SupplyVoltage 3.15 3.3 3.45 V USB1_VDDA18 USB1 PHY SupplyVoltage 1.71 1.8 1.89 VSupply Voltage USB1_VDDA33 USB1 PHY SupplyVoltage 3.15 3.3 3.45 V DVDD18 (2) 1.8VLogicSupply 1.71 1.8 1.89 V SATA_VDDR SATA PHY InternalRegulatorSupplyVoltage 1.71 1.8 1.89 V DDR_DVDD18 (2) DDR2 PHY SupplyVoltage 1.71 1.8 1.89 V 0.49* 0.5* 0.51*DDR_VREF DDR2/mDDR referencevoltage VDDR_DVDD18 DDR_DVDD18 DDR_DVDD18 DDR2/mDDR impedance control,DDR_ZP Vss Vconnectedvia50Ω resistortoVss VSS Core LogicDigitalGround PLL0_VSSA PLL0 Ground PLL1_VSSA PLL1 Ground SATA_VSS SATA PHY GroundSupply 0 0 0 VGround OSCVSS (3) OscillatorGround RTC_VSS (3) RTC OscillatorGround USB0_VSSA USB0 PHY Ground USB0_VSSA33 USB0 PHY Ground High-levelinputvoltage,Dual-voltageI/O,3.3V(4) 2 V High-levelinputvoltage,Dual-voltageI/O,1.8V (4) 0.65*DVDD VVoltage VIHInputHigh High-levelinputvoltage,RTC_XI 0.8*RTC_CVDD V High-levelinputvoltage,OSCIN 0.8*CVDD V Low-levelinputvoltage,Dual-voltageI/O,3.3V(4) 0.8 V Low-levelinputvoltage,Dual-voltageI/O,1.8V (4) 0.35*DVDD VVoltage VILInputLow Low-levelinputvoltage,RTC_XI 0.2*RTC_CVDD V Low-levelinputvoltage,OSCIN 0.2*CVDD V USB USB0_VBUS USB externalchargepump input 0 5.25 V (1) The RTC providesan optionforisolatingtheRTC_CVDD fromtheCVDD toreducecurrentleakagewhen theRTC ispowered independently.Ifthesepower suppliesarenotisolated(CTRL.SPLITPOWER=0), RTC_CVDD must be equaltoorgreaterthanCVDD. Ifthesepower suppliesareisolated(CTRL.SPLITPOWER=1), RTC_CVDD may be lowerthanCVDD. (2) DVDD18 must be powered even ifalloftheDVDD3318_x suppliesareoperatedat3.3V. (3) When an externalcrystalisused oscillator(OSC_VSS, RTC_VSS) groundmust be keptseparatefromothergroundsand connected directlytothecrystalloadcapacitorground.These pinsareshortedtoVSS on thedeviceitselfand shouldnotbe connectedtoVSS on thecircuitboard.Ifa crystalisnotused and theclockinputisdrivendirectly,thentheoscillatorVSS may be connectedtoboardground. (4) These IO specificationsapplytothedual-voltageIOs onlyand do notapplytoDDR2/mDDR orSATA interfaces.DDR2/mDDR IOs are 1.8VIOs and adheretotheJESD79-2A standard.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Recommended OperatingConditions(continued) NAME DESCRIPTION CONDITION MIN NOM MAX UNIT Differential Differentialinputvoltage,SATA_REFCLKP andClockInput 250 2000 mVSATA_REFCLKNVoltage Transition Transitiontime,10%-90%, AllInputs(unlessotherwisett 0.25Por10 (5) nsTime specifiedintheelectricaldatasections) Operating Militarytemperaturegrade CVDD = 1.2VFPLL0_SYSCLK1,6 0 345(6) MHzFrequency (M suffix) operatingpoint (5) Whicheverissmaller.P = theperiodoftheappliedsignal.Maintainingtransitiontimesas fastas possibleisrecommended toimprove noiseimmunityon inputsignals. (6) Thisoperatingpointis300 MHz on revision1.xsilicon. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOperatingConditions 79 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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4.3 Notes on Recommended Power-On Hours (POH)

The informationin the sectionbelow is provided solelyforyour convenience and does not extend or modify thewarrantyprovidedunder TI’s standardterms and conditionsforTIsemiconductor products. To avoidsignificantdegradation,thedevicepower-onhours(POH) must be limitedtothefollowing: Table4-1.Recommended Power-On Hours Silicon OperatingJunction Power-On Hours [POH]Speed Grade Nominal CVDD Voltage(V)Revision Temperature (Tj) (hours) B 345 MHz 0 to105°C 1.2V 100,000 B 345 MHz -55to125°C 1.2V 29,145 The above notationscannot be deemed a warrantyor deemed to extend or modify the warrantyunder TI’s standardterms and conditionsforTIsemiconductor products.

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4.4 ElectricalCharacteristicsOver Recommended Ranges ofSupply Voltageand

OperatingJunctionTemperature (UnlessOtherwiseNoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DVDD= 3.15V,IOH = -4mA 2.4 VHigh-leveloutputvoltage (dual-voltageLVCMOS IOs at3.3V)(1) DVDD= 3.15V,IOH = -100μA 2.95 VVOH High-leveloutputvoltage DVDD= 1.71V,IOH = -2mA DVDD-0.45 V(dual-voltageLVCMOS IOs at1.8V)(1) DVDD= 3.15V,IOL = 4mA 0.4 VLow-leveloutputvoltage (dual-voltageLVCMOS I/Osat3.3V) DVDD= 3.15V,IOL = 100 μA 0.2 VVOL Low-leveloutputvoltage DVDD= 1.71V,IOL = 2mA 0.45 V(dual-voltageLVCMOS I/Osat1.8V) VI= VSS toDVDD without ±9 μAopposinginternalresistor VI = VSS toDVDD with Inputcurrent(1) opposinginternalpullup 70 310 μA (dual-voltageLVCMOS I/Os) resistor(3) II (2) VI = VSS toDVDD with opposinginternalpulldown -75 -270 μA resistor(3) VI = VSS toDVDD with Inputcurrent(DDR2/mDDR I/Os) opposinginternalpulldown -77 -286 μA resistor(3) High-leveloutputcurrent(1) IOH -6 mA(dual-voltageLVCMOS I/Os) Low-leveloutputcurrent(1) IOL 6 mA(dual-voltageLVCMOS I/Os) Inputcapacitance(dual-voltageLVCMOS) 3 pF Capacitance Outputcapacitance(dual-voltageLVCMOS) 3 pF (1) These IO specificationsapplytothedual-voltageIOs onlyand do notapplytoDDR2/mDDR orSATA interfaces.DDR2/mDDR IOs are standard.SATA I/OsadheretotheSATA-I and SATA-IIstandards. (2) IIappliestoinput-onlypinsand bi-directionalpins.Forinput-onlypins,IIindicatestheinputleakagecurrent.Forbi-directionalpins,II indicatestheinputleakagecurrentand off-state(Hi-Z)outputleakagecurrent. (3) Appliesonlytopinswithan internalpullup(IPU)orpulldown(IPD)resistor.The pull-upand pull-downstrengthsshown representthe minimum and maximum strengthacrossprocessvariation. Copyright© 2011–2013,Texas InstrumentsIncorporated DeviceOperatingConditions 81 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

75 85 95 105 115 125 135 145 155 Operating Life Wirebond Life Estimated Life (Hrs) Continuous T (°C)J OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com A. See datasheetforabsolutemaximum and minimum recommended operatingconditions. B. Siliconoperatinglifedesigngoalis10 yearsat105°C junctiontemperature(doesnotincludepackage interconnect life). C. The predictedoperatinglifetimevs.junctiontemperatureisbased on reliabilitymodelingusingelectromigrationas the dominantfailuremechanism affectingdevicewearoutforthespecificdeviceprocessand designcharacteristics. Figure4-1.OMAPL138-EP Operating/WirebondLifeDeratingChart

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Vref =□VIL MAX□(or□VOL MAX) Vref =□VIH MIN□(or□VOH MIN) Vref Transmission□Line 4.0□pF 1.85□pF Z0□=□50 Ω (see□note) Tester Pin□Electronics Data Sheet□Timing□Reference□Point Output Under Test 42 Ω 3.5□nH Device□Pin (see□note) OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013

5 PeripheralInformationand ElectricalSpecifications

5.1 Parameter Information

5.1.1 Parameter InformationDevice-SpecificInformation

A. The data sheet providestimingat the devicepin.For outputtiminganalysis,the testerpin electronicsand its transmissionlineeffectsmust be takenintoaccount.A transmissionlinewitha delayof2 ns orlongercan be used to producethedesiredtransmissionlineeffect.The transmissionlineisintendedas a loadonly.Itisnotnecessaryto add orsubtractthetransmissionlinedelay(2ns orlonger)fromthedatasheettimings. Inputrequirementsinthisdatasheetaretestedwithan inputslewrateof< 4 Voltspernanosecond (4V/ns)atthe devicepinand theinputsignalsaredrivenbetween 0V and theappropriateIO supplyrailforthesignal. Figure5-2.TestLoad CircuitforAC Timing Measurements The loadcapacitancevaluestatedisonlyforcharacterizationand measurement ofAC timingsignals.This loadcapacitancevaluedoes notindicatethemaximum loadthedeviceiscapableofdriving.

5.1.1.1 SignalTransitionLevels

Allinputand outputtimingparametersarereferencedtoVrefforboth"0"and "1"logiclevels. For3.3V I/O,Vref= 1.65V. For1.8V I/O,Vref= 0.9V. For1.2V I/O,Vref= 0.6V. Figure5-3.Inputand Output VoltageReferenceLevelsforAC Timing Measurements Allriseand falltransitiontimingparametersare referencedto VIL MAX and VIH MIN forinputclocks, VOL MAX and VOH MIN foroutputclocks Figure5-4.Rise and FallTransitionTime VoltageReferenceLevels Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 83 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.2 Recommended Clock and ControlSignalTransitionBehavior

Allclocksand controlsignalsmust transitionbetween VIH and VIL (orbetween VIL and VIH)ina monotonic manner.

5.3 Power Supplies

5.3.1 Power-On Sequence

The deviceshouldbe powered-oninthefollowingorder: 1. RTC (RTC_CVDD) may be powered froman externaldevice(suchas a battery)priortoallother suppliesbeingappliedorpowered-upatthesame timeas CVDD. IftheRTC isnotused,RTC_CVDD shouldbe connectedtoCVDD. RTC_CVDD shouldnotbe leftunpowered whileCVDD ispowered. 2. Core logicsupplies: (a) Allvariable1.3V-1.0Vcorelogicsupplies(CVDD) (b) Allstaticcorelogicsupplies(RVDD, PLL0_VDDA, PLL1_VDDA ,USB_CVDD, SATA_VDD). If voltagescalingisnotused on thedevice,groups2a)and 2b)can be controlledfromthesame power supplyand powered up together. 3. Allstatic1.8VIO supplies(DVDD18, DDR_DVDD18 ,USB0_VDDA18, USB1_VDDA18 and SATA_VDDR) and any oftheLVCMOS IO supplygroupsused at1.8Vnominal(DVDD3318_A, DVDD3318_B, orDVDD3318_C). 4. Allanalog3.3VPHY supplies(USB0_VDDA33 and USB1_VDDA33; thesearenotrequiredifboth USB0 and USB1 arenotused)and any oftheLVCMOS IO supplygroupsused at3.3Vnominal (DVDD3318_A, DVDD3318_B, orDVDD3318_C). There isno specificrequiredvoltageramp rateforany ofthesuppliesas longas theLVCMOS supplies operatedat 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed the STATIC 1.8V suppliesby more than2 volts. RESET must be maintainedactiveuntilallpower supplieshave reachedtheirnominalvalues.

5.3.2 Power-OffSequence

The power suppliescan be powered-offin any orderas long as LVCMOS suppliesoperatedat 3.3V (DVDD3318_A, DVDD3318_B, orDVDD3318_C) neverexceed static1.8V suppliesby more than2 volts. There isno specificrequiredvoltageramp down rateforany ofthesupplies(exceptas requiredtomeet theabove mentionedvoltagecondition).

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5.4 Reset

5.4.1 Power-On Reset (POR)

A power-onreset(POR) isrequiredtoplacethedeviceina known good stateafterpower-up.Power-On Reset isinitiatedby bringingRESET and TRST low atthesame time.POR setsallofthedeviceinternal logicto itsdefaultstate.Allpinsare tri-statedwiththe exceptionof RESETOUT which remainsactive throughthe resetsequence.RESETOUT isan outputforuse by othercontrollersin the system that indicatesthedeviceiscurrentlyinreset. RTCK ismaintainedactivethrougha POR. A summary oftheeffectsofPower-On Resetisgivenbelow:

Allinternallogic(includingemulationlogicand thePLL logic)isresettoitsdefaultstate
Internalmemory isnotmaintainedthrougha POR
RESETOUT goes active
Alldevicepinsgo toa high-impedancestate
The RTC peripheralisnotresetduringa POR. A softwaresequence isrequiredtoresettheRTC A watchdogresettriggersa POR.

5.4.2 Warm Reset

A warm resetprovidesa limitedresettothedevice.Warm Reset isinitiatedby bringingonlyRESET low (TRST ismaintainedhighthrougha warm reset).Warm resetsetscertainportionsofthedevicetotheir defaultstatewhileleavingothersunaltered.Allpinsaretri-statedwiththeexceptionofRESETOUT which remainsactivethroughtheresetsequence.RESETOUT isan outputforuse by othercontrollersinthe systemthatindicatesthedeviceiscurrentlyinreset. RTCK ismaintainedactivethrougha POR. A summary oftheeffectsofWarm Resetisgivenbelow:

Allinternallogic(exceptfortheemulationlogicand thePLL logic)isresettoitsdefaultstate
Internalmemory ismaintainedthrougha warm reset
RESETOUT goes active
Alldevicepinsgo toa high-impedancestate
The RTC peripheralisnot resetduringa warm reset.A softwaresequence isrequiredto resetthe RTC Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 85 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

Ramping Power Supplies Stable Clock Source Stable 2 3 TRST OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com

5.4.3 Reset ElectricalData Timings

Table5-1assumes testingovertherecommended operatingconditions. Table5-1.Reset Timing Requirements(1)(2)(3) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 1 tw(RSTL) Pulsewidth,RESET/ TRST low 100 100 100 ns 2 tsu(BPV-RSTH) Setuptime,bootpinsvalidbeforeRESET/ TRST high 20 20 20 ns 3 th(RSTH-BPV) Holdtime,bootpinsvalidafterRESET/ TRST high 20 20 20 ns td(RSTH-RESETOUTH) RESET hightoRESETOUT high;Warm reset 4096 4096 4096 cycles(4) RESET hightoRESETOUT high;Power-onReset 6169 6169 6169 5 td(RSTL-RESETOUTL) Delaytime,RESET/ TRST lowtoRESETOUT low 14 16 20 ns (1) RESETOUT ismultiplexedwithotherpinfunctions.See theTerminalFunctionstable,Table2-5fordetails. (2) Forpower-onreset(POR),theresettimingsinthistablerefertoRESET and TRST together.Forwarm reset,theresettimingsinthis tablerefertoRESET only(TRST isheldhigh). (3) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (4) OSCIN cycles. Figure5-5.Power-On Reset (RESET and TRST active)Timing

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Boot□Pins Config Power□Supplies□Stable 2 3 Driven□or□Hi-Z OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-6.Warm Reset (RESET active,TRST high)Timing Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 87 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

Clock□Input to□PLL OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com

5.5 CrystalOscillatoror ExternalClock Input

The deviceincludestwo choicestoprovidean externalclockinput,which isfedtotheon-chipPLLs to generatehigh-frequencysystem clocks.These optionsare illustratedinFigure5-7 and Figure5-8. For inputclockfrequenciesbetween 12 and 20 MHz, a crystalwith80 ohm max ESR isrecommended. For inputclockfrequenciesbetween 20 and 30 MHz, a crystalwith60 ohm max ESR isrecommended. Typicalloadcapacitancevaluesare10-20pF,where theloadcapacitanceistheseriescombinationofC1 and C2. The CLKMODE bitinthePLLCTL registermust be 0 touse theon-chiposcillator.IfCLKMODE issetto1, theinternaloscillatorisdisabled. Figure5-7 illustratesthe optionthatuses on-chip1.2V oscillatorwithexternalcrystalcircuit.Figure5-8 illustratestheoptionthatuses an external1.2Vclockinput. Figure5-7.On-Chip Oscillator Table5-2.OscillatorTiming Requirements(1) PARAMETER MIN MAX UNIT fosc Oscillatorfrequencyrange(OSCIN/OSCOUT) 12 30 MHz (1) Crystaloscillatorcannotbe operatedbeyond 105°C.

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to□PLL NC OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-8.External1.2VClock Source Table5-3.OSCIN Timing Requirements foran ExternallyDrivenClock(1) PARAMETER MIN MAX UNIT fOSCIN OSCIN frequencyrange 12 50 MHz tc(OSCIN) Cycletime,externalclockdrivenon OSCIN 20 ns tw(OSCINH) Pulsewidthhigh,externalclockon OSCIN 0.4tc(OSCIN) ns tw(OSCINL) Pulsewidthlow,externalclockon OSCIN 0.4tc(OSCIN) ns tt(OSCIN) Transitiontime,OSCIN 0.25Por10 (2) ns tj(OSCIN) Periodjitter,OSCIN 0.02P ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) Whicheverissmaller.P = theperiodoftheappliedsignal.Maintainingtransitiontimesas fastas possibleisrecommended toimprove noiseimmunityon inputsignals.

5.6 Clock PLLs

The devicehas two PLL controllersthatprovideclocksto differentpartsof the system.PLL0 provides clocks(thoughvariousdividers)to most of the components of the device.PLL1 providesclocksto the mDDR/DDR2 Controllerand providesan alternateclocksourcefortheASYNC3 clockdomain.Thisallows theperipheralson theASYNC3 clockdomain tobe immune tofrequencyscalingoperationon PLL0. The PLL controllerprovidesthefollowing:

Glitch-FreeTransitions(onchangingclocksettings)
Domain ClocksAlignment
ClockGating
PLL power down The variousclockoutputsgivenby thecontrollerareas follows:
Domain Clocks:SYSCLK [1:n]
AuxiliaryClockfromreferenceclocksource:AUXCLK Variousdividersthatcan be used areas follows:
Post-PLLDivider:POSTDIV
SYSCLK Divider:D1, ¼ ,Dn Variousothercontrolssupportedareas follows:
PLL MultiplierControl:PLLM
SoftwareprogrammablePLL Bypass:PLLEN Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 89 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

0.1 µF 0.01 µF 50R1.14V - 1.32V 50RVSS PLL1_VDDA PLL1_VSSA Ferrite Bead: Murata BLM31PG500SN1L or Equivalent 0.1 µF 0.01 µF 50R1.14V - 1.32V 50RVSS PLL0_VDDA PLL0_VSSA OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com

5.6.1 PLL Device-SpecificInformation

The deviceDSP generatesthehigh-frequencyinternalclocksitrequiresthroughan on-chipPLL. The PLL requiressome externalfilteringcomponents toreducepower supplynoiseas shown inFigure5- Figure5-9.PLL ExternalFilteringComponents The externalfilteringcomponents shown above providenoiseimmunityforthe PLLs. PLL0_VDDA and PLL1_VDDA should not be connected togetherto providenoise immunity between the two PLLs. Likewise,PLL0_VSSA and PLL1_VSSA shouldnotbe connectedtogether. The inputtothePLL iseitherfromtheon-chiposcillatororfroman externalclockon theOSCIN pin.PLL0 outputsseven clocksthathave programmable divideroptions.PLL1 outputsthreeclocksthathave programmabledivideroptions.Figure5-10illustratesthehigh-levelviewofthePLL Topology. The PLLs aredisabledby defaultaftera devicereset.They must be configuredby softwareaccordingto theallowableoperatingconditionslistedinTable5-4 beforeenablingthedevicetorun from thePLL by settingPLLEN = 1.

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PLLDIV1 (/1) SYSCLK1 PLLDIV2 (/2) SYSCLK2 PLLDIV4 (/4) SYSCLK4 PLLDIV5 (/3) SYSCLK5 PLLDIV6 (/1) SYSCLK6 PLLDIV7 (/6) SYSCLK7 DIV4.5 1

0 EMIFA

CFGCHIP3[EMA_CLKSRC] PREDIV PLLM Square Wave Crystal PLL1_SYSCLK3 PLLCTL[EXTCLKSRC] AUXCLK PLL PLLDIV3 (/3) SYSCLK3 DDR2/mDDR Internal Clock Source PLLDIV2 (/2) PLLDIV3 (/3) PLLDIV1 (/1) PLLCTL[PLLEN] POSTDIV PLLM PLL PLLCTL[PLLEN] PLLCTL[CLKMODE] POSTDIV PLLC0 OBSCLK (CLKOUT Pin) DIV4.5 OSCDIV PLL Controller 0 PLL Controller 1 SYSCLK2 SYSCLK3 SYSCLK1 OSCIN 14h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 SYSCLK5 SYSCLK6 SYSCLK7 PLLC1 OBSCLK OCSEL[OCSRC] 14h 17h 18h 19h SYSCLK1 SYSCLK2 SYSCLK3 OCSEL[OCSRC] OSCDIV PLLC1 OBSCLK OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-10.PLL Topology Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 91 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

2000 NMax PLL Lock Time =

m where N = Pre-Divider Ratio M = PLL Multiplier OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-4.Allowed PLL OperatingConditions(PLL0 and PLL1) DefaultNO. PARAMETER MIN MAX UNITValue

1 PLLRST :Assertiontimeduringinitialization N/A 1000 N/A ns

Lock time:The timethattheapplicationhas towaitfor OSCIN2 thePLL toacquirelockbeforesettingPLLEN, after N/A N/A cycleschangingPREDIV, PLLM, orOSCIN (1)

3 PREDIV :Pre-dividervalue /1 /1 /32 -

30 (ifinternaloscillatorisused)4 PLLREF :PLL inputfrequency 12 MHz50 (ifexternalclockisused)

5 PLLM :PLL multipliervalues x20 x4 x32

6 PLLOUT :PLL outputfrequency N/A 300 600 MHz

7 POSTDIV :Post-dividervalue /1 /1 /32 -

(1) The multipliervaluesmust be chosen such thatthePLL outputfrequency(atPLLOUT) isbetween300 and 600 MHz, butthefrequency goingintotheSYSCLK dividers(afterthepostdivider)cannotexceed themaximum clockfrequencydefinedforthedeviceata given voltageoperatingpoint.

5.6.2 Device Clock Generation

PLL0 iscontrolledby PLL Controller0 and PLL1 iscontrolledby PLL Controller1. PLLC0 and PLLC1 manage the clockratios,alignment,and gatingforthe system clocksto the chip.The PLLCs are responsibleforcontrollingallmodes of the PLL throughsoftware,interms of pre-divisionof the clock inputs(PLLC0 only),multiplyfactorswithinthePLLs, and post-divisionforeach ofthechip-levelclocks fromthePLLs outputs.PLLC0 alsocontrolsresetpropagationthroughthechip,clockalignment,and test points. PLLC0 providesclocksforthe majorityof the system but PLLC1 providesclocksto the mDDR/DDR2 Controllerand the ASYNC3 clockdomain to providefrequencyscalingimmunityto a definedset or peripherals.The ASYNC3 clockdomain can eitherderiveitsclockfrom PLL1_SYSCLK2 (forfrequency scalingimmunityfrom PLL0) or from PLL0_SYSCLK2 (forsynchronoustimingwithPLL0) dependingon theapplicationrequirements.Inaddition,some peripheralshave specificclockoptionsindependentofthe ASYNC clockdomain.

5.6.3 Dynamic Voltageand Frequency Scaling(DVFS)

The processorsupportsmultipleoperatingpointsby scalingvoltageand frequencyto minimizepower consumptionfora givenlevelofprocessorperformance. Frequency scalingisachievedby modifyingthe settingof the PLL controllers’multipliers,post-dividers (POSTDIV), and system clockdividers(SYSCLKn). Modificationof the POSTDIV and SYSCLK values does notrequirerelockingthePLL and provideslowerlatencytoswitchbetween operatingpoints,butat the expense of the frequenciesbeing limitedby the integerdividevalues(onlythe dividevaluesare alteredthe PLL multiplierisleftunmodified).Non integerdividefrequencyvaluescan be achievedby changingboththemultiplierand thedividevalues,butwhen thePLL multiplierischanged thePLL must relock,incurringadditionallatencytochange between operatingpoints.Detailedinformationon modifying thePLL Controllersettingscan be foundintheOMAPL138 C6-IntegraDSP+ARM TechnicalReference Manual (SPRUH77 ).

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Voltagescalingis enabled from outsidethe deviceby controllingan externalvoltageregulator.The processormay communicate withtheregulatorusingGPIOs, I2C orsome otherinterface.When switching between voltage-frequencyoperatingpoints,the voltagemust always supportthe desiredfrequency. When moving from a high-performanceoperatingpointto a lower performanceoperatingpoint,the frequencyshouldbe loweredfirstfollowedby thevoltage.When moving froma low-performanceoperating pointtoa higherperformanceoperatingpoint,thevoltageshouldbe raisedfirstfollowedby thefrequency. VoltageoperatingpointsrefertotheCVdd voltageatthatpoint.Otherstaticsuppliesmust be maintained attheirnominalvoltagesatalloperatingpoints. The maximum voltageslewrateforCVdd supplychanges is1 mV/us. For additionalinformationon power management solutionsfrom TI forthisprocessor,followthe Power Management linkintheProductFolderon www.ti.comforthisprocessor. The processorsupportsmultipleclockdomains some of which have clockratiorequirementsto each other.SYSCLK1:SYSCLK2:SYSCLK4:SYSCLK6 are synchronous to each other and the SYSCLKn dividersmust alwaysbe configuredsuch thattheratiobetween thesedomains is1:2:4:1.The ASYNC and ASYNC3 clockdomains are asynchronous to the otherclockdomains and have no specificratio requirement. Table5-5summarizesthemaximum internalclockfrequenciesateach ofthevoltageoperatingpoints. Table5-5.Maximum InternalClock FrequenciesatEach VoltageOperatingPoint CLOCK SOURCE CLOCK DOMAIN 1.2VNOM PLL0_SYSCLK1 DSP subsystem 345 MHz SYSCLK2 clockdomain peripheralsand optionalclocksourceforASYNC3 clockdomainPLL0_SYSCLK2 187.5MHzperipherals OptionalclockforASYNC1 clockdomainPLL0_SYSCLK3 (See ASYNC1 row) PLL0_SYSCLK4 SYSCLK4 domain peripherals 93.75MHz PLL0_SYSCLK5 Not used on thisprocessor - PLL0_SYSCLK6 ARM subsystem 345 MHz PLL0_SYSCLK7 Optional50 MHz clocksourceforEMAC RMII interface 50 MHz DDR2/mDDR InterfaceclocksourcePLL1_SYSCLK1 312 MHz(memory interfaceclockisone-halfofthevalueshown) PLL1_SYSCLK2 OptionalclocksourceforASYNC3 clockdomain peripherals 150 MHz PLL1_SYSCLK3 AlternateclocksourceinputtoPLL Controller0 75 MHz McASP AUXCLK Bypass clocksourcefortheMcASP 50 MHz PLL0_AUXCLK Bypass clocksourcefortheUSB0 and USB1 48 MHz Async Mode 148 MHz ASYNC1 ASYNC ClockDomain (EMIFA) SDRAM Mode 100 MHz ASYNC2 ASYNC2 ClockDomain (multipleperipherals) 50 MHz ASYNC3 ASYNC3 ClockDomain (multipleperipherals) 150 MHz Some interfaceshave specificlimitationson supportedmodes/speeds at each operatingpoint.See the correspondingperipheralsectionsofthisdocument formore information. TIprovidessoftwarecomponents (calledthePower Manager) toperformDVFS and abstractthetaskfrom the user.The Power Manager controlschanging operatingpoints(bothfrequencyand voltage)and handlestherelatedtasksinvolvedsuch as informing/controllingperipheralstoprovidegracefultransitions between operatingpoints.The Power Manager isbundledas a component ofDSP/BIOS. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 93 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.7 Interrupts

The devicehas a largenumber ofinterruptstoservicetheneeds ofitsmany peripheralsand subsystems. Both theARM and C674x CPUs are capableofservicingtheseinterruptsequally.The interruptscan be selectivelyenabledordisabledineitherofthecontrollers.Also,theARM and DSP can communicate with each otherthroughinterruptscontrolledby registersintheSYSCFG module.

5.7.1 ARM CPU Interrupts

The ARM9 CPU coresupportstwo directinterrupts:FIQ and IRQ. The ARM InterruptController(AINTC) extends the number of interruptsto 100, and providesfeatureslikeprogrammable masking,priority, hardwarenestingsupport,and interruptvectorgeneration.

5.7.1.1 ARM InterruptController(AINTC)InterruptSignalHierarchy

The ARM Interruptcontrollerorganizesinterruptsintothefollowinghierarchy:

PeripheralInterruptRequests – IndividualInterruptSourcesfromPeripherals
101 System Interrupts – One or more PeripheralInterruptRequests are combined (fixedconfiguration)to generatea System Interrupt. – Afterprioritization,theAINTC willprovidean interruptvectorbased uniquetoeach System Interrupt
32 InterruptChannels – Each System Interruptismapped toone ofthe32 InterruptChannels – Channel Number determinesthe firstlevelof prioritization,Channel 0 ishighestpriorityand 31 lowest. – Ifmore thanone system interruptismapped toa channel,prioritywithinthechannelisdetermined by systeminterruptnumber (0highestpriority)
HostInterrupts(FIQand IRQ) – InterruptChannels0 and 1 generatetheARM FIQ interrupt – InterruptChannels2 through31 GeneratetheARM IRQ interrupt
Debug Interrupts – Two Debug Interruptsaresupportedand can be used totriggereventsinthedebug subsystem – Sourcescan be selectedfromany oftheSystem InterruptsorHostInterrupts

5.7.1.2 AINTC Hardware VectorGeneration

The AINTC alsogeneratesan interruptvectorinhardwareforbothIRQ and FIQ hostinterrupts.Thismay be used to accelerateinterruptdispatch.A unique vectoris generatedforeach of the 100 system interrupts.The vectoriscomputed inhardwareas: VECTOR = BASE + (SYSTEM INTERRUPT NUMBER × SIZE) Where BASE and SIZE are programmable. The computed vectoris a 32-bitaddress which may dispatchedtousinga singleinstructionoftypeLDR PC, [PC,#-<offset_12>]attheFIQ and IRQ vector locations(0xFFFF0018 and 0xFFFF001C respectively).

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5.7.1.3 AINTC Hardware InterruptNestingSupport

Interruptnestingoccurs when an interruptserviceroutinere-enablesinterrupts,to allowthe CPU to interruptthe ISR ifa higherpriorityevent occurs.The AINTC provideshardware supportto facilitate interruptnesting.Itsupportsboth globaland per host interrupt(FIQ and IRQ in thiscase) automatic nesting.Ifenabled,theAINTC willautomaticallyupdatean internalnestingregisterthattemporarilymasks interruptsatand below thepriorityofthecurrentinterruptchannel.Then iftheISR re-enablesinterrupts; onlyhigherprioritychannelswillbe abletointerruptit.The nestinglevelisrestoredby theISR by writing tothenestinglevelregisteron completion.Supportfornestingcan be enabled/disabledby software,with theoptionofautomaticnestingon a globalorperhostinterruptbasis;ormanual nesting.

5.7.1.4 AINTC System InterruptAssignments

Table5-6.AINTC System InterruptAssignments System Interrupt InterruptName Source

0 COMMTX ARM

1 COMMRX ARM

2 NINT ARM

3 PRU_EVTOUT0 PRUSS Interrupt

4 PRU_EVTOUT1 PRUSS Interrupt

5 PRU_EVTOUT2 PRUSS Interrupt

6 PRU_EVTOUT3 PRUSS Interrupt

7 PRU_EVTOUT4 PRUSS Interrupt

8 PRU_EVTOUT5 PRUSS Interrupt

9 PRU_EVTOUT6 PRUSS Interrupt

10 PRU_EVTOUT7 PRUSS Interrupt

11 EDMA3_0_CC0_INT0 EDMA3_0 ChannelController0 Shadow Region0 Transfer

12 EDMA3_0_CC0_ERRINT EDMA3_0 ChannelController0 ErrorInterrupt

13 EDMA3_0_TC0_ERRINT EDMA3_0 TransferController0 ErrorInterrupt

14 EMIFA_INT EMIFA

15 IIC0_INT I2C0

16 MMCSD0_INT0 MMCSD0 MMC/SD Interrupt

17 MMCSD0_INT1 MMCSD0 SDIO Interrupt

18 PSC0_ALLINT PSC0

19 RTC_IRQS[1:0] RTC

20 SPI0_INT SPI0

21 T64P0_TINT12 Timer64P0 Interrupt12

22 T64P0_TINT34 Timer64P0 Interrupt34

23 T64P1_TINT12 Timer64P1 Interrupt12

24 T64P1_TINT34 Timer64P1 Interrupt34

25 UART0_INT UART0

27 PROTERR SYSCFG ProtectionShared Interrupt

28 SYSCFG_CHIPINT0 SYSCFG CHIPSIG Register

29 SYSCFG_CHIPINT1 SYSCFG CHIPSIG Register

30 SYSCFG_CHIPINT2 SYSCFG CHIPSIG Register

31 SYSCFG_CHIPINT3 SYSCFG CHIPSIG Register

32 EDMA3_0_TC1_ERRINT EDMA3_0 TransferController1 ErrorInterrupt

33 EMAC_C0RXTHRESH EMAC -Core 0 ReceiveThresholdInterrupt

34 EMAC_C0RX EMAC -Core 0 ReceiveInterrupt

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-6.AINTC System InterruptAssignments (continued) System Interrupt InterruptName Source

35 EMAC_C0TX EMAC -Core 0 TransmitInterrupt

36 EMAC_C0MISC EMAC -Core 0 MiscellaneousInterrupt

37 EMAC_C1RXTHRESH EMAC -Core 1 ReceiveThresholdInterrupt

38 EMAC_C1RX EMAC -Core 1 ReceiveInterrupt

39 EMAC_C1TX EMAC -Core 1 TransmitInterrupt

40 EMAC_C1MISC EMAC -Core 1 MiscellaneousInterrupt

41 DDR2_MEMERR DDR2 Controller

42 GPIO_B0INT GPIO Bank 0 Interrupt

43 GPIO_B1INT GPIO Bank 1 Interrupt

44 GPIO_B2INT GPIO Bank 2 Interrupt

45 GPIO_B3INT GPIO Bank 3 Interrupt

46 GPIO_B4INT GPIO Bank 4 Interrupt

47 GPIO_B5INT GPIO Bank 5 Interrupt

48 GPIO_B6INT GPIO Bank 6 Interrupt

49 GPIO_B7INT GPIO Bank 7 Interrupt

50 GPIO_B8INT GPIO Bank 8 Interrupt

51 IIC1_INT I2C1

52 LCDC_INT LCD Controller

53 UART_INT1 UART1

54 MCASP_INT McASP0 Combined RX /TX Interrupts

55 PSC1_ALLINT PSC1

56 SPI1_INT SPI1

57 UHPI_ARMINT UHPI ARM Interrupt

58 USB0_INT USB0 Interrupt

59 USB1_HCINT USB1 OHCI HostControllerInterrupt

60 USB1_RWAKEUP USB1 Remote Wakeup Interrupt

61 UART2_INT UART2

63 EHRPWM0 HiResTimer/PWM0 Interrupt

64 EHRPWM0TZ HiResTimer/PWM0 TripZone Interrupt

65 EHRPWM1 HiResTimer/PWM1 Interrupt

66 EHRPWM1TZ HiResTimer/PWM1 TripZone Interrupt

67 SATA_INT SATA Controller

68 T64P2_ALL Timer64P2 -Combined TINT12 and TINT34

69 ECAP0 ECAP0

70 ECAP1 ECAP1

71 ECAP2 ECAP2

72 MMCSD1_INT0 MMCSD1 MMC/SD Interrupt

73 MMCSD1_INT1 MMCSD1 SDIO Interrupt

74 T64P2_CMPINT0 Timer64P2 -Compare 0

75 T64P2_CMPINT1 Timer64P2 -Compare 1

76 T64P2_CMPINT2 Timer64P2 -Compare 2

77 T64P2_CMPINT3 Timer64P2 -Compare 3

78 T64P2_CMPINT4 Timer64P2 -Compare 4

79 T64P2_CMPINT5 Timer64P2 -Compare 5

80 T64P2_CMPINT6 Timer64P2 -Compare 6

81 T64P2_CMPINT7 Timer64P2 -Compare 7

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-6.AINTC System InterruptAssignments (continued) System Interrupt InterruptName Source

82 T64P3_CMPINT0 Timer64P3 -Compare 0

83 T64P3_CMPINT1 Timer64P3 -Compare 1

84 T64P3_CMPINT2 Timer64P3 -Compare 2

85 T64P3_CMPINT3 Timer64P3 -Compare 3

86 T64P3_CMPINT4 Timer64P3 -Compare 4

87 T64P3_CMPINT5 Timer64P3 -Compare 5

88 T64P3_CMPINT6 Timer64P3 -Compare 6

89 T64P3_CMPINT7 Timer64P3 -Compare 7

90 ARMCLKSTOPREQ PSC0

91 uPP_ALLINT uPP Combined Interrupt

ChannelIEnd-of-LineInterrupt
ChannelIEnd-of-WindowInterrupt
ChannelIDMA Access Interrupt
ChannelIOverflow-UnderrunInterrupt
ChannelIDMA Programming ErrorInterrupt
ChannelQ End-of-LineInterrupt
ChannelQ End-of-WindowInterrupt
ChannelQ DMA Access Interrupt
ChannelQ Overflow-UnderrunInterrupt
ChannelQ DMA Programming ErrorInterrupt

92 VPIF_ALLINT VPIF Combined Interrupt

Channel0 Frame Interrupt
Channel1 Frame Interrupt
Channel2 Frame Interrupt
Channel3 Frame Interrupt
ErrorInterrupt

93 EDMA3_1_CC0_INT0 EDMA3_1 ChannelController0 Shadow Region0 Transfer

94 EDMA3_1_CC0_ERRINT EDMA3_1Channel Controller0 ErrorInterrupt

95 EDMA3_1_TC0_ERRINT EDMA3_1 TransferController0 ErrorInterrupt

96 T64P3_ALL Timer64P 3 -Combined TINT12 and TINT34

97 MCBSP0_RINT McBSP0 ReceiveInterrupt

98 MCBSP0_XINT McBSP0 TransmitInterrupt

99 MCBSP1_RINT McBSP1 ReceiveInterrupt

100 MCBSP1_XINT McBSP1 TransmitInterrupt

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5.7.1.5 AINTC Memory Map

Table5-7.AINTC Memory Map BYTE ADDRESS ACRONYM DESCRIPTION 0xFFFE E000 REV RevisionRegister 0xFFFE E004 CR ControlRegister 0xFFFE E008 -0xFFFE E00F - Reserved 0xFFFE E010 GER GlobalEnableRegister 0xFFFE E014 -0xFFFE E01B - Reserved 0xFFFE E01C GNLR GlobalNestingLevelRegister 0xFFFE E020 SISR System InterruptStatusIndexedSetRegister 0xFFFE E024 SICR System InterruptStatusIndexedClearRegister 0xFFFE E028 EISR System InterruptEnableIndexedSetRegister 0xFFFE E02C EICR System InterruptEnableIndexedClearRegister 0xFFFE E030 - Reserved 0xFFFE E034 HIEISR HostInterruptEnableIndexedSetRegister 0xFFFE E038 HIEICR HostInterruptEnableIndexedClearRegister 0xFFFE E03C -0xFFFE E04F - Reserved 0xFFFE E050 VBR VectorBase Register 0xFFFE E054 VSR VectorSizeRegister 0xFFFE E058 VNR VectorNullRegister 0xFFFE E05C -0xFFFE E07F - Reserved 0xFFFE E080 GPIR GlobalPrioritizedIndexRegister 0xFFFE E084 GPVR GlobalPrioritizedVectorRegister 0xFFFE E088 -0xFFFE E1FF - Reserved 0xFFFE E200 SRSR[1] System InterruptStatusRaw /SetRegisters 0xFFFE E204 SRSR[2] 0xFFFE E208 SRSR[3] 0xFFFE E20C SRSR[4] 0xFFFE E210- 0xFFFE E27F - Reserved 0xFFFE E280 SECR[1] System InterruptStatusEnabled/ClearRegisters 0xFFFE E284 SECR[2] 0xFFFE E288 SECR[3] 0xFFFE E28C SECR[4] 0xFFFE E290 -0xFFFE E2FF - Reserved 0xFFFE E300 ESR[1] System InterruptEnableSetRegisters 0xFFFE E304 ESR[2] 0xFFFE E308 ESR[3] 0xFFFE E30C ESR[4] 0xFFFE E310 -0xFFFE E37F - Reserved 0xFFFE E380 ECR[1] System InterruptEnableClearRegisters 0xFFFE E384 ECR[2] 0xFFFE E388 ECR[3] 0xFFFE E38C ECR[4] 0xFFFE E390 -0xFFFE E3FF - Reserved

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-7.AINTC Memory Map (continued) BYTE ADDRESS ACRONYM DESCRIPTION 0xFFFE E400 -0xFFFE E45B CMR[0] ChannelMap Registers 0xFFFE E404 CMR[1] 0xFFFE E408 CMR[2] 0xFFFE E40C CMR[3] 0xFFFE E410 CMR[4] 0xFFFE E414 CMR[5] 0xFFFE E418 CMR[6] 0xFFFE E41C CMR[7] 0xFFFE E420 CMR[8] 0xFFFE E424 CMR[9] 0xFFFE E428 CMR[10] 0xFFFE E42C CMR[11] 0xFFFE E430 CMR[12] 0xFFFE E434 CMR[13] 0xFFFE E438 CMR[14] 0xFFFE E43C CMR[15] 0xFFFE E440 CMR[16] 0xFFFE E444 CMR[17] 0xFFFE E448 CMR[18] 0xFFFE E44C CMR[19] 0xFFFE E450 CMR[20] 0xFFFE E454 CMR[21] 0xFFFE E458 CMR[22] 0xFFFE E45C CMR[23] 0xFFFE E460 CMR[24] 0xFFFE E464 CMR[25] 0xFFFE E468 -0xFFFE E8FF - Reserved 0xFFFE E900 HIPIR[1] HostInterruptPrioritizedIndexRegisters 0xFFFE E904 HIPIR[2] 0xFFFE E908 -0xFFFE F0FF - Reserved 0xFFFE F100 HINLR[1] HostInterruptNestingLevelRegisters 0xFFFE F104 HINLR[2] 0xFFFE F108 -0xFFFE F4FF - Reserved 0xFFFE F500 HIER HostInterruptEnableRegister 0xFFFE F504 -0xFFFE F5FF - Reserved 0xFFFE F600 HIPVR[1] HostInterruptPrioritizedVectorRegisters 0xFFFE F604 HIPVR[2] 0xFFFE F608 -0xFFFE FFFF - Reserved Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 99 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.7.2 DSP Interrupts

The C674x DSP interruptcontrollercombines deviceeventsinto12 prioritizedinterrupts.The sourcefor each of the 12 CPU interruptsis user programmable and is listedin Table 5-8. Also,the interrupt controllercontrolsthe generationof the CPU exceptions,NMI, and emulationinterrupts.Table 5-9 summarizestheC674x interruptcontrollerregistersand memory locations. Referto theC674x DSP MegaModule ReferenceGuide (SPRUFK5 ) and the TMS320C674x DSP CPU and InstructionSetReferenceGuide (SPRUFE8 )fordetailsoftheC674x interrupts. Table5-8.OMAPL138 DSP Interrupts EVT# InterruptName Source

0 EVT0 C674x IntCtl0

1 EVT1 C674x IntCtl1

2 EVT2 C674x IntCtl2

3 EVT3 C674x IntCtl3

4 T64P0_TINT12 Timer64P0 -TINT12

5 SYSCFG_CHIPINT2 SYSCFG CHIPSIG Register

6 PRU_EVTOUT0 PRUSS Interrupt

7 EHRPWM0 HiResTimer/PWM0 Interrupt

8 EDMA3_0_CC0_INT1 EDMA3_0 ChannelController0 Shadow Region1 Transfer

9 EMU_DTDMA C674x-ECM

10 EHRPWM0TZ HiResTimer/PWM0 TripZone Interrupt

11 EMU_RTDXRX C674x-RTDX

12 EMU_RTDXTX C674x-RTDX

13 IDMAINT0 C674x-EMC

14 IDMAINT1 C674x-EMC

15 MMCSD0_INT0 MMCSD0 MMC/SD Interrupt

16 MMCSD0_INT1 MMCSD0 SDIO Interrupt

17 PRU_EVTOUT1 PRUSS Interrupt

18 EHRPWM1 HiResTimer/PWM1 Interrupt

19 USB0_INT USB0 Interrupt

20 USB1_HCINT USB1 OHCI HostControllerInterrupt

21 USB1_RWAKEUP USB1 Remote Wakeup Interrupt

22 PRU_EVTOUT2 PRUSS Interrupt

23 EHRPWM1TZ HiResTimer/PWM1 TripZone Interrupt

24 SATA_INT SATA Controller

25 T64P2_TINTALL Timer64P2 Combined TINT12 and TINT 34 Interrupt

26 EMAC_C0RXTHRESH EMAC -Core 0 ReceiveThresholdInterrupt

27 EMAC_C0RX EMAC -Core 0 ReceiveInterrupt

28 EMAC_C0TX EMAC -Core 0 TransmitInterrupt

29 EMAC_C0MISC EMAC -Core 0 MiscellaneousInterrupt

30 EMAC_C1RXTHRESH EMAC -Core 1 ReceiveThresholdInterrupt

31 EMAC_C1RX EMAC -Core 1 ReceiveInterrupt

32 EMAC_C1TX EMAC -Core 1 TransmitInterrupt

33 EMAC_C1MISC EMAC -Core 1 MiscellaneousInterrupt

34 UHPI_DSPINT UHPI DSP Interrupt

35 PRU_EVTOUT3 PRUSS Interrupt

36 IIC0_INT I2C0

37 SP0_INT SPI0

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38 UART0_INT UART0

39 PRU_EVTOUT5 PRUSS Interrupt

40 T64P1_TINT12 Timer64P1 Interrupt12

41 GPIO_B1INT GPIO Bank 1 Interrupt

42 IIC1_INT I2C1

43 SPI1_INT SPI1

44 PRU_EVTOUT6 PRUSS Interrupt

45 ECAP0 ECAP0

46 UART_INT1 UART1

47 ECAP1 ECAP1

48 T64P1_TINT34 Timer64P1 Interrupt34

49 GPIO_B2INT GPIO Bank 2 Interrupt

50 PRU_EVTOUT7 PRUSS Interrupt

51 ECAP2 ECAP2

52 GPIO_B3INT GPIO Bank 3 Interrupt

53 MMCSD1_INT1 MMCSD1 SDIO Interrupt

54 GPIO_B4INT GPIO Bank 4 Interrupt

55 EMIFA_INT EMIFA

56 EDMA3_0_CC0_ERRINT EDMA3_0 ChannelController0 ErrorInterrupt

57 EDMA3_0_TC0_ERRINT EDMA3_0 TransferController0 ErrorInterrupt

58 EDMA3_0_TC1_ERRINT EDMA3_0 TransferController1 ErrorInterrupt

59 GPIO_B5INT GPIO Bank 5 Interrupt

60 DDR2_MEMERR DDR2 Memory ErrorInterrupt

61 MCASP0_INT McASP0 Combined RX/TX Interrupts

62 GPIO_B6INT GPIO Bank 6 Interrupt

63 RTC_IRQS RTC Combined

64 T64P0_TINT34 Timer64P0 Interrupt34

65 GPIO_B0INT GPIO Bank 0 Interrupt

66 PRU_EVTOUT4 PRUSS Interrupt

67 SYSCFG_CHIPINT3 SYSCFG_CHIPSIG Register

68 MMCSD1_INT0 MMCSD1 MMC/SD Interrupt

69 UART2_INT UART2

70 PSC0_ALLINT PSC0

71 PSC1_ALLINT PSC1

72 GPIO_B7INT GPIO Bank 7 Interrupt

73 LCDC_INT LDC Controller

74 PROTERR SYSCFG ProtectionShared Interrupt

75 GPIO_B8INT GPIO Bank 8 Interrupt

78 T64P2_CMPINT0 Timer64P2 -Compare Interrupt0

79 T64P2_CMPINT1 Timer64P2 -Compare Interrupt1

80 T64P2_CMPINT2 Timer64P2 -Compare Interrupt2

81 T64P2_CMPINT3 Timer64P2 -Compare Interrupt3

82 T64P2_CMPINT4 Timer64P2 -Compare Interrupt4

83 T64P2_CMPINT5 Timer64P2 -Compare Interrupt5

84 T64P2_CMPINT6 Timer64P2 -Compare Interrupt6

85 T64P2_CMPINT7 Timer64P2 -Compare Interrupt7

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-8.OMAPL138 DSP Interrupts(continued) EVT# InterruptName Source

86 T64P3_TINTALL Timer64P3 Combined TINT12 and TINT 34 Interrupt

87 MCBSP0_RINT McBSP0 ReceiveInterrupt

88 MCBSP0_XINT McBSP0 TransmitInterrupt

89 MCBSP1_RINT McBSP1 ReceiveInterrupt

90 MCBSP1_XINT McBSP1 TransmitInterrupt

91 EDMA3_1_CC0_INT1 EDMA3_1 ChannelController0 Shadow Region1 Transfer

92 EDMA3_1_CC0_ERRINT EDMA3_1 ChannelController0 ErrorInterrupt

93 EDMA3_1_TC0_ERRINT EDMA3_1 TransferController0 ErrorInterrupt

94 UPP_INT uPP Combined Interrupt

95 VPIF_INT VPIF Combined Interrupt

96 INTERR C674x-IntCtl

97 EMC_IDMAERR C674x-EMC

113 PMC_ED C674x-PMC

116 UMC_ED1 C674x-UMC

117 UMC_ED2 C674x-UMC

118 PDC_INT C674x-PDC

119 SYS_CMPA C674x-SYS

120 PMC_CMPA C674x-PMC

121 PMC_CMPA C674x-PMC

122 DMC_CMPA C674x-DMC

123 DMC_CMPA C674x-DMC

124 UMC_CMPA C674x-UMC

125 UMC_CMPA C674x-UMC

126 EMC_CMPA C674x-EMC

127 EMC_BUSERR C674x-EMC

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-9.C674x DSP InterruptControllerRegisters BYTE ADDRESS ACRONYM DESCRIPTION 0x0180 0000 EVTFLAG0 Eventflagregister0 0x0180 0004 EVTFLAG1 Eventflagregister1 0x0180 0008 EVTFLAG2 Eventflagregister2 0x0180 000C EVTFLAG3 Eventflagregister3 0x0180 0020 EVTSET0 Eventsetregister0 0x0180 0024 EVTSET1 Eventsetregister1 0x0180 0028 EVTSET2 Eventsetregister2 0x0180 002C EVTSET3 Eventsetregister3 0x0180 0040 EVTCLR0 Eventclearregister0 0x0180 0044 EVTCLR1 Eventclearregister1 0x0180 0048 EVTCLR2 Eventclearregister2 0x0180 004C EVTCLR3 Eventclearregister3 0x0180 0080 EVTMASK0 Eventmask register0 0x0180 0084 EVTMASK1 Eventmask register1 0x0180 0088 EVTMASK2 Eventmask register2 0x0180 008C EVTMASK3 Eventmask register3 0x0180 00A0 MEVTFLAG0 Masked eventflagregister0 0x0180 00A4 MEVTFLAG1 Masked eventflagregister1 0x0180 00A8 MEVTFLAG2 Masked eventflagregister2 0x0180 00AC MEVTFLAG3 Masked eventflagregister3 0x0180 00C0 EXPMASK0 Exceptionmask register0 0x0180 00C4 EXPMASK1 Exceptionmask register1 0x0180 00C8 EXPMASK2 Exceptionmask register2 0x0180 00CC EXPMASK3 Exceptionmask register3 0x0180 00E0 MEXPFLAG0 Masked exceptionflagregister0 0x0180 00E4 MEXPFLAG1 Masked exceptionflagregister1 0x0180 00E8 MEXPFLAG2 Masked exceptionflagregister2 0x0180 00EC MEXPFLAG3 Masked exceptionflagregister3 0x0180 0104 INTMUX1 Interruptmux register1 0x0180 0108 INTMUX2 Interruptmux register2 0x0180 010C INTMUX3 Interruptmux register3 0x0180 0140 -0x0180 0144 - Reserved 0x0180 0180 INTXSTAT Interruptexceptionstatus 0x0180 0184 INTXCLR Interruptexceptionclear 0x0180 0188 INTDMASK Dropped interruptmask register 0x0180 01C0 EVTASRT Eventassertregister Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 103 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.8 Power and Sleep Controller(PSC)

The Power and SleepControllers(PSC) areresponsibleformanaging transitionsofsystem power on/off, clockon/off,resets(deviceleveland module level).Itisused primarilytoprovidegranularpower control foron chipmodules (peripheralsand CPU). A PSC module consistsofa GlobalPSC (GPSC) and a setof LocalPSCs (LPSCs).The GPSC containsmemory mapped registers,PSC interrupts,a statemachine for each peripheral/moduleitcontrols.An LPSC isassociatedwitheverymodule thatiscontrolledby thePSC and providesclockand resetcontrol. The PSC includesthefollowingfeatures:

Providesa softwareinterfaceto: – Controlmodule clockenable/disable – Controlmodule reset – ControlCPU localreset
SupportsIcePickemulationfeatures:power,clockand reset PSC0 controls16 localPSCs. PSC1 controls32 localPSCs. Table5-10.Power and Sleep Controller(PSC) Registers PSC0 BYTE PSC1 BYTE ACRONYM REGISTER DESCRIPTIONADDRESS ADDRESS 0x01C1 0000 0x01E2 7000 REVID PeripheralRevisionand ClassInformationRegister 0x01C1 0018 0x01E2 7018 INTEVAL InterruptEvaluationRegister 0x01C1 0040 0x01E2 7040 MERRPR0 Module ErrorPendingRegister0 (module0-15)(PSC0) Module ErrorPendingRegister0 (module0-31)(PSC1) 0x01C1 0050 0x01E2 7050 MERRCR0 Module ErrorClearRegister0 (module0-15)(PSC0) Module ErrorClearRegister0 (module0-31)(PSC1) 0x01C1 0060 0x01E2 7060 PERRPR Power ErrorPendingRegister 0x01C1 0068 0x01E2 7068 PERRCR Power ErrorClearRegister 0x01C1 0120 0x01E2 7120 PTCMD Power Domain TransitionCommand Register 0x01C1 0128 0x01E2 7128 PTSTAT Power Domain TransitionStatusRegister 0x01C1 0200 0x01E2 7200 PDSTAT0 Power Domain 0 StatusRegister 0x01C1 0204 0x01E2 7204 PDSTAT1 Power Domain 1 StatusRegister 0x01C1 0300 0x01E2 7300 PDCTL0 Power Domain 0 ControlRegister 0x01C1 0304 0x01E2 7304 PDCTL1 Power Domain 1 ControlRegister 0x01C1 0400 0x01E2 7400 PDCFG0 Power Domain 0 ConfigurationRegister 0x01C1 0404 0x01E2 7404 PDCFG1 Power Domain 1 ConfigurationRegister 0x01C1 0800 0x01E2 7800 MDSTAT0 Module 0 StatusRegister 0x01C1 0804 0x01E2 7804 MDSTAT1 Module 1 StatusRegister 0x01C1 0808 0x01E2 7808 MDSTAT2 Module 2 StatusRegister 0x01C1 080C 0x01E2 780C MDSTAT3 Module 3 StatusRegister 0x01C1 0810 0x01E2 7810 MDSTAT4 Module 4 StatusRegister 0x01C1 0814 0x01E2 7814 MDSTAT5 Module 5 StatusRegister 0x01C1 0818 0x01E2 7818 MDSTAT6 Module 6 StatusRegister 0x01C1 081C 0x01E2 781C MDSTAT7 Module 7 StatusRegister 0x01C1 0820 0x01E2 7820 MDSTAT8 Module 8 StatusRegister 0x01C1 0824 0x01E2 7824 MDSTAT9 Module 9 StatusRegister 0x01C1 0828 0x01E2 7828 MDSTAT10 Module 10 StatusRegister 0x01C1 082C 0x01E2 782C MDSTAT11 Module 11 StatusRegister 0x01C1 0830 0x01E2 7830 MDSTAT12 Module 12 StatusRegister 0x01C1 0834 0x01E2 7834 MDSTAT13 Module 13 StatusRegister

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-10.Power and Sleep Controller(PSC) Registers(continued) PSC0 BYTE PSC1 BYTE ACRONYM REGISTER DESCRIPTIONADDRESS ADDRESS 0x01C1 0838 0x01E2 7838 MDSTAT14 Module 14 StatusRegister 0x01C1 083C 0x01E2 783C MDSTAT15 Module 15 StatusRegister - 0x01E2 7840 MDSTAT16 Module 16 StatusRegister - 0x01E2 7844 MDSTAT17 Module 17 StatusRegister - 0x01E2 7848 MDSTAT18 Module 18 StatusRegister - 0x01E2 784C MDSTAT19 Module 19 StatusRegister - 0x01E2 7850 MDSTAT20 Module 20 StatusRegister - 0x01E2 7854 MDSTAT21 Module 21 StatusRegister - 0x01E2 7858 MDSTAT22 Module 22 StatusRegister - 0x01E2 785C MDSTAT23 Module 23 StatusRegister - 0x01E2 7860 MDSTAT24 Module 24 StatusRegister - 0x01E2 7864 MDSTAT25 Module 25 StatusRegister - 0x01E2 7868 MDSTAT26 Module 26 StatusRegister - 0x01E2 786C MDSTAT27 Module 27 StatusRegister - 0x01E2 7870 MDSTAT28 Module 28 StatusRegister - 0x01E2 7874 MDSTAT29 Module 29 StatusRegister - 0x01E2 7878 MDSTAT30 Module 30 StatusRegister - 0x01E2 787C MDSTAT31 Module 31 StatusRegister 0x01C1 0A00 0x01E2 7A00 MDCTL0 Module 0 ControlRegister 0x01C1 0A04 0x01E2 7A04 MDCTL1 Module 1 ControlRegister 0x01C1 0A08 0x01E2 7A08 MDCTL2 Module 2 ControlRegister 0x01C1 0A0C 0x01E2 7A0C MDCTL3 Module 3 ControlRegister 0x01C1 0A10 0x01E2 7A10 MDCTL4 Module 4 ControlRegister 0x01C1 0A14 0x01E2 7A14 MDCTL5 Module 5 ControlRegister 0x01C1 0A18 0x01E2 7A18 MDCTL6 Module 6 ControlRegister 0x01C1 0A1C 0x01E2 7A1C MDCTL7 Module 7 ControlRegister 0x01C1 0A20 0x01E2 7A20 MDCTL8 Module 8 ControlRegister 0x01C1 0A24 0x01E2 7A24 MDCTL9 Module 9 ControlRegister 0x01C1 0A28 0x01E2 7A28 MDCTL10 Module 10 ControlRegister 0x01C1 0A2C 0x01E2 7A2C MDCTL11 Module 11 ControlRegister 0x01C1 0A30 0x01E2 7A30 MDCTL12 Module 12 ControlRegister 0x01C1 0A34 0x01E2 7A34 MDCTL13 Module 13 ControlRegister 0x01C1 0A38 0x01E2 7A38 MDCTL14 Module 14 ControlRegister 0x01C1 0A3C 0x01E2 7A3C MDCTL15 Module 15 ControlRegister - 0x01E2 7A40 MDCTL16 Module 16 ControlRegister - 0x01E2 7A44 MDCTL17 Module 17 ControlRegister - 0x01E2 7A48 MDCTL18 Module 18 ControlRegister - 0x01E2 7A4C MDCTL19 Module 19 ControlRegister - 0x01E2 7A50 MDCTL20 Module 20 ControlRegister - 0x01E2 7A54 MDCTL21 Module 21 ControlRegister - 0x01E2 7A58 MDCTL22 Module 22 ControlRegister - 0x01E2 7A5C MDCTL23 Module 23 ControlRegister - 0x01E2 7A60 MDCTL24 Module 24 ControlRegister - 0x01E2 7A64 MDCTL25 Module 25 ControlRegister - 0x01E2 7A68 MDCTL26 Module 26 ControlRegister - 0x01E2 7A6C MDCTL27 Module 27 ControlRegister - 0x01E2 7A70 MDCTL28 Module 28 ControlRegister Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 105 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-10.Power and Sleep Controller(PSC) Registers(continued) PSC0 BYTE PSC1 BYTE ACRONYM REGISTER DESCRIPTIONADDRESS ADDRESS - 0x01E2 7A74 MDCTL29 Module 29 ControlRegister - 0x01E2 7A78 MDCTL30 Module 30 ControlRegister - 0x01E2 7A7C MDCTL31 Module 31 ControlRegister

5.8.1 Power Domain and Module Topology

The deviceincludestwo PSC modules. Each PSC module controlsclockstatesforseveraloftheon chipmodules,controllersand interconnect components.Table 5-11 and Table 5-12 liststhe setof peripherals/modulesthatare controlledby the PSC, thepower domain theyareassociatedwith,theLPSC assignmentand thedefault(power-onreset) Table5-11.PSC0 DefaultModule Configuration LPSC Module Name Power Domain DefaultModule State Auto Sleep/Wake Only Number

0 EDMA3 ChannelController0 AlwaysON (PD0) SwRstDisable —

1 EDMA3 TransferController0 AlwaysON (PD0) SwRstDisable —

2 EDMA3 TransferController1 AlwaysON (PD0) SwRstDisable —

3 EMIFA (Br7) AlwaysON (PD0) SwRstDisable —

4 SPI 0 AlwaysON (PD0) SwRstDisable —

5 MMC/SD 0 AlwaysON (PD0) SwRstDisable —

6 ARM InterruptController AlwaysON (PD0) SwRstDisable —

7 ARM RAM/ROM AlwaysON (PD0) Enable Yes

8 — — — —

9 UART 0 AlwaysON (PD0) SwRstDisable —

10 SCR0 (Br0,Br 1,Br 2,Br 8) AlwaysON (PD0) Enable Yes

11 SCR1 (Br4) AlwaysON (PD0) Enable Yes

12 SCR2 (Br3,Br 5,Br 6) AlwaysON (PD0) Enable Yes

13 PRUSS AlwaysON (PD0) SwRstDisable —

14 ARM AlwaysON (PD0) SwRstDisable —

15 DSP PD_DSP (PD1) Enable —

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-12.PSC1 DefaultModule Configuration LPSC Module Name Power Domain DefaultModule State Auto Sleep/Wake Only Number

0 EDMA3 ChannelController1 AlwaysON (PD0) SwRstDisable —

1 USB0 (USB2.0) AlwaysON (PD0) SwRstDisable — 2 USB1 (USB1.1) AlwaysON (PD0) SwRstDisable —

3 GPIO AlwaysON (PD0) SwRstDisable —

4 UHPI AlwaysON (PD0) SwRstDisable —

5 EMAC AlwaysON (PD0) SwRstDisable —

6 DDR2 (andSCR_F3) AlwaysON (PD0) SwRstDisable —

7 McASP0 (+ McASP0 FIFO) AlwaysON (PD0) SwRstDisable —

8 SATA AlwaysON (PD0) SwRstDisable —

9 VPIF AlwaysON (PD0) SwRstDisable —

10 SPI 1 AlwaysON (PD0) SwRstDisable —

11 I2C 1 AlwaysON (PD0) SwRstDisable —

12 UART 1 AlwaysON (PD0) SwRstDisable —

13 UART 2 AlwaysON (PD0) SwRstDisable —

14 McBSP0 (+ McBSP0 FIFO) AlwaysON (PD0) SwRstDisable —

15 McBSP1 (+ McBSP1 FIFO) AlwaysON (PD0) SwRstDisable —

16 LCDC AlwaysON (PD0) SwRstDisable —

17 eHRPWM0/1 AlwaysON (PD0) SwRstDisable —

18 MMCSD1 AlwaysON (PD0) SwRstDisable —

19 uPP AlwaysON (PD0) SwRstDisable —

20 ECAP0/1/2 AlwaysON (PD0) SwRstDisable —

21 EDMA3 TransferController2 AlwaysON (PD0) SwRstDisable —

22 — — — — 23 — — — —

24 SCR_F0 (andbridgeF0) AlwaysON (PD0) Enable Yes

25 SCR_F1 (andbridgeF1) AlwaysON (PD0) Enable Yes

26 SCR_F2 (andbridgeF2) AlwaysON (PD0) Enable Yes

27 SCR_F6 (andbridgeF3) AlwaysON (PD0) Enable Yes

28 SCR_F7 (andbridgeF4) AlwaysON (PD0) Enable Yes

29 SCR_F8 (andbridgeF5) AlwaysON (PD0) Enable Yes

30 BridgeF7 (DDR Controllerpath) AlwaysON (PD0) Enable Yes

31 Shared RAM (includingSCR_F4 PD_SHRAM Enable —

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5.8.1.1 Power Domain States

A power domain can onlybe inone ofthetwo states:ON orOFF, definedas follows:

ON: power tothedomain ison
OFF: power tothedomain isoff For bothPSC0 and PSC1, theAlways ON domain,orPD0 power domain,isalwaysintheON statewhen thechipispowered-on.Thisdomain isnotprogrammabletoOFF state.
On PSC0 PD1/PD_DSP Domain:ControlsthesleepstateforDSP L1 and L2 Memories
On PSC1 PD1/PD_SHRAM Domain:Controlsthesleepstateforthe128K Shared RAM

5.8.1.2 Module States

The PSC definesseveralpossiblestatesfora module.Thisstatesare essentiallya combinationofthe module resetassertedorde-assertedand module clockon/enabledoroff/disabled.The module statesare definedinTable5-13. Table5-13.Module States Module State Module Reset Module Module StateDefinition Clock Enable De-asserted On A module intheenablestatehas itsmodule resetde-assertedand ithas itsclockon. Thisisthenormaloperationalstatefora givenmodule Disable De-asserted Off A module inthedisabledstatehas itsmodule resetde-assertedand ithas itsmodule clockoff.Thisstateistypicallyused fordisablinga module clocktosave power.The deviceisdesignedinfullstaticCMOS, so when you stopa module clock,itretainsthe module’s state.When theclockisrestarted,themodule resumes operatingfromthe stoppingpoint. SyncReset Asserted On A module stateintheSyncResetstatehas itsmodule resetassertedand ithas its clockon.Generally,softwareisnotexpectedtoinitiatethisstate SwRstDisable Asserted Off A module intheSwResetDisablestatehas itsmodule resetassertedand ithas its clockdisabled.Afterinitialpower-on,severalmodules come up intheSwRstDisable state.Generally,softwareisnotexpectedtoinitiatethisstate AutoSleep De-asserted Off A module intheAutoSleepstatealsohas itsmodule resetde-assertedand itsmodule clockdisabled,similartotheDisablestate.However thisisa specialstate,once a module isconfiguredinthisstateby software,itcan “automatically”transitionto “Enable”statewhenever thereisan internalread/writerequestmade toit,and after servicingtherequestitwill“automatically”transitionintothesleepstate(withmodule resetrede-assertedand module clockdisabled),withoutany softwareintervention. The transitionfromsleeptoenabledand back tosleepstatehas some cyclelatency associatedwithit.Itisnotenvisionedtouse thismode when peripheralsarefully operationaland moving data. AutoWake De-asserted Off A module intheAutoWake statealsohas itsmodule resetde-assertedand itsmodule clockdisabled,similartotheDisablestate.However thisisa specialstate,once a module isconfiguredinthisstateby software,itwill“automatically”transitionto “Enable”statewhenever thereisan internalread/writerequestmade toit,and will remaininthe“Enabled”statefromthenon (withmodule resetrede-assertedand module clockon),withoutany softwareintervention.The transitionfromsleepto enabledstatehas some cyclelatencyassociatedwithit.Itisnotenvisionedtouse this mode when peripheralsarefullyoperationaland moving data.

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5.9 Enhanced DirectMemory Access Controller(EDMA3)

The EDMA3 controllerhandlesalldatatransfersbetween memories and thedeviceslaveperipheralson the device.These data transfersincludecache servicing,non-cacheablememory accesses,user- programmed datatransfers,and hostaccesses.

5.9.1 EDMA3 Channel SynchronizationEvents

Each EDMA3 channel controllersupportsup to 32 channelswhich serviceperipheralsand memory. Table 5-14 liststhe source of the EDMA3 synchronizationevents associatedwith each of the programmableEDMA channels. Table5-14.EDMA SynchronizationEvents EDMA3 Channel Controller0 Event Event Name /Source Event Event Name /Source

0 McASP0 Receive 16 MMCSD0 Receive

1 McASP0 Transmit 17 MMCSD0 Transmit

2 McBSP0 Receive 18 SPI1 Receive

3 McBSP0 Transmit 19 SPI1 Transmit

4 McBSP1 Receive 20 PRU_EVTOUT6

5 McBSP1 Transmit 21 PRU_EVTOUT7

6 GPIO Bank 0 Interrupt 22 GPIO Bank 2 Interrupt

7 GPIO Bank 1 Interrup 23 GPIO Bank 3 Interrupt

8 UART0 Receive 24 I2C0 Receive

9 UART0 Transmit 25 I2C0 Transmit

10 Timer64P0 EventOut 12 26 I2C1 Receive

11 Timer64P0 EventOut 34 27 I2C1 Transmit

12 UART1 Receive 28 GPIO Bank 4 Interrupt

13 UART1 Transmit 29 GPIO Bank 5 Interrupt

14 SPI0 Receive 30 UART2 Receive

15 SPI0 Transmit 31

Event EventName /Source Event EventName /Source

0 Timer64P2 Compare Event0 16 GPIO Bank 6 Interrupt

1 Timer64P2 Compare Event1 17 GPIO Bank 7 Interrupt

2 Timer64P2 Compare Event2 18 GPIO Bank 8 Interrupt

3 Timer64P2 Compare Event3 19 Reserved

4 Timer64P2 Compare Event4 20 Reserved

5 Timer64P2 Compare Event5 21 Reserved

6 Timer64P2 Compare Event6 22 Reserved

7 Timer64P2 Compare Event7 23 Reserved

8 Timer64P3 Compare Event0 24 Timer64P2 EventOut 12

9 Timer64P3 Compare Event1 25 Timer64P2 EventOut 34

10 Timer64P3 Compare Event2 26 Timer64P3 EventOut 12

11 Timer64P3 Compare Event3 27 Timer64P3 EventOut 34

12 Timer64P3 Compare Event4 28 MMCSD1 Receive

13 Timer64P3 Compare Event5 29 MMCSD1 Transmit

14 Timer64P3 Compare Event6 30 Reserved

15 Timer64P3 Compare Event7 31 Reserved

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5.9.2 EDMA3 PeripheralRegisterDescriptions

Table5-15isthelistofEDMA3 ChannelControllerRegistersand Table5-16isthelistofEDMA3 Transfer Controllerregisters. Table5-15.EDMA3 Channel Controller(EDMA3CC) Registers EDMA3_0 Channel EDMA3_1 Channel ACRONYM REGISTER DESCRIPTION Controller0 Controller0 BYTE ADDRESS BYTE ADDRESS 0x01C0 0000 0x01E3 0000 PID PeripheralIdentificationRegister 0x01C0 0004 0x01E3 0004 CCCFG EDMA3CC ConfigurationRegister GlobalRegisters 0x01C0 0200 0x01E3 0200 QCHMAP0 QDMA Channel0 Mapping Register 0x01C0 0204 0x01E3 0204 QCHMAP1 QDMA Channel1 Mapping Register 0x01C0 0208 0x01E3 0208 QCHMAP2 QDMA Channel2 Mapping Register 0x01C0 020C 0x01E3 020C QCHMAP3 QDMA Channel3 Mapping Register 0x01C0 0210 0x01E3 0210 QCHMAP4 QDMA Channel4 Mapping Register 0x01C0 0214 0x01E3 0214 QCHMAP5 QDMA Channel5 Mapping Register 0x01C0 0218 0x01E3 0218 QCHMAP6 QDMA Channel6 Mapping Register 0x01C0 021C 0x01E3 021C QCHMAP7 QDMA Channel7 Mapping Register 0x01C0 0240 0x01E3 0240 DMAQNUM0 DMA ChannelQueue Number Register0 0x01C0 0244 0x01E3 0244 DMAQNUM1 DMA ChannelQueue Number Register1 0x01C0 0248 0x01E3 0248 DMAQNUM2 DMA ChannelQueue Number Register2 0x01C0 024C 0x01E3 024C DMAQNUM3 DMA ChannelQueue Number Register3 0x01C0 0260 0x01E3 0260 QDMAQNUM QDMA ChannelQueue Number Register 0x01C0 0284 0x01E3 0284 QUEPRI Queue PriorityRegister(1) 0x01C0 0300 0x01E3 0300 EMR EventMissedRegister 0x01C0 0308 0x01E3 0308 EMCR EventMissedClearRegister 0x01C0 0310 0x01E3 0310 QEMR QDMA EventMissedRegister 0x01C0 0314 0x01E3 0314 QEMCR QDMA EventMissedClearRegister 0x01C0 0318 0x01E3 0318 CCERR EDMA3CC ErrorRegister 0x01C0 031C 0x01E3 031C CCERRCLR EDMA3CC ErrorClearRegister 0x01C0 0320 0x01E3 0320 EEVAL ErrorEvaluateRegister 0x01C0 0340 0x01E3 0340 DRAE0 DMA RegionAccess EnableRegisterforRegion0 0x01C0 0348 0x01E3 0348 DRAE1 DMA RegionAccess EnableRegisterforRegion1 0x01C0 0350 0x01E3 0350 DRAE2 DMA RegionAccess EnableRegisterforRegion2 0x01C0 0358 0x01E3 0358 DRAE3 DMA RegionAccess EnableRegisterforRegion3 0x01C0 0380 0x01E3 0380 QRAE0 QDMA RegionAccess EnableRegisterforRegion0 0x01C0 0384 0x01E3 0384 QRAE1 QDMA RegionAccess EnableRegisterforRegion1 0x01C0 0388 0x01E3 0388 QRAE2 QDMA RegionAccess EnableRegisterforRegion2 0x01C0 038C 0x01E3 038C QRAE3 QDMA RegionAccess EnableRegisterforRegion3 0x01C0 0400 -0x01C0 043C 0x01E3 0400 -0x01E3 043C Q0E0-Q0E15 EventQueue EntryRegistersQ0E0-Q0E15 0x01C0 0440 -0x01C0 047C 0x01E3 0440 -0x01E3 047C Q1E0-Q1E15 EventQueue EntryRegistersQ1E0-Q1E15 0x01C0 0600 0x01E3 0600 QSTAT0 Queue 0 StatusRegister 0x01C0 0604 0x01E3 0604 QSTAT1 Queue 1 StatusRegister 0x01C0 0620 0x01E3 0620 QWMTHRA Queue Watermark ThresholdA Register 0x01C0 0640 0x01E3 0640 CCSTAT EDMA3CC StatusRegister (1) On previousarchitectures,theEDMA3TC prioritywas controlledby thequeue priorityregister(QUEPRI) intheEDMA3CC memory- map. However forthisdevice,theprioritycontrolforthetransfercontrollersiscontrolledby thechip-levelregistersintheSystem ConfigurationModule.You shoulduse thechip-levelregistersand notQUEPRI toconfiguretheTC priority.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-15.EDMA3 Channel Controller(EDMA3CC) Registers(continued) EDMA3_0 Channel EDMA3_1 Channel ACRONYM REGISTER DESCRIPTION Controller0 Controller0 BYTE ADDRESS BYTE ADDRESS GlobalChannel Registers 0x01C0 1000 0x01E3 1000 ER EventRegister 0x01C0 1008 0x01E3 1008 ECR EventClearRegister 0x01C0 1010 0x01E3 1010 ESR EventSetRegister 0x01C0 1018 0x01E3 1018 CER ChainedEventRegister 0x01C0 1020 0x01E3 1020 EER EventEnableRegister 0x01C0 1028 0x01E3 1028 EECR EventEnableClearRegister 0x01C0 1030 0x01E3 1030 EESR EventEnableSetRegister 0x01C0 1038 0x01E3 1038 SER SecondaryEventRegister 0x01C0 1040 0x01E3 1040 SECR SecondaryEventClearRegister 0x01C0 1050 0x01E3 1050 IER InterruptEnableRegister 0x01C0 1058 0x01E3 1058 IECR InterruptEnableClearRegister 0x01C0 1060 0x01E3 1060 IESR InterruptEnableSetRegister 0x01C0 1068 0x01E3 1068 IPR InterruptPendingRegister 0x01C0 1070 0x01E3 1070 ICR InterruptClearRegister 0x01C0 1078 0x01E3 1078 IEVAL InterruptEvaluateRegister 0x01C0 1080 0x01E3 1080 QER QDMA EventRegister 0x01C0 1084 0x01E3 1084 QEER QDMA EventEnableRegister 0x01C0 1088 0x01E3 1088 QEECR QDMA EventEnableClearRegister 0x01C0 108C 0x01E3 108C QEESR QDMA EventEnableSetRegister 0x01C0 1090 0x01E3 1090 QSER QDMA SecondaryEventRegister 0x01C0 1094 0x01E3 1094 QSECR QDMA SecondaryEventClearRegister Shadow Region 0 Channel Registers 0x01C0 2000 0x01E3 2000 ER EventRegister 0x01C0 2008 0x01E3 2008 ECR EventClearRegister 0x01C0 2010 0x01E3 2010 ESR EventSetRegister 0x01C0 2018 0x01E3 2018 CER ChainedEventRegister 0x01C0 2020 0x01E3 2020 EER EventEnableRegister 0x01C0 2028 0x01E3 2028 EECR EventEnableClearRegister 0x01C0 2030 0x01E3 2030 EESR EventEnableSetRegister 0x01C0 2038 0x01E3 2038 SER SecondaryEventRegister 0x01C0 2040 0x01E3 2040 SECR SecondaryEventClearRegister 0x01C0 2050 0x01E3 2050 IER InterruptEnableRegister 0x01C0 2058 0x01E3 2058 IECR InterruptEnableClearRegister 0x01C0 2060 0x01E3 2060 IESR InterruptEnableSetRegister 0x01C0 2068 0x01E3 2068 IPR InterruptPendingRegister 0x01C0 2070 0x01E3 2070 ICR InterruptClearRegister 0x01C0 2078 0x01E3 2078 IEVAL InterruptEvaluateRegister 0x01C0 2080 0x01E3 2080 QER QDMA EventRegister 0x01C0 2084 0x01E3 2084 QEER QDMA EventEnableRegister 0x01C0 2088 0x01E3 2088 QEECR QDMA EventEnableClearRegister 0x01C0 208C 0x01E3 208C QEESR QDMA EventEnableSetRegister 0x01C0 2090 0x01E3 2090 QSER QDMA SecondaryEventRegister 0x01C0 2094 0x01E3 2094 QSECR QDMA SecondaryEventClearRegister Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 111 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-15.EDMA3 Channel Controller(EDMA3CC) Registers(continued) EDMA3_0 Channel EDMA3_1 Channel ACRONYM REGISTER DESCRIPTION Controller0 Controller0 BYTE ADDRESS BYTE ADDRESS Shadow Region 1 Channel Registers 0x01C0 2200 0x01E3 2200 ER EventRegister 0x01C0 2208 0x01E3 2208 ECR EventClearRegister 0x01C0 2210 0x01E3 2210 ESR EventSetRegister 0x01C0 2218 0x01E3 2218 CER ChainedEventRegister 0x01C0 2220 0x01E3 2220 EER EventEnableRegister 0x01C0 2228 0x01E3 2228 EECR EventEnableClearRegister 0x01C0 2230 0x01E3 2230 EESR EventEnableSetRegister 0x01C0 2238 0x01E3 2238 SER SecondaryEventRegister 0x01C0 2240 0x01E3 2240 SECR SecondaryEventClearRegister 0x01C0 2250 0x01E3 2250 IER InterruptEnableRegister 0x01C0 2258 0x01E3 2258 IECR InterruptEnableClearRegister 0x01C0 2260 0x01E3 2260 IESR InterruptEnableSetRegister 0x01C0 2268 0x01E3 2268 IPR InterruptPendingRegister 0x01C0 2270 0x01E3 2270 ICR InterruptClearRegister 0x01C0 2278 0x01E3 2278 IEVAL InterruptEvaluateRegister 0x01C0 2280 0x01E3 2280 QER QDMA EventRegister 0x01C0 2284 0x01E3 2284 QEER QDMA EventEnableRegister 0x01C0 2288 0x01E3 2288 QEECR QDMA EventEnableClearRegister 0x01C0 228C 0x01E3 228C QEESR QDMA EventEnableSetRegister 0x01C0 2290 0x01E3 2290 QSER QDMA SecondaryEventRegister 0x01C0 2294 0x01E3 2294 QSECR QDMA SecondaryEventClearRegister 0x01C0 4000 -0x01C0 4FFF 0x01E3 4000 -0x01E3 4FFF — ParameterRAM (PaRAM) Table5-16.EDMA3 TransferController(EDMA3TC) Registers EDMA3_0 EDMA3_0 EDMA3_1 ACRONYM REGISTER DESCRIPTION Transfer Transfer Transfer Controller0 Controller1 Controller0 BYTE ADDRESS BYTE ADDRESS BYTE ADDRESS 0x01C0 8000 0x01C0 8400 0x01E3 8000 PID PeripheralIdentificationRegister 0x01C0 8004 0x01C0 8404 0x01E3 8004 TCCFG EDMA3TC ConfigurationRegister 0x01C0 8100 0x01C0 8500 0x01E3 8100 TCSTAT EDMA3TC ChannelStatusRegister 0x01C0 8120 0x01C0 8520 0x01E3 8120 ERRSTAT ErrorStatusRegister 0x01C0 8124 0x01C0 8524 0x01E3 8124 ERREN ErrorEnableRegister 0x01C0 8128 0x01C0 8528 0x01E3 8128 ERRCLR ErrorClearRegister 0x01C0 812C 0x01C0 852C 0x01E3 812C ERRDET ErrorDetailsRegister 0x01C0 8130 0x01C0 8530 0x01E3 8130 ERRCMD ErrorInterruptCommand Register 0x01C0 8140 0x01C0 8540 0x01E3 8140 RDRATE Read Command Rate Register 0x01C0 8240 0x01C0 8640 0x01E3 8240 SAOPT SourceActiveOptionsRegister 0x01C0 8244 0x01C0 8644 0x01E3 8244 SASRC SourceActiveSourceAddressRegister 0x01C0 8248 0x01C0 8648 0x01E3 8248 SACNT SourceActiveCount Register 0x01C0 824C 0x01C0 864C 0x01E3 824C SADST SourceActiveDestinationAddressRegister 0x01C0 8250 0x01C0 8650 0x01E3 8250 SABIDX SourceActiveB-IndexRegister 0x01C0 8254 0x01C0 8654 0x01E3 8254 SAMPPRXY SourceActiveMemory ProtectionProxyRegister 0x01C0 8258 0x01C0 8658 0x01E3 8258 SACNTRLD SourceActiveCount ReloadRegister 0x01C0 825C 0x01C0 865C 0x01E3 825C SASRCBREF SourceActiveSourceAddressB-ReferenceRegister 0x01C0 8260 0x01C0 8660 0x01E3 8260 SADSTBREF SourceActiveDestinationAddressB-ReferenceRegister

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-16.EDMA3 TransferController(EDMA3TC) Registers(continued) EDMA3_0 EDMA3_0 EDMA3_1 ACRONYM REGISTER DESCRIPTION Transfer Transfer Transfer Controller0 Controller1 Controller0 BYTE ADDRESS BYTE ADDRESS BYTE ADDRESS 0x01C0 8280 0x01C0 8680 0x01E3 8280 DFCNTRLD DestinationFIFO SetCount ReloadRegister 0x01C0 8284 0x01C0 8684 0x01E3 8284 DFSRCBREF DestinationFIFO SetSourceAddressB-Reference Register 0x01C0 8288 0x01C0 8688 0x01E3 8288 DFDSTBREF DestinationFIFO SetDestinationAddressB-Reference Register 0x01C0 8300 0x01C0 8700 0x01E3 8300 DFOPT0 DestinationFIFO OptionsRegister0 0x01C0 8304 0x01C0 8704 0x01E3 8304 DFSRC0 DestinationFIFO SourceAddressRegister0 0x01C0 8308 0x01C0 8708 0x01E3 8308 DFCNT0 DestinationFIFO Count Register0 0x01C0 830C 0x01C0 870C 0x01E3 830C DFDST0 DestinationFIFO DestinationAddressRegister0 0x01C0 8310 0x01C0 8710 0x01E3 8310 DFBIDX0 DestinationFIFO B-IndexRegister0 0x01C0 8314 0x01C0 8714 0x01E3 8314 DFMPPRXY0 DestinationFIFO Memory ProtectionProxyRegister0 0x01C0 8340 0x01C0 8740 0x01E3 8340 DFOPT1 DestinationFIFO OptionsRegister1 0x01C0 8344 0x01C0 8744 0x01E3 8344 DFSRC1 DestinationFIFO SourceAddressRegister1 0x01C0 8348 0x01C0 8748 0x01E3 8348 DFCNT1 DestinationFIFO Count Register1 0x01C0 834C 0x01C0 874C 0x01E3 834C DFDST1 DestinationFIFO DestinationAddressRegister1 0x01C0 8350 0x01C0 8750 0x01E3 8350 DFBIDX1 DestinationFIFO B-IndexRegister1 0x01C0 8354 0x01C0 8754 0x01E3 8354 DFMPPRXY1 DestinationFIFO Memory ProtectionProxyRegister1 0x01C0 8380 0x01C0 8780 0x01E3 8380 DFOPT2 DestinationFIFO OptionsRegister2 0x01C0 8384 0x01C0 8784 0x01E3 8384 DFSRC2 DestinationFIFO SourceAddressRegister2 0x01C0 8388 0x01C0 8788 0x01E3 8388 DFCNT2 DestinationFIFO Count Register2 0x01C0 838C 0x01C0 878C 0x01E3 838C DFDST2 DestinationFIFO DestinationAddressRegister2 0x01C0 8390 0x01C0 8790 0x01E3 8390 DFBIDX2 DestinationFIFO B-IndexRegister2 0x01C0 8394 0x01C0 8794 0x01E3 8394 DFMPPRXY2 DestinationFIFO Memory ProtectionProxyRegister2 0x01C0 83C0 0x01C0 87C0 0x01E3 83C0 DFOPT3 DestinationFIFO OptionsRegister3 0x01C0 83C4 0x01C0 87C4 0x01E3 83C4 DFSRC3 DestinationFIFO SourceAddressRegister3 0x01C0 83C8 0x01C0 87C8 0x01E3 83C8 DFCNT3 DestinationFIFO Count Register3 0x01C0 83CC 0x01C0 87CC 0x01E3 83CC DFDST3 DestinationFIFO DestinationAddressRegister3 0x01C0 83D0 0x01C0 87D0 0x01E3 83D0 DFBIDX3 DestinationFIFO B-IndexRegister3 0x01C0 83D4 0x01C0 87D4 0x01E3 83D4 DFMPPRXY3 DestinationFIFO Memory ProtectionProxyRegister3 Table5-17shows an abbreviationofthesetofregisterswhichmake up theparametersetforeach of128 EDMA3 events.Each oftheparameterregistersetsconsistof8 32-bitword entries.Table5-18shows the parametersetentryregisterswithrelativememory addresslocationswithineach oftheparametersets. Table5-17.EDMA3 Parameter Set RAM EDMA3_0 EDMA3_1 Channel Controller0 Channel Controller0 DESCRIPTION BYTE ADDRESS RANGE BYTE ADDRESS RANGE 0x01C0 4000 -0x01C0 401F 0x01E3 4000 -0x01E3 401F ParametersSet0 (832-bitwords) 0x01C0 4020 -0x01C0 403F 0x01E3 4020 -0x01E3 403F ParametersSet1 (832-bitwords) 0x01C0 4040 -0x01CC0 405F 0x01E3 4040 -0x01CE3 405F ParametersSet2 (832-bitwords) 0x01C0 4060 -0x01C0 407F 0x01E3 4060 -0x01E3 407F ParametersSet3 (832-bitwords) 0x01C0 4080 -0x01C0 409F 0x01E3 4080 -0x01E3 409F ParametersSet4 (832-bitwords) 0x01C0 40A0 -0x01C0 40BF 0x01E3 40A0 -0x01E3 40BF ParametersSet5 (832-bitwords) 0x01C0 4FC0 -0x01C0 4FDF 0x01E3 4FC0 -0x01E3 4FDF ParametersSet126 (832-bitwords) 0x01C0 4FE0 -0x01C0 4FFF 0x01E3 4FE0 -0x01E3 4FFF ParametersSet127 (832-bitwords) Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 113 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-18.Parameter Set Entries OFFSET BYTE ADDRESS ACRONYM PARAMETER ENTRYWITHIN THE PARAMETER SET 0x0000 OPT Option 0x0004 SRC SourceAddress 0x0008 A_B_CNT A Count,B Count 0x000C DST DestinationAddress 0x0010 SRC_DST_BIDX SourceB Index,DestinationB Index 0x0014 LINK_BCNTRLD LinkAddress,B Count Reload 0x0018 SRC_DST_CIDX SourceC Index,DestinationC Index 0x001C CCNT C Count

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5.10 ExternalMemory InterfaceA (EMIFA)

EMIFA isone of two externalmemory interfacessupportedon the device.Itisprimarilyintendedto supportasynchronousmemory types,such as NAND and NOR flashand AsynchronousSRAM. However on thisdevice,EMIFA alsoprovidesa secondaryinterfacetoSDRAM.

5.10.1 EMIFA Asynchronous Memory Support

EMIFA supportsasynchronous:

SRAM memories
NAND Flashmemories
NOR Flashmemories The EMIFA databus widthisup to16-bits.Thedevicesupportsup to23 addresslinesand two external wait/interruptinputs.Up tofourasynchronouschipselectsaresupportedby EMIFA (EMA_CS[5:2]). Each chipselecthas thefollowingindividuallyprogrammableattributes:
Data Bus Width
Read cycletimings:setup,hold,strobe
Writecycletimings:setup,hold,strobe
Bus turnaroundtime
ExtendedWaitOptionWithProgrammable Timeout
SelectStrobeOption
NAND flashcontrollersupports1-bitand 4-bitECC calculationon blocksof512 bytes.

5.10.2 EMIFA Synchronous DRAM Memory Support

The devicesupports16-bitSDRAM inadditiontotheasynchronousmemories listedinSection5.10.1.It has a singleSDRAM chipselect(EMA_CS[0]).SDRAM configurationsthataresupportedare:

One, Two, and FourBank SDRAM devices
DeviceswithEight,Nine,Ten,and ElevenColumn Address
CAS Latencyoftwo orthreeclockcycles
SixteenBitData Bus Width Additionally,theSDRAM interfaceofEMIFA supportsplacingtheSDRAM inSelfRefreshand Powerdown Modes. SelfRefreshmode allowstheSDRAM tobe putintoa lowpower statewhilestillretainingmemory contents;sincetheSDRAM willcontinuetorefreshitselfeven withoutclocksfromthedevice.Powerdown mode achieveseven lowerpower,exceptthe devicemust periodicallywake the SDRAM up and issue refreshesifdataretentionisrequired. Finally,notethattheEMIFA does notsupportMobileSDRAM devices. Table5-19shows thesupportedSDRAM configurationsforEMIFA. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 115 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-19.EMIFA Supported SDRAM Configurations(1) SDRAM EMIFA Data Total Total MemoryMemory Number of Bus Size Rows Columns Banks Memory Memory DensityData Bus Memories (bits) (Mbits) (Mbytes) (Mbits)Width (bits) 1 16 16 8 1 256 32 256 1 16 16 8 2 512 64 512 1 16 16 8 4 1024 128 1024 1 16 16 9 1 512 64 512 1 16 16 9 2 1024 128 1024 16 1 16 16 9 4 2048 256 2048 1 16 16 10 1 1024 128 1024 1 16 16 10 2 2048 256 2048 1 16 16 10 4 4096 512 4096 1 16 16 11 1 2048 256 2048 1 16 16 11 2 4096 512 4096 1 16 15 11 4 4096 512 4096 2 16 16 8 1 256 32 128 2 16 16 8 2 512 64 256 2 16 16 8 4 1024 128 512 2 16 16 9 1 512 64 256 2 16 16 9 2 1024 128 512 8 2 16 16 9 4 2048 256 1024 2 16 16 10 1 1024 128 512 2 16 16 10 2 2048 256 1024 2 16 16 10 4 4096 512 2048 2 16 16 11 1 2048 256 1024 2 16 16 11 2 4096 512 2048 2 16 15 11 4 4096 512 2048 (1) The shaded cellsindicateconfigurationsthatarepossibleon theEMIFA interfacebutas ofthiswritingSDRAM memories capableof supportingthesedensitiesarenotavailableinthemarket.

5.10.3 EMIFA SDRAM Loading Limitations

EMIFA supportsSDRAM up to 100 MHz with up to two SDRAM or asynchronous memory loads. Additionalloadswilllimitthe SDRAM operationto lowerspeeds and the maximum speed shouldbe confirmedby boardsimulationusingIBISmodels.

5.10.4 EMIFA Connection Examples

Figure5-11illustratesan example ofhow SDRAM, NOR, and NAND flashdevicesmightbe connectedto EMIFA simultaneously.The SDRAM chip selectmust be EMA_CS[0]. Note thatthe NOR flashis connectedtoEMA_CS[2] and theNAND flashisconnectedtoEMA_CS[3] inthisexample.Note thatany typeofasynchronousmemory may be connectedtoEMA_CS[5:2]. The on-chipbootloadermakes some assumptionson whichchipselectthecontainsthebootimage,and thisdepends on thebootmode. For NOR bootmode; theon-chipbootloaderrequiresthattheimage be storedinNOR flashon EMA_CS[2]. For NAND bootmode, thebootloaderrequiresthatthebootimage is storedinNAND flashon EMA_CS[3]. Itisalwayspossibletohave theimage span multiplechipselects, butthismust be supportedby second stagebootcode storedintheexternalflash.

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EMA_CLK EMA_BA[1:0] EMA_CS[0] EMA_CAS EMA_RAS EMA_WE CLK CE WE EMIFA SDRAM 2M□x□16□x□4 BankEMA_SDCKE CAS RAS CKE BA[1:0] LDQM UDQM DQ[15:0] A[11:0] EMA_A[12:0] EMA_WE_DQM[0] EMA_WE_DQM[1] EMA_D[15:0] EMA_CS[2] EMA_CS[3] EMA_WAIT EMA_OE GPIO (6□Pins)RESET A[0] A[12:1] DQ[15:0] CE WE OE RESET A[18:13] RY/ Y B NOR FLASH 512K□x□16 ALE CLE DQ[15:0] CE WE RE RB NAND FLASH 1Gb□x□16 EMA_BA[1] EMA_A[1] EMA_A[2] ... DVDD RESET OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 A likelyuse case withmore thanone EMIFA chipselectused forNAND flashisillustratedinFigure5-12. Thisfigureshows how two multiplaneNAND flashdeviceswithtwo chipselectseach wouldconnecttothe EMIFA. Inthiscase ifNAND isthebootmemory, thenthebootimage needs tobe storedintheNAND area selectedby EMA_CS[3]. Part of the applicationimage could spillover intothe NAND regions selectedby otherEMIFA chipselects;but would relyon the code storedin the EMA_CS[3] area to bootloadit. Figure5-11.Connection Diagram: SDRAM, NOR, NAND Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 117 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

EMA_A[1] EMA_A[2] EMA_D[7:0] EMA_CS[2] EMA_CS[3] EMA_WE EMA_OE ALE CLE DQ[7:0] CE1 CE2 WE RE R/ 1 B R/ 2 B EMIFA NAND FLASH x8, MultiPlane ALE CLE DQ[7:0] CE1 CE2 WE RE R/ 1 B R/ 2 B NAND FLASH x8, MultiPlane DVDD EMA_WAIT EMA_CS[4] EMA_CS[5] OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-12.EMIFA Connection Diagram: MultipleNAND FlashPlanes

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5.10.5 ExternalMemory InterfaceRegisterDescriptions

Table5-20.ExternalMemory Interface(EMIFA) Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x6800 0000 MIDR Module ID Register 0x6800 0004 AWCC AsynchronousWaitCycleConfigurationRegister 0x6800 0008 SDCR SDRAM ConfigurationRegister 0x6800 000C SDRCR SDRAM RefreshControlRegister 0x6800 0010 CE2CFG Asynchronous1 ConfigurationRegister 0x6800 0014 CE3CFG Asynchronous2 ConfigurationRegister 0x6800 0018 CE4CFG Asynchronous3 ConfigurationRegister 0x6800 001C CE5CFG Asynchronous4 ConfigurationRegister 0x6800 0020 SDTIMR SDRAM TimingRegister 0x6800 003C SDSRETR SDRAM SelfRefreshExitTimingRegister 0x6800 0040 INTRAW EMIFA InterruptRaw Register 0x6800 0044 INTMSK EMIFA InterruptMask Register 0x6800 0048 INTMSKSET EMIFA InterruptMask SetRegister 0x6800 004C INTMSKCLR EMIFA InterruptMask ClearRegister 0x6800 0060 NANDFCR NAND FlashControlRegister 0x6800 0064 NANDFSR NAND FlashStatusRegister 0x6800 0070 NANDF1ECC NAND Flash1 ECC Register(CS2 Space) 0x6800 0074 NANDF2ECC NAND Flash2 ECC Register(CS3 Space) 0x6800 0078 NANDF3ECC NAND Flash3 ECC Register(CS4 Space) 0x6800 007C NANDF4ECC NAND Flash4 ECC Register(CS5 Space) 0x6800 00BC NAND4BITECCLOAD NAND Flash4-BitECC Load Register 0x6800 00C0 NAND4BITECC1 NAND Flash4-BitECC Register1 0x6800 00C4 NAND4BITECC2 NAND Flash4-BitECC Register2 0x6800 00C8 NAND4BITECC3 NAND Flash4-BitECC Register3 0x6800 00CC NAND4BITECC4 NAND Flash4-BitECC Register4 0x6800 00D0 NANDERRADD1 NAND Flash4-BitECC ErrorAddressRegister1 0x6800 00D4 NANDERRADD2 NAND Flash4-BitECC ErrorAddressRegister2 0x6800 00D8 NANDERRVAL1 NAND Flash4-BitECC ErrorValueRegister1 0x6800 00DC NANDERRVAL2 NAND Flash4-BitECC ErrorValueRegister2 Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 119 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.10.6 EMIFA ElectricalData/Timing

Table5-21throughTable5-24assume testingoverrecommended operatingconditions. Table5-21.Timing Requirements forEMIFA SDRAM Interface NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Inputsetuptime,readdatavalidon EMA_D[15:0]before19 tsu(EMA_DV-EM_CLKH) 2 3 3 nsEMA_CLK rising Inputholdtime,readdatavalidon EMA_D[15:0]after20 th(CLKH-DIV) 1.6 1.6 1.6 nsEMA_CLK rising Table5-22.SwitchingCharacteristicsforEMIFA SDRAM Interface NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 1 tc(CLK)(1) Cycletime,EMIF clockEMA_CLK 10 15 20 ns 2 tw(CLK)(1) Pulsewidth,EMIF clockEMA_CLK highorlow 3 5 8 ns 3 td(CLKH-CSV) Delaytime,EMA_CLK risingtoEMA_CS[0] valid 7 9.5 13 ns 4 toh(CLKH-CSIV) Outputholdtime,EMA_CLK risingtoEMA_CS[0] invalid 1 1 1 ns 5 td(CLKH-DQMV) Delaytime,EMA_CLK risingtoEMA_ WE_DQM[1:0] valid 7 9.5 13 ns Outputholdtime,EMA_CLK risingtoEMA_ WE_DQM[1:0]6 toh(CLKH-DQMIV) 1 1 1 nsinvalid Delaytime,EMA_CLK risingtoEMA_A[12:0]and7 td(CLKH-AV) 7 9.5 13 nsEMA_BA[1:0] valid Outputholdtime,EMA_CLK risingtoEMA_A[12:0]and8 toh(CLKH-AIV) 1 1 1 nsEMA_BA[1:0] invalid 9 td(CLKH-DV) Delaytime,EMA_CLK risingtoEMA_D[15:0]valid 7 9.5 13 ns 10 toh(CLKH-DIV) Outputholdtime,EMA_CLK risingtoEMA_D[15:0]invalid 1 1 1 ns 11 td(CLKH-RASV) Delaytime,EMA_CLK risingtoEMA_RAS valid 7 9.5 13 ns 12 toh(CLKH-RASIV) Outputholdtime,EMA_CLK risingtoEMA_RAS invalid 1 1 1 ns 13 td(CLKH-CASV) Delaytime,EMA_CLK risingtoEMA_CAS valid 7 9.5 13 ns 14 toh(CLKH-CASIV) Outputholdtime,EMA_CLK risingtoEMA_CAS invalid 1 1 1 ns 15 td(CLKH-WEV) Delaytime,EMA_CLK risingtoEMA_WE valid 7 9.5 13 ns 16 toh(CLKH-WEIV) Outputholdtime,EMA_CLK risingtoEMA_WE invalid 1 1 1 ns 17 tdis(CLKH-DHZ) (1) Delaytime,EMA_CLK risingtoEMA_D[15:0]tri-stated 7 9.5 13 ns 18 tena(CLKH-DLZ) (1) Outputholdtime,EMA_CLK risingtoEMA_D[15:0]driving 1 1 1 ns (1) These parametersarenotproductiontestedand arespecifiedby designtowork from-40°C to125°C.

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EMA_CLK EMA_BA[1:0] EMA_A[12:0] EMA_D[15:0] 2 2 17 182 EM_CLK Delay BASIC SDRAM READ OPERA TION EMA_CS[0] EMA_WE _DQM[1:0] EMA_RAS EMA_CAS EMA_WE EMA_CLK EMA_BA[1:0] EMA_A[12:0] EMA_D[15:0] 2 2 BASIC SDRAM WRITE OPERA TION EMA_CS[0] EMA_WE _DQM[1:0] EMA_RAS EMA_CAS EMA_WE OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-13.EMIFA Basic SDRAM WriteOperation Figure5-14.EMIFA Basic SDRAM Read Operation Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 121 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-23.Timing Requirements forEMIFA Asynchronous Memory Interface(1) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX READS and WRITES E tc(CLK) Cycletime,EMIFA module clock 6.75 15 20 ns 2 tw(EM_WAIT) Pulseduration,EM_WAIT assertionand deassertion 2E 2E 2E ns READS 12 tsu(EMDV-EMOEH) Setuptime,EM_D[15:0]validbeforeEM_OE high 3 5 7 ns 13 th(EMOEH-EMDIV) Holdtime,EM_D[15:0]validafterEM_OE high 0 0 0 ns SetupTime,EM_WAIT assertedbeforeend ofStrobe14 tsu (EMOEL-EMWAIT) 4E+3 4E+3 4E+3 nsPhase (2) WRITES SetupTime,EM_WAIT assertedbeforeend ofStrobe28 tsu (EMWEL-EMWAIT) 4E+3 4E+3 4E+3 nsPhase(2) (1) E = EMA_CLK periodorinns.EMA_CLK isselectedeitheras SYSCLK3 orthePLL0 outputclockdividedby 4.5.As an example,when SYSCLK3 isselectedand setto100MHz, E=10ns (2) Setupbeforeend ofSTROBE phase (ifno extendedwaitstatesareinserted)by whichEM_WAIT must be assertedtoadd extended waitstates.Figure5-17and Figure5-18describeEMIF transactionsthatincludeextendedwaitstatesinsertedduringtheSTROBE phase.However,cyclesinsertedas partofthisextendedwaitperiodshouldnotbe counted;the4E requirementistothestartofwhere theHOLD phase wouldbeginiftherewere no extendedwaitcycles.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-24.SwitchingCharacteristicsforEMIFA Asynchronous Memory Interface(1)(2)(3) NO. PARAMETER UNIT MIN Nom MAX READS and WRITES 1 td(TURNAROUND) Turnaroundtime (TA)*E-3 (TA)*E (TA)*E+ 3 ns READS EMIF readcycletime(EW = 0) (RS+RST+RH)*E -3 (RS+RST+RH)*E (RS+RST+RH)*E + 3 ns 3 tc(EMRCYCLE) (RS+RST+RH+(EWC*16))*E (RS+RST+RH+(EWC*16))*EEMIF readcycletime(EW = 1) (RS+RST+RH+(EWC*16))*E ns-3 + 3 Outputsetuptime,EMA_CE[5:2] lowtoEMA_OE low(SS = 0) (RS)*E-3 (RS)*E (RS)*E+3 ns 4 tsu(EMCEL-EMOEL) Outputsetuptime,EMA_CE[5:2] lowtoEMA_OE low(SS = 1) -3 0 +3 ns Outputholdtime,EMA_OE hightoEMA_CE[5:2] high(SS = 0) (RH)*E-3 (RH)*E (RH)*E+ 3 ns 5 th(EMOEH-EMCEH) Outputholdtime,EMA_OE hightoEMA_CE[5:2] high(SS = 1) -3 0 +3 ns 6 tsu(EMBAV-EMOEL) Outputsetuptime,EMA_BA[1:0] validtoEMA_OE low (RS)*E-3 (RS)*E (RS)*E+3 ns 7 th(EMOEH-EMBAIV) Outputholdtime,EMA_OE hightoEMA_BA[1:0] invalid (RH)*E-3 (RH)*E (RH)*E+3 ns 8 tsu(EMBAV-EMOEL) Outputsetuptime,EMA_A[13:0]validtoEMA_OE low (RS)*E-3 (RS)*E (RS)*E+3 ns 9 th(EMOEH-EMAIV) Outputholdtime,EMA_OE hightoEMA_A[13:0]invalid (RH)*E-3 (RH)*E (RH)*E+3 ns EMA_OE activelowwidth(EW = 0) (RST)*E-3 (RST)*E (RST)*E+3 ns 10 tw(EMOEL) EMA_OE activelowwidth(EW = 1) (RST+(EWC*16))*E-3 (RST+(EWC*16))*E (RST+(EWC*16))*E+3 ns 11 td(EMWAITH-EMOEH) DelaytimefromEMA_WAIT deassertedtoEMA_OE high 3E-3 4E 4E+3 ns WRITES EMIF writecycletime(EW = 0) (WS+WST+WH)*E-3 (WS+WST+WH)*E (WS+WST+WH)*E+3 ns 15 tc(EMWCYCLE) (WS+WST+WH+(EWC*16))* (WS+WST+WH+(EWC*16))*EMIF writecycletime(EW = 1) (WS+WST+WH+(EWC*16))*E nsE -3 E + 3 Outputsetuptime,EMA_CE[5:2] lowtoEMA_WE low(SS = 0) (WS)*E -3 (WS)*E (WS)*E + 3 ns 16 tsu(EMCEL-EMWEL) Outputsetuptime,EMA_CE[5:2] lowtoEMA_WE low(SS = 1) -3 0 +3 ns Outputholdtime,EMA_WE hightoEMA_CE[5:2] high(SS = 0) (WH)*E-3 (WH)*E (WH)*E+3 ns 17 th(EMWEH-EMCEH) Outputholdtime,EMA_WE hightoEMA_CE[5:2] high(SS = 1) -3 0 +3 ns 18 tsu(EMDQMV-EMWEL) Outputsetuptime,EMA_BA[1:0] validtoEMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns 19 th(EMWEH-EMDQMIV) Outputholdtime,EMA_WE hightoEMA_BA[1:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns 20 tsu(EMBAV-EMWEL) Outputsetuptime,EMA_BA[1:0] validtoEMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns 21 th(EMWEH-EMBAIV) Outputholdtime,EMA_WE hightoEMA_BA[1:0] invalid (WH)*E-3 (WH)*E (WH)*E+3 ns 22 tsu(EMAV-EMWEL) Outputsetuptime,EMA_A[13:0]validtoEMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns 23 th(EMWEH-EMAIV) Outputholdtime,EMA_WE hightoEMA_A[13:0]invalid (WH)*E-3 (WH)*E (WH)*E+3 ns (1) TA = Turnaround,RS = Read setup,RST = Read strobe,RH = Read hold,WS = Writesetup,WST = Writestrobe,WH = Writehold,MEWC = Maximum externalwaitcycles.These parametersareprogrammed viatheAsynchronousBank and AsynchronousWaitCycleConfigurationRegisters.These supportthefollowingrangeofvalues:TA[4-1],RS[16-1],RST[64- 1],RH[8-1],WS[16-1],WST[64-1],WH[8-1],and MEW[1-256]. (2) E = EMA_CLK periodorinns.EMA_CLK isselectedeitheras SYSCLK3 orthePLL0 outputclockdividedby 4.5.As an example,when SYSCLK3 isselectedand setto100MHz, E=10ns. (3) EWC = externalwaitcyclesdeterminedby EMA_WAIT inputsignal.EWC supportsthefollowingrangeofvaluesEWC[256-1].Note thatthemaximum waittimebeforetimeoutisspecified by bitfieldMEWC intheAsynchronousWaitCycleConfigurationRegister. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 123 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

EMA_CS[5:2] EMA_BA[1:0] EMA_A[22:0] EMA_OE EMA_D[15:0] EMA_WE 3 1 EMA_ _DQM[1:0]WE EMA_A_RW OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-24.SwitchingCharacteristicsforEMIFA Asynchronous Memory Interface(1)(2)(3) (continued) NO. PARAMETER UNIT MIN Nom MAX EMA_WE activelowwidth(EW = 0) (WST)*E-3 (WST)*E (WST)*E+3 ns 24 tw(EMWEL) EMA_WE activelowwidth(EW = 1) (WST+(EWC*16))*E-3 (WST+(EWC*16))*E (WST+(EWC*16))*E+3 ns 25 td(EMWAITH-EMWEH) DelaytimefromEMA_WAIT deassertedtoEMA_WE high 3E-3 4E 4E+3 ns 26 tsu(EMDV-EMWEL) Outputsetuptime,EMA_D[15:0]validtoEMA_WE low (WS)*E-3 (WS)*E (WS)*E+3 ns 27 th(EMWEH-EMDIV) Outputholdtime,EMA_WE hightoEMA_D[15:0]invalid (WH)*E-3 (WH)*E (WH)*E+3 ns Figure5-15.Asynchronous Memory Read Timing forEMIFA

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EMA_CS[5:2] Asserted Deasserted EMA_BA[1:0] EMA_A[22:0] EMA_D[15:0] EMA_OE EMA_WAIT SETUP STROBE Extended Due to EMA_WAIT STROBE HOLD EMA_A_RW EMA_CS[5:2] EMA_BA[1:0] EMA_A[22:0] EMA_WE EMA_D[15:0] EMA_OE 26 27 EMA_ _DQM[1:0]WE EMA_A_RW OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-16.Asynchronous Memory WriteTiming forEMIFA Figure5-17.EMA_WAIT Read Timing Requirements Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 125 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

EMA_A[22:0] EMA_CS[5:2] EMA_BA[1:0] EMA_D[15:0] EMA_A_RW EMA_WE EMA_WAIT OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-18.EMA_WAIT WriteTiming Requirements

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5.11 DDR2/mDDR Controller

The DDR2/mDDR Memory Controlleris a dedicatedinterfaceto DDR2/mDDR SDRAM. Itsupports JESD79-2A standardcompliantDDR2 SDRAM devicesand compliantMobileDDR SDRAM devices. The DDR2/mDDR Memory Controllersupportthefollowingfeatures:

JESD79-2A standardcompliantDDR2 SDRAM
MobileDDR SDRAM
512 MByte memory space forDDR2
256 MByte memory space formDDR
CAS latencies: – DDR2: 2,3,4 and 5 – mDDR: 2 and 3
Internalbanks: – DDR2: 1,2,4 and 8 – mDDR:1, 2 and 4
Burstlength:8
Bursttype:sequential
1 chipselect(CS)signal
Page sizes:256,512,1024 and 2048
SDRAM autoinitialization
Self-refreshmode
Partialarrayself-refresh(formDDR)
Power down mode
Prioritizedrefresh
Programmable refreshrateand backlogcounter
Programmable timingparameters
Littleendian

5.11.1 DDR2/mDDR Memory ControllerElectricalData/Timing

Table5-25.SwitchingCharacteristicsOver Recommended OperatingConditionsforDDR2/mDDR Memory Controller(1) MIN MAX MIN MAX MIN MAX DDR2 125 156 125 150 — (2) — (2) Cycletime,1 tc(DDR_CLK) MHzDDR_CLKP /DDR_CLKN mDDR 105 150 100 133 95 133 (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) DDR2 isnotsupportedatthisvoltageoperatingpoint. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 127 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.11.2 DDR2/mDDR ControllerRegisterDescription(s)

Table5-26.DDR2/mDDR ControllerRegisters BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0xB000 0000 REVID RevisionID Register 0xB000 0004 SDRSTAT SDRAM StatusRegister 0xB000 0008 SDCR SDRAM ConfigurationRegister 0xB000 000C SDRCR SDRAM RefreshControlRegister 0xB000 0010 SDTIMR1 SDRAM TimingRegister1 0xB000 0014 SDTIMR2 SDRAM TimingRegister2 0xB000 001C SDCR2 SDRAM ConfigurationRegister2 0xB000 0020 PBBPR PeripheralBus BurstPriorityRegister 0xB000 0040 PC1 PerformanceCounter1 Registers 0xB000 0044 PC2 PerformanceCounter2 Register 0xB000 0048 PCC PerformanceCounterConfigurationRegister 0xB000 004C PCMRS PerformanceCounterMasterRegionSelectRegister 0xB000 0050 PCT PerformanceCounterTime Register 0xB000 00C0 IRR InterruptRaw Register 0xB000 00C4 IMR InterruptMask Register 0xB000 00C8 IMSR InterruptMask SetRegister 0xB000 00CC IMCR InterruptMask ClearRegister 0xB000 00E4 DRPYC1R DDR PHY ControlRegister1 0x01E2 C000 VTPIO_CTL VTP IO ControlRegister

5.11.3 DDR2/mDDR Interface

This sectionprovidesthe timingspecificationforthe DDR2/mDDR interfaceas a PCB design and manufacturingspecification.The design rulesconstrainPCB tracelength,PCB traceskew, signal integrity,cross-talk,and signaltiming.These rules,when followed,resultin a reliableDDR2/mDDR memory system withouttheneed fora complex timingclosureprocess.For more informationregarding guidelinesforusingthisDDR2/mDDR specification,UnderstandingTI'sPCB RoutingRule-BasedDDR2 TimingSpecification(SPRAAV0 ). 5.11.3.1DDR2/mDDR InterfaceSchematic Figure5-19 shows theDDR2/mDDR interfaceschematicfora single-memoryDDR2/mDDR system.The dual-memory system shown inFigure5-20. Pin numbers forthe devicecan be obtainedfrom the pin descriptionsection.

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DDR2/mDDR Memory Controller DDR_D[7] DDR2/mDDR DDR_DQM[0] ODT DQ0 DQ7 DDR_D[8] DDR_D[15] DQ8 DQ15 LDM LDQS LDQS DDR_DQM[1] DDR_DQS[1] UDM UDQS UDQS DDR_BA[0] DDR_BA[2] BA0 BA2 DDR_A[0] DDR_A[13] DDR_CS DDR_CAS CS CAS DDR_RAS DDR_WE RAS WE DDR_CKE CKE DDR_CLKP DDR_CLKN CK CK DDR_DQGATE0 DDR_DQGATE1 DDR_ZP DDR_VREF

1 K Ω 1%

DDR_DVDD18 VREF 1 K Ω 1%0.1 μF 0.1 μF

0.1 F μ

(2) (2) 50 5 Ω % T Terminator, if desired. See terminator comments. DQ7 A13 0.1 μF 0.1 μF T Terminator, if desired. See terminator comments. DDR_D[0] NC TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT TTT T T T T T T VREF (3) T Terminator, if desired. See terminator comments. (2) DDR_DQS[0] NC (1) OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 (1) See Figure5-26forDQGATE routingspecifications. (2) ForDDR2, one ofthesecapacitorscan be eliminatedifthedividerand itscapacitorsareplacedneara deviceVREF pin.FormDDR, thesecapacitorscan be eliminatedcompletely. (3) VREF appliesinthecase ofDDR2 memories.FormDDR, theDDR_VREF pinstillneeds tobe connectedtothedividercircuit. Figure5-19.DDR2/mDDR Single-Memory High LevelSchematic Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 129 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

DDR2/mDDR Memory Controller DDR_D[0:7] Lower ByteDDR2/mDDR DDR_DQM[0] DDR_DQS[0] ODT DQ0 - DQ7 BA0-BA2CK CK DM DQS DQS CS CAS RAS DDR_BA[0:2] CKE BA0-BA2 DDR_A[0:13] DDR_CLKP A0-A13 DDR_CLKN DDR_CS CK CS DDR_CAS DDR_RAS CAS RAS DDR_WE WE DDR_D[8:15] DQS DQ0 - DQ7 DDR_DQGATE0 DDR_DQGATE1 T T T T T T T T T T T T T T DDR_ZP VREF (3) DDR_VREF DDR_DVDD18 VREF 1 K Ω 1%0.1 μF 0.1 μF 0.1 μF (2) 0.1 μF (2) 0.1 μF (2) 50 5 Ω % T Terminator, if desired. See terminator comments. ODT A0-A13 WE VREF Upper ByteDDR2/mDDR CK DDR_CKE CKET DDR_DQM1 DMT DDR_DQS1 DQST NC NC (1) OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com (1) See Figure5-26forDQGATE routingspecifications. (2) ForDDR2, one ofthesecapacitorscan be eliminatedifthedividerand itscapacitorsareplacedneara deviceVREF pin.FormDDR, thesecapacitorscan be eliminatedcompletely. (3) VREF appliesinthecase ofDDR2 memories.FormDDR, theDDR_VREF pinstillneeds tobe connectedtothedividercircuit. Figure5-20.DDR2/mDDR Dual-Memory High LevelSchematic

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 5.11.3.2Compatible JEDEC DDR2/mDDR Devices Table 5-27 shows the parametersof the JEDEC DDR2/mDDR devicesthatare compatiblewiththis interface.Generally,the DDR2/mDDR interfaceiscompatiblewithx16 DDR2/mDDR-400 speed grade DDR2/mDDR devices. The devicealsosupportsJEDEC DDR2/mDDR x8 devicesinthedualchipconfiguration.Inthiscase,one chipsuppliesthe upper byteand the second chipsuppliesthe lowerbyte.Addresses and most control signalsaresharedjustlikeregulardualchipmemory configurations. Table5-27.Compatible JEDEC DDR2/mDDR Devices NO. PARAMETER MIN MAX UNIT

1 JEDEC DDR2/mDDR DeviceSpeed Grade(1) DDR2/mDDR-400

2 JEDEC DDR2/mDDR DeviceBitWidth x8 x16 Bits

3 JEDEC DDR2/mDDR DeviceCount(2) 1 2 Devices

(1) HigherDDR2/mDDR speed gradesaresupporteddue toinherentJEDEC DDR2/mDDR backwardscompatibility. (2) Supportedconfigurationsareone 16-bitDDR2/mDDR memory ortwo 8-bitDDR2/mDDR memories 5.11.3.3PCB Stackup The minimum stackuprequiredforroutingthe deviceis a sixlayerstackas shown in Table 5-28. Additionallayersmay be added tothePCB stackup toaccommodate othercircuitryortoreducethesize ofthePCB footprint.Completestackup specificationsareprovidedinTable5-29. Table5-28.Device Minimum PCB Stack Up LAYER TYPE DESCRIPTION

1 Signal Top RoutingMostlyHorizontal

2 Plane Ground

3 Plane Power

4 Signal InternalRouting

5 Plane Ground

6 Signal BottomRoutingMostlyVertical

Table5-29.PCB Stack Up Specifications NO. PARAMETER MIN TYP MAX UNIT

1 PCB Routing/PlaneLayers 6

2 SignalRoutingLayers 3

3 FullgroundlayersunderDDR2/mDDR routingregion 2

4 Number ofgroundplanecutsallowedwithinDDR routingregion 0

5 Number ofgroundreferenceplanesrequiredforeach DDR2/mDDR routinglayer 1

6 Number oflayersbetween DDR2/mDDR routinglayerand referencegroundplane 0

7 PCB RoutingFeatureSize 4 Mils

8 PCB TraceWidthw 4 Mils

8 PCB BGA escape viapad size 18 Mils

9 PCB BGA escape viaholesize 8 Mils

10 DeviceBGA pad size(1)

11 DDR2/mDDR DeviceBGA pad size(2)

12 SingleEnded Impedance,Zo 50 75 Ω

13 Impedance Control(3) Z-5 Z Z+5 Ω

(1) PleaserefertotheFlipChipBallGridArrayPackage ReferenceGuide (SPRU811 )fordeviceBGA pad size. (2) PleaserefertotheDDR2/mDDR devicemanufacturerdocumentationfortheDDR2/mDDR deviceBGA pad size. (3) Z isthenominalsingledended impedance selectedforthePCB specifiedby item12. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 131 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

X Y OFFSET Recommended□DDR2/mDDR Device□Orientation Y Y OFFSET DDR2/mDDR Device DDR2/mDDRController OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com 5.11.3.4Placement Figure5-20 shows the requiredplacementforthe deviceas wellas the DDR2/mDDR devices.The dimensionsforFigure5-21aredefinedinTable5-30.The placementdoes notrestrictthesideofthePCB thatthe devicesare mounted on. The ultimatepurpose of the placementisto limitthe maximum trace lengthsand allowforproper routingspace. For single-memoryDDR2/mDDR systems,the second DDR2/mDDR deviceisomittedfromtheplacement. Figure5-21.OMAPL138 and DDR2/mDDR Device Placement Table5-30.Placement Specifications(1)(2) NO. PARAMETER MIN MAX UNIT

1 X 1750 Mils

2 Y 1280 Mils

3 Y Offset (3)650 Mils

4 Clearancefromnon-DDR2/mDDR signaltoDDR2/mDDR KeepoutRegion(4) 4 w (5)

(1) See Figure5-21fordimensiondefinitions. (2) Measurements fromcenterofdevicetocenterofDDR2/mDDR device. (3) Forsinglememory systemsitisrecommended thatY Offsetbe as smallas possible. (4) Non-DDR2/mDDR signalsallowedwithinDDR2/mDDR keepoutregionprovidedtheyareseparatedfromDDR2/mDDR routinglayersby a groundplane. (5) w = PCB tracewidthas definedinTable5-29.

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Region□should□encompass□all□DDR2/mDDR□circuitry□and□varies depending□on□placement.□Non-DDR2/mDDR□signals□should□not□be routed□on□the□DDR□signal□layers□within□the□DDR2/mDDR□keep□out region.□Non-DDR2/mDDR□signals□may□be□routed□in□the□region provided□they□are□routed□on□layers□separated□from□DDR2/mDDR signal□layers□by□a□ground□layer.□No□breaks□should□be□allowed□in□the reference□ground□layers□in□this□region.□In□addition,□the□1.8□V□power plane□should□cover□the□entire□keep□out□region. OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 5.11.3.5DDR2/mDDR Keep Out Region The regionof the PCB used forthe DDR2/mDDR circuitrymust be isolatedfrom othersignals.The DDR2/mDDR keep out regionisdefinedforthispurpose and isshown inFigure5-22. The sizeof this regionvarieswiththeplacementand DDR routing.Additionalclearancesrequiredforthekeep outregion areshown inTable5-30. Figure5-22.DDR2/mDDR Keepout Region Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 133 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com 5.11.3.6Bulk Bypass Capacitors Bulk bypass capacitorsare requiredformoderate speed bypassingof the DDR2/mDDR and other circuitry.Table 5-31 containsthe minimum numbers and capacitancerequiredforthe bulk bypass capacitors.Note thatthistableonlycoversthe bypass needs of the Soc and DDR2/mDDR interfaces. Additionalbulkbypasscapacitancemay be needed forothercircuitry. Table5-31.Bulk Bypass Capacitors NO. PARAMETER MIN MAX UNIT

1 DDR_DVDD18 SupplyBulkBypass CapacitorCount(1) 3 Devices

2 DDR_DVDD18 SupplyBulkBypass TotalCapacitance 30 μF

3 DDR#1 BulkBypass CapacitorCount(1) 1 Devices

4 DDR#1 BulkBypass TotalCapacitance 22 μF

5 DDR#2 BulkBypass CapacitorCount(1)(2) 1 Devices

6 DDR#2 BulkBypass TotalCapacitance(2) 22 μF

(1) These devicesshouldbe placednearthedevicetheyarebypassing,butpreferenceshouldbe giventotheplacementofthehigh-speed (HS)bypasscaps. (2) Onlyused on dual-memorysystems. 5.11.3.7High-Speed Bypass Capacitors High-speed (HS) bypass capacitorsare criticalfor proper DDR2/mDDR interfaceoperation.It is particularlyimportanttominimizetheparasiticseriesinductanceoftheHS bypass cap,Soc/DDR2/mDDR power, and Soc/DDR2/mDDR ground connections.Table 5-32 containsthe specificationforthe HS bypasscapacitorsas wellas forthepower connectionson thePCB. Table5-32.High-Speed Bypass Capacitors NO. PARAMETER MIN MAX UNIT

1 HS Bypass CapacitorPackage Size(1) 0402 10 Mils

2 DistancefromHS bypasscapacitortodevicebeingbypassed 250 Mils

3 Number ofconnectionviasforeach HS bypasscapacitor 2(2) Vias

4 Tracelengthfrombypasscapacitorcontacttoconnectionvia 1 30 Mils

5 Number ofconnectionviasforeach DDR2/mDDR devicepower orgroundballs 1 Vias

6 TracelengthfromDDR2/mDDR devicepower balltoconnectionvia 35 Mils

7 DDR_DVDD18 SupplyHS Bypass CapacitorCount(3) 10 Devices

8 DDR_DVDD18 SupplyHS Bypass CapacitorTotalCapacitance 0.6 μF

9 DDR#1 HS Bypass CapacitorCount(3) 8 Devices

10 DDR#1 HS Bypass CapacitorTotalCapacitance 0.4 μF

11 DDR#2 HS Bypass CapacitorCount(3)(4) 8 Devices

12 DDR#2 HS Bypass CapacitorTotalCapacitance(4) 0.4 μF (1) LxW, 10 milunits,i.e.,a 0402 isa 40x20 milsurfacemount capacitor (2) An additionalHS bypasscapacitorcan sharetheconnectionviasonlyifitismounted on theoppositesideoftheboard. (3) These devicesshouldbe placedas closeas possibletothedevicebeingbypassed. (4) Onlyused on dual-memorysystems.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 5.11.3.8Net Classes Table 5-33 liststhe clocknet classesforthe DDR2/mDDR interface.Table 5-34 liststhe signalnet classes,and associatedclocknetclasses,forthesignalsintheDDR2/mDDR interface.These netclasses areused fortheterminationand routingrulesthatfollow. Table5-33.Clock Net Class Definitions CLOCK NET CLASS Soc PIN NAMES CK DDR_CLKP /DDR_CLKN DQS0 DDR_DQS[0] DQS1 DDR_DQS[1] Table5-34.SignalNet Class Definitions ASSOCIATED CLOCK SIGNAL NET CLASS NET CLASS Soc PIN NAMES ADDR_CTRL CK DDR_BA[2:0],DDR_A[13:0],DDR_CS, DDR_CAS, DDR_RAS, DDR_WE, DDR_CKE D0 DQS0 DDR_D[7:0],DDR_DQM0 D1 DQS1 DDR_D[15:8],DDR_DQM1 DQGATE CK, DQS0, DQS1 DDR_DQGATE0, DDR_DQGATE1 5.11.3.9DDR2/mDDR SignalTermination No terminationsof any kindare requiredinorderto meet signalintegrityand overshootrequirements. Serialterminatorsare permitted,ifdesired,toreduceEMI risk;however,serialterminationsare theonly typepermitted.Table5-35shows thespecificationsfortheseriesterminators. Table5-35.DDR2/mDDR SignalTerminations(1)(2)(3) NO. PARAMETER MIN TYP MAX UNIT

1 CK Net Class 0 10 Ω

2 ADDR_CTRL Net Class 0 22 Zo Ω

3 Data ByteNet Classes(DQS[0],DQS[1],D0, D1)(4) 0 22 Zo Ω

4 DQGATE Net Class(DQGATE) 0 10 Zo Ω

(1) Onlyseriesterminationispermitted,parallelorSST specificallydisallowed. (2) Terminatorvalueslargerthantypicalonlyrecommended toaddressEMI issues. (3) Terminationvalueshouldbe uniformacrossnetclass. (4) When no terminationisused on datalines(0Ω),theDDR2/mDDR devicesmust be programmed tooperatein60% strengthmode. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 135 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

DDR2/mDDR□Device VREF□Nominal□Minimum Trace□Width□is□20□Mils VREF□Bypass□Capacitor Neck□down□to□minimum□in□BGA escape regions□is□acceptable.□Narrowing□to accomodate□via□congestion□for□short distances□is□also□acceptable.□Best performance□is□obtained□if□the□width of□VREF□is□maximized. DDR2/mDDR OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com 5.11.3.10VREF Routing VREF is used as a referenceby the inputbuffersof the DDR2/mDDR memories as wellas the OMAPL138. VREF isintendedtobe halftheDDR2/mDDR power supplyvoltageand shouldbe created usinga resistivedivideras shown inFigure5-19.Othermethods ofcreatingVREF arenotrecommended. Figure5-23shows thelayoutguidelinesforVREF. Figure5-23.VREF Routing and Topology

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A T DDR2/mDDRController OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 5.11.3.11DDR2/mDDR CK and ADDR_CTRL Routing Figure5-24 shows thetopologyoftheroutingfortheCK and ADDR_CTRL netclasses.The routeisa balancedT as itisintendedthatthelengthofsegments B and C be equal.Inaddition,thelengthofA shouldbe maximized. Figure5-24.CK and ADDR_CTRL Routing and Topology Table5-36.CK and ADDR_CTRL Routing Specification NO. PARAMETER MIN TYP MAX UNIT

1 CentertoCenterCK-CKN Spacing(1) 2w (2)

2 CK A toB/A toC Skew LengthMismatch(3) 25 Mils

3 CK B toC Skew LengthMismatch 25 Mils

4 CentertocenterCK tootherDDR2/mDDR tracespacing(1) 4w (2)

5 CK/ADDR_CTRL nominaltracelength(4) CACLM-50 CACLM CACLM+50 Mils

6 ADDR_CTRL toCK Skew LengthMismatch 100 Mils

7 ADDR_CTRL toADDR_CTRL Skew LengthMismatch 100 Mils

8 CentertocenterADDR_CTRL tootherDDR2/mDDR tracespacing(1) 4w (2)

9 CentertocenterADDR_CTRL tootherADDR_CTRL tracespacing(1) 3w (2)

10 ADDR_CTRL A toB/A toC Skew LengthMismatch(3) 100 Mils

11 ADDR_CTRL B toC Skew LengthMismatch 100 Mils

(1) Centertocenterspacingisallowedtofalltominimum (w)forup to500 milsofroutedlengthtoaccommodate BGA escape and routing congestion. (2) w = PCB tracewidthas definedinTable5-29. (3) Seriesterminator,ifused,shouldbe locatedclosesttodevice. (4) CACLM isthelongestManhattandistanceoftheCK and ADDR_CTRL netclasses. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 137 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

T DDR2/mDDRController T OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-25 shows thetopologyand routingfortheDQS and D netclass;theroutesare pointtopoint. Skew matchingacrossbytesisnotneeded norrecommended. Figure5-25.DQS and D Routing and Topology Table5-37.DQS and D Routing Specification NO. PARAMETER MIN TYP MAX UNIT

1 CentertocenterDQS tootherDDR2/mDDR tracespacing(1) 4w (2)

2 DQS/D nominaltracelength(3)(4) DQLM-50 DQLM DQLM+50 Mils

3 D toDQS Skew LengthMismatch(4) 100 Mils

4 D toD Skew LengthMismatch(4) 100 Mils

5 CentertocenterD tootherDDR2/mDDR tracespacing(1)(5) 4w (2)

6 CentertoCenterD tootherD tracespacing(1)(6) 3w (2)

(1) Centertocenterspacingisallowedtofalltominimum (w)forup to500 milsofroutedlengthtoaccommodate BGA escape and routing congestion. (2) w = PCB tracewidthas definedinTable5-29. (3) Seriesterminator,ifused,shouldbe locatedclosesttoDDR. (4) Thereisno need and itisnotrecommended toskew match acrossdatabytes,i.e.,fromDQS0 and databyte0 toDQS1 and databyte (5) D 's fromotherDQS domains areconsideredotherDDR2/mDDR trace. (6) DQLM isthelongestManhattandistanceofeach oftheDQS and D netclass.

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T T DDR2/mDDRController F OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-26shows theroutingfortheDQGATE netclass.Table5-38containstheroutingspecification. Figure5-26.DQGATE Routing Table5-38.DQGATE Routing Specification NO. PARAMETER MIN TYP MAX UNIT

1 DQGATE LengthF CKB0B (1)

2 CentertocenterDQGATE toany othertracespacing 4w (2)

3 DQS/D nominaltracelength DQLM-50 DQLM DQLM+50 Mils

4 DQGATE Skew (3) 100 Mils

(1) CKB0B1 isthesum ofthelengthoftheCK netplustheaveragelengthoftheDQS0 and DQS1 nets. (2) w = PCB tracewidthas definedinTable5-29. (3) Skew fromCKB0B1 5.11.3.12MDDR/DDR2 Boundary Scan Limitations Due to DDR implementationand timingrestrictions,itwas not possibleto placeboundary scan cells between corelogicand theIO likeboundaryscan cellsforotherIO.Instead,theboundaryscan cellsare tapped-offtotheDDR PHY and thereistheequivalentofa multiplexerinsidetheDDR PHY whichselects between functionaland boundaryscan paths. The implicationforboundaryscan isthattheDDR pinswillnotsupporttheSAMPLE functionoftheoutput enable cellson the DDR pins and thisis a violationof IEEE 1149.1.FullEXTEST and PRELOAD capabilityisstillavailable. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 139 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.12 Memory ProtectionUnits

The MPU performsmemory protectionchecking.Itreceivesrequestsfroma bus masterinthesystemand checkstheaddressagainstthefixedand programmableregionstosee iftheaccessisallowed.Ifallowed, thetransferispassed unmodifiedtoitsoutputbus (tothetargetedaddress).Ifthetransferisillegal(fails theprotectioncheck)thentheMPU does notpass thetransfertotheoutputbus butratherservicesthe transferinternallyback totheinputbus (topreventa hang) returningthefaultstatustotherequestoras wellas generatingan interruptaboutthefault.The followingfeaturesaresupportedby theMPU:

Providesmemory protectionforfixedand programmableaddressranges.
Supportsmultipleprogrammableaddressregion.
Supportssecureand debug accessprivileges.
Supportsread,write,and executeaccessprivileges.
Supportsprivid(8)associationswithranges.
Generatesan interruptwhen thereisa protectionviolation,and savesviolatingtransferparameters.
MMR accessisalsoprotected. Table5-39.MPU1 ConfigurationRegisters MPU1 ACRONYM REGISTER DESCRIPTIONBYTE ADDRESS 0x01E1 4000 REVID RevisionID 0x01E1 4004 CONFIG Configuration 0x01E1 4010 IRAWSTAT Interruptraw status/set 0x01E1 4014 IENSTAT Interruptenablestatus/clear 0x01E1 4018 IENSET Interruptenable 0x01E1 401C IENCLR Interruptenableclear 0x01E1 4020 -0x01E1 41FF - Reserved 0x01E1 4200 PROG1_MPSAR Programmable range1,startaddress 0x01E1 4204 PROG1_MPEAR Programmable range1,end address 0x01E1 4208 PROG1_MPPA Programmable range1,memory page protectionattributes 0x01E1 420C -0x01E1 420F - Reserved 0x01E1 4210 PROG2_MPSAR Programmable range2,startaddress 0x01E1 4214 PROG2_MPEAR Programmable range2,end address 0x01E1 4218 PROG2_MPPA Programmable range2,memory page protectionattributes 0x01E1 421C -0x01E1 421F - Reserved 0x01E1 4220 PROG3_MPSAR Programmable range3,startaddress 0x01E1 4224 PROG3_MPEAR Programmable range3,end address 0x01E1 4228 PROG3_MPPA Programmable range3,memory page protectionattributes 0x01E1 422C -0x01E1 422F - Reserved 0x01E1 4230 PROG4_MPSAR Programmable range4,startaddress 0x01E1 4234 PROG4_MPEAR Programmable range4,end address 0x01E1 4238 PROG4_MPPA Programmable range4,memory page protectionattributes 0x01E1 423C -0x01E1 423F - Reserved 0x01E1 4240 PROG5_MPSAR Programmable range5,startaddress 0x01E1 4244 PROG5_MPEAR Programmable range5,end address 0x01E1 4248 PROG5_MPPA Programmable range5,memory page protectionattributes 0x01E1 424C -0x01E1 424F - Reserved 0x01E1 4250 PROG6_MPSAR Programmable range6,startaddress 0x01E1 4254 PROG6_MPEAR Programmable range6,end address 0x01E1 4258 PROG6_MPPA Programmable range6,memory page protectionattributes 0x01E1 425C -0x01E1 42FF - Reserved

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-39.MPU1 ConfigurationRegisters(continued) MPU1 ACRONYM REGISTER DESCRIPTIONBYTE ADDRESS 0x01E1 4300 FLTADDRR Faultaddress 0x01E1 4304 FLTSTAT Faultstatus 0x01E1 4308 FLTCLR Faultclear 0x01E1 430C -0x01E1 4FFF - Reserved Table5-40.MPU2 ConfigurationRegisters MPU2 ACRONYM REGISTER DESCRIPTIONBYTE ADDRESS 0x01E1 5000 REVID RevisionID 0x01E1 5004 CONFIG Configuration 0x01E1 5010 IRAWSTAT Interruptraw status/set 0x01E1 5014 IENSTAT Interruptenablestatus/clear 0x01E1 5018 IENSET Interruptenable 0x01E1 501C IENCLR Interruptenableclear 0x01E1 5020 -0x01E1 51FF - Reserved 0x01E1 5200 PROG1_MPSAR Programmable range1,startaddress 0x01E1 5204 PROG1_MPEAR Programmable range1,end address 0x01E1 5208 PROG1_MPPA Programmable range1,memory page protectionattributes 0x01E1 520C -0x01E1 520F - Reserved 0x01E1 5210 PROG2_MPSAR Programmable range2,startaddress 0x01E1 5214 PROG2_MPEAR Programmable range2,end address 0x01E1 5218 PROG2_MPPA Programmable range2,memory page protectionattributes 0x01E1 521C -0x01E1 521F - Reserved 0x01E1 5220 PROG3_MPSAR Programmable range3,startaddress 0x01E1 5224 PROG3_MPEAR Programmable range3,end address 0x01E1 5228 PROG3_MPPA Programmable range3,memory page protectionattributes 0x01E1 522C -0x01E1 522F - Reserved 0x01E1 5230 PROG4_MPSAR Programmable range4,startaddress 0x01E1 5234 PROG4_MPEAR Programmable range4,end address 0x01E1 5238 PROG4_MPPA Programmable range4,memory page protectionattributes 0x01E1 523C -0x01E1 523F - Reserved 0x01E1 5240 PROG5_MPSAR Programmable range5,startaddress 0x01E1 5244 PROG5_MPEAR Programmable range5,end address 0x01E1 5248 PROG5_MPPA Programmable range5,memory page protectionattributes 0x01E1 524C -0x01E1 524F - Reserved 0x01E1 5250 PROG6_MPSAR Programmable range6,startaddress 0x01E1 5254 PROG6_MPEAR Programmable range6,end address 0x01E1 5258 PROG6_MPPA Programmable range6,memory page protectionattributes 0x01E1 525C -0x01E1 525F - Reserved 0x01E1 5260 PROG7_MPSAR Programmable range7,startaddress 0x01E1 5264 PROG7_MPEAR Programmable range7,end address 0x01E1 5268 PROG7_MPPA Programmable range7,memory page protectionattributes 0x01E1 526C -0x01E1 526F - Reserved 0x01E1 5270 PROG8_MPSAR Programmable range8,startaddress 0x01E1 5274 PROG8_MPEAR Programmable range8,end address 0x01E1 5278 PROG8_MPPA Programmable range8,memory page protectionattributes 0x01E1 527C -0x01E1 527F - Reserved Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 141 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-40.MPU2 ConfigurationRegisters(continued) MPU2 ACRONYM REGISTER DESCRIPTIONBYTE ADDRESS 0x01E1 5280 PROG9_MPSAR Programmable range9,startaddress 0x01E1 5284 PROG9_MPEAR Programmable range9,end address 0x01E1 5288 PROG9_MPPA Programmable range9,memory page protectionattributes 0x01E1 528C -0x01E1 528F - Reserved 0x01E1 5290 PROG10_MPSAR Programmable range10,startaddress 0x01E1 5294 PROG10_MPEAR Programmable range10,end address 0x01E1 5298 PROG10_MPPA Programmable range10,memory page protectionattributes 0x01E1 529C -0x01E1 529F - Reserved 0x01E1 52A0 PROG11_MPSAR Programmable range11,startaddress 0x01E1 52A4 PROG11_MPEAR Programmable range11,end address 0x01E1 52A8 PROG11_MPPA Programmable range11,memory page protectionattributes 0x01E1 52AC -0x01E1 52AF - Reserved 0x01E1 52B0 PROG12_MPSAR Programmable range12,startaddress 0x01E1 52B4 PROG12_MPEAR Programmable range12,end address 0x01E1 52B8 PROG12_MPPA Programmable range12,memory page protectionattributes 0x01E1 52BC -0x01E1 52FF - Reserved 0x01E1 5300 FLTADDRR Faultaddress 0x01E1 5304 FLTSTAT Faultstatus 0x01E1 5308 FLTCLR Faultclear 0x01E1 530C -0x01E1 5FFF - Reserved

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5.13 MMC /SD /SDIO (MMCSD0, MMCSD1)

5.13.1 MMCSD PeripheralDescription

The deviceincludesan two MMCSD controllerswhicharecompliantwithMMC V4.0,SecureDigitalPart1 PhysicalLayerSpecificationV1.1and SecureDigitalInputOutput(SDIO)V2.0specifications. The MMC/SD Controllerhave followingfeatures:

MultiMediaCard(MMC)
SecureDigital(SD)Memory Card
MMC/SD protocolsupport
SD highcapacitysupport
SDIO protocolsupport
Programmable clockfrequency
512 bitRead/WriteFIFO tolowersystemoverhead
SlaveEDMA transfercapability The deviceMMC/SD Controllerdoes notsupportSPI mode.

5.13.2 MMCSD PeripheralRegisterDescription(s)

Table5-41.MultimediaCard/SecureDigital(MMC/SD) Card ControllerRegisters MMCSD0 MMCSD1 ACRONYM REGISTER DESCSRIPTIONBYTE ADDRESS BYTE ADDRESS 0x01C4 0000 0x01E1 B000 MMCCTL MMC ControlRegister 0x01C4 0004 0x01E1 B004 MMCCLK MMC Memory ClockControlRegister 0x01C4 0008 0x01E1 B008 MMCST0 MMC StatusRegister0 0x01C4 000C 0x01E1 B00C MMCST1 MMC StatusRegister1 0x01C4 0010 0x01E1 B010 MMCIM MMC InterruptMask Register 0x01C4 0014 0x01E1 B014 MMCTOR MMC Response Time-OutRegister 0x01C4 0018 0x01E1 B018 MMCTOD MMC Data Read Time-OutRegister 0x01C4 001C 0x01E1 B01C MMCBLEN MMC BlockLengthRegister 0x01C4 0020 0x01E1 B020 MMCNBLK MMC Number ofBlocksRegister 0x01C4 0024 0x01E1 B024 MMCNBLC MMC Number ofBlocksCounterRegister 0x01C4 0028 0x01E1 B028 MMCDRR MMC Data ReceiveRegister 0x01C4 002C 0x01E1 B02C MMCDXR MMC Data TransmitRegister 0x01C4 0030 0x01E1 B030 MMCCMD MMC Command Register 0x01C4 0034 0x01E1 B034 MMCARGHL MMC Argument Register 0x01C4 0038 0x01E1 B038 MMCRSP01 MMC Response Register0 and 1 0x01C4 003C 0x01E1 B03C MMCRSP23 MMC Response Register2 and 3 0x01C4 0040 0x01E1 B040 MMCRSP45 MMC Response Register4 and 5 0x01C4 0044 0x01E1 B044 MMCRSP67 MMC Response Register6 and 7 0x01C4 0048 0x01E1 B048 MMCDRSP MMC Data Response Register 0x01C4 0050 0x01E1 B050 MMCCIDX MMC Command IndexRegister 0x01C4 0064 0x01E1 B064 SDIOCTL SDIO ControlRegister 0x01C4 0068 0x01E1 B068 SDIOST0 SDIO StatusRegister0 0x01C4 006C 0x01E1 B06C SDIOIEN SDIO InterruptEnableRegister 0x01C4 0070 0x01E1 B070 SDIOIST SDIO InterruptStatusRegister 0x01C4 0074 0x01E1 B074 MMCFIFOCTL MMC FIFO ControlRegister Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 143 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.13.3 MMC/SD ElectricalData/Timing

Table5-42throughTable5-43assume testingoverrecommended operatingconditions. Table5-42.Timing Requirements forMMC/SD (1) (seeFigure5-28and Figure5-30) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX tsu(CMDV-1 Setuptime,MMCSD_CMD validbeforeMMCSD_CLK high 4 4 6 ns CLKH) 2 th(CLKH-CMDV) Holdtime,MMCSD_CMD validafterMMCSD_CLK high 2.5 2.5 2.5 ns 3 tsu(DATV-CLKH) Setuptime,MMCSD_DATx validbeforeMMCSD_CLK high 4.5 5 6 ns 4 th(CLKH-DATV) Holdtime,MMCSD_DATx validafterMMCSD_CLK high 2.5 2.5 2.5 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Table5-43.SwitchingCharacteristicsforMMC/SD (1)(seeFigure5-27through Figure5-30) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 7 f(CLK) Operatingfrequency,MMCSD_CLK 0 52 0 50 0 25 MHz 8 f(CLK_ID) Identificationmode frequency,MMCSD_CLK 0 400 0 400 0 400 KHz 9 tW(CLKL) Pulsewidth,MMCSD_CLK low 6.5 6.5 10 ns 10 tW(CLKH) Pulsewidth,MMCSD_CLK high 6.5 6.5 10 ns 11 tr(CLK) Risetime,MMCSD_CLK 3 3 10 ns 12 tf(CLK) Falltime,MMCSD_CLK 3 3 10 ns 13 td(CLKL-CMD) Delaytime,MMCSD_CLK lowtoMMCSD_CMD transition -4 2.5 -4 3 -4 4 ns 14 td(CLKL-DAT) Delaytime,MMCSD_CLK lowtoMMCSD_DATx transition -4 3.3 -4 3.5 -4 4 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted.

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MMCSD_CLK MMCSD_DA Tx 3 3 ST ART D0 D1 Dx END MMCSD_CLK MMCSD_DATx 1414 14 14 ST ART XMIT V alid Valid Valid END MMCSD_CLK MMCSD_CMD 1097 ST ART XMIT V alid Valid Valid END MMCSD_CLK MMCSD_CMD 13 13 13 OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-27.MMC/SD Host Command Timing Figure5-28.MMC/SD Card Response Timing Figure5-29.MMC/SD Host WriteTiming Figure5-30.MMC/SD Host Read and Card CRC StatusTiming Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 145 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.14 SerialATA Controller(SATA)

The SerialATA Controller(SATA) providesa singleHBA portoperatinginAHCI mode and isused to interfaceto data storagedevicesat both 1.5 Gbits/secondand 3.0 Gbits/secondlinespeeds. AHCI describesa system memory structurethatcontainsa genericarea forcontroland status,and a tableof entriesdescribinga command listwhere each command listentrycontainsinformationnecessaryto programan SATA device,and a pointertoa descriptortablefortransferringdatabetween systemmemory and thedevice. The SATA Controllersupportsthefollowingfeatures:

SerialATA 1.5Gbps (Gen 1i)and 3 Gbps (Gen 2i)linespeeds
SupportfortheAHCI controllerspec 1.1
IntegratedSERDES PHY
IntegratedRx and Tx databuffers
SupportsallSATA power management features
InternalDMA engineperport
Hardware-assistednativecommand queuing(NCQ) forup to32 entries
32-bitaddressing
Supportsportmultiplierwithcommand-based switching
ActivityLED support
Mechanicalpresenceswitch
Coldpresencedetect The SATA Controllersupportisdependenton theCPU voltageoperatingpoint:
AtCVDD = 1.3V,SATA Gen 2i(3.0Gbps) and SATA Gen 1i(1.5Gbps) aresupported.
AtCVDD = 1.2V,SATA Gen 2i(3.0Gbps) and SATA Gen 1i(1.5Gbps) aresupported.
AtCVDD = 1.1V,SATA Gen 1i(1.5Gbps) onlyissupported.
AtCVDD = 1.0V,SATA isnotsupported.

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5.14.1 SATA RegisterDescriptions

Table5-44isa listoftheSATA Controllerregisters. Table5-44.SATA ControllerRegisters BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E1 8000 CAP HBA CapabilitiesRegister 0x01E1 8004 GHC GlobalHBA ControlRegister 0x01E1 8008 IS InterruptStatusRegister 0x01E1 800C PI PortsImplementedRegister 0x01E1 8010 VS AHCI VersionRegister 0x01E1 8014 CCC_CTL Command CompletionCoalescingControlRegister 0x01E1 8018 CCC_PORTS Command CompletionCoalescingPortsRegister 0x01E1 80A0 BISTAFR BIST ActiveFIS Register 0x01E1 80A4 BISTCR BIST ControlRegister 0x01E1 80A8 BISTFCTR BIST FIS Count Register 0x01E1 80AC BISTSR BIST StatusRegister 0x01E1 80B0 BISTDECR BIST DWORD ErrorCount Register 0x01E1 80E0 TIMER1MS BIST DWORD ErrorCount Register 0x01E1 80E8 GPARAM1R GlobalParameter1 Register 0x01E1 80EC GPARAM2R GlobalParameter2 Register 0x01E1 80F0 PPARAMR PortParameterRegister 0x01E1 80F4 TESTR TestRegister 0x01E1 80F8 VERSIONR VersionRegister 0x01E1 80FC IDR ID Register 0x01E1 8100 P0CLB PortCommand ListBase AddressRegister 0x01E1 8108 P0FB PortFIS Base AddressRegister 0x01E1 8110 P0IS PortInterruptStatusRegister 0x01E1 8114 P0IE PortInterruptEnableRegister 0x01E1 8118 P0CMD PortCommand Register 0x01E1 8120 P0TFD PortTask FileData Register 0x01E1 8124 P0SIG PortSignatureRegister 0x01E1 8128 P0SSTS PortSerialATA StatusRegister 0x01E1 812C P0SCTL PortSerialATA ControlRegister 0x01E1 8130 P0SERR PortSerialATA ErrorRegister 0x01E1 8134 P0SACT PortSerialATA ActiveRegister 0x01E1 8138 P0CI PortCommand IssueRegister 0x01E1 813C P0SNTF PortSerialATA NotificationRegister 0x01E1 8170 P0DMACR PortDMA ControlRegister 0x01E1 8178 P0PHYCR PortPHY ControlRegister 0x01E1 817C P0PHYSR PortPHY StatusRegister Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 147 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SA T A Interface(Processor) SA T A Connector SA T A_TXN SA T A_TXP SA T A_RXN SA T A_RXP SA T A_REFCLKN SA T A_REFCLKP TX– TX+ RX– RX+ L VDS Oscillator CLK– CLK+ SA T A_REG 0.1uF 10nF 10nF 10nF 10nF 10nF 10nF OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com 5.14.2 1.SATA Interface ThissectionprovidesthetimingspecificationfortheSATA interfaceas a PCB designand manufacturing specification.The designrulesconstrainPCB tracelength,PCB traceskew, signalintegrity,cross-talk, and signaltiming.TIhas performedthesimulationand system designwork toensuretheSATA interface requirementsaremet. 5.14.2.1SATA InterfaceSchematic Figure5-31shows theSATA interfaceschematic. Figure5-31.SATA InterfaceHigh LevelSchematic 5.14.2.2Compatible SATA Components and Modes Table5-45shows thecompatibleSATA components and supportedmodes. Note thattheonlysupported configurationisan internalcablefromtheprocessorhosttotheSATA device. Table5-45.SATA Supported Modes PARAMETER MIN MAX UNIT SUPPORTED TransferRates 1.5 3.0 Gbps eSATA No xSATA No Backplane No InternalCable Yes

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 5.14.2.3PCB Stackup Specifications Table5-46shows thestackupand featuresizesrequiredforSATA. Table5-46.SATA PCB Stackup Specifications PARAMETER MIN TYP MAX UNIT PCB Routing/PlaneLayers 4 6 Layers SignalRoutingLayers 2 3 Layers Number ofgroundplanecutsallowedwithinSATA routingregion 0 Layers Number oflayersbetween SATA routingregionand referencegroundplane 0 PCB RoutingFeatureSize 4 Mils PCB TraceWidthw 4 Mils PCB BGA escape viapad size 18 Mils PCB BGA escape viaholesize 8 Mils DeviceBGA pad size(1) (1) PleaserefertotheFlipChipBallGridArrayPackage ReferenceGuide (SPRU811 )fordeviceBGA pad size. 5.14.2.4Routing Specifications The SATA data signaltracesare edge-coupledand must be routedto achieveexactly100 Ohms differentialimpedance.This isimpactedby tracewidth,tracespacing,distancebetween planes,and dielectricmaterial.Verifywitha properPCB manufacturingtoolthatthe tracegeometry forboth data signalpairsresultsin exactly100 ohms differentialimpedance traces.Table 5-47 shows the routing specificationsforthedataand REFCLK signals. Table5-47.SATA Routing Specifications PARAMETER MIN TYP MAX UNIT DevicetoSATA headertracelength 7000 Mils REFCLK tracelengthfromoscillatortoDevice 2000 Mils Number ofstubsallowedon SATA traces 0 Stubs TX/RX pairdifferentialimpedance 100 Ohms Number ofviason each SATA trace 3 Vias(1) SATA differentialpairtoany othertracespacing 2*DS (2) (1) Viasmust be used inpairswiththeirdistanceminimized. (2) DS isthedifferentialspacingoftheSATA traces. 5.14.2.5Coupling Capacitors AC couplingcapacitorsare requiredon the receivedata pairas wellas the REFCLK pair.Table 5-48 shows therequirementsforthesecapacitors. Table5-48.SATA Bypass and Coupling CapacitorsRequirements PARAMETER MIN TYP MAX UNIT SATA AC couplingcapacitorvalue 0.3 10 12 nF SATA AC couplingcapacitorpackage size 0603 10 Mils(1)(2) (1) LxW, 10 milunits,i.e.,a 0402 isa 40x20 milsurfacemount capacitor. (2) The physicalsizeofthecapacitorshouldbe as smallas possible. 5.14.2.6SATA InterfaceClock Source requirements A high-quality,low-jitterdifferentialclocksource is requiredforthe SATA PHY. The SATA interface requiresa LVDS differentialclock source to be provided at signals SATA_REFCLKP and SATA_REFCLKN. The clocksourceshouldbe placedphysicallyas closetotheprocessoras possible. Table5-49shows therequirementsfortheclocksource. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 149 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-49.SATA InputClock Source Requirements(1) PARAMETER MIN TYP MAX UNIT ClockFrequency(2) 75 345 MHz Jitter 50 ps pk-pk DutyCycle 40 60 % Rise/FallTime 700 ps (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) Discreteclockfrequencypointsaresupportedbased on thePLL multiplierused intheSATA PHY.

5.14.3 SATA Unused SignalConfiguration

IftheSATA interfaceisnotused,theSATA signalsshouldbe configuredas shown below. Table5-50.Unused SATA SignalConfiguration SATA SignalName ConfigurationifSATA peripheralisnot used SATA_RXP No Connect SATA_RXN No Connect SATA_TXP No Connect SATA_TXN No Connect SATA_REFCLKP No Connect SATA_REFCLKN No Connect SATA_MPSWITCH May be used as GPIO orotherperipheralfunction SATA_CP_DET May be used as GPIO orotherperipheralfunction SATA_CP_POD May be used as GPIO orotherperipheralfunction SATA_LED May be used as GPIO orotherperipheralfunction SATA_REG No Connect SATA_VDDR No Connect SATA_VDD Priortosiliconrevision2.0,thissupplymust be connectedtoa static1.2Vnominalsupply.Forsilicon revision2.0and later,thissupplymay be leftunconnectedforadditionalpower conservation. SATA_VSS Vss

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Receive□Logic C lock/Fram e G enerator State□Machine Clock□Check□and Serializer□0 Serializer□1 Serializer□y GIO Control DIT□RAM 384□C 384□U Optional Transm it Form atter Receive Form atter Transm it Logic C lock/Fram e G enerator State□Machine McASP Peripheral Configuration Bus McASP DMA Bus (Dedicated) AHCLKRx ACLKRx AFSRx AMUTEINx AMUTEx AFSXx ACLKXx AHCLKXx AXRx[0] AXRx[1] AXRx[y] Pins Function Receive□Master□Clock Receive□Bit□Clock R eceive Left/R ight C lock or Fram e Sync Transm it M aster C lock Transm it B it C lock Transm it Left/R ight C lock or Fram e Sync Transm it/R eceive Serial D ata Pin Transm it/R eceive Serial D ata Pin Transm it/R eceive Serial D ata Pin Error□Detection The□McASP DOES□NOT□have□a dedicated AMUTEIN□pin. OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013

5.15 MultichannelAudio SerialPort(McASP)

The McASP serialportisspecificallydesignedformultichannelaudioapplications.Itskey featuresare:

Flexibleclockand framesyncgenerationlogicand on-chipdividers
Up tosixteentransmitorreceivedatapinsand serializers
Largenumber ofserialdataformatoptions,including: – TDM Frames with2 to32 timeslotsperframe(periodic)or1 slotperframe(burst) – Time slotsof8,12,16,20,24,28,and 32 bits – Firstbitdelay0,1,or2 clocks – MSB orLSB firstbitorder – Left-orright-aligneddatawords withintimeslots
DIT Mode with384-bitChannelStatusand 384-bitUser Data registers
Extensiveerrorcheckingand mute generationlogic
Allunused pinsGPIO-capable
Transmit& Receive FIFO Buffersallowthe McASP to operateat a highersample rateby making it more toleranttoDMA latency.
Dynamic AdjustmentofClockDividers – ClockDividerValuemay be changed withoutresettingtheMcASP Figure5-32.McASP Block Diagram Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 151 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com

5.15.1 McASP PeripheralRegistersDescription(s)

Registersforthe McASP are summarized in Table 5-51. The registersare accessed throughthe peripheralconfigurationport.The receivebufferregisters(RBUF) and transmitbufferregisters(XBUF) can alsobe accessedthroughtheDMA port,as listedinTable5-52 RegistersfortheMcASP Audio FIFO (AFIFO)are summarized inTable5-53.Note thattheAFIFO Write FIFO (WFIFO) and Read FIFO (RFIFO)have independentcontroland statusregisters.The AFIFO control registersareaccessedthroughtheperipheralconfigurationport. Table5-51.McASP RegistersAccessed Through PeripheralConfigurationPort BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01D0 0000 REV Revisionidentificationregister 0x01D0 0010 PFUNC Pinfunctionregister 0x01D0 0014 PDIR Pindirectionregister 0x01D0 0018 PDOUT Pindataoutputregister 0x01D0 001C PDIN Read returns:Pindatainputregister 0x01D0 001C PDSET Writesaffect:Pindatasetregister(alternatewriteaddress:PDOUT) 0x01D0 0020 PDCLR Pindataclearregister(alternatewriteaddress:PDOUT) 0x01D0 0044 GBLCTL Globalcontrolregister 0x01D0 0048 AMUTE Audiomute controlregister 0x01D0 004C DLBCTL Digitalloopbackcontrolregister 0x01D0 0050 DITCTL DIT mode controlregister 0x01D0 0060 Receiverglobalcontrolregister:AliasofGBLCTL, onlyreceivebitsareaffected-allowsRGBLCTL receivertobe resetindependentlyfromtransmitter 0x01D0 0064 RMASK Receiveformatunitbitmask register 0x01D0 0068 RFMT Receivebitstreamformatregister 0x01D0 006C AFSRCTL Receiveframesynccontrolregister 0x01D0 0070 ACLKRCTL Receiveclockcontrolregister 0x01D0 0074 AHCLKRCTL Receivehigh-frequencyclockcontrolregister 0x01D0 0078 RTDM ReceiveTDM timeslot0-31register 0x01D0 007C RINTCTL Receiverinterruptcontrolregister 0x01D0 0080 RSTAT Receiverstatusregister 0x01D0 0084 RSLOT CurrentreceiveTDM timeslotregister 0x01D0 0088 RCLKCHK Receiveclockcheckcontrolregister 0x01D0 008C REVTCTL ReceiverDMA eventcontrolregister 0x01D0 00A0 Transmitterglobalcontrolregister.AliasofGBLCTL, onlytransmitbitsareaffected-allowsXGBLCTL transmittertobe resetindependentlyfromreceiver 0x01D0 00A4 XMASK Transmitformatunitbitmask register 0x01D0 00A8 XFMT Transmitbitstreamformatregister 0x01D0 00AC AFSXCTL Transmitframesynccontrolregister 0x01D0 00B0 ACLKXCTL Transmitclockcontrolregister 0x01D0 00B4 AHCLKXCTL Transmithigh-frequencyclockcontrolregister 0x01D0 00B8 XTDM TransmitTDM timeslot0-31register 0x01D0 00BC XINTCTL Transmitterinterruptcontrolregister 0x01D0 00C0 XSTAT Transmitterstatusregister 0x01D0 00C4 XSLOT CurrenttransmitTDM timeslotregister 0x01D0 00C8 XCLKCHK Transmitclockcheckcontrolregister 0x01D0 00CC XEVTCTL TransmitterDMA eventcontrolregister 0x01D0 0100 DITCSRA0 Left(evenTDM timeslot)channelstatusregister(DITmode) 0 0x01D0 0104 DITCSRA1 Left(evenTDM timeslot)channelstatusregister(DITmode) 1 0x01D0 0108 DITCSRA2 Left(evenTDM timeslot)channelstatusregister(DITmode) 2

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-51.McASP RegistersAccessed Through PeripheralConfigurationPort(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01D0 010C DITCSRA3 Left(evenTDM timeslot)channelstatusregister(DITmode) 3 0x01D0 0110 DITCSRA4 Left(evenTDM timeslot)channelstatusregister(DITmode) 4 0x01D0 0114 DITCSRA5 Left(evenTDM timeslot)channelstatusregister(DITmode) 5 0x01D0 0118 DITCSRB0 Right(oddTDM timeslot)channelstatusregister(DITmode) 0 0x01D0 011C DITCSRB1 Right(oddTDM timeslot)channelstatusregister(DITmode) 1 0x01D0 0120 DITCSRB2 Right(oddTDM timeslot)channelstatusregister(DITmode) 2 0x01D0 0124 DITCSRB3 Right(oddTDM timeslot)channelstatusregister(DITmode) 3 0x01D0 0128 DITCSRB4 Right(oddTDM timeslot)channelstatusregister(DITmode) 4 0x01D0 012C DITCSRB5 Right(oddTDM timeslot)channelstatusregister(DITmode) 5 0x01D0 0130 DITUDRA0 Left(evenTDM timeslot)channeluserdataregister(DITmode) 0 0x01D0 0134 DITUDRA1 Left(evenTDM timeslot)channeluserdataregister(DITmode) 1 0x01D0 0138 DITUDRA2 Left(evenTDM timeslot)channeluserdataregister(DITmode) 2 0x01D0 013C DITUDRA3 Left(evenTDM timeslot)channeluserdataregister(DITmode) 3 0x01D0 0140 DITUDRA4 Left(evenTDM timeslot)channeluserdataregister(DITmode) 4 0x01D0 0144 DITUDRA5 Left(evenTDM timeslot)channeluserdataregister(DITmode) 5 0x01D0 0148 DITUDRB0 Right(oddTDM timeslot)channeluserdataregister(DITmode) 0 0x01D0 014C DITUDRB1 Right(oddTDM timeslot)channeluserdataregister(DITmode) 1 0x01D0 0150 DITUDRB2 Right(oddTDM timeslot)channeluserdataregister(DITmode) 2 0x01D0 0154 DITUDRB3 Right(oddTDM timeslot)channeluserdataregister(DITmode) 3 0x01D0 0158 DITUDRB4 Right(oddTDM timeslot)channeluserdataregister(DITmode) 4 0x01D0 015C DITUDRB5 Right(oddTDM timeslot)channeluserdataregister(DITmode) 5 0x01D0 0180 SRCTL0 Serializercontrolregister0 0x01D0 0184 SRCTL1 Serializercontrolregister1 0x01D0 0188 SRCTL2 Serializercontrolregister2 0x01D0 018C SRCTL3 Serializercontrolregister3 0x01D0 0190 SRCTL4 Serializercontrolregister4 0x01D0 0194 SRCTL5 Serializercontrolregister5 0x01D0 0198 SRCTL6 Serializercontrolregister6 0x01D0 019C SRCTL7 Serializercontrolregister7 0x01D0 01A0 SRCTL8 Serializercontrolregister8 0x01D0 01A4 SRCTL9 Serializercontrolregister9 0x01D0 01A8 SRCTL10 Serializercontrolregister10 0x01D0 01AC SRCTL11 Serializercontrolregister11 0x01D0 01B0 SRCTL12 Serializercontrolregister12 0x01D0 01B4 SRCTL13 Serializercontrolregister13 0x01D0 01B8 SRCTL14 Serializercontrolregister14 0x01D0 01BC SRCTL15 Serializercontrolregister15 Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 153 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-51.McASP RegistersAccessed Through PeripheralConfigurationPort(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01D0 0200 XBUF0 (1) Transmitbufferregisterforserializer0 0x01D0 0204 XBUF1 (1) Transmitbufferregisterforserializer1 0x01D0 0208 XBUF2 (1) Transmitbufferregisterforserializer2 0x01D0 020C XBUF3 (1) Transmitbufferregisterforserializer3 0x01D0 0210 XBUF4 (1) Transmitbufferregisterforserializer4 0x01D0 0214 XBUF5 (1) Transmitbufferregisterforserializer5 0x01D0 0218 XBUF6 (1) Transmitbufferregisterforserializer6 0x01D0 021C XBUF7 (1) Transmitbufferregisterforserializer7 0x01D0 0220 XBUF8 (1) Transmitbufferregisterforserializer8 0x01D0 0224 XBUF9 (1) Transmitbufferregisterforserializer9 0x01D0 0228 XBUF10 (1) Transmitbufferregisterforserializer10 0x01D0 022C XBUF11 (1) Transmitbufferregisterforserializer11 0x01D0 0230 XBUF12 (1) Transmitbufferregisterforserializer12 0x01D0 0234 XBUF13 (1) Transmitbufferregisterforserializer13 0x01D0 0238 XBUF14 (1) Transmitbufferregisterforserializer14 0x01D0 023C XBUF15 (1) Transmitbufferregisterforserializer15 0x01D0 0280 RBUF0 (2) Receivebufferregisterforserializer0 0x01D0 0284 RBUF1 (2) Receivebufferregisterforserializer1 0x01D0 0288 RBUF2 (2) Receivebufferregisterforserializer2 0x01D0 028C RBUF3 (2) Receivebufferregisterforserializer3 0x01D0 0290 RBUF4 (2) Receivebufferregisterforserializer4 0x01D0 0294 RBUF5 (2) Receivebufferregisterforserializer5 0x01D0 0298 RBUF6 (2) Receivebufferregisterforserializer6 0x01D0 029C RBUF7 (2) Receivebufferregisterforserializer7 0x01D0 02A0 RBUF8 (2) Receivebufferregisterforserializer8 0x01D0 02A4 RBUF9 (2) Receivebufferregisterforserializer9 0x01D0 02A8 RBUF10 (2) Receivebufferregisterforserializer10 0x01D0 02AC RBUF11 (2) Receivebufferregisterforserializer11 0x01D0 02B0 RBUF12 (2) Receivebufferregisterforserializer12 0x01D0 02B4 RBUF13 (2) Receivebufferregisterforserializer13 0x01D0 02B8 RBUF14 (2) Receivebufferregisterforserializer14 0x01D0 02BC RBUF15 (2) Receivebufferregisterforserializer15 (1) WritestoXRBUF originatefromperipheralconfigurationportonlywhen XBUSEL = 1 inXFMT. (2) Reads fromXRBUF originateon peripheralconfigurationportonlywhen RBUSEL = 1 inRFMT. Table5-52.McASP RegistersAccessed Through DMA Port ACCESS BYTE ACRONYM REGISTER DESCRIPTION TYPE ADDRESS Read 0x01D0 2000 RBUF ReceivebufferDMA portaddress.Cyclesthroughreceiveserializers,skippingovertransmit Accesses serializersand inactiveserializers.Startsatthelowestserializeratthebeginningofeach timeslot.Reads fromDMA portonlyifXBUSEL = 0 inXFMT. Write 0x01D0 2000 XBUF TransmitbufferDMA portaddress.Cyclesthroughtransmitserializers,skippingoverreceive Accesses and inactiveserializers.Startsatthelowestserializeratthebeginningofeach timeslot. WritestoDMA portonlyifRBUSEL = 0 inRFMT.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-53.McASP AFIFO RegistersAccessed Through PeripheralConfigurationPort BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01D0 1000 AFIFOREV AFIFO revisionidentificationregister 0x01D0 1010 WFIFOCTL WriteFIFO controlregister 0x01D0 1014 WFIFOSTS WriteFIFO statusregister 0x01D0 1018 RFIFOCTL Read FIFO controlregister 0x01D0 101C RFIFOSTS Read FIFO statusregister

5.15.2 McASP ElectricalData/Timing

5.15.2.1MultichannelAudio SerialPort0 (McASP0) Timing Table5-54and Table5-56assume testingoverrecommended operatingconditions(seeFigure5-33and Figure5-34). Table5-54.Timing Requirements forMcASP0 (1.3V,1.2V,1.1V)(1)(2) 1.3V,1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX 1 tc(AHCLKRX) (3) Cycletime,AHCLKR/X 25 28 ns 2 tw(AHCLKRX) (3) Pulseduration,AHCLKR/X highorlow 12.5 14 ns 3 tc(ACLKRX) (3) Cycletime,ACLKR/X AHCLKR/X ext 25(4) 28(4) ns Pulseduration,ACLKR/W highor AHCLKR/X ext4 tw(ACLKRX) (3) 12.5 14 nslow AHCLKR/X int 11.5 12 ns Setuptime,5 tsu(AFSRX-ACLKRX) (3) AHCLKR/X extinput 4 5 nsAFSR/X inputtoACLKR/X (5) AHCLKR/X extoutput 4 5 ns AHCLKR/X int -1 -2 ns Holdtime,6 th(ACLKRX-AFSRX) AHCLKR/X extinput 1 1 nsAFSR/X inputafterACLKR/X (5) AHCLKR/X extoutput 1 1 ns AHCLKR/X int 11.5 12 nsSetuptime,7 tsu(AXR-ACLKRX) (3) AXR0[n]inputtoACLKR/X (5)(6) AHCLKR/X ext 4 5 ns AHCLKR/X int -1 -2 nsHoldtime, 8 th(ACLKRX-AXR) AXR0[n]inputafter AHCLKR/X extinput 3 4 ns ACLKR/X (5)(6) AHCLKR/X extoutput 3 4 ns (1) ACLKX0 internal– McASP0 ACLKXCTL.CLKXM = 1,PDIR.ACLKX = 1 ACLKX0 externalinput– McASP0 ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 0 ACLKX0 externaloutput– McASP0 ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 1 ACLKR0 internal– McASP0 ACLKRCTL.CLKRM = 1,PDIR.ACLKR =1 ACLKR0 externalinput– McASP0 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 0 ACLKR0 externaloutput– McASP0 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 1 (2) P = SYSCLK2 period (3) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (4) Thistimingislimitedby thetimingshown or2P,whicheverisgreater. (5) McASP0 ACLKXCTL.ASYNC=1: Receiverisclockedby itsown ACLKR0 (6) McASP0 ACLKXCTL.ASYNC=0: Receiverisclockedby transmitter's ACLKX0 Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 155 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-55.Timing Requirements forMcASP0 (1.0V)(1)(2) 1.0V NO. PARAMETER UNIT MIN MAX 1 tc(AHCLKRX) (3) Cycletime,AHCLKR/X 35 ns 2 tw(AHCLKRX) (3) Pulseduration,AHCLKR/X highorlow 17.5 ns 3 tc(ACLKRX) (3) Cycletime,ACLKR/X AHCLKR/X ext 35(4) ns 4 tw(ACLKRX) (3) Pulseduration,ACLKR/W highorlow AHCLKR/X ext 17.5 ns AHCLKR/X int 16 ns Setuptime,5 tsu(AFSRX-ACLKRX) (3) AHCLKR/X extinput 5.5 nsAFSR/X inputtoACLKR/X (5) AHCLKR/X extoutput 5.5 ns AHCLKR/X int -2 ns Holdtime,6 th(ACLKRX-AFSRX) AHCLKR/X extinput 1 nsAFSR/X inputafterACLKR/X (5) AHCLKR/X extoutput 1 ns AHCLKR/X int 16 nsSetuptime,7 tsu(AXR-ACLKRX) (3) AXR0[n]inputtoACLKR/X (5)(6) AHCLKR/X ext 5.5 ns AHCLKR/X int -2 ns Holdtime,8 th(ACLKRX-AXR) AHCLKR/X extinput 5 nsAXR0[n]inputafterACLKR/X (5)(6) AHCLKR/X extoutput 5 ns (1) ACLKX0 internal– McASP0 ACLKXCTL.CLKXM = 1,PDIR.ACLKX = 1 ACLKX0 externalinput– McASP0 ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 0 ACLKX0 externaloutput– McASP0 ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 1 ACLKR0 internal– McASP0 ACLKRCTL.CLKRM = 1,PDIR.ACLKR =1 ACLKR0 externalinput– McASP0 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 0 ACLKR0 externaloutput– McASP0 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 1 (2) P = SYSCLK2 period (3) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (4) Thistimingislimitedby thetimingshown or2P,whicheverisgreater. (5) McASP0 ACLKXCTL.ASYNC=1: Receiverisclockedby itsown ACLKR0 (6) McASP0 ACLKXCTL.ASYNC=0: Receiverisclockedby transmitter's ACLKX0

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-56.SwitchingCharacteristicsforMcASP0 (1.3V,1.2V,1.1V)(1) 1.3V,1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX 9 tc(AHCLKRX) (2) Cycletime,AHCLKR/X 25 28 ns 10 tw(AHCLKRX) (2) Pulseduration,AHCLKR/X highorlow AH – 2.5(3) AH – 2.5(3) ns 11 tc(ACLKRX) (2) Cycletime,ACLKR/X ACLKR/X int 25(4)(5) 28(4)(5) ns Pulseduration,ACLKR/X highor12 tw(ACLKRX) (2) ACLKR/X int A – 2.5(6) A – 2.5(6) nslow ACLKR/X int -1 6 -1 8 ns Delaytime,ACLKR/X transmit13 td(ACLKRX-AFSRX) ACLKR/X extinput 2 13.5 2 14.5 nsedge toAFSX/R outputvalid(7) ACLKR/X extoutput 2 13.5 2 14.5 ns ACLKR/X int -1 6 -1 8 ns Delaytime,ACLKX transmitedge14 td(ACLKX-AXRV) ACLKR/X extinput 2 13.5 2 15 nstoAXR outputvalid ACLKR/X extoutput 2 13.5 2 15 ns Disabletime,ACLKR/X transmit ACLKR/X int 0 6 0 8 ns 15 tdis(ACLKX-AXRHZ) (2) edge toAXR highimpedance ACLKR/X ext 2 13.5 2 15 nsfollowinglastdatabit (1) McASP0 ACLKX0 internal– ACLKXCTL.CLKXM = 1,PDIR.ACLKX = 1 ACLKX0 externalinput– McASP0 ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 0 ACLKX0 externaloutput– McASP0ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 1 ACLKR0 internal– McASP0 ACLKR0CTL.CLKRM = 1,PDIR.ACLKR =1 ACLKR0 externalinput– McASP0 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 0 ACLKR0 externaloutput– McASP0 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 1 (2) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (3) AH = (AHCLKR/X period)/2inns.Forexample,when AHCLKR/X periodis25 ns,use AH = 12.5ns. (4) P = SYSCLK2 period (5) Thistimingislimitedby thetimingshown or2P,whicheverisgreater. (6) A = (ACLKR/X period)/2inns.Forexample,when AHCLKR/X periodis25 ns,use AH = 12.5ns. (7) McASP0 ACLKXCTL.ASYNC=1: Receiverisclockedby itsown ACLKR0 Table5-57.SwitchingCharacteristicsforMcASP0 (1.0V)(1) 1.0V NO. PARAMETER UNIT MIN MAX 9 tc(AHCLKRX) (2) Cycletime,AHCLKR/X 35 ns 10 tw(AHCLKRX) (2) Pulseduration,AHCLKR/X highorlow AH – 2.5(3) ns 11 tc(ACLKRX) (2) Cycletime,ACLKR/X ACLKR/X int 35(4)(5) ns 12 tw(ACLKRX) (2) Pulseduration,ACLKR/X highorlow ACLKR/X int A – 2.5(6) ns ACLKR/X int -0.5 10 ns Delaytime,ACLKR/X transmitedge toAFSX/R output13 td(ACLKRX-AFSRX) ACLKR/X extinput 2 19 nsvalid(7) ACLKR/X extoutput 2 19 ns ACLKR/X int -0.5 10 ns 14 td(ACLKX-AXRV) Delaytime,ACLKX transmitedge toAXR outputvalid ACLKR/X extinput 2 19 ns ACLKR/X extoutput 2 19 ns ACLKR/X int 0 10 nsDisabletime,ACLKR/X transmitedge toAXR high15 tdis(ACLKX-AXRHZ) (2) impedance followinglastdatabit ACLKR/X ext 2 19 ns (1) McASP0 ACLKX0 internal– ACLKXCTL.CLKXM = 1,PDIR.ACLKX = 1 ACLKX0 externalinput– McASP0 ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 0 ACLKX0 externaloutput– McASP0ACLKXCTL.CLKXM = 0,PDIR.ACLKX = 1 ACLKR0 internal– McASP0 ACLKR0CTL.CLKRM = 1,PDIR.ACLKR =1 ACLKR0 externalinput– McASP0 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 0 ACLKR0 externaloutput– McASP0 ACLKRCTL.CLKRM = 0,PDIR.ACLKR = 1 (2) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (3) AH = (AHCLKR/X period)/2inns.Forexample,when AHCLKR/X periodis25 ns,use AH = 12.5ns. (4) P = SYSCLK2 period (5) Thistimingislimitedby thetimingshown or2P,whicheverisgreater. (6) A = (ACLKR/X period)/2inns.Forexample,when AHCLKR/X periodis25 ns,use AH = 12.5ns. (7) McASP0 ACLKXCTL.ASYNC=1: Receiverisclockedby itsown ACLKR0 Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 157 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) AXR[n] (Data In/Receive) ACLKR/X (CLKRP = CLKXP = 0)(A) ACLKR/X (CLKRP = CLKXP = 1)(B) OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com A. For CLKRP = CLKXP = 0, the McASP transmitterisconfiguredforrisingedge (toshiftdata out)and the McASP receiverisconfiguredforfallingedge (toshiftdatain). B. For CLKRP = CLKXP = 1,theMcASP transmitterisconfiguredforfallingedge (toshiftdataout)and theMcASP receiverisconfiguredforrisingedge (toshiftdatain). Figure5-33.McASP InputTimings

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A0 A1 B0 B1 A30 A31 B30 B31 C0 C1 C2 C3 C31 AHCLKR/X (Falling Edge Polarity) AHCLKR/X (Rising Edge Polarity) AFSR/X (Bit Width, 0 Bit Delay) AFSR/X (Bit Width, 1 Bit Delay) AFSR/X (Bit Width, 2 Bit Delay) AFSR/X (Slot Width, 0 Bit Delay) AFSR/X (Slot Width, 1 Bit Delay) AFSR/X (Slot Width, 2 Bit Delay) AXR[n] (Data Out/Transmit) ACLKR/X (CLKRP = CLKXP = 0)(B) ACLKR/X (CLKRP = CLKXP = 1)(A) OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 A. For CLKRP = CLKXP = 1,theMcASP transmitterisconfiguredforfallingedge (toshiftdataout)and theMcASP receiverisconfiguredforrisingedge (toshiftdatain). B. For CLKRP = CLKXP = 0, the McASP transmitterisconfiguredforrisingedge (toshiftdata out)and the McASP receiverisconfiguredforfallingedge (toshiftdatain). Figure5-34.McASP Output Timings Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 159 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.16 MultichannelBufferedSerialPort(McBSP)

The McBSP providesthesefunctions:

Full-duplexcommunication
Double-buffereddataregisters,whichallowa continuousdatastream
Independentframingand clockingforreceiveand transmit
Directinterfaceto industry-standardcodecs, analog interfacechips (AICs),and other serially connectedanalog-to-digital(A/D)and digital-to-analog(D/A)devices
Externalshiftclockoran internal,programmablefrequencyshiftclockfordatatransfer
Transmit& Receive FIFO Buffersallowthe McBSP to operateat a highersample rateby making it more toleranttoDMA latency Ifinternalclocksourceisused,theCLKGDV fieldoftheSample Rate GeneratorRegister(SRGR) must alwaysbe settoa valueof1 orgreater.

5.16.1 McBSP PeripheralRegisterDescription(s)

Table5-58.McBSP/FIFO Registers McBSP0 McBSP1 ACRONYM REGISTER DESCRIPTIONBYTE ADDRESS BYTE ADDRESS McBSP Registers 0x01D1 0000 0x01D1 1000 DRR McBSP Data ReceiveRegister(read-only) 0x01D1 0004 0x01D1 1004 DXR McBSP Data TransmitRegister 0x01D1 0008 0x01D1 1008 SPCR McBSP SerialPortControlRegister 0x01D1 000C 0x01D1 100C RCR McBSP ReceiveControlRegister 0x01D1 0010 0x01D1 1010 XCR McBSP TransmitControlRegister 0x01D1 0014 0x01D1 1014 SRGR McBSP Sample Rate Generatorregister 0x01D1 0018 0x01D1 1018 MCR McBSP MultichannelControlRegister 0x01D1 001C 0x01D1 101C RCERE0 McBSP Enhanced ReceiveChannelEnableRegister0 PartitionA/B 0x01D1 0020 0x01D1 1020 XCERE0 McBSP Enhanced TransmitChannelEnableRegister0 PartitionA/B 0x01D1 0024 0x01D1 1024 PCR McBSP PinControlRegister 0x01D1 0028 0x01D1 1028 RCERE1 McBSP Enhanced ReceiveChannelEnableRegister1 PartitionC/D 0x01D1 002C 0x01D1 102C XCERE1 McBSP Enhanced TransmitChannelEnableRegister1 PartitionC/D 0x01D1 0030 0x01D1 1030 RCERE2 McBSP Enhanced ReceiveChannelEnableRegister2 PartitionE/F 0x01D1 0034 0x01D1 1034 XCERE2 McBSP Enhanced TransmitChannelEnableRegister2 PartitionE/F 0x01D1 0038 0x01D1 1038 RCERE3 McBSP Enhanced ReceiveChannelEnableRegister3 PartitionG/H 0x01D1 003C 0x01D1 103C XCERE3 McBSP Enhanced TransmitChannelEnableRegister3 PartitionG/H McBSP FIFO Controland StatusRegisters 0x01D1 0800 0x01D1 1800 BFIFOREV BFIFO RevisionIdentificationRegister 0x01D1 0810 0x01D1 1810 WFIFOCTL WriteFIFO ControlRegister 0x01D1 0814 0x01D1 1814 WFIFOSTS WriteFIFO StatusRegister 0x01D1 0818 0x01D1 1818 RFIFOCTL Read FIFO ControlRegister 0x01D1 081C 0x01D1 181C RFIFOSTS Read FIFO StatusRegister McBSP FIFO Data Registers 0x01F1 0000 0x01F1 1000 RBUF McBSP FIFO ReceiveBuffer 0x01F1 0000 0x01F1 1000 XBUF McBSP FIFO TransmitBuffer

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5.16.2 McBSP ElectricalData/Timing

The followingassume testingoverrecommended operatingconditions.

5.16.2.1 MultichannelBufferedSerialPort(McBSP) Timing

Table5-59.Timing Requirements forMcBSP0 1.3V,1.2V,1.1V(seeFigure5-35) 1.3V,1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX 2 tc(CKRX) (2) Cycletime,CLKR/X CLKR/X ext 2P or20(3)(4) 2P or25(3)(4) ns Pulseduration,CLKR/X highorCLKR/X3 tw(CKRX) (2) CLKR/X ext P -1(5) P -1(5) nslow CLKR int 14 15.5Setuptime,externalFSR highbefore5 tsu(FRH-CKRL) nsCLKR low CLKR ext 4 5 CLKR int 6 6Holdtime,externalFSR highafter6 th(CKRL-FRH) (2) nsCLKR low CLKR ext 3 3 CLKR int 14 15.5 7 tsu(DRV-CKRL) Setuptime,DR validbeforeCLKR low ns CLKR ext 4 5 CLKR int 3 3 8 th(CKRL-DRV) (2) Holdtime,DR validafterCLKR low ns CLKR ext 3 3 CLKX int 14 15.5Setuptime,externalFSX highbefore10 tsu(FXH-CKXL) nsCLKX low CLKX ext 4 5 CLKX int 6 6Holdtime,externalFSX highafter11 th(CKXL-FXH) nsCLKX low CLKX ext 3 3 (1) CLKRP = CLKXP = FSRP = FSXP = 0.Ifpolarityofany ofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (3) P = ASYNC3 periodinns.Forexample,when theASYNC clockdomain isrunningat100 MHz, use 10 ns. (4) Use whichevervalueisgreater.Minimum CLKR/X cycletimesmust be met,even when CLKR/X isgeneratedby an internalclock source.The minimum CLKR/X cycletimesarebased on internallogicspeed;themaximum usablespeed may be lowerdue toEDMA limitationsand AC timingrequirements. (5) Thisparameterappliestothemaximum McBSP frequency.Operateserialclocks(CLKR/X)inthereasonablerangeof40/60dutycycle. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 161 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-60.Timing Requirements forMcBSP0 1.0V(seeFigure5-35) 1.0V NO. PARAMETER UNIT MIN MAX 2 tc(CKRX) (2) Cycletime,CLKR/X CLKR/X ext 2P or26.6(3)(4) ns 3 tw(CKRX) (2) Pulseduration,CLKR/X highorCLKR/X low CLKR/X ext P -1(5) ns CLKR int 20 5 tsu(FRH-CKRL) Setuptime,externalFSR highbeforeCLKR low ns CLKR ext 5 CLKR int 6 6 th(CKRL-FRH) (2) Holdtime,externalFSR highafterCLKR low ns CLKR ext 3 CLKR int 20 7 tsu(DRV-CKRL) (2) Setuptime,DR validbeforeCLKR low ns CLKR ext 5 CLKR int 3 8 th(CKRL-DRV) Holdtime,DR validafterCLKR low ns CLKR ext 3 CLKX int 20 10 tsu(FXH-CKXL) Setuptime,externalFSX highbeforeCLKX low ns CLKX ext 5 CLKX int 6 11 th(CKXL-FXH) (2) Holdtime,externalFSX highafterCLKX low ns CLKX ext 3 (1) CLKRP = CLKXP = FSRP = FSXP = 0.Ifpolarityofany ofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (3) P = ASYNC3 periodinns.Forexample,when theASYNC clockdomain isrunningat100 MHz, use 10 ns. (4) Use whichevervalueisgreater.Minimum CLKR/X cycletimesmust be met,even when CLKR/X isgeneratedby an internalclock source.The minimum CLKR/X cycletimesarebased on internallogicspeed;themaximum usablespeed may be lowerdue toEDMA limitationsand AC timingrequirements. (5) Thisparameterappliestothemaximum McBSP frequency.Operateserialclocks(CLKR/X)inthereasonablerangeof40/60dutycycle.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-61.SwitchingCharacteristicsforMcBSP0 1.3V,1.2V,1.1V(2) (seeFigure5-35) 1.3V,1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX Delaytime,CLKS hightoCLKR/X highfor1 td(CKSH-CKRXH) 2 14.5 2 16 nsinternalCLKR/X generatedfromCLKS input 2 tc(CKRX) (3) Cycletime,CLKR/X CLKR/X int 2P or20(4)(5)(6) 2P or25(4)(5)(6) ns Pulseduration,CLKR/X highor3 tw(CKRX) (3) CLKR/X int C -2(7) C + 2(7) C -2(7) C + 2(7) nsCLKR/X low CLKR int -4 5.5 -4 5.5Delaytime,CLKR hightointernal4 td(CKRH-FRV) nsFSR valid CLKR ext 2 14.5 2 16 CLKX int -4 5.5 -4 5.5Delaytime,CLKX hightointernal9 td(CKXH-FXV) (3) nsFSX valid CLKX ext 2 14.5 2 16 Disabletime,DX highimpedance CLKX int -4 7.5 -5.5 7.5 12 tdis(CKXH-DXHZ) (3) followinglastdatabitfromCLKX ns CLKX ext -2 16 -22 16high Delaytime,CLKX hightoDX13 td(CKXH-DXV) (3) nsvalid CLKX ext 2 + D1 (8) 14.5+ D2 (8) 2 + D1 (8) 16 + D2 (8) Delaytime,FSX hightoDX valid FSX int -4(9) 5(9) -4(9) 5(9) 14 td(FXH-DXV) (3) nsONLY applieswhen indata FSX ext -2(9) 14.5(9) -2(9) 16(9) delay0 (XDATDLY = 00b)mode (1) CLKRP = CLKXP = FSRP = FSXP = 0.Ifpolarityofany ofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) Minimum delaytimesalsorepresentminimum outputholdtimes. (3) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (4) Minimum CLKR/X cycletimesmust be met,even when CLKR/X isgeneratedby an internalclocksource.Minimum CLKR/X cycletimes arebased on internallogicspeed;themaximum usablespeed may be lowerdue toEDMA limitationsand AC timingrequirements. (5) P = ASYNC3 periodinns.Forexample,when theASYNC clockdomain isrunningat100 MHz, use 10 ns. (6) Use whichevervalueisgreater. (7) C = H orL S = sample rategeneratorinputclock= P ifCLKSM = 1 (P = ASYNC period) S = sample rategeneratorinputclock= P_clksifCLKSM = 0 (P_clks= CLKS period) H = CLKX highpulsewidth= (CLKGDV/2 + 1)*S ifCLKGDV iseven H = (CLKGDV + 1)/2*S ifCLKGDV isodd L = CLKX lowpulsewidth= (CLKGDV/2) *S ifCLKGDV iseven L = (CLKGDV + 1)/2*S ifCLKGDV isodd CLKGDV shouldbe setappropriatelytoensuretheMcBSP bitratedoes notexceed themaximum limit(see(4)above). (8) ExtradelayfromCLKX hightoDX validappliesonlytothefirstdatabitofa device,ifand onlyifDXENA = 1 inSPCR. ifDXENA = 0,thenD1 = D2 = 0 ifDXENA = 1,thenD1 = 6P,D2 = 12P (9) ExtradelayfromFSX hightoDX validappliesonlytothefirstdatabitofa device,ifand onlyifDXENA = 1 inSPCR. ifDXENA = 0,thenD1 = D2 = 0 ifDXENA = 1,thenD1 = 6P,D2 = 12P Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 163 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-62.SwitchingCharacteristicsforMcBSP0 1.0V(2) (seeFigure5-35) 1.0V NO. PARAMETER UNIT MIN MAX Delaytime,CLKS hightoCLKR/X highforinternalCLKR/X1 td(CKSH-CKRXH) 3 21.5 nsgeneratedfromCLKS input 2 tc(CKRX) (3) Cycletime,CLKR/X CLKR/X int 2P or26.6(4)(5)(6) ns 3 tw(CKRX) (3) Pulseduration,CLKR/X highorCLKR/X low CLKR/X int C -2(7) C + 2(7) ns CLKR int -4 10 4 td(CKRH-FRV) Delaytime,CLKR hightointernalFSR valid ns CLKR ext 2.5 21.5 CLKX int -4 10 9 td(CKXH-FXV) Delaytime,CLKX hightointernalFSX valid ns CLKX ext 2.5 21.5 CLKX int -4 10tdis(CKXH- Disabletime,DX highimpedance followinglastdata12 ns DXHZ) (3) bitfromCLKX high CLKX ext -2 21.5 CLKX int -4+ D1 (8) 10 + D2 (8) 13 td(CKXH-DXV) (3) Delaytime,CLKX hightoDX valid ns CLKX ext 2.5+ D1 (8) 21.5+ D2 (8) Delaytime,FSX hightoDX valid FSX int -4(9) 5(9) 14 td(FXH-DXV) nsONLY applieswhen indata FSX ext -2(9) 21.5(9) delay0 (XDATDLY = 00b)mode (1) CLKRP = CLKXP = FSRP = FSXP = 0.Ifpolarityofany ofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) Minimum delaytimesalsorepresentminimum outputholdtimes. (3) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (4) Minimum CLKR/X cycletimesmust be met,even when CLKR/X isgeneratedby an internalclocksource.Minimum CLKR/X cycletimes arebased on internallogicspeed;themaximum usablespeed may be lowerdue toEDMA limitationsand AC timingrequirements. (5) P = ASYNC3 periodinns.Forexample,when theASYNC clockdomain isrunningat100 MHz, use 10 ns. (6) Use whichevervalueisgreater. (7) C = H orL S = sample rategeneratorinputclock= P ifCLKSM = 1 (P = ASYNC period) S = sample rategeneratorinputclock= P_clksifCLKSM = 0 (P_clks= CLKS period) H = CLKX highpulsewidth= (CLKGDV/2 + 1)*S ifCLKGDV iseven H = (CLKGDV + 1)/2*S ifCLKGDV isodd L = CLKX lowpulsewidth= (CLKGDV/2) *S ifCLKGDV iseven L = (CLKGDV + 1)/2*S ifCLKGDV isodd CLKGDV shouldbe setappropriatelytoensuretheMcBSP bitratedoes notexceed themaximum limit(see(4)above). (8) ExtradelayfromCLKX hightoDX validappliesonlytothefirstdatabitofa device,ifand onlyifDXENA = 1 inSPCR. ifDXENA = 0,thenD1 = D2 = 0 ifDXENA = 1,thenD1 = 6P,D2 = 12P (9) ExtradelayfromFSX hightoDX validappliesonlytothefirstdatabitofa device,ifand onlyifDXENA = 1 inSPCR. ifDXENA = 0,thenD1 = D2 = 0 ifDXENA = 1,thenD1 = 6P,D2 = 12P

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-63.Timing Requirements forMcBSP1 1.3V,1.2V,1.1V(seeFigure5-35) 1.3V,1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX 2 tc(CKRX) (2) Cycletime,CLKR/X CLKR/X ext 2P or20(3)(4) 2P or25(3)(5) ns Pulseduration,CLKR/X highor3 tw(CKRX) (2) CLKR/X ext P -1(6) P -1(7) nsCLKR/X low CLKR int 15 18Setuptime,externalFSR highbefore5 tsu(FRH-CKRL) nsCLKR low CLKR ext 5 5 CLKR int 6 6Holdtime,externalFSR highafter6 th(CKRL-FRH) (2) nsCLKR low CLKR ext 3 3 CLKR int 15 18 7 tsu(DRV-CKRL) Setuptime,DR validbeforeCLKR low ns CLKR ext 5 5 CLKR int 3 3 8 th(CKRL-DRV) Holdtime,DR validafterCLKR low ns CLKR ext 3 3 CLKX int 15 18Setuptime,externalFSX highbefore10 tsu(FXH-CKXL) nsCLKX low CLKX ext 5 5 CLKX int 6 6Holdtime,externalFSX highafter11 th(CKXL-FXH) (2) nsCLKX low CLKX ext 3 3 (1) CLKRP = CLKXP = FSRP = FSXP = 0.Ifpolarityofany ofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (3) P = ASYNC3 periodinns.Forexample,when theASYNC clockdomain isrunningat100 MHz, use 10 ns. (4) Use whichevervalueisgreater.Minimum CLKR/X cycletimesmust be met,even when CLKR/X isgeneratedby an internalclock source.The minimum CLKR/X cycletimesarebased on internallogicspeed;themaximum usablespeed may be lowerdue toEDMA limitationsand AC timingrequirements. (5) Use whichevervalueisgreater.Minimum CLKR/X cycletimesmust be met,even when CLKR/X isgeneratedby an internalclock source.The minimum CLKR/X cycletimesarebased on internallogicspeed;themaximum usablespeed may be lowerdue toEDMA limitationsand AC timingrequirements. (6) Thisparameterappliestothemaximum McBSP frequency.Operateserialclocks(CLKR/X)inthereasonablerangeof40/60dutycycle. (7) Thisparameterappliestothemaximum McBSP frequency.Operateserialclocks(CLKR/X)inthereasonablerangeof40/60dutycycle. Table5-64.Timing Requirements forMcBSP1 1.0V(seeFigure5-35) 1.0V NO. PARAMETER UNIT MIN MAX 2 tc(CKRX) (2) Cycletime,CLKR/X CLKR/X ext 2P or26.6(3)(4) ns 3 tw(CKRX) (2) Pulseduration,CLKR/X highorCLKR/X low CLKR/X ext P -1(5) ns CLKR int 21 5 tsu(FRH-CKRL) Setuptime,externalFSR highbeforeCLKR low ns CLKR ext 10 CLKR int 6 6 th(CKRL-FRH) (2) Holdtime,externalFSR highafterCLKR low ns CLKR ext 3 CLKR int 21 7 tsu(DRV-CKRL) Setuptime,DR validbeforeCLKR low ns CLKR ext 10 CLKR int 3 8 th(CKRL-DRV) Holdtime,DR validafterCLKR low ns CLKR ext 3 CLKX int 21 10 tsu(FXH-CKXL) Setuptime,externalFSX highbeforeCLKX low ns CLKX ext 10 CLKX int 6 11 th(CKXL-FXH) (2) Holdtime,externalFSX highafterCLKX low ns CLKX ext 3 (1) CLKRP = CLKXP = FSRP = FSXP = 0.Ifpolarityofany ofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (3) P = ASYNC3 periodinns.Forexample,when theASYNC clockdomain isrunningat100 MHz, use 10 ns. (4) Use whichevervalueisgreater.Minimum CLKR/X cycletimesmust be met,even when CLKR/X isgeneratedby an internalclock source.The minimum CLKR/X cycletimesarebased on internallogicspeed;themaximum usablespeed may be lowerdue toEDMA limitationsand AC timingrequirements. (5) Thisparameterappliestothemaximum McBSP frequency.Operateserialclocks(CLKR/X)inthereasonablerangeof40/60dutycycle. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 165 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-65.SwitchingCharacteristicsforMcBSP1 1.3V,1.2V,1.1V(2) (seeFigure5-35) 1.3V,1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX Delaytime,CLKS hightoCLKR/X highforinternal1 td(CKSH-CKRXH) 0.5 16.5 1.5 18 nsCLKR/X generatedfromCLKS input 2 tc(CKRX) (3) Cycletime,CLKR/X CLKR/X int 2P or20(4)(5)(6) 2P or25(4)(5)(6) ns Pulseduration,CLKR/X highor3 tw(CKRX) (3) CLKR/X int C -2(7) C + 2(7) C -2(7) C + 2(7) nsCLKR/X low CLKR int -4 6.5 -4 13Delaytime,CLKR hightointernal4 td(CKRH-FRV) (3) nsFSR valid CLKR ext 1 16.5 1 18 CLKX int -4 6.5 -4 13Delaytime,CLKX hightointernal9 td(CKXH-FXV) (3) nsFSX valid CLKX ext 1 16.5 1 18 Disabletime,DX highimpedance CLKX int -4 6.5 -4 13 12 tdis(CKXH-DXHZ) (3) followinglastdatabitfromCLKX ns CLKX ext -2 16.5 -2 18high 13 td(CKXH-DXV) Delaytime,CLKX hightoDX valid ns CLKX ext 1 + D1 (8) 16.5+ D2 (8) 1 + D1 (8) 18 + D2 (8) Delaytime,FSX hightoDX valid FSX int -4(9) 6.5(9) -4(9) 13(9) 14 td(FXH-DXV) (3) nsONLY applieswhen indata FSX ext -2(9) 16.5(9) -2(9) 18(10) delay0 (XDATDLY = 00b)mode (1) CLKRP = CLKXP = FSRP = FSXP = 0.Ifpolarityofany ofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) Minimum delaytimesalsorepresentminimum outputholdtimes. (3) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (4) Minimum CLKR/X cycletimesmust be met,even when CLKR/X isgeneratedby an internalclocksource.Minimum CLKR/X cycletimes arebased on internallogicspeed;themaximum usablespeed may be lowerdue toEDMA limitationsand AC timingrequirements. (5) P = ASYNC3 periodinns.Forexample,when theASYNC clockdomain isrunningat100 MHz, use 10 ns. (6) Use whichevervalueisgreater. (7) C = H orL S = sample rategeneratorinputclock= P ifCLKSM = 1 (P = ASYNC period) S = sample rategeneratorinputclock= P_clksifCLKSM = 0 (P_clks= CLKS period) H = CLKX highpulsewidth= (CLKGDV/2 + 1)*S ifCLKGDV iseven H = (CLKGDV + 1)/2*S ifCLKGDV isodd L = CLKX lowpulsewidth= (CLKGDV/2) *S ifCLKGDV iseven L = (CLKGDV + 1)/2*S ifCLKGDV isodd CLKGDV shouldbe setappropriatelytoensuretheMcBSP bitratedoes notexceed themaximum limit(see(4)above). (8) ExtradelayfromCLKX hightoDX validappliesonlytothefirstdatabitofa device,ifand onlyifDXENA = 1 inSPCR. ifDXENA = 0,thenD1 = D2 = 0 ifDXENA = 1,thenD1 = 6P,D2 = 12P (9) ExtradelayfromFSX hightoDX validappliesonlytothefirstdatabitofa device,ifand onlyifDXENA = 1 inSPCR. ifDXENA = 0,thenD1 = D2 = 0 ifDXENA = 1,thenD1 = 6P,D2 = 12P (10)ExtradelayfromFSX hightoDX validappliesonlytothefirstdatabitofa device,ifand onlyifDXENA = 1 inSPCR. ifDXENA = 0,thenD1 = D2 = 0 ifDXENA = 1,thenD1 = 6P,D2 = 12P

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-66.SwitchingCharacteristicsforMcBSP1 1.0V(2) (seeFigure5-35) 1.0V NO. PARAMETER UNIT MIN MAX Delaytime,CLKS hightoCLKR/X highforinternalCLKR/X1 td(CKSH-CKRXH) 1.5 23 nsgeneratedfromCLKS input 2 tc(CKRX) (3) Cycletime,CLKR/X CLKR/X int 2P or26.6(4)(5)(6) ns 3 tw(CKRX) (3) Pulseduration,CLKR/X highorCLKR/X low CLKR/X int C -2(7) C + 2(7) ns CLKR int -4 13 4 td(CKRH-FRV) Delaytime,CLKR hightointernalFSR valid ns CLKR ext 2.5 23 CLKX int -4 13 9 td(CKXH-FXV) Delaytime,CLKX hightointernalFSX valid ns CLKX ext 1 23 CLKX int -4 13Disabletime,DX highimpedance followinglast12 tdis(CKXH-DXHZ)(3) nsdatabitfromCLKX high CLKX ext -2 23 CLKX int -4+ D1 (8) 13 + D2 (9) 13 td(CKXH-DXV) Delaytime,CLKX hightoDX valid ns CLKX ext 1 + D1 (9) 23 + D2 (9) Delaytime,FSX hightoDX valid FSX int -4(10) 13(10) 14 td(FXH-DXV) (3) nsONLY applieswhen indata FSX ext -2(10) 23(10) delay0 (XDATDLY = 00b)mode (1) CLKRP = CLKXP = FSRP = FSXP = 0.Ifpolarityofany ofthesignalsisinverted,thenthetimingreferencesofthatsignalarealso inverted. (2) Minimum delaytimesalsorepresentminimum outputholdtimes. (3) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (4) Minimum CLKR/X cycletimesmust be met,even when CLKR/X isgeneratedby an internalclocksource.Minimum CLKR/X cycletimes arebased on internallogicspeed;themaximum usablespeed may be lowerdue toEDMA limitationsand AC timingrequirements. (5) P = ASYNC3 periodinns.Forexample,when theASYNC clockdomain isrunningat100 MHz, use 10 ns. (6) Use whichevervalueisgreater. (7) C = H orL S = sample rategeneratorinputclock= P ifCLKSM = 1 (P = ASYNC period) S = sample rategeneratorinputclock= P_clksifCLKSM = 0 (P_clks= CLKS period) H = CLKX highpulsewidth= (CLKGDV/2 + 1)*S ifCLKGDV iseven H = (CLKGDV + 1)/2*S ifCLKGDV isodd L = CLKX lowpulsewidth= (CLKGDV/2) *S ifCLKGDV iseven L = (CLKGDV + 1)/2*S ifCLKGDV isodd CLKGDV shouldbe setappropriatelytoensuretheMcBSP bitratedoes notexceed themaximum limit(see(4)above). (8) ExtradelayfromCLKX hightoDX validappliesonlytothefirstdatabitofa device,ifand onlyifDXENA = 1 inSPCR. ifDXENA = 0,thenD1 = D2 = 0 ifDXENA = 1,thenD1 = 6P,D2 = 12P (9) ExtradelayfromCLKX hightoDX validappliesonlytothefirstdatabitofa device,ifand onlyifDXENA = 1 inSPCR. ifDXENA = 0,thenD1 = D2 = 0 ifDXENA = 1,thenD1 = 6P,D2 = 12P (10)ExtradelayfromFSX hightoDX validappliesonlytothefirstdatabitofa device,ifand onlyifDXENA = 1 inSPCR. ifDXENA = 0,thenD1 = D2 = 0 ifDXENA = 1,thenD1 = 6P,D2 = 12P Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 167 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

FSR□external CLKR/X□(no□need□to□resync) CLKR/X□(needs□resync) Bit(n1) (n2) (n3) Bit□0 Bit(n1) (n2) (n3) CLKS CLKR FSR□(int) FSR□(ext) DR CLKX FSX□(int) FSX□(ext) FSX□(XDATDLY=00b) DX 13 (A) 13 (A) OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-35.McBSP Timing(B) Table5-67.Timing Requirements forMcBSP0 FSR When GSYNC = 1(1)(seeFigure5-36) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 1 tsu(FRH-CKSH) Setuptime,FSR highbeforeCLKS high 4 4.5 5 ns 2 th(CKSH-FRH) Holdtime,FSR highafterCLKS high 4 4 4 ns (1) These parametersarenotproductiontestedand arespecifiedby designtowork from-40°C to125°C. Table5-68.Timing Requirements forMcBSP1 FSR When GSYNC = 1(1)(seeFigure5-36) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 1 tsu(FRH-CKSH) Setuptime,FSR highbeforeCLKS high 5 5 10 ns 2 th(CKSH-FRH) Holdtime,FSR highafterCLKS high 4 4 4 ns (1) These parametersarenotproductiontestedand arespecifiedby designtowork from-40°C to125°C. Figure5-36.FSR Timing When GSYNC = 1

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(all pins) State Machine Clock Control SPIx_SIMO SPIx_SOMI SPIx_ENA SPIx_SCS SPIx_CLK OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013

5.17 SerialPeripheralInterfacePorts(SPI0,SPI1)

Figure5-37isa blockdiagramoftheSPI module,whichisa simpleshiftregisterand bufferpluscontrol logic.Data iswrittentotheshiftregisterbeforetransmissionoccursand isreadfromthebufferattheend oftransmission.The SPI can operateeitheras a master,inwhich case,itinitiatesa transferand drives theSPIx_CLK pin,or as a slave.Four clockphase and polarityoptionsare supportedas wellas many dataformattingoptions. Figure5-37.Block Diagram ofSPI Module The SPI supports3-, 4-, and 5-pinoperationwith three basic pins (SPIx_CLK, SPIx_SIMO, and SPIx_SOMI) and two optionalpins(SPIx_SCS, SPIx_ENA). The optionalSPIx_SCS (SlaveChip Select)pinismost usefultoenableinslavemode when thereare otherslavedeviceson thesame SPI port.The devicewillonlyshiftdataand drivetheSPIx_SOMI pin when SPIx_SCS isheldlow. Inslavemode, SPIx_ENA isan optionaloutput.The SPIx_ENA outputprovidesthestatusoftheinternal transmitbuffer(SPIDAT0/1registers).Infour-pinmode withtheenableoption,SPIx_ENA isassertedonly when the transmitbufferisfull,indicatingthatthe slaveisready to beginanothertransfer.In five-pin mode, the SPIx_ENA is additionallyqualifiedby SPIx_SCS being asserted.This allowsa single handshake linetobe sharedby multipleslaveson thesame SPI bus. Inmastermode, theSPIx_ENA pinisan optionalinputand themastercan be configuredtodelaythestart ofthenexttransferuntiltheslaveassertsSPIx_ENA. The additionofthishandshake signalsimplifiesSPI communicationsand,on average,increasesSPI bus throughputsincethemasterdoes notneed todelay each transferlongenough toallowfortheworst-caselatencyoftheslavedevice.Instead,each transfer can beginas soon as boththemasterand slavehave actuallyservicedthepreviousSPI transfer. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 169 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

Optional − Slave Chip Select Optional Enable (Ready) SLA VE SPIMASTER SPI SPIx_SIMOSPIx_SIMO SPIx_SOMI SPIx_SOMI SPIx_CLK SPIx_CLK SPIx_ENA SPIx_ENA SPIx_SCS SPIx_SCS OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-38.IllustrationofSPI Master-to-SPISlaveConnection

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5.17.1 SPI PeripheralRegistersDescription(s)

Table5-69isa listoftheSPI registers. Table5-69.SPIx ConfigurationRegisters SPI0 SPI1 ACRONYM DESCRIPTIONBYTE ADDRESS BYTE ADDRESS 0x01C4 1000 0x01F0 E000 SPIGCR0 GlobalControlRegister0 0x01C4 1004 0x01F0 E004 SPIGCR1 GlobalControlRegister1 0x01C4 1008 0x01F0 E008 SPIINT0 InterruptRegister 0x01C4 100C 0x01F0 E00C SPILVL InterruptLevelRegister 0x01C4 1010 0x01F0 E010 SPIFLG FlagRegister 0x01C4 1014 0x01F0 E014 SPIPC0 PinControlRegister0 (PinFunction) 0x01C4 1018 0x01F0 E018 SPIPC1 PinControlRegister1 (PinDirection) 0x01C4 101C 0x01F0 E01C SPIPC2 PinControlRegister2 (PinData In) 0x01C4 1020 0x01F0 E020 SPIPC3 PinControlRegister3 (PinData Out) 0x01C4 1024 0x01F0 E024 SPIPC4 PinControlRegister4 (PinData Set) 0x01C4 1028 0x01F0 E028 SPIPC5 PinControlRegister5 (PinData Clear) 0x01C4 102C 0x01F0 E02C Reserved Reserved-Do notwritetothisregister 0x01C4 1030 0x01F0 E030 Reserved Reserved-Do notwritetothisregister 0x01C4 1034 0x01F0 E034 Reserved Reserved-Do notwritetothisregister 0x01C4 1038 0x01F0 E038 SPIDAT0 ShiftRegister0 (withoutformatselect) 0x01C4 103C 0x01F0 E03C SPIDAT1 ShiftRegister1 (withformatselect) 0x01C4 1040 0x01F0 E040 SPIBUF BufferRegister 0x01C4 1044 0x01F0 E044 SPIEMU EmulationRegister 0x01C4 1048 0x01F0 E048 SPIDELAY DelayRegister 0x01C4 104C 0x01F0 E04C SPIDEF DefaultChipSelectRegister 0x01C4 1050 0x01F0 E050 SPIFMT0 FormatRegister0 0x01C4 1054 0x01F0 E054 SPIFMT1 FormatRegister1 0x01C4 1058 0x01F0 E058 SPIFMT2 FormatRegister2 0x01C4 105C 0x01F0 E05C SPIFMT3 FormatRegister3 0x01C4 1060 0x01F0 E060 INTVEC0 InterruptVectorforSPI INT0 0x01C4 1064 0x01F0 E064 INTVEC1 InterruptVectorforSPI INT1 Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 171 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.17.2 SPI ElectricalData/Timing

5.17.2.1SerialPeripheralInterface(SPI)Timing Table5-70throughTable5-85assume testingoverrecommended operatingconditions(seeFigure5-39 throughFigure5-42). Table5-70.GeneralTiming Requirements forSPI0 Master Modes (1)(2) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 1 tc(SPC)M CycleTime,SPI0_CLK, AllMasterModes 20(3) 256P 30(3) 256P 40(3) 256P ns 2 tw(SPCH)M PulseWidthHigh,SPI0_CLK, AllMasterModes 0.5M-1 0.5M-1 0.5M-1 ns 3 tw(SPCL)M PulseWidthLow, SPI0_CLK, AllMasterModes 0.5M-1 0.5M-1 0.5M-1 ns Polarity= 0,Phase = 0, 5 5 6toSPI0_CLK rising Polarity= 0,Phase = 1, -0.5M+5 -0.5M+5 -0.5M+6Delay,initialdatabitvalidon toSPI0_CLK rising 4 td(SIMO_SPC)M SPI0_SIMO afterinitialedge ns Polarity= 1,Phase = 0,on SPI0_CLK (4) 5 5 6toSPI0_CLK falling Polarity= 1,Phase = 1, -0.5M+5 -0.5M+5 -0.5M+6toSPI0_CLK falling Polarity= 0,Phase = 0, 5 5 6fromSPI0_CLK rising Polarity= 0,Phase = 1, 5 5 6Delay,subsequentbitsvalid fromSPI0_CLK falling 5 td(SPC_SIMO)M on SPI0_SIMO aftertransmit ns Polarity= 1,Phase = 0,edge ofSPI0_CLK 5 5 6fromSPI0_CLK falling Polarity= 1,Phase = 1, 5 5 6fromSPI0_CLK rising Polarity= 0,Phase = 0, 0.5M-3 0.5M-3 0.5M-3fromSPI0_CLK falling Polarity= 0,Phase = 1, 0.5M-3 0.5M-3 0.5M-3Outputholdtime,SPI0_SIMO fromSPI0_CLK rising 6 toh(SPC_SIMO)M validafterreceiveedge of ns Polarity= 1,Phase = 0,SPI0_CLK 0.5M-3 0.5M-3 0.5M-3fromSPI0_CLK rising Polarity= 1,Phase = 1, 0.5M-3 0.5M-3 0.5M-3fromSPI0_CLK falling Polarity= 0,Phase = 0, 1.5 1.5 1.5toSPI0_CLK falling Polarity= 0,Phase = 1, 1.5 1.5 1.5InputSetupTime,SPI0_SOMI toSPI0_CLK rising 7 tsu(SOMI_SPC)M validbeforereceiveedge of ns Polarity= 1,Phase = 0,SPI0_CLK 1.5 1.5 1.5toSPI0_CLK rising Polarity= 1,Phase = 1, 1.5 1.5 1.5toSPI0_CLK falling Polarity= 0,Phase = 0, 4 4 5fromSPI0_CLK falling Polarity= 0,Phase = 1, 4 4 5InputHoldTime,SPI0_SOMI fromSPI0_CLK rising 8 tih(SPC_SOMI)M validafterreceiveedge of ns Polarity= 1,Phase = 0,SPI0_CLK 4 4 5fromSPI0_CLK rising Polarity= 1,Phase = 1, 4 4 5fromSPI0_CLK falling (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) P = SYSCLK2 period;M = tc(SPC)M (SPImasterbitclockperiod) (3) Thistimingislimitedby thetimingshown or3P,whicheverisgreater. (4) Firstbitmay be MSB orLSB dependingupon SPI configuration.MO(0) referstofirstbitand MO(n) referstolastbitoutputon SPI0_SIMO. MI(0)referstothefirstbitinputand MI(n)referstothelastbitinputon SPI0_SOMI.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-71.GeneralTiming Requirements forSPI0 SlaveModes (1) 9 tc(SPC)S(2) CycleTime,SPI0_CLK, AllSlaveModes 40(3) 50(3) 60(3) ns 10 tw(SPCH)S (2) PulseWidthHigh,SPI0_CLK, AllSlaveModes 18 22 27 ns 11 tw(SPCL)S (2) PulseWidthLow, SPI0_CLK, AllSlaveModes 18 22 27 ns Polarity= 0,Phase = 0, 2P 2P 2PtoSPI0_CLK rising Polarity= 0,Phase = 1,Setuptime,transmitdata 2P 2P 2PtoSPI0_CLK risingwrittentoSPI before12 tsu(SOMI_SPC)S (2) nsinitialclockedge from Polarity= 1,Phase = 0, 2P 2P 2Pmaster.(4)(5) toSPI0_CLK falling Polarity= 1,Phase = 1, 2P 2P 2PtoSPI0_CLK falling Polarity= 0,Phase = 0, 17 20 27fromSPI0_CLK rising Polarity= 0,Phase = 1,Delay,subsequentbits 17 20 27fromSPI0_CLK fallingvalidon SPI0_SOMI13 td(SPC_SOMI)S nsaftertransmitedge of Polarity= 1,Phase = 0, 17 20 27SPI0_CLK fromSPI0_CLK falling Polarity= 1,Phase = 1, 17 20 27fromSPI0_CLK rising Polarity= 0,Phase = 0, 0.5S-6 0.5S-16 0.5S-20fromSPI0_CLK falling Polarity= 0,Phase = 1,Outputholdtime, 0.5S-6 0.5S-16 0.5S-20fromSPI0_CLK risingSPI0_SOMI validafter14 toh(SPC_SOMI)S (2) nsreceiveedge of Polarity= 1,Phase = 0, 0.5S-6 0.5S-16 0.5S-20SPI0_CLK fromSPI0_CLK rising Polarity= 1,Phase = 1, 0.5S-6 0.5S-16 0.5S-20fromSPI0_CLK falling Polarity= 0,Phase = 0, 1.5 1.5 1.5toSPI0_CLK falling Polarity= 1,Phase = 1, 1.5 1.5 1.5toSPI0_CLK falling Polarity= 0,Phase = 0, 4 4 5fromSPI0_CLK falling Polarity= 0,Phase = 1,InputHoldTime, 4 4 5fromSPI0_CLK risingSPI0_SIMO validafter16 tih(SPC_SIMO)S (2) nsreceiveedge of Polarity= 1,Phase = 0, 4 4 5SPI0_CLK fromSPI0_CLK rising Polarity= 1,Phase = 1, 4 4 5fromSPI0_CLK falling (1) P = SYSCLK2 period;S = tc(SPC)S (SPIslavebitclockperiod) (2) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (3) Thistimingislimitedby thetimingshown or3P,whicheverisgreater. (4) Firstbitmay be MSB orLSB dependingupon SPI configuration.SO(0) referstofirstbitand SO(n) referstolastbitoutputon SPI0_SOMI. SI(0)referstothefirstbitinputand SI(n)referstothelastbitinputon SPI0_SIMO. (5) Measured fromtheterminationofthewriteofnew datatotheSPI module,Inanalyzingthroughputrequirements,additionalinternalbus cyclesmust be accountedfortoallowdatatobe writtentotheSPI module by theCPU. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 173 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-72.AdditionalSPI0 Master Timings,4-PinEnable Option (1)(2)(3) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity= 0,Phase = 0, 3P+5 3P+5 3P+6toSPI0_CLK rising Polarity= 0,Phase = 1, 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6toSPI0_CLK risingDelayfromslaveassertionofSPI0_ENA17 td(ENA_SPC)M nsactivetofirstSPI0_CLK frommaster.(4) Polarity= 1,Phase = 0, 3P+5 3P+5 3P+6toSPI0_CLK falling Polarity= 1,Phase = 1, 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6toSPI0_CLK falling Polarity= 0,Phase = 0, 0.5M+P+5 0.5M+P+5 0.5M+P+6fromSPI0_CLK falling Polarity= 0,Phase = 1, P+5 P+5 P+6Max delayforslavetodeassertSPI0_ENA fromSPI0_CLK falling 18 td(SPC_ENA)M afterfinalSPI0_CLK edge toensure ns Polarity= 1,Phase = 0,masterdoes notbeginthenexttransfer.(5) 0.5M+P+5 0.5M+P+5 0.5M+P+6fromSPI0_CLK rising Polarity= 1,Phase = 1, P+5 P+5 P+6fromSPI0_CLK rising (1) These parametersareinadditiontothegeneraltimingsforSPI mastermodes (Table5-70). (2) P = SYSCLK2 period;M = tc(SPC)M (SPImasterbitclockperiod) (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourmasterclockingmodes. (4) Inthecase where themasterSPI isreadywithnew databeforeSPI0_ENA assertion. (5) Inthecase where themasterSPI isreadywithnew databeforeSPI0_EN A deassertion. Table5-73.AdditionalSPI0 Master Timings,4-PinChip SelectOption (1)(2)(3) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity= 0,Phase = 0, 2P-1 2P-2 2P-3toSPI0_CLK rising Polarity= 0,Phase = 1, 0.5M+2P-1 0.5M+2P-2 0.5M+2P-3toSPI0_CLK risingDelayfromSPI0_SCS activetofirst19 td(SCS_SPC)M nsSPI0_CLK (4)(5) Polarity= 1,Phase = 0, 2P-1 2P-2 2P-3toSPI0_CLK falling Polarity= 1,Phase = 1, 0.5M+2P-1 0.5M+2P-2 0.5M+2P-3toSPI0_CLK falling (1) These parametersareinadditiontothegeneraltimingsforSPI mastermodes (Table5-70). (2) P = SYSCLK2 period;M = tc(SPC)M (SPImasterbitclockperiod) (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourmasterclockingmodes. (4) Inthecase where themasterSPI isreadywithnew databeforeSPI0_SCS assertion. (5) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.C2TDELAY[4:0].

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-73.AdditionalSPI0 Master Timings,4-PinChip SelectOption (1)(2)(3) (continued) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity= 0,Phase = 0, 0.5M+P-1 0.5M+P-2 0.5M+P-3fromSPI0_CLK falling Polarity= 0,Phase = 1, P-1 P-2 P-3fromSPI0_CLK fallingDelayfromfinalSPI0_CLK edge tomaster20 td(SPC_SCS)M nsdeassertingSPI0_SCS (6)(7) Polarity= 1,Phase = 0, 0.5M+P-1 0.5M+P-2 0.5M+P-3fromSPI0_CLK rising Polarity= 1,Phase = 1, P-1 P-2 P-3fromSPI0_CLK rising (6) Exceptformodes when SPIDAT1.CSHOLD isenabledand thereisadditionaldatatotransmit.Inthiscase,SPI0_SCS willremainasserted. (7) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.T2CDELAY[4:0]. Table5-74.AdditionalSPI0 Master Timings,5-PinOption (1)(2)(3) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity= 0,Phase = 0, 0.5M+P+5 0.5M+P+5 0.5M+P+6fromSPI0_CLK falling Polarity= 0,Phase = 1,Max delayforslavetodeassert P+5 P+5 P+6fromSPI0_CLK fallingSPI0_ENA afterfinalSPI0_CLK18 td(SPC_ENA)M nsedge toensuremasterdoes not Polarity= 1,Phase = 0, 0.5M+P+5 0.5M+P+5 0.5M+P+6beginthenexttransfer.(4) fromSPI0_CLK rising Polarity= 1,Phase = 1, P+5 P+5 P+6fromSPI0_CLK rising Polarity= 0,Phase = 0, 0.5M+P-2 0.5M+P-2 0.5M+P-3fromSPI0_CLK falling Polarity= 0,Phase = 1, P-2 P-2 P-3DelayfromfinalSPI0_CLK edge to fromSPI0_CLK falling 20 td(SPC_SCS)M masterdeassertingSPI0_SCS (5) ns Polarity= 1,Phase = 0,(6) 0.5M+P-2 0.5M+P-2 0.5M+P-3fromSPI0_CLK rising Polarity= 1,Phase = 1, P-2 P-2 P-3fromSPI0_CLK rising Max delayforslaveSPI todriveSPI0_ENA validaftermaster 21 td(SCSL_ENAL)M assertsSPI0_SCS todelaythemasterfrombeginningthe C2TDELAY+P C2TDELAY+P C2TDELAY+P ns nexttransfer, (1) These parametersareinadditiontothegeneraltimingsforSPI mastermodes (Table5-71). (2) P = SYSCLK2 period;M = tc(SPC)M (SPImasterbitclockperiod) (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourmasterclockingmodes. (4) Inthecase where themasterSPI isreadywithnew databeforeSPI0_ENA deassertion. (5) Exceptformodes when SPIDAT1.CSHOLD isenabledand thereisadditionaldatatotransmit.Inthiscase,SPI0_SCS willremainasserted. (6) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.T2CDELAY[4:0]. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 175 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-74.AdditionalSPI0 Master Timings,5-PinOption (1)(2)(3) (continued) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity= 0,Phase = 0, 2P-2 2P-2 2P-3toSPI0_CLK rising Polarity= 0,Phase = 1, 0.5M+2P-2 0.5M+2P-2 0.5M+2P-3toSPI0_CLK risingDelayfromSPI0_SCS activeto22 td(SCS_SPC)M nsfirstSPI0_CLK (7)(8)(9) Polarity= 1,Phase = 0, 2P-2 2P-2 2P-3toSPI0_CLK falling Polarity= 1,Phase = 1, 0.5M+2P-2 0.5M+2P-2 0.5M+2P-3toSPI0_CLK falling Polarity= 0,Phase = 0, 3P+5 3P+5 3P+6toSPI0_CLK rising Polarity= 0,Phase = 1, 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6toSPI0_CLK risingDelayfromassertionofSPI0_ENA23 td(ENA_SPC)M nslowtofirstSPI0_CLK edge.(10) Polarity= 1,Phase = 0, 3P+5 3P+5 3P+6toSPI0_CLK falling Polarity= 1,Phase = 1, 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6toSPI0_CLK falling (7) IfSPI0_ENA isassertedimmediatelysuch thatthetransmissionisnotdelayedby SPI0_ENA. (8) Inthecase where themasterSPI isreadywithnew databeforeSPI0_SCS assertion. (9) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.C2TDELAY[4:0]. (10)IfSPI0_ENA was initiallydeassertedhighand SPI0_CLK isdelayed. Table5-75.AdditionalSPI0 SlaveTimings,4-PinEnable Option (1)(2)(3) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX (1) These parametersareinadditiontothegeneraltimingsforSPI slavemodes (Table5-71). (2) P = SYSCLK2 period;M = tc(SPC)M (SPImasterbitclockperiod) (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourslaveclockingmodes.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-76.AdditionalSPI0 SlaveTimings,4-PinChip SelectOption (1)(2)(3)(4) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX RequireddelayfromSPI0_SCS assertedatslavetofirstSPI0_CLK edge25 td(SCSL_SPC)S P + 1.5 P + 1.5 P + 1.5 nsatslave. Polarity= 0,Phase = 0, 0.5M+P+4 0.5M+P+4 0.5M+P+5fromSPI0_CLK falling Polarity= 0,Phase = 1, P+4 P+4 P+5fromSPI0_CLK fallingRequireddelayfromfinalSPI0_CLK edge26 td(SPC_SCSH)S nsbeforeSPI0_SCS isdeasserted. Polarity= 1,Phase = 0, 0.5M+P+4 0.5M+P+4 0.5M+P+5fromSPI0_CLK rising Polarity= 1,Phase = 1, P+4 P+4 P+5fromSPI0_CLK rising 27 tena(SCSL_SOMI)S DelayfrommasterassertingSPI0_SCS toslavedrivingSPI0_SOMI valid P+17.5 P+20 P+27 ns 28 tdis(SCSH_SOMI)S DelayfrommasterdeassertingSPI0_SCS toslave3-statingSPI0_SOMI P+17.5 P+20 P+27 ns (1) These parametersarenotproductiontestedand arespecifiedby designtowork from-40°C to125°C. (2) These parametersareinadditiontothegeneraltimingsforSPI slavemodes (Table5-71). (3) P = SYSCLK2 period;M = tc(SPC)M (SPImasterbitclockperiod) (4) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourslaveclockingmodes. Table5-77.AdditionalSPI0 SlaveTimings,5-PinOption (1)(2)(3)(4) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX RequireddelayfromSPI0_SCS assertedatslavetofirst25 td(SCSL_SPC)S P + 1.5 P + 1.5 P + 1.5 nsSPI0_CLK edge atslave. Polarity= 0,Phase = 0, 0.5M+P+4 0.5M+P+4 0.5M+P+5fromSPI0_CLK falling Polarity= 0,Phase = 1, P+4 P+4 P+5Requireddelayfromfinal fromSPI0_CLK falling 26 td(SPC_SCSH)S SPI0_CLK edge beforeSPI0_SCS ns Polarity= 1,Phase = 0,isdeasserted. 0.5M+P+4 0.5M+P+4 0.5M+P+5fromSPI0_CLK rising Polarity= 1,Phase = 1, P+4 P+4 P+5fromSPI0_CLK rising DelayfrommasterassertingSPI0_SCS toslavedriving27 tena(SCSL_SOMI)S P+17.5 P+20 P+27 nsSPI0_SOMI valid DelayfrommasterdeassertingSPI0_SCS toslave3-stating28 tdis(SCSH_SOMI)S P+17.5 P+20 P+27 nsSPI0_SOMI (1) These parametersarenotproductiontestedand arespecifiedby designtowork from-40°C to125°C. (2) These parametersareinadditiontothegeneraltimingsforSPI slavemodes (Table5-71). (3) P = SYSCLK2 period;M = tc(SPC)M (SPImasterbitclockperiod) (4) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourslaveclockingmodes. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 177 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-77.AdditionalSPI0 SlaveTimings,5-PinOption (1)(2)(3)(4) (continued) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX DelayfrommasterdeassertingSPI0_SCS toslavedriving29 tena(SCSL_ENA)S 17.5 20 27 nsSPI0_ENA valid Polarity= 0,Phase = 0, 2.5P+17.5 2.5P+20 2.5P+27fromSPI0_CLK falling fromSPI0_CLK rising Polarity= 1,Phase = 1, 2.5P+17.5 2.5P+20 2.5P+27fromSPI0_CLK falling (5) SPI0_ENA isdrivenlowafterthetransmissioncompletesiftheSPIINT0.ENABLE_HIGHZ bitisprogrammed to0.Otherwiseitistri-stated.Iftri-stated,an externalpullupresistorshould be used toprovidea validleveltothemaster.Thisoptionisusefulwhen tyingseveralSPI slavedevicestoa singlemaster.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-78.GeneralTiming Requirements forSPI1 Master Modes (1)(2) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 1 tc(SPC)M CycleTime,SPI1_CLK, AllMasterModes 20(3) 256P 30(3) 256P 40(3) 256P ns 2 tw(SPCH)M PulseWidthHigh,SPI1_CLK, AllMasterModes 0.5M-1 0.5M-1 0.5M-1 ns 3 tw(SPCL)M PulseWidthLow, SPI1_CLK, AllMasterModes 0.5M-1 0.5M-1 0.5M-1 ns Polarity= 0,Phase = 0, 5 5 6toSPI1_CLK rising Polarity= 0,Phase = 1, -0.5M+5 -0.5M+5 -0.5M+6Delay,initialdatabitvalidon toSPI1_CLK rising 4 td(SIMO_SPC)M SPI1_SIMO toinitialedge on ns Polarity= 1,Phase = 0,SPI1_CLK (4) 5 5 6toSPI1_CLK falling Polarity= 1,Phase = 1, -0.5M+5 -0.5M+5 -0.5M+6toSPI1_CLK falling Polarity= 0,Phase = 0, 5 5 6fromSPI1_CLK rising Polarity= 0,Phase = 1, 5 5 6Delay,subsequentbitsvalid fromSPI1_CLK falling 5 td(SPC_SIMO)M on SPI1_SIMO aftertransmit ns Polarity= 1,Phase = 0,edge ofSPI1_CLK 5 5 6fromSPI1_CLK falling Polarity= 1,Phase = 1, 5 5 6fromSPI1_CLK rising Polarity= 0,Phase = 0, 0.5M-3 0.5M-3 0.5M-3fromSPI1_CLK falling Polarity= 0,Phase = 1, 0.5M-3 0.5M-3 0.5M-3Outputholdtime,SPI1_SIMO fromSPI1_CLK rising 6 toh(SPC_SIMO)M validafterreceiveedge of ns Polarity= 1,Phase = 0,SPI1_CLK 0.5M-3 0.5M-3 0.5M-3fromSPI1_CLK rising Polarity= 1,Phase = 1, 0.5M-3 0.5M-3 0.5M-3fromSPI1_CLK falling Polarity= 0,Phase = 0, 1.5 1.5 1.5toSPI1_CLK falling Polarity= 0,Phase = 1, 1.5 1.5 1.5InputSetupTime, toSPI1_CLK rising 7 tsu(SOMI_SPC)M SPI1_SOMI validbefore ns Polarity= 1,Phase = 0,receiveedge ofSPI1_CLK 1.5 1.5 1.5toSPI1_CLK rising Polarity= 1,Phase = 1, 1.5 1.5 1.5toSPI1_CLK falling Polarity= 0,Phase = 0, 4 5 6fromSPI1_CLK falling Polarity= 0,Phase = 1, 4 5 6InputHoldTime,SPI1_SOMI fromSPI1_CLK rising 8 tih(SPC_SOMI)M validafterreceiveedge of ns Polarity= 1,Phase = 0,SPI1_CLK 4 5 6fromSPI1_CLK rising Polarity= 1,Phase = 1, 4 5 6fromSPI1_CLK falling (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) P = SYSCLK2 period;M = tc(SPC)M (SPImasterbitclockperiod) (3) Thistimingislimitedby thetimingshown or3P,whicheverisgreater. (4) Firstbitmay be MSB orLSB dependingupon SPI configuration.MO(0) referstofirstbitand MO(n) referstolastbitoutputon SPI1_SIMO. MI(0)referstothefirstbitinputand MI(n)referstothelastbitinputon SPI1_SOMI. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 179 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-79.GeneralTiming Requirements forSPI1 SlaveModes (1) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 9 tc(SPC)S(2) CycleTime,SPI1_CLK, AllSlaveModes 40(3) 50(3) 60(3) ns 10 tw(SPCH)S (2) PulseWidthHigh,SPI1_CLK, AllSlaveModes 18 22 27 ns 11 tw(SPCL)S (2) PulseWidthLow, SPI1_CLK, AllSlaveModes 18 22 27 ns Polarity= 0,Phase = 0, 2P 2P 2PtoSPI1_CLK rising Polarity= 0,Phase = 1,Setuptime,transmitdata 2P 2P 2PtoSPI1_CLK risingwrittentoSPI beforeinitial12 tsu(SOMI_SPC)S (2) nsclockedge from Polarity= 1,Phase = 0, 2P 2P 2Pmaster.(4)(5) toSPI1_CLK falling Polarity= 1,Phase = 1, 2P 2P 2PtoSPI1_CLK falling Polarity= 0,Phase = 0, 15 17 19fromSPI1_CLK rising Polarity= 0,Phase = 1, 15 17 19Delay,subsequentbits fromSPI1_CLK falling 13 td(SPC_SOMI)S validon SPI1_SOMI after ns Polarity= 1,Phase = 0,transmitedge ofSPI1_CLK 15 17 19fromSPI1_CLK falling Polarity= 1,Phase = 1, 15 17 19fromSPI1_CLK rising Polarity= 0,Phase = 0, 0.5S-4 0.5S-10 0.5S-12fromSPI1_CLK falling Polarity= 0,Phase = 1, 0.5S-4 0.5S-10 0.5S-12Outputholdtime, fromSPI1_CLK rising 14 toh(SPC_SOMI)S (2) SPI1_SOMI validafter ns Polarity= 1,Phase = 0,receiveedge ofSPI1_CLK 0.5S-4 0.5S-10 0.5S-12fromSPI1_CLK rising Polarity= 1,Phase = 1, 0.5S-4 0.5S-10 0.5S-12fromSPI1_CLK falling Polarity= 0,Phase = 0, 1.5 1.5 1.5toSPI1_CLK falling Polarity= 0,Phase = 1, 1.5 1.5 1.5InputSetupTime, toSPI1_CLK rising 15 tsu(SIMO_SPC)S (2) SPI1_SIMO validbefore ns Polarity= 1,Phase = 0,receiveedge ofSPI1_CLK 1.5 1.5 1.5toSPI1_CLK rising Polarity= 1,Phase = 1, 1.5 1.5 1.5toSPI1_CLK falling Polarity= 0,Phase = 0, 4 5 6fromSPI1_CLK falling Polarity= 0,Phase = 1, 4 5 6InputHoldTime, fromSPI1_CLK rising 16 tih(SPC_SIMO)S (2) SPI1_SIMO validafter ns Polarity= 1,Phase = 0,receiveedge ofSPI1_CLK 4 5 6fromSPI1_CLK rising Polarity= 1,Phase = 1, 4 5 6fromSPI1_CLK falling (1) P = SYSCLK2 period;S = tc(SPC)S (SPIslavebitclockperiod) (2) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (3) Thistimingislimitedby thetimingshown or3P,whicheverisgreater. (4) Firstbitmay be MSB orLSB dependingupon SPI configuration.SO(0) referstofirstbitand SO(n) referstolastbitoutputon SPI1_SOMI. SI(0)referstothefirstbitinputand SI(n)referstothelastbitinputon SPI1_SIMO. (5) Measured fromtheterminationofthewriteofnew datatotheSPI module,Inanalyzingthroughputrequirements,additionalinternalbus cyclesmust be accountedfortoallowdatatobe writtentotheSPI module by theCPU.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-80.Additional(1)SPI1 Master Timings,4-PinEnable Option(2)(3) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity= 0,Phase = 0, 3P+5 3P+5 3P+6toSPI1_CLK rising Delayfromslave Polarity= 0,Phase = 1, 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6assertionof toSPI1_CLK rising 17 td(EN A_SPC)M SPI1_ENA activeto ns Polarity= 1,Phase = 0,firstSPI1_CLK from 3P+5 3P+5 3P+6toSPI1_CLK fallingmaster.(4) Polarity= 1,Phase = 1, 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6toSPI1_CLK falling Polarity= 0,Phase = 0, 0.5M+P+5 0.5M+P+5 0.5M+P+6fromSPI1_CLK fallingMax delayforslaveto Polarity= 0,Phase = 1,deassertSPI1_ENA P+5 P+5 P+6fromSPI1_CLK fallingafterfinalSPI1_CLK18 td(SPC_ENA)M nsedge toensure Polarity= 1,Phase = 0, 0.5M+P+5 0.5M+P+5 0.5M+P+6masterdoes notbegin fromSPI1_CLK rising thenexttransfer.(5) Polarity= 1,Phase = 1, P+5 P+5 P+6fromSPI1_CLK rising (1) These parametersareinadditiontothegeneraltimingsforSPI mastermodes (Table5-78). (2) P = SYSCLK2 period;M = tc(SPC)M (SPImasterbitclockperiod) (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourmasterclockingmodes. (4) Inthecase where themasterSPI isreadywithnew databeforeSPI1_ENA assertion. (5) Inthecase where themasterSPI isreadywithnew databeforeSPI1_ENA deassertion. Table5-81.Additional(1)SPI1 Master Timings,4-PinChip SelectOption(2)(3) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity= 0,Phase = 0, 2P-1 2P-5 2P-6toSPI1_CLK rising Polarity= 0,Phase = 1,Delayfrom 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6toSPI1_CLK risingSPI1_SCS active19 td(SCS_SPC)M nstofirst Polarity= 1,Phase = 0, 2P-1 2P-5 2P-6SPI1_CLK (4)(5) toSPI1_CLK falling Polarity= 1,Phase = 1, 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6toSPI1_CLK falling Polarity= 0,Phase = 0, 0.5M+P-1 0.5M+P-5 0.5M+P-6fromSPI1_CLK falling Delayfromfinal Polarity= 0,Phase = 1, P-1 P-5 P-6SPI1_CLK edge to fromSPI1_CLK falling 20 td(SPC_SCS)M master ns Polarity= 1,Phase = 0,deasserting 0.5M+P-1 0.5M+P-5 0.5M+P-6fromSPI1_CLK risingSPI1_SCS (6)(7) Polarity= 1,Phase = 1, P-1 P-5 P-6fromSPI1_CLK rising (1) These parametersareinadditiontothegeneraltimingsforSPI mastermodes (Table5-78). (2) P = SYSCLK2 period;M = tc(SPC)M (SPImasterbitclockperiod) (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourmasterclockingmodes. (4) Inthecase where themasterSPI isreadywithnew databeforeSPI1_SCS assertion. (5) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.C2TDELAY[4:0]. (6) Exceptformodes when SPIDAT1.CSHOLD isenabledand thereisadditionaldatatotransmit.Inthiscase,SPI1_SCS willremain asserted. (7) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.T2CDELAY[4:0]. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 181 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-82.Additional(1)SPI1 Master Timings,5-PinOption(2)(3) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity= 0,Phase = 0, 0.5M+P+5 0.5M+P+5 0.5M+P+6fromSPI1_CLK falling Polarity= 0,Phase = 1,Max delayforslavetodeassert P+5 P+5 P+6fromSPI1_CLK fallingSPI1_ENA afterfinalSPI1_CLK18 td(SPC_ENA)M nsedge toensuremasterdoes not Polarity= 1,Phase = 0, 0.5M+P+5 0.5M+P+5 0.5M+P+6beginthenexttransfer.(4) fromSPI1_CLK rising Polarity= 1,Phase = 1, P+5 P+5 P+6fromSPI1_CLK rising Polarity= 0,Phase = 0, 0.5M+P-1 0.5M+P-5 0.5M+P-6fromSPI1_CLK falling Polarity= 0,Phase = 1, P-1 P-5 P-6fromSPI1_CLK fallingDelayfromfinalSPI1_CLK edge to20 td(SPC_SCS)M nsmasterdeassertingSPI1_SCS (5)(6) Polarity= 1,Phase = 0, 0.5M+P-1 0.5M+P-5 0.5M+P-6fromSPI1_CLK rising Polarity= 1,Phase = 1, P-1 P-5 P-6fromSPI1_CLK rising Max delayforslaveSPI todriveSPI1_ENA validaftermaster 21 td(SCSL_ENAL)M assertsSPI1_SCS todelaythe C2TDELAY+P C2TDELAY+P C2TDELAY+P ns masterfrombeginningthenexttransfer, Polarity= 0,Phase = 0, 2P-1 2P-5 2P-6toSPI1_CLK rising Polarity= 0,Phase = 1, 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6toSPI1_CLK risingDelayfromSPI1_SCS activetofirst22 td(SCS_SPC)M nsSPI1_CLK (7)(8)(9) Polarity= 1,Phase = 0, 2P-1 2P-5 2P-6toSPI1_CLK falling Polarity= 1,Phase = 1, 0.5M+2P-1 0.5M+2P-5 0.5M+2P-6toSPI1_CLK falling (1) These parametersareinadditiontothegeneraltimingsforSPI mastermodes (Table5-79). (2) P = SYSCLK2 period;M = tc(SPC)M (SPImasterbitclockperiod) (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourmasterclockingmodes. (4) Inthecase where themasterSPI isreadywithnew databeforeSPI1_ENA deassertion. (5) Exceptformodes when SPIDAT1.CSHOLD isenabledand thereisadditionaldatatotransmit.Inthiscase,SPI1_SCS willremainasserted. (6) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.T2CDELAY[4:0]. (7) IfSPI1_ENA isassertedimmediatelysuch thatthetransmissionisnotdelayedby SPI1_ENA. (8) Inthecase where themasterSPI isreadywithnew databeforeSPI1_SCS assertion. (9) Thisdelaycan be increasedundersoftwarecontrolby theregisterbitfieldSPIDELAY.C2TDELAY[4:0].

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-82.Additional(1)SPI1 Master Timings,5-PinOption(2)(3) (continued) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity= 0,Phase = 0, 3P+5 3P+5 3P+6toSPI1_CLK rising Polarity= 0,Phase = 1, 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6toSPI1_CLK risingDelayfromassertionofSPI1_ENA23 td(ENA_SPC)M nslowtofirstSPI1_CLK edge.(10) Polarity= 1,Phase = 0, 3P+5 3P+5 3P+6toSPI1_CLK falling Polarity= 1,Phase = 1, 0.5M+3P+5 0.5M+3P+5 0.5M+3P+6toSPI1_CLK falling (10)IfSPI1_ENA was initiallydeassertedhighand SPI1_CLK isdelayed. Table5-83.Additional(1)SPI1 SlaveTimings,4-PinEnable Option(2)(3) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX (1) These parametersareinadditiontothegeneraltimingsforSPI slavemodes (Table5-79). (2) P = SYSCLK2 period;M = tc(SPC)M (SPImasterbitclockperiod) (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourslaveclockingmodes. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 183 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-84.Additional(1)SPI1 SlaveTimings,4-PinChip SelectOption(2)(3) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX RequireddelayfromSPI1_SCS assertedatslavetofirstSPI1_CLK edge at25 td(SCSL_SPC)S P+1.5 P+1.5 P+1.5 nsslave. Polarity= 0,Phase = 0, 0.5M+P+4 0.5M+P+5 0.5M+P+6fromSPI1_CLK falling Polarity= 0,Phase = 1, P+4 P+5 P+6fromSPI1_CLK fallingRequireddelayfromfinalSPI1_CLK edge26 td(SPC_SCSH)S nsbeforeSPI1_SCS isdeasserted. Polarity= 1,Phase = 0, 0.5M+P+4 0.5M+P+5 0.5M+P+6fromSPI1_CLK rising Polarity= 1,Phase = 1, P+4 P+5 P+6fromSPI1_CLK rising 27 tena(SCSL_SOMI)S DelayfrommasterassertingSPI1_SCS toslavedrivingSPI1_SOMI valid P+15 P+17 P+19 ns 28 tdis(SCSH_SOMI)S DelayfrommasterdeassertingSPI1_SCS toslave3-statingSPI1_SOMI P+15 P+17 P+19 ns (1) These parametersareinadditiontothegeneraltimingsforSPI slavemodes (Table5-79). (2) P = SYSCLK2 period;M = tc(SPC)M (SPImasterbitclockperiod) (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourslaveclockingmodes. Table5-85.Additional(1)SPI1 SlaveTimings,5-PinOption(2)(3) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX RequireddelayfromSPI1_SCS assertedatslavetofirst25 td(SCSL_SPC)S P+1.5 P+1.5 P+1.5 nsSPI1_CLK edge atslave. Polarity= 0,Phase = 0, 0.5M+P+4 0.5M+P+5 0.5M+P+6fromSPI1_CLK falling Polarity= 0,Phase = 1, P+4 P+5 P+6Requireddelayfromfinal fromSPI1_CLK falling 26 td(SPC_SCSH)S SPI1_CLK edge beforeSPI1_SCS ns Polarity= 1,Phase = 0,isdeasserted. 0.5M+P+4 0.5M+P+5 0.5M+P+6fromSPI1_CLK rising Polarity= 1,Phase = 1, P+4 P+5 P+6fromSPI1_CLK rising DelayfrommasterassertingSPI1_SCS toslavedriving27 tena(SCSL_SOMI)S P+15 P+17 P+19 nsSPI1_SOMI valid DelayfrommasterdeassertingSPI1_SCS toslave3-stating28 tdis(SCSH_SOMI)S P+15 P+17 P+19 nsSPI1_SOMI DelayfrommasterdeassertingSPI1_SCS toslavedriving29 tena(SCSL_ENA)S 15 17 19 nsSPI1_ENA valid (1) These parametersareinadditiontothegeneraltimingsforSPI slavemodes (Table5-79). (2) P = SYSCLK2 period;M = tc(SPC)M (SPImasterbitclockperiod) (3) Figureshows onlyPolarity= 0,Phase = 0 as an example.Tablegivesparametersforallfourslaveclockingmodes.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-85.Additional(1)SPI1 SlaveTimings,5-PinOption(2)(3) (continued) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Polarity= 0,Phase = 0, 2.5P+15 2.5P+17 2.5P+19fromSPI1_CLK falling Polarity= 0,Phase = 1, 2.5P+15 2.5P+17 2.5P+19Delayfromfinalclockreceiveedge fromSPI1_CLK rising 30 tdis(SPC_ENA)S on SPI1_CLK toslave3-statingor ns Polarity= 1,Phase = 0,drivinghighSPI1_ENA. (4) 2.5P+15 2.5P+17 2.5P+19fromSPI1_CLK rising Polarity= 1,Phase = 1, 2.5P+15 2.5P+17 2.5P+19fromSPI1_CLK falling (4) SPI1_ENA isdrivenlowafterthetransmissioncompletesiftheSPIINT0.ENABLE_HIGHZ bitisprogrammed to0.Otherwiseitistri-stated.Iftri-stated,an externalpullupresistorshould be used toprovidea validleveltothemaster.Thisoptionisusefulwhen tyingseveralSPI slavedevicestoa singlemaster. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 185 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) 4 5 5 6 MASTER MODE POLARITY = 0 PHASE = 0 MASTER MODE POLARITY = 0 PHASE = 1 MASTER MODE POLARITY = 1 PHASE = 0 MASTER MODE POLARITY = 1 PHASE = 1 OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-39.SPI Timings— Master Mode

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SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_CLK SPIx_SIMO SPIx_SOMI SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) 1110 SLA VE MODE POLARITY = 0 PHASE = 0 SLA VE MODE POLARITY = 0 PHASE = 1 SLA VE MODE POLARITY = 1 PHASE = 0 SLA VE MODE POLARITY = 1 PHASE = 1 OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-40.SPI Timings— SlaveMode Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 187 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

MASTER MODE 4 PIN WITH CHIP SELECT SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_ENA SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_SCS SPIx_CLK SPIx_SIMO SPIx_SOMI SPIx_ENA SPIx_SCS MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MO(0) MO(1) MO(n−1) MO(n) MI(0) MI(1) MI(n−1) MI(n) MASTER MODE 4 PIN WITH ENABLE MASTER MODE 5 PIN A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3−STATE (REQUIRES EXTERNAL PULLUP) DESEL (A) DESEL (A) OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-41.SPI Timings— Master Mode (4-Pinand 5-Pin)

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SPIx_CLK SPIx_SOMI SPIx_SIMO SPIx_ENA SPIx_CLK SPIx_SOMI SPIx_SIMO SPIx_SCS SPIx_CLK SPIx_SOMI SPIx_SIMO SPIx_ENA SPIx_SCS SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SO(0) SO(1) SO(n−1) SO(n) SI(0) SI(1) SI(n−1) SI(n) SLA VE MODE 4 PIN WITH ENABLE SLA VE MODE 4 PIN WITH CHIP SELECT SLA VE MODE 5 PIN DESEL (A) DESEL (A) A. DESELECTED IS PROGRAMMABLE EITHER HIGH OR 3−STATE (REQUIRES EXTERNAL PULLUP) OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-42.SPI Timings— SlaveMode (4-Pinand 5-Pin) Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 189 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

I2Cx_SCL I2Cx_SDA Control Interrupt/DMA I2CIERx Interrupt Enable Register I2CSTRx Interrupt Status Register I2CSRCx Interrupt Source Register Control I2CPFUNC Pin Function Register I2CPDIR Pin Direction Register I2CPDIN Pin Data In Register I2CPDOUT Pin Data Out Register I2CPDSET Pin Data Set Register I2CPDCLR Pin Data Clear Register Interrupt DMA Requests OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com

5.18 Inter-IntegratedCircuitSerialPorts(I2C)

5.18.1 I2C Device-SpecificInformation

Each I2C portsupports:

CompatiblewithPhilips® I2C SpecificationRevision2.1(January2000)
FastMode up to400 Kbps (nofail-safeI/Obuffers)
NoiseFiltertoRemove Noise50 ns orless
Seven-and Ten-BitDeviceAddressingModes
Master(Transmit/Receive)and Slave(Transmit/Receive)Functionality
Events:DMA, Interrupt,orPolling
General-PurposeI/OCapabilityifnotused as I2C Figure5-43isblockdiagramofthedeviceI2C Module. Figure5-43.I2C Module Block Diagram

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5.18.2 I2C PeripheralRegistersDescription(s)

Table5-86isthelistoftheI2C registers. Table5-86.Inter-IntegratedCircuit(I2C)Registers I2C0 I2C1 ACRONYM REGISTER DESCRIPTIONBYTE ADDRESS BYTE ADDRESS 0x01C2 2000 0x01E2 8000 ICOAR I2C Own AddressRegister 0x01C2 2004 0x01E2 8004 ICIMR I2C InterruptMask Register 0x01C2 2008 0x01E2 8008 ICSTR I2C InterruptStatusRegister 0x01C2 200C 0x01E2 800C ICCLKL I2C ClockLow-Time DividerRegister 0x01C2 2010 0x01E2 8010 ICCLKH I2C ClockHigh-TimeDividerRegister 0x01C2 2014 0x01E2 8014 ICCNT I2C Data Count Register 0x01C2 2018 0x01E2 8018 ICDRR I2C Data ReceiveRegister 0x01C2 201C 0x01E2 801C ICSAR I2C SlaveAddressRegister 0x01C2 2020 0x01E2 8020 ICDXR I2C Data TransmitRegister 0x01C2 2024 0x01E2 8024 ICMDR I2C Mode Register 0x01C2 2028 0x01E2 8028 ICIVR I2C InterruptVectorRegister 0x01C2 202C 0x01E2 802C ICEMDR I2C ExtendedMode Register 0x01C2 2030 0x01E2 8030 ICPSC I2C PrescalerRegister 0x01C2 2034 0x01E2 8034 REVID1 I2C RevisionIdentificationRegister1 0x01C2 2038 0x01E2 8038 REVID2 I2C RevisionIdentificationRegister2 0x01C2 2048 0x01E2 8048 ICPFUNC I2C PinFunctionRegister 0x01C2 204C 0x01E2 804C ICPDIR I2C PinDirectionRegister 0x01C2 2050 0x01E2 8050 ICPDIN I2C PinData InRegister 0x01C2 2054 0x01E2 8054 ICPDOUT I2C PinData Out Register 0x01C2 2058 0x01E2 8058 ICPDSET I2C PinData SetRegister 0x01C2 205C 0x01E2 805C ICPDCLR I2C PinData ClearRegister Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 191 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.18.3 I2C ElectricalData/Timing

5.18.3.1Inter-IntegratedCircuit(I2C)Timing Table5-87and Table5-88assume testingoverrecommended operatingconditions(seeFigure5-44and Figure5-45). Table5-87.Timing Requirements forI2C Input(1) NO. PARAMETER Standard Mode FastMode UNIT MIN MAX MIN MAX 1 tc(SCL) Cycletime,I2Cx_SCL 10 2.5 μs 2 tsu(SCLH-SDAL) Setuptime,I2Cx_SCL highbeforeI2Cx_SDA low 4.7 0.6 μs 3 th(SCLL-SDAL) Holdtime,I2Cx_SCL lowafterI2Cx_SDA low 4 0.6 μs 4 tw(SCLL) Pulseduration,I2Cx_SCL low 4.7 1.3 μs 5 tw(SCLH) Pulseduration,I2Cx_SCL high 4 0.6 μs 6 tsu(SDA-SCLH) Setuptime,I2Cx_SDA beforeI2Cx_SCL high 250 100 ns 7 th(SDA-SCLL) Holdtime,I2Cx_SDA afterI2Cx_SCL low 0 0 0.9 μs 8 tw(SDAH) Pulseduration,I2Cx_SDA high 4.7 1.3 μs 9 tr(SDA) Risetime,I2Cx_SDA 1000 20 + 0.1Cb 300 ns 10 tr(SCL) Risetime,I2Cx_SCL 1000 20 + 0.1Cb 300 ns 11 tf(SDA) Falltime,I2Cx_SDA 300 20 + 0.1Cb 300 ns 12 tf(SCL) Falltime,I2Cx_SCL 300 20 + 0.1Cb 300 ns 13 tsu(SCLH-SDAH) Setuptime,I2Cx_SCL highbeforeI2Cx_SDA high 4 0.6 μs 14 tw(SP) Pulseduration,spike(mustbe suppressed) N/A 0 50 ns

15 C b Capacitiveloadforeach bus line 400 400 pF

(1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Table5-88.SwitchingCharacteristicsforI2C(1)(2) NO. PARAMETER Standard Mode FastMode UNIT MIN MAX MIN MAX 16 tc(SCL) Cycletime,I2Cx_SCL 10 2.5 μs 17 tsu(SCLH-SDAL) Setuptime,I2Cx_SCL highbeforeI2Cx_SDA low 4.7 0.6 μs 18 th(SDAL-SCLL) Holdtime,I2Cx_SCL lowafterI2Cx_SDA low 4 0.6 μs 19 tw(SCLL) Pulseduration,I2Cx_SCL low 4.7 1.3 μs 20 tw(SCLH) Pulseduration,I2Cx_SCL high 4 0.6 μs 21 tsu(SDAV-SCLH) Setuptime,I2Cx_SDA validbeforeI2Cx_SCL high 250 100 ns 22 th(SCLL-SDAV) Holdtime,I2Cx_SDA validafterI2Cx_SCL low 0 0 0.9 μs 23 tw(SDAH) Pulseduration,I2Cx_SDA high 4.7 1.3 μs 28 tsu(SCLH-SDAH) Setuptime,I2Cx_SCL highbeforeI2Cx_SDA high 4 0.6 μs (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) I2C must be configuredcorrectlytomeet thetimingsinTable5-88.

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I2Cx_SDA I2Cx_SCL 26 24 6 14 Stop Start Repeated Start Stop I2Cx_SDA I2Cx_SCL 11 9 OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-44.I2C Receive Timings Figure5-45.I2C TransmitTimings Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 193 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.19 UniversalAsynchronous Receiver/Transmitter(UART)

Each UART has thefollowingfeatures:

16-bytestoragespace forboththetransmitterand receiverFIFOs
1,4,8,or14 byteselectablereceiverFIFO triggerlevelforautoflowcontroland DMA
DMA signalingcapabilityforbothreceivedand transmitteddata
Programmable auto-rtsand auto-ctsforautoflowcontrol
Programmable Baud Rate up to12 MBaud
Programmable OversamplingOptionsofx13 and x16
Frequencypre-scalevaluesfrom1 to65,535togenerateappropriatebaud rates
Prioritizedinterrupts
Programmable serialdataformats – 5,6,7,or8-bitcharacters – Even,odd,orno paritybitgenerationand detection – 1,1.5,or2 stopbitgeneration
Falsestartbitdetection
Linebreakgenerationand detection
Internaldiagnosticcapabilities – Loopback controlsforcommunicationslinkfaultisolation – Break,parity,overrun,and framingerrorsimulation
Modem controlfunctions(CTS,RTS) The UART registersarelistedinSection5.19.1

5.19.1 UART PeripheralRegistersDescription(s)

Table5-89isthelistofUART registers. Table5-89.UART Registers UART0 UART1 UART2 ACRONYM REGISTER DESCRIPTIONBYTE ADDRESS BYTE ADDRESS BYTE ADDRESS 0x01C4 2000 0x01D0 C000 0x01D0 D000 RBR ReceiverBufferRegister(readonly) 0x01C4 2000 0x01D0 C000 0x01D0 D000 THR TransmitterHoldingRegister(writeonly) 0x01C4 2004 0x01D0 C004 0x01D0 D004 IER InterruptEnableRegister 0x01C4 2008 0x01D0 C008 0x01D0 D008 IIR InterruptIdentificationRegister(readonly) 0x01C4 2008 0x01D0 C008 0x01D0 D008 FCR FIFO ControlRegister(writeonly) 0x01C4 200C 0x01D0 C00C 0x01D0 D00C LCR LineControlRegister 0x01C4 2010 0x01D0 C010 0x01D0 D010 MCR Modem ControlRegister 0x01C4 2014 0x01D0 C014 0x01D0 D014 LSR LineStatusRegister 0x01C4 2018 0x01D0 C018 0x01D0 D018 MSR Modem StatusRegister 0x01C4 201C 0x01D0 C01C 0x01D0 D01C SCR ScratchpadRegister 0x01C4 2020 0x01D0 C020 0x01D0 D020 DLL DivisorLSB Latch 0x01C4 2024 0x01D0 C024 0x01D0 D024 DLH DivisorMSB Latch 0x01C4 2028 0x01D0 C028 0x01D0 D028 REVID1 RevisionIdentificationRegister1 0x01C4 2030 0x01D0 C030 0x01D0 D030 PWREMU_MGMT Power and EmulationManagement Register 0x01C4 2034 0x01D0 C034 0x01D0 D034 MDR Mode DefinitionRegister

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UART_TXDn UART_RXDn Data Bits Bit Start OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013

5.19.2 UART ElectricalData/Timing

Table5-90.Timing Requirements forUART Receive(1)(2)(seeFigure5-46) NO. PARAMETER UNIT MIN MAX 4 tw(URXDB) Pulseduration,receivedatabit(RXDn) 0.96U 1.05U ns 5 tw(URXSB) Pulseduration,receivestartbit 0.96U 1.05U ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) U = UART baud time= 1/programmedbaud rate. Table5-91.SwitchingCharacteristicsOver Recommended OperatingConditionsforUARTx Transmit(1)(2) (seeFigure5-46) NO. PARAMETER UNIT MIN MAX 1 f(baud) Maximum programmablebaud rate D/E (3)(4) MBaud (5) 2 tw(UTXDB) Pulseduration,transmitdatabit(TXDn) U -2 U + 2 ns 3 tw(UTXSB) Pulseduration,transmitstartbit U -2 U + 2 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) U = UART baud time= 1/programmedbaud rate. (3) D = UART inputclockinMHz. ForUART0, theUART inputclockisSYSCLK2. ForUART1 orUART2, theUART inputclockisASYNC3 (eitherPLL0_SYCLK2 orPLL1_SYSCLK2). (4) E = UART divisorx UART samplingrate.The UART divisorissetthroughtheUART divisorlatchregisters(DLL and DLH).The UART samplingrateissetthroughtheover-samplingmode selectbit(OSM_SEL) oftheUART mode definitionregister(MDR). (5) Baud rateisnotindicativeofdatarate.Actualdataratewillbe limitedby systemfactorssuch as EDMA loading,EMIF/DDR loading, systemfrequency,etc. Figure5-46.UART Transmit/ReceiveTiming Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 195 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com 5.20 UniversalSerialBus OTG Controller(USB0) [USB2.0 OTG] The USB2.0 peripheralsupportsthefollowingfeatures:

USB 2.0peripheralatspeeds highspeed (HS:480 Mb/s)and fullspeed (FS:12 Mb/s)
USB 2.0hostatspeeds HS, FS, and lowspeed (LS:1.5Mb/s)
Alltransfermodes (control,bulk,interrupt,and isochronous)
4 Transmit(TX)and 4 Receive(RX)endpointsinadditiontoendpoint0
FIFO RAM – 4K endpoint – Programmable size
IntegratedUSB 2.0HighSpeed PHY
Connectstoa standardCharge Pump forVBUS 5 V generation
RNDIS mode foracceleratingRNDIS typeprotocolsusingshortpacketterminationoverUSB ImportantNotice:The USB0 controllermodule clock(PLL0_SYSCLK2) must be greaterthan30 MHz for properoperationoftheUSB controller.A clockrateof60 MHz or greaterisrecommended toavoiddata throughputreduction. Table5-92isthelistofUSB OTG registers. Table5-92.UniversalSerialBus OTG (USB0) Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E0 0000 REVID RevisionRegister 0x01E0 0004 CTRLR ControlRegister 0x01E0 0008 STATR StatusRegister 0x01E0 000C EMUR EmulationRegister 0x01E0 0010 MODE Mode Register 0x01E0 0014 AUTOREQ AutorequestRegister 0x01E0 0018 SRPFIXTIME SRP FixTime Register 0x01E0 001C TEARDOWN Teardown Register 0x01E0 0020 INTSRCR USB InterruptSourceRegister 0x01E0 0024 INTSETR USB InterruptSourceSetRegister 0x01E0 0028 INTCLRR USB InterruptSourceClearRegister 0x01E0 002C INTMSKR USB InterruptMask Register 0x01E0 0030 INTMSKSETR USB InterruptMask SetRegister 0x01E0 0034 INTMSKCLRR USB InterruptMask ClearRegister 0x01E0 0038 INTMASKEDR USB InterruptSourceMasked Register 0x01E0 003C EOIR USB End ofInterruptRegister 0x01E0 0040 - Reserved 0x01E0 0050 GENRNDISSZ1 GenericRNDIS SizeEP1 0x01E0 0054 GENRNDISSZ2 GenericRNDIS SizeEP2 0x01E0 0058 GENRNDISSZ3 GenericRNDIS SizeEP3 0x01E0 005C GENRNDISSZ4 GenericRNDIS SizeEP4 0x01E0 0400 FADDR FunctionAddressRegister 0x01E0 0401 POWER Power Management Register 0x01E0 0402 INTRTX InterruptRegisterforEndpoint0 plusTransmitEndpoints1 to4 0x01E0 0404 INTRRX InterruptRegisterforReceiveEndpoints1 to4 0x01E0 0406 INTRTXE InterruptenableregisterforINTRTX 0x01E0 0408 INTRRXE InterruptEnableRegisterforINTRRX 0x01E0 040A INTRUSB InterruptRegisterforCommon USB Interrupts 0x01E0 040B INTRUSBE InterruptEnableRegisterforINTRUSB

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-92.UniversalSerialBus OTG (USB0) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E0 040C FRAME Frame Number Register 0x01E0 040E INDEX IndexRegisterforSelectingtheEndpointStatusand ControlRegisters 0x01E0 040F TESTMODE RegistertoEnabletheUSB 2.0TestModes Indexed Registers These registersoperateon theendpointselectedby theINDEX register 0x01E0 0410 TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint (IndexregistersettoselectEndpoints1-4only) 0x01E0 0412 PERI_CSR0 ControlStatusRegisterforEndpoint0 inPeripheralMode. (IndexregistersettoselectEndpoint0) HOST_CSR0 ControlStatusRegisterforEndpoint0 inHostMode. (IndexregistersettoselectEndpoint0) PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint. (IndexregistersettoselectEndpoints1-4) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint. (IndexregistersettoselectEndpoints1-4) 0x01E0 0414 RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint (IndexregistersettoselectEndpoints1-4only) 0x01E0 0416 PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint. (IndexregistersettoselectEndpoints1-4) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint. (IndexregistersettoselectEndpoints1-4) 0x01E0 0418 COUNT0 Number ofReceivedBytesinEndpoint0 FIFO. (IndexregistersettoselectEndpoint0) RXCOUNT Number ofBytesinHostReceiveEndpointFIFO. (IndexregistersettoselectEndpoints1-4) 0x01E0 041A HOST_TYPE0 Definesthespeed ofEndpoint0 HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostTransmitendpoint.(IndexregistersettoselectEndpoints1-4only) 0x01E0 041B HOST_NAKLIMIT0 SetstheNAK responsetimeouton Endpoint0. (IndexregistersettoselectEndpoint0) HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTransmitendpoint.(Indexregistersetto selectEndpoints1-4only) 0x01E0 041C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostReceiveendpoint.(IndexregistersettoselectEndpoints1-4only) 0x01E0 041D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostReceiveendpoint.(Indexregistersettoselect Endpoints1-4only) 0x01E0 041F CONFIGDATA Returnsdetailsofcoreconfiguration.(IndexregistersettoselectEndpoint0) FIFO 0x01E0 0420 FIFO0 Transmitand ReceiveFIFO RegisterforEndpoint0 0x01E0 0424 FIFO1 Transmitand ReceiveFIFO RegisterforEndpoint1 0x01E0 0428 FIFO2 Transmitand ReceiveFIFO RegisterforEndpoint2 0x01E0 042C FIFO3 Transmitand ReceiveFIFO RegisterforEndpoint3 0x01E0 0430 FIFO4 Transmitand ReceiveFIFO RegisterforEndpoint4 OTG Device Control 0x01E0 0460 DEVCTL DeviceControlRegister Dynamic FIFO Control 0x01E0 0462 TXFIFOSZ TransmitEndpointFIFO Size (IndexregistersettoselectEndpoints1-4only) 0x01E0 0463 RXFIFOSZ ReceiveEndpointFIFO Size (IndexregistersettoselectEndpoints1-4only) 0x01E0 0464 TXFIFOADDR TransmitEndpointFIFO Address (IndexregistersettoselectEndpoints1-4only) Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 197 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-92.UniversalSerialBus OTG (USB0) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E0 0466 RXFIFOADDR ReceiveEndpointFIFO Address (IndexregistersettoselectEndpoints1-4only) 0x01E0 046C HWVERS Hardware VersionRegister TargetEndpoint 0 ControlRegisters,ValidOnly inHost Mode 0x01E0 0480 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated TransmitEndpoint. 0x01E0 0482 TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmit Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 0483 TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 0484 RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated ReceiveEndpoint. 0x01E0 0486 RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceive Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 0487 RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. TargetEndpoint 1 ControlRegisters,ValidOnly inHost Mode 0x01E0 0488 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated TransmitEndpoint. 0x01E0 048A TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmit Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 048B TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 048C RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated ReceiveEndpoint. 0x01E0 048E RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceive Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 048F RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. TargetEndpoint 2 ControlRegisters,ValidOnly inHost Mode 0x01E0 0490 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated TransmitEndpoint. 0x01E0 0492 TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmit Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 0493 TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 0494 RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated ReceiveEndpoint. 0x01E0 0496 RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceive Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 0497 RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. TargetEndpoint 3 ControlRegisters,ValidOnly inHost Mode 0x01E0 0498 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated TransmitEndpoint.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-92.UniversalSerialBus OTG (USB0) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E0 049A TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmit Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 049B TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 049C RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated ReceiveEndpoint. 0x01E0 049E RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceive Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 049F RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. TargetEndpoint 4 ControlRegisters,ValidOnly inHost Mode 0x01E0 04A0 TXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated TransmitEndpoint. 0x01E0 04A2 TXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedTransmit Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 04A3 TXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedTransmitEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 04A4 RXFUNCADDR Addressofthetargetfunctionthathas tobe accessedthroughtheassociated ReceiveEndpoint. 0x01E0 04A6 RXHUBADDR Addressofthehub thathas tobe accessedthroughtheassociatedReceive Endpoint.Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. 0x01E0 04A7 RXHUBPORT Portofthehub thathas tobe accessedthroughtheassociatedReceiveEndpoint. Thisisused onlywhen fullspeed orlowspeed deviceisconnectedviaa USB2.0 high-speedhub. Controland StatusRegisterforEndpoint 0 0x01E0 0502 PERI_CSR0 ControlStatusRegisterforEndpoint0 inPeripheralMode HOST_CSR0 ControlStatusRegisterforEndpoint0 inHostMode 0x01E0 0508 COUNT0 Number ofReceivedBytesinEndpoint0 FIFO 0x01E0 050A HOST_TYPE0 DefinestheSpeed ofEndpoint0 0x01E0 050B HOST_NAKLIMIT0 SetstheNAK Response Timeouton Endpoint0 0x01E0 050F CONFIGDATA Returnsdetailsofcoreconfiguration. Controland StatusRegisterforEndpoint 1 0x01E0 0510 TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint 0x01E0 0512 PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint(peripheralmode) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint(hostmode) 0x01E0 0514 RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint 0x01E0 0516 PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint(peripheralmode) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint(hostmode) 0x01E0 0518 RXCOUNT Number ofBytesinHostReceiveendpointFIFO 0x01E0 051A HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostTransmitendpoint. 0x01E0 051B HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTransmitendpoint. 0x01E0 051C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostReceiveendpoint. 0x01E0 051D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostReceiveendpoint. Controland StatusRegisterforEndpoint 2 Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 199 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-92.UniversalSerialBus OTG (USB0) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E0 0520 TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint 0x01E0 0522 PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint(peripheralmode) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint(hostmode) 0x01E0 0524 RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint 0x01E0 0526 PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint(peripheralmode) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint(hostmode) 0x01E0 0528 RXCOUNT Number ofBytesinHostReceiveendpointFIFO 0x01E0 052A HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostTransmitendpoint. 0x01E0 052B HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTransmitendpoint. 0x01E0 052C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostReceiveendpoint. 0x01E0 052D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostReceiveendpoint. Controland StatusRegisterforEndpoint 3 0x01E0 0530 TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint 0x01E0 0532 PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint(peripheralmode) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint(hostmode) 0x01E0 0534 RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint 0x01E0 0536 PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint(peripheralmode) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint(hostmode) 0x01E0 0538 RXCOUNT Number ofBytesinHostReceiveendpointFIFO 0x01E0 053A HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostTransmitendpoint. 0x01E0 053B HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTransmitendpoint. 0x01E0 053C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostReceiveendpoint. 0x01E0 053D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostReceiveendpoint. Controland StatusRegisterforEndpoint 4 0x01E0 0540 TXMAXP Maximum PacketSizeforPeripheral/HostTransmitEndpoint 0x01E0 0542 PERI_TXCSR ControlStatusRegisterforPeripheralTransmitEndpoint(peripheralmode) HOST_TXCSR ControlStatusRegisterforHostTransmitEndpoint(hostmode) 0x01E0 0544 RXMAXP Maximum PacketSizeforPeripheral/HostReceiveEndpoint 0x01E0 0546 PERI_RXCSR ControlStatusRegisterforPeripheralReceiveEndpoint(peripheralmode) HOST_RXCSR ControlStatusRegisterforHostReceiveEndpoint(hostmode) 0x01E0 0548 RXCOUNT Number ofBytesinHostReceiveendpointFIFO 0x01E0 054A HOST_TXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostTransmitendpoint. 0x01E0 054B HOST_TXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostTransmitendpoint. 0x01E0 054C HOST_RXTYPE Setstheoperatingspeed,transactionprotocoland peripheralendpointnumber for thehostReceiveendpoint. 0x01E0 054D HOST_RXINTERVAL SetsthepollingintervalforInterrupt/ISOCtransactionsortheNAK response timeouton BulktransactionsforhostReceiveendpoint. DMA Registers 0x01E0 1000 DMAREVID DMA RevisionRegister 0x01E0 1004 TDFDQ DMA Teardown FreeDescriptorQueue ControlRegister 0x01E0 1008 DMAEMU DMA EmulationControlRegister

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-92.UniversalSerialBus OTG (USB0) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E0 1800 TXGCR[0] TransmitChannel0 GlobalConfigurationRegister 0x01E0 1808 RXGCR[0] ReceiveChannel0 GlobalConfigurationRegister 0x01E0 180C RXHPCRA[0] ReceiveChannel0 HostPacketConfigurationRegisterA 0x01E0 1810 RXHPCRB[0] ReceiveChannel0 HostPacketConfigurationRegisterB 0x01E0 1820 TXGCR[1] TransmitChannel1 GlobalConfigurationRegister 0x01E0 1828 RXGCR[1] ReceiveChannel1 GlobalConfigurationRegister 0x01E0 182C RXHPCRA[1] ReceiveChannel1 HostPacketConfigurationRegisterA 0x01E0 1830 RXHPCRB[1] ReceiveChannel1 HostPacketConfigurationRegisterB 0x01E0 1840 TXGCR[2] TransmitChannel2 GlobalConfigurationRegister 0x01E0 1848 RXGCR[2] ReceiveChannel2 GlobalConfigurationRegister 0x01E0 184C RXHPCRA[2] ReceiveChannel2 HostPacketConfigurationRegisterA 0x01E0 1850 RXHPCRB[2] ReceiveChannel2 HostPacketConfigurationRegisterB 0x01E0 1860 TXGCR[3] TransmitChannel3 GlobalConfigurationRegister 0x01E0 1868 RXGCR[3] ReceiveChannel3 GlobalConfigurationRegister 0x01E0 186C RXHPCRA[3] ReceiveChannel3 HostPacketConfigurationRegisterA 0x01E0 1870 RXHPCRB[3] ReceiveChannel3 HostPacketConfigurationRegisterB 0x01E0 2000 DMA_SCHED_CTRL DMA SchedulerControlRegister 0x01E0 2800 WORD[0] DMA SchedulerTableWord 0 0x01E0 2804 WORD[1] DMA SchedulerTableWord 1 0x01E0 28FC WORD[63] DMA SchedulerTableWord 63 Queue Manager Registers 0x01E0 4000 QMGRREVID Queue Manager RevisionRegister 0x01E0 4008 DIVERSION Queue DiversionRegister 0x01E0 4020 FDBSC0 FreeDescriptor/BufferStarvationCount Register0 0x01E0 4024 FDBSC1 FreeDescriptor/BufferStarvationCount Register1 0x01E0 4028 FDBSC2 FreeDescriptor/BufferStarvationCount Register2 0x01E0 402C FDBSC3 FreeDescriptor/BufferStarvationCount Register3 0x01E0 4080 LRAM0BASE LinkingRAM Region0 Base AddressRegister 0x01E0 4084 LRAM0SIZE LinkingRAM Region0 SizeRegister 0x01E0 4088 LRAM1BASE LinkingRAM Region1 Base AddressRegister 0x01E0 4090 PEND0 Queue PendingRegister0 0x01E0 4094 PEND1 Queue PendingRegister1 0x01E0 5000 QMEMRBASE[0] Memory Region0 Base AddressRegister 0x01E0 5004 QMEMRCTRL[0] Memory Region0 ControlRegister 0x01E0 5010 QMEMRBASE[1] Memory Region1 Base AddressRegister 0x01E0 5014 QMEMRCTRL[1] Memory Region1 ControlRegister 0x01E0 50F0 QMEMRBASE[15] Memory Region15 Base AddressRegister 0x01E0 50F4 QMEMRCTRL[15] Memory Region15 ControlRegister 0x01E0 600C CTRLD[0] Queue Manager Queue 0 ControlRegisterD 0x01E0 601C CTRLD[1] Queue Manager Queue 1 ControlRegisterD 0x01E0 63FC CTRLD[63] Queue Manager Queue 63 StatusRegisterD 0x01E0 6800 QSTATA[0] Queue Manager Queue 0 StatusRegisterA 0x01E0 6804 QSTATB[0] Queue Manager Queue 0 StatusRegisterB 0x01E0 6808 QSTATC[0] Queue Manager Queue 0 StatusRegisterC Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 201 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

90% VOH 10% VOL USB_DM USB_DP tper − tjr OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-92.UniversalSerialBus OTG (USB0) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E0 6810 QSTATA[1] Queue Manager Queue 1 StatusRegisterA 0x01E0 6814 QSTATB[1] Queue Manager Queue 1 StatusRegisterB 0x01E0 6818 QSTATC[1] Queue Manager Queue 1 StatusRegisterC 0x01E0 6BF0 QSTATA[63] Queue Manager Queue 63 StatusRegisterA 0x01E0 6BF4 QSTATB[63] Queue Manager Queue 63 StatusRegisterB 0x01E0 6BF8 QSTATC[63] Queue Manager Queue 63 StatusRegisterC 5.20.1 USB0 [USB2.0]ElectricalData/Timing The USB PHY PLL can supportinputclockofthefollowingfrequencies:12.0MHz, 13.0MHz, 19.2MHz, ppm (maximum). Table5-93.SwitchingCharacteristicsOver Recommended OperatingConditionsforUSB0 [USB2.0](see Figure5-47)(1) LOW SPEED FULL SPEED HIGH SPEEDNO. PARAMETER UNIT1.5Mbps 12 Mbps 480 Mbps MIN MAX MIN MAX MIN MAX 1 tr(D) Risetime,USB_DP and USB_DM signals(2) 75 300 4 20 0.5 ns 2 tf(D) Falltime,USB_DP and USB_DM signals(2) 75 300 4 20 0.5 ns 3 trfM Rise/Falltime,matching(3) 80 120 90 111 – – % 4 VCRS Outputsignalcross-overvoltage(2) 1.3 2 1.3 2 – – V 5 tjr(source)NT Source(Host)Driverjitter,nexttransition 2 2 (4)ns tjr(FUNC)NT FunctionDriverjitter,nexttransition 25 2 (4) ns 6 tjr(source)PT Source(Host)Driverjitter,pairedtransition(5) 1 1 (4) ns tjr(FUNC)PT FunctionDriverjitter,pairedtransition 10 1 (4) ns 7 tw(EOPT) Pulseduration,EOP transmitter 1250 1500 160 175 – – ns 8 tw(EOPR) Pulseduration,EOP receiver 670 82 – ns 9 t(DRATE) Data Rate 1.5 12 480 Mb/s 10 ZDRV DriverOutputResistance – – 40.5 49.5 40.5 49.5 Ω

11 ZINP ReceiverInputImpedance 100k 100k - - Ω

(1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) Low Speed:C L = 200 pF,FullSpeed:C L = 50 pF,HighSpeed:C L = 50 pF (3) tRFM = (tr/tf)x 100.[ExcludingthefirsttransactionfromtheIdlestate.] (4) Formore detailedinformation,see theUniversalSerialBus SpecificationRevision2.0,Chapter7.Electrical. (5) tjr= tpx(1)-tpx(0) Figure5-47.USB2.0 IntegratedTransceiverInterfaceTiming

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 5.21 UniversalSerialBus Host Controller(USB1) [USB1.1 OHCI] AlltheUSB interfacesforthisdevicearecompliantwithUniversalSerialBus Specifications,Revision1.1. Table5-94isthelistofUSB HostControllerregisters. Table5-94.USB Host ControllerRegisters USB1 ACRONYM REGISTER DESCRIPTIONBYTE ADDRESS 0x01E2 5000 HCREVISION OHCI RevisionNumber Register 0x01E2 5004 HCCONTROL HC OperatingMode Register 0x01E2 5008 HCCOMMANDSTATUS HC Command and StatusRegister 0x01E2 500C HCINTERRUPTSTATUS HC Interruptand StatusRegister 0x01E2 5010 HCINTERRUPTENABLE HC InterruptEnableRegister 0x01E2 5014 HCINTERRUPTDISABLE HC InterruptDisableRegister 0x01E2 5018 HCHCCA HC HCAA AddressRegister(1) 0x01E2 501C HCPERIODCURRENTED HC CurrentPeriodicRegister(1) 0x01E2 5020 HCCONTROLHEADED HC Head ControlRegister(1) 0x01E2 5024 HCCONTROLCURRENTED HC CurrentControlRegister(1) 0x01E2 5028 HCBULKHEADED HC Head BulkRegister(1) 0x01E2 502C HCBULKCURRENTED HC CurrentBulkRegister(1) 0x01E2 5030 HCDONEHEAD HC Head Done Register(1) 0x01E2 5034 HCFMINTERVAL HC Frame IntervalRegister 0x01E2 5038 HCFMREMAINING HC Frame RemainingRegister 0x01E2 503C HCFMNUMBER HC Frame Number Register 0x01E2 5040 HCPERIODICSTART HC PeriodicStartRegister 0x01E2 5044 HCLSTHRESHOLD HC Low-Speed ThresholdRegister 0x01E2 5048 HCRHDESCRIPTORA HC Root Hub A Register 0x01E2 504C HCRHDESCRIPTORB HC Root Hub B Register 0x01E2 5050 HCRHSTATUS HC Root Hub StatusRegister 0x01E2 5054 HCRHPORTSTATUS1 HC Port1 Statusand ControlRegister(2) 0x01E2 5058 HCRHPORTSTATUS2 HC Port2 Statusand ControlRegister(3) (1) Restrictionsapplytothephysicaladdressesused intheseregisters. (2) ConnectedtotheintegratedUSB1.1 phy pins(USB1_DM, USB1_DP). (3) Althoughthecontrollerimplementstwo ports,thesecond portcannotbe used. Table5-95.SwitchingCharacteristicsOver Recommended OperatingConditionsforUSB1 USB1.1 NO. PARAMETER LOW SPEED FULL SPEED UNIT MIN MAX MAX MAX U1 tr Risetime,USB.DP and USB.DM signals(2) 75(2) 300(2) 4(2) 20(2) ns U2 tf Falltime,USB.DP and USB.DM signals(2) 75(2) 300(2) 4(2) 20(2) ns U3 tRFM Rise/Falltimematching(3) 80(3) 120(3) 90(3) 110(3) % U4 VCRS Outputsignalcross-overvoltage(2) 1.3(2) 2(2) 1.3(2) 2(2) V U5 tj Differentialpropagationjitter(4) -25(4) 25(4) -2(4) 2(4) ns U6 fop Operatingfrequency(5) 1.5 12 MHz (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) Low Speed:C L = 200 pF.HighSpeed:C L = 50pF (3) tRFM =(tr/tf)x 100 (4) tjr= tpx(1)-tpx(0) (5) fop = 1/tper Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 203 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.22 EthernetMedia Access Controller(EMAC)

The EthernetMedia Access Controller(EMAC) providesan efficientinterfacebetween deviceand the network.The EMAC supportsboth10Base-T and 100Base-TX,or10 Mbits/second(Mbps)and 100 Mbps ineitherhalf-orfull-duplexmode, withhardwareflowcontroland qualityofservice(QOS) support. The EMAC controlstheflowofpacketdatafromthedevicetothePHY. The MDIO module controlsPHY configurationand statusmonitoring. Both the EMAC and the MDIO modules interfaceto the devicethrougha custom interfacethatallows efficientdata transmissionand reception.This custom interfaceis referredto as the EMAC control module,and isconsideredintegralto the EMAC/MDIO peripheral.The controlmodule isalsoused to multiplexand controlinterrupts.

5.22.1 EMAC PeripheralRegisterDescription(s)

Table5-96.EthernetMedia Access Controller(EMAC) Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 3000 TXREV TransmitRevisionRegister 0x01E2 3004 TXCONTROL TransmitControlRegister 0x01E2 3008 TXTEARDOWN TransmitTeardown Register 0x01E2 3010 RXREV ReceiveRevisionRegister 0x01E2 3014 RXCONTROL ReceiveControlRegister 0x01E2 3018 RXTEARDOWN ReceiveTeardown Register 0x01E2 3080 TXINTSTATRAW TransmitInterruptStatus(Unmasked) Register 0x01E2 3084 TXINTSTATMASKED TransmitInterruptStatus(Masked)Register 0x01E2 3088 TXINTMASKSET TransmitInterruptMask SetRegister 0x01E2 308C TXINTMASKCLEAR TransmitInterruptClearRegister 0x01E2 3090 MACINVECTOR MAC InputVectorRegister 0x01E2 3094 MACEOIVECTOR MAC End Of InterruptVectorRegister 0x01E2 30A0 RXINTSTATRAW ReceiveInterruptStatus(Unmasked) Register 0x01E2 30A4 RXINTSTATMASKED ReceiveInterruptStatus(Masked)Register 0x01E2 30A8 RXINTMASKSET ReceiveInterruptMask SetRegister 0x01E2 30AC RXINTMASKCLEAR ReceiveInterruptMask ClearRegister 0x01E2 30B0 MACINTSTATRAW MAC InterruptStatus(Unmasked) Register 0x01E2 30B4 MACINTSTATMASKED MAC InterruptStatus(Masked)Register 0x01E2 30B8 MACINTMASKSET MAC InterruptMask SetRegister 0x01E2 30BC MACINTMASKCLEAR MAC InterruptMask ClearRegister 0x01E2 3100 RXMBPENABLE ReceiveMulticast/Broadcast/PromiscuousChannelEnableRegister 0x01E2 3104 RXUNICASTSET ReceiveUnicastEnableSetRegister 0x01E2 3108 RXUNICASTCLEAR ReceiveUnicastClearRegister 0x01E2 310C RXMAXLEN ReceiveMaximum LengthRegister 0x01E2 3110 RXBUFFEROFFSET ReceiveBufferOffsetRegister 0x01E2 3114 RXFILTERLOWTHRESH ReceiveFilterLow PriorityFrame ThresholdRegister 0x01E2 3120 RX0FLOWTHRESH ReceiveChannel0 Flow ControlThresholdRegister 0x01E2 3124 RX1FLOWTHRESH ReceiveChannel1 Flow ControlThresholdRegister 0x01E2 3128 RX2FLOWTHRESH ReceiveChannel2 Flow ControlThresholdRegister 0x01E2 312C RX3FLOWTHRESH ReceiveChannel3 Flow ControlThresholdRegister 0x01E2 3130 RX4FLOWTHRESH ReceiveChannel4 Flow ControlThresholdRegister 0x01E2 3134 RX5FLOWTHRESH ReceiveChannel5 Flow ControlThresholdRegister 0x01E2 3138 RX6FLOWTHRESH ReceiveChannel6 Flow ControlThresholdRegister 0x01E2 313C RX7FLOWTHRESH ReceiveChannel7 Flow ControlThresholdRegister

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-96.EthernetMedia Access Controller(EMAC) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 3140 RX0FREEBUFFER ReceiveChannel0 FreeBufferCount Register 0x01E2 3144 RX1FREEBUFFER ReceiveChannel1 FreeBufferCount Register 0x01E2 3148 RX2FREEBUFFER ReceiveChannel2 FreeBufferCount Register 0x01E2 314C RX3FREEBUFFER ReceiveChannel3 FreeBufferCount Register 0x01E2 3150 RX4FREEBUFFER ReceiveChannel4 FreeBufferCount Register 0x01E2 3154 RX5FREEBUFFER ReceiveChannel5 FreeBufferCount Register 0x01E2 3158 RX6FREEBUFFER ReceiveChannel6 FreeBufferCount Register 0x01E2 315C RX7FREEBUFFER ReceiveChannel7 FreeBufferCount Register 0x01E2 3160 MACCONTROL MAC ControlRegister 0x01E2 3164 MACSTATUS MAC StatusRegister 0x01E2 3168 EMCONTROL EmulationControlRegister 0x01E2 316C FIFOCONTROL FIFO ControlRegister 0x01E2 3170 MACCONFIG MAC ConfigurationRegister 0x01E2 3174 SOFTRESET SoftResetRegister 0x01E2 31D0 MACSRCADDRLO MAC SourceAddressLow BytesRegister 0x01E2 31D4 MACSRCADDRHI MAC SourceAddressHighBytesRegister 0x01E2 31D8 MACHASH1 MAC Hash AddressRegister1 0x01E2 31DC MACHASH2 MAC Hash AddressRegister2 0x01E2 31E0 BOFFTEST Back OffTestRegister 0x01E2 31E4 TPACETEST TransmitPacingAlgorithmTestRegister 0x01E2 31E8 RXPAUSE ReceivePause TimerRegister 0x01E2 31EC TXPAUSE TransmitPause TimerRegister 0x01E2 3200 -0x01E2 32FC (seeTable5-97) EMAC StatisticsRegisters 0x01E2 3500 MACADDRLO MAC AddressLow BytesRegister,Used inReceiveAddressMatching 0x01E2 3504 MACADDRHI MAC AddressHighBytesRegister,Used inReceiveAddressMatching 0x01E2 3508 MACINDEX MAC IndexRegister 0x01E2 3600 TX0HDP TransmitChannel0 DMA Head DescriptorPointerRegister 0x01E2 3604 TX1HDP TransmitChannel1 DMA Head DescriptorPointerRegister 0x01E2 3608 TX2HDP TransmitChannel2 DMA Head DescriptorPointerRegister 0x01E2 360C TX3HDP TransmitChannel3 DMA Head DescriptorPointerRegister 0x01E2 3610 TX4HDP TransmitChannel4 DMA Head DescriptorPointerRegister 0x01E2 3614 TX5HDP TransmitChannel5 DMA Head DescriptorPointerRegister 0x01E2 3618 TX6HDP TransmitChannel6 DMA Head DescriptorPointerRegister 0x01E2 361C TX7HDP TransmitChannel7 DMA Head DescriptorPointerRegister 0x01E2 3620 RX0HDP ReceiveChannel0 DMA Head DescriptorPointerRegister 0x01E2 3624 RX1HDP ReceiveChannel1 DMA Head DescriptorPointerRegister 0x01E2 3628 RX2HDP ReceiveChannel2 DMA Head DescriptorPointerRegister 0x01E2 362C RX3HDP ReceiveChannel3 DMA Head DescriptorPointerRegister 0x01E2 3630 RX4HDP ReceiveChannel4 DMA Head DescriptorPointerRegister 0x01E2 3634 RX5HDP ReceiveChannel5 DMA Head DescriptorPointerRegister 0x01E2 3638 RX6HDP ReceiveChannel6 DMA Head DescriptorPointerRegister 0x01E2 363C RX7HDP ReceiveChannel7 DMA Head DescriptorPointerRegister 0x01E2 3640 TX0CP TransmitChannel0 CompletionPointerRegister 0x01E2 3644 TX1CP TransmitChannel1 CompletionPointerRegister 0x01E2 3648 TX2CP TransmitChannel2 CompletionPointerRegister 0x01E2 364C TX3CP TransmitChannel3 CompletionPointerRegister 0x01E2 3650 TX4CP TransmitChannel4 CompletionPointerRegister Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 205 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-96.EthernetMedia Access Controller(EMAC) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 3654 TX5CP TransmitChannel5 CompletionPointerRegister 0x01E2 3658 TX6CP TransmitChannel6 CompletionPointerRegister 0x01E2 365C TX7CP TransmitChannel7 CompletionPointerRegister 0x01E2 3660 RX0CP ReceiveChannel0 CompletionPointerRegister 0x01E2 3664 RX1CP ReceiveChannel1 CompletionPointerRegister 0x01E2 3668 RX2CP ReceiveChannel2 CompletionPointerRegister 0x01E2 366C RX3CP ReceiveChannel3 CompletionPointerRegister 0x01E2 3670 RX4CP ReceiveChannel4 CompletionPointerRegister 0x01E2 3674 RX5CP ReceiveChannel5 CompletionPointerRegister 0x01E2 3678 RX6CP ReceiveChannel6 CompletionPointerRegister 0x01E2 367C RX7CP ReceiveChannel7 CompletionPointerRegister Table5-97.EMAC StatisticsRegisters BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 3200 RXGOODFRAMES Good ReceiveFrames Register BroadcastReceiveFrames Register0x01E2 3204 RXBCASTFRAMES (Totalnumber ofgood broadcastframesreceived) MulticastReceiveFrames Register0x01E2 3208 RXMCASTFRAMES (Totalnumber ofgood multicastframesreceived) 0x01E2 320C RXPAUSEFRAMES Pause ReceiveFrames Register ReceiveCRC ErrorsRegister0x01E2 3210 RXCRCERRORS (Totalnumber offramesreceivedwithCRC errors) ReceiveAlignment/CodeErrorsRegister0x01E2 3214 RXALIGNCODEERRORS (Totalnumber offramesreceivedwithalignment/codeerrors) ReceiveOversizedFrames Register0x01E2 3218 RXOVERSIZED (Totalnumber ofoversizedframesreceived) ReceiveJabberFrames Register0x01E2 321C RXJABBER (Totalnumber ofjabberframesreceived) ReceiveUndersizedFrames Register0x01E2 3220 RXUNDERSIZED (Totalnumber ofundersizedframesreceived) 0x01E2 3224 RXFRAGMENTS ReceiveFrame FragmentsRegister 0x01E2 3228 RXFILTERED FilteredReceiveFrames Register 0x01E2 322C RXQOSFILTERED ReceivedQOS FilteredFrames Register ReceiveOctetFrames Register0x01E2 3230 RXOCTETS (Totalnumber ofreceivedbytesingood frames) Good TransmitFrames Register0x01E2 3234 TXGOODFRAMES (Totalnumber ofgood framestransmitted) 0x01E2 3238 TXBCASTFRAMES BroadcastTransmitFrames Register 0x01E2 323C TXMCASTFRAMES MulticastTransmitFrames Register 0x01E2 3240 TXPAUSEFRAMES Pause TransmitFrames Register 0x01E2 3244 TXDEFERRED DeferredTransmitFrames Register 0x01E2 3248 TXCOLLISION TransmitCollisionFrames Register 0x01E2 324C TXSINGLECOLL TransmitSingleCollisionFrames Register 0x01E2 3250 TXMULTICOLL TransmitMultipleCollisionFrames Register 0x01E2 3254 TXEXCESSIVECOLL TransmitExcessiveCollisionFrames Register 0x01E2 3258 TXLATECOLL TransmitLateCollisionFrames Register 0x01E2 325C TXUNDERRUN TransmitUnderrunErrorRegister 0x01E2 3260 TXCARRIERSENSE TransmitCarrierSense ErrorsRegister 0x01E2 3264 TXOCTETS TransmitOctetFrames Register 0x01E2 3268 FRAME64 Transmitand Receive64 OctetFrames Register

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-97.EMAC StatisticsRegisters(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 326C FRAME65T127 Transmitand Receive65 to127 OctetFrames Register 0x01E2 3270 FRAME128T255 Transmitand Receive128 to255 OctetFrames Register 0x01E2 3274 FRAME256T511 Transmitand Receive256 to511 OctetFrames Register 0x01E2 3278 FRAME512T1023 Transmitand Receive512 to1023 OctetFrames Register 0x01E2 327C FRAME1024TUP Transmitand Receive1024 to1518 OctetFrames Register 0x01E2 3280 NETOCTETS NetworkOctetFrames Register 0x01E2 3284 RXSOFOVERRUNS ReceiveFIFO orDMA StartofFrame OverrunsRegister 0x01E2 3288 RXMOFOVERRUNS ReceiveFIFO orDMA MiddleofFrame OverrunsRegister 0x01E2 328C RXDMAOVERRUNS ReceiveDMA StartofFrame and MiddleofFrame OverrunsRegister Table5-98.EMAC ControlModule Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 2000 REV EMAC ControlModule RevisionRegister 0x01E2 2004 SOFTRESET EMAC ControlModule SoftwareResetRegister 0x01E2 200C INTCONTROL EMAC ControlModule InterruptControlRegister 0x01E2 2010 C0RXTHRESHEN EMAC ControlModule InterruptCore 0 ReceiveThresholdInterruptEnableRegister 0x01E2 2014 C0RXEN EMAC ControlModule InterruptCore 0 ReceiveInterruptEnableRegister 0x01E2 2018 C0TXEN EMAC ControlModule InterruptCore 0 TransmitInterruptEnableRegister 0x01E2 201C C0MISCEN EMAC ControlModule InterruptCore 0 MiscellaneousInterruptEnableRegister 0x01E2 2020 C1RXTHRESHEN EMAC ControlModule InterruptCore 1 ReceiveThresholdInterruptEnableRegister 0x01E2 2024 C1RXEN EMAC ControlModule InterruptCore 1 ReceiveInterruptEnableRegister 0x01E2 2028 C1TXEN EMAC ControlModule InterruptCore 1 TransmitInterruptEnableRegister 0x01E2 202C C1MISCEN EMAC ControlModule InterruptCore 1 MiscellaneousInterruptEnableRegister 0x01E2 2030 C2RXTHRESHEN EMAC ControlModule InterruptCore 2 ReceiveThresholdInterruptEnableRegister 0x01E2 2034 C2RXEN EMAC ControlModule InterruptCore 2 ReceiveInterruptEnableRegister 0x01E2 2038 C2TXEN EMAC ControlModule InterruptCore 2 TransmitInterruptEnableRegister 0x01E2 203C C2MISCEN EMAC ControlModule InterruptCore 2 MiscellaneousInterruptEnableRegister 0x01E2 2040 C0RXTHRESHSTAT EMAC ControlModule InterruptCore 0 ReceiveThresholdInterruptStatusRegister 0x01E2 2044 C0RXSTAT EMAC ControlModule InterruptCore 0 ReceiveInterruptStatusRegister 0x01E2 2048 C0TXSTAT EMAC ControlModule InterruptCore 0 TransmitInterruptStatusRegister 0x01E2 204C C0MISCSTAT EMAC ControlModule InterruptCore 0 MiscellaneousInterruptStatusRegister 0x01E2 2050 C1RXTHRESHSTAT EMAC ControlModule InterruptCore 1 ReceiveThresholdInterruptStatusRegister 0x01E2 2054 C1RXSTAT EMAC ControlModule InterruptCore 1 ReceiveInterruptStatusRegister 0x01E2 2058 C1TXSTAT EMAC ControlModule InterruptCore 1 TransmitInterruptStatusRegister 0x01E2 205C C1MISCSTAT EMAC ControlModule InterruptCore 1 MiscellaneousInterruptStatusRegister 0x01E2 2060 C2RXTHRESHSTAT EMAC ControlModule InterruptCore 2 ReceiveThresholdInterruptStatusRegister 0x01E2 2064 C2RXSTAT EMAC ControlModule InterruptCore 2 ReceiveInterruptStatusRegister 0x01E2 2068 C2TXSTAT EMAC ControlModule InterruptCore 2 TransmitInterruptStatusRegister 0x01E2 206C C2MISCSTAT EMAC ControlModule InterruptCore 2 MiscellaneousInterruptStatusRegister 0x01E2 2070 C0RXIMAX EMAC ControlModule InterruptCore 0 ReceiveInterruptsPer MillisecondRegister 0x01E2 2074 C0TXIMAX EMAC ControlModule InterruptCore 0 TransmitInterruptsPer MillisecondRegister 0x01E2 2078 C1RXIMAX EMAC ControlModule InterruptCore 1 ReceiveInterruptsPer MillisecondRegister 0x01E2 207C C1TXIMAX EMAC ControlModule InterruptCore 1 TransmitInterruptsPer MillisecondRegister 0x01E2 2080 C2RXIMAX EMAC ControlModule InterruptCore 2 ReceiveInterruptsPer MillisecondRegister 0x01E2 2084 C2TXIMAX EMAC ControlModule InterruptCore 2 TransmitInterruptsPer MillisecondRegister Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 207 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

MII_TXCLK 2 3 MII_RXCLK 2 3 OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-99.EMAC ControlModule RAM BYTE ADDRESS DESCRIPTION 0x01E2 0000 -0x01E2 1FFF EMAC LocalBufferDescriptorMemory

5.22.1.1 EMAC ElectricalData/Timing

Table5-100.Timing Requirements forMII_RXCLK (seeFigure5-48)(1) NO. 10 Mbps 100 Mbps 10 Mbps UNIT MIN MAX MIN MAX MIN MAX 1 tc(MII_RXCLK) Cycletime,MII_RXCLK 400 40 400 ns 2 tw(MII_RXCLKH) Pulseduration,MII_RXCLK high 140 14 140 ns 3 tw(MII_RXCLKL) Pulseduration,MII_RXCLK low 140 14 140 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Figure5-48.MII_RXCLK Timing (EMAC -Receive) Table5-101.Timing Requirements forMII_TXCLK (seeFigure5-49)(1) NO. PARAMETER 10 Mbps 100 Mbps 10 Mbps UNIT MIN MAX MIN MAX MIN MAX 1 tc(MII_TXCLK) Cycletime,MII_TXCLK 400 40 400 ns 2 tw(MII_TXCLKH) Pulseduration,MII_TXCLK high 140 14 140 ns 3 tw(MII_TXCLKL) Pulseduration,MII_TXCLK low 140 14 140 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Figure5-49.MII_TXCLK Timing (EMAC -Transmit)

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MII_TCLK□(Input) MII_TXD[3]-MII_TXD[0], MII_TXEN□(Outputs) MII_RXCLK□(Input) MII_RXD[3]-MII_RXD[0], MII_RXDV,□MII_RXER□(Inputs) OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-102.Timing Requirements forEMAC MIIReceive 10/100Mbit/s(1)(2)(seeFigure5-50) NO. PARAMETER UNIT MIN MAX 1 tsu(MRXD-MII_RXCLKH) Setuptime,receiveselectedsignalsvalidbeforeMII_RXCLK high 8 ns 2 th(MII_RXCLKH-MRXD) Holdtime,receiveselectedsignalsvalidafterMII_RXCLK high 8 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) Receiveselectedsignalsinclude:MII_RXD[3]-MII_RXD[0],MII_RXDV, and MII_RXER. Figure5-50.EMAC Receive InterfaceTiming Table5-103.SwitchingCharacteristicsOver Recommended OperatingConditionsforEMAC MIITransmit 10/100Mbit/s(1)(2)(seeFigure5-51) MIN MAX MIN MAX td(MII_TXCLKH-1 Delaytime,MII_TXCLK hightotransmitselectedsignalsvalid 2 25 2 32 ns MTXD) (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) Transmitselectedsignalsinclude:MTXD3-MTXD0, and MII_TXEN. Figure5-51.EMAC TransmitInterfaceTiming Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 209 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

RMII_MHz_50_CLK RMII_TXEN RMII_TXD[1:0] RMII_RXD[1:0] RMII_CRS_DV RMII_RXER 2 3 5 5 8 9 OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-104.Timing Requirements forEMAC RMII(1) 1.3V,1.2V,1.1V(2) NO. PARAMETER UNIT MIN TYP MAX 1 tc(REFCLK) CycleTime,RMII_MHZ_50_CLK 20 ns 2 tw(REFCLKH) PulseWidth,RMII_MHZ_50_CLK High 7 13 ns 3 tw(REFCLKL) PulseWidth,RMII_MHZ_50_CLK Low 7 13 ns 6 tsu(RXD-REFCLK) InputSetupTime,RXD ValidbeforeRMII_MHZ_50_CLK High 4 ns 7 th(REFCLK-RXD) InputHoldTime,RXD ValidafterRMII_MHZ_50_CLK High 2 ns 8 tsu(CRSDV-REFCLK) InputSetupTime,CRSDV ValidbeforeRMII_MHZ_50_CLK High 4 ns 9 th(REFCLK-CRSDV) InputHoldTime,CRSDV ValidafterRMII_MHZ_50_CLK High 2 ns 10 tsu(RXER-REFCLK) InputSetupTime,RXER ValidbeforeRMII_MHZ_50_CLK High 4 ns 11 th(REFCLKR-RXER) InputHoldTime,RXER ValidafterRMII_MHZ_50_CLK High 2 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) RMII isnotsupportedatoperatingpointsbelow1.1Vnominal Note:Per theRMII industryspecification,theRMII referenceclock(RMII_MHZ_50_CLK) must have jitter toleranceof50 ppm orless. Table5-105.SwitchingCharacteristicsOver Recommended OperatingConditionsforEMAC RMII(1) 1.3V,1.2V,1.1V(2) NO. PARAMETER UNIT MIN TYP MAX 4 td(REFCLK-TXD) OutputDelayTime,RMII_MHZ_50_CLK HightoTXD Valid 2.5 13 ns 5 td(REFCLK-TXEN) OutputDelayTime,RMII_MHZ_50_CLK HightoTXEN Valid 2.5 13 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) RMII isnotsupportedatoperatingpointsbelow1.1Vnominal. Figure5-52.RMII Timing Diagram

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5.23 Management Data Input/Output(MDIO)

The Management Data Input/Output(MDIO) module continuouslypollsall32 MDIO addressesinorderto enumerateallPHY devicesinthesystem. The Management Data Input/Output(MDIO) module implementsthe802.3serialmanagement interfaceto interrogateand controlEthernetPHY(s) usinga shared two-wirebus. Host softwareuses the MDIO module to configurethe auto-negotiationparametersof each PHY attachedto the EMAC, retrievethe negotiationresults,and configurerequiredparametersinthe EMAC module forcorrectoperation.The module is designed to allow almost transparentoperationof the MDIO interface,with very little maintenancefromthecoreprocessor.Onlyone PHY may be connectedatany giventime.

5.23.1 MDIO RegisterDescription(s)

Table5-106.MDIO RegisterMemory Map BYTE ADDRESS ACRONYM REGISTER NAME 0x01E2 4000 REV RevisionIdentificationRegister 0x01E2 4004 CONTROL MDIO ControlRegister 0x01E2 4008 ALIVE MDIO PHY AliveStatusRegister 0x01E2 400C LINK MDIO PHY LinkStatusRegister 0x01E2 4010 LINKINTRAW MDIO LinkStatusChange Interrupt(Unmasked) Register 0x01E2 4014 LINKINTMASKED MDIO LinkStatusChange Interrupt(Masked)Register 0x01E2 4018 – Reserved 0x01E2 4020 USERINTRAW MDIO User Command CompleteInterrupt(Unmasked) Register 0x01E2 4024 USERINTMASKED MDIO User Command CompleteInterrupt(Masked)Register 0x01E2 4028 USERINTMASKSET MDIO User Command CompleteInterruptMask SetRegister 0x01E2 402C USERINTMASKCLEAR MDIO User Command CompleteInterruptMask ClearRegister 0x01E2 4030 -0x01E2 407C – Reserved 0x01E2 4080 USERACCESS0 MDIO User Access Register0 0x01E2 4084 USERPHYSEL0 MDIO User PHY SelectRegister0 0x01E2 4088 USERACCESS1 MDIO User Access Register1 0x01E2 408C USERPHYSEL1 MDIO User PHY SelectRegister1 0x01E2 4090 -0x01E2 47FF – Reserved Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 211 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

(output) MDCLK MDIO (input) 3 3 OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com

5.23.2 Management Data Input/Output(MDIO) ElectricalData/Timing

Table5-107.Timing Requirements forMDIO Input(seeFigure5-53and Figure5-54)(1) NO. PARAMETER UNIT MIN MAX MIN MAX 1 tc(MDCLK) Cycletime,MDCLK 400 400 ns 2 tw(MDCLK) Pulseduration,MDCLK high/low 180 180 ns 3 tt(MDCLK) Transitiontime,MDCLK 5 5 ns 4 tsu(MDIO-MDCLKH) Setuptime,MDIO datainputvalidbeforeMDCLK high 16 21 ns 5 th(MDCLKH-MDIO) Holdtime,MDIO datainputvalidafterMDCLK high 0 0 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Figure5-53.MDIO InputTiming Table5-108.SwitchingCharacteristicsOver Recommended OperatingConditionsforMDIO Output (seeFigure5-54)(1) 1.3V,1.2V,1.1V, 1.0VNO. PARAMETER UNIT MIN MAX 7 td(MDCLKL-MDIO) Delaytime,MDCLK lowtoMDIO dataoutputvalid 0 100 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Figure5-54.MDIO Output Timing

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5.24 LCD Controller(LCDC)

The LCD controllerconsistsoftwo independentcontrollers,theRasterControllerand theLCD Interface DisplayDriver(LIDD)controller.Each controlleroperatesindependentlyfrom the otherand onlyone of them isactiveatany giventime.

The RasterControllerhandlesthesynchronousLCD interface.Itprovidestimingand dataforconstant graphicsrefreshtoa passivedisplay.Itsupportsa wide varietyofmonochrome and full-colordisplay typesand sizesby use ofprogrammabletimingcontrols,a built-inpalette,and a gray-scale/serializer. Graphicsdataisprocessedand storedinframebuffers.A framebufferisa contiguousmemory block inthesystem.A built-inDMA enginesuppliesthegraphicsdatatotheRasterenginewhich,inturn, outputstotheexternalLCD device.
The LIDD ControllersupportstheasynchronousLCD interface.Itprovidesfull-timingprogrammability ofcontrolsignals(CS,WE, OE, ALE) and outputdata. The maximum resolutionforthe LCD controlleris 1024 x 1024 pixels.The maximum frame rateis determinedby theimage sizeincombinationwiththepixelclockrate.Fordetails,see SPRAB93. Table5-109liststheLCD Controllerregisters. Table5-109.LCD ControllerRegisters BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E1 3000 REVID LCD RevisionIdentificationRegister 0x01E1 3004 LCD_CTRL LCD ControlRegister 0x01E1 3008 LCD_STAT LCD StatusRegister 0x01E1 300C LIDD_CTRL LCD LIDD ControlRegister 0x01E1 3010 LIDD_CS0_CONF LCD LIDD CS0 ConfigurationRegister 0x01E1 3014 LIDD_CS0_ADDR LCD LIDD CS0 AddressRead/WriteRegister 0x01E1 3018 LIDD_CS0_DATA LCD LIDD CS0 Data Read/WriteRegister 0x01E1 301C LIDD_CS1_CONF LCD LIDD CS1 ConfigurationRegister 0x01E1 3020 LIDD_CS1_ADDR LCD LIDD CS1 AddressRead/WriteRegister 0x01E1 3024 LIDD_CS1_DATA LCD LIDD CS1 Data Read/WriteRegister 0x01E1 3028 RASTER_CTRL LCD RasterControlRegister 0x01E1 302C RASTER_TIMING_0 LCD RasterTiming0 Register 0x01E1 3030 RASTER_TIMING_1 LCD RasterTiming1 Register 0x01E1 3034 RASTER_TIMING_2 LCD RasterTiming2 Register 0x01E1 3038 RASTER_SUBPANEL LCD RasterSubpanelDisplayRegister 0x01E1 3040 LCDDMA_CTRL LCD DMA ControlRegister 0x01E1 3044 LCDDMA_FB0_BASE LCD DMA Frame Buffer0 Base AddressRegister 0x01E1 3048 LCDDMA_FB0_CEILING LCD DMA Frame Buffer0 CeilingAddressRegister 0x01E1 304C LCDDMA_FB1_BASE LCD DMA Frame Buffer1 Base AddressRegister 0x01E1 3050 LCDDMA_FB1_CEILING LCD DMA Frame Buffer1 CeilingAddressRegister Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 213 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

LCD_AC_ENB_CS LCD_PCLK

1 W_SU

(0 to 31) W_STROBE (1 to 63) W_HOLD (1 to 15) CS_DELAY (0 to 3) R_SU (0 to 31) R_STROBE (1 to 63) R_HOLD (1 to 15) CS_DELAY (0 to 3) LCD_CLK (SYSCLK2) Write Data 5 14 Data[7:0] Not Used 8 9 10 11 RS R/W (E1) LCD_D[15:0] LCD_VSYNC LCD_HSYNC Read Status (LCD_MCLK) OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com

5.24.1 LCD InterfaceDisplayDriver(LIDD Mode)

Table5-110.Timing Requirements forLCD LIDD Mode (1) MIN MAX MIN MAX 16 tsu(LCD_D) Setuptime,LCD_D[15:0]validbeforeLCD_CLK (SYSCLK2) high 7 8 ns 17 th(LCD_D) Holdtime,LCD_D[15:0]validafterLCD_CLK (SYSCLK2) high 0 0 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Table5-111.SwitchingCharacteristicsOver Recommended OperatingConditionsforLCD LIDD Mode (1) MIN MAX MIN MAX 4 td(LCD_D_V) Delaytime,LCD_CLK (SYSCLK2) hightoLCD_D[15:0]valid(write) 0 7 0 9 ns 5 td(LCD_D_I) Delaytime,LCD_CLK (SYSCLK2) hightoLCD_D[15:0]invalid(write) 0 7 0 9 ns 6 td(LCD_E_A ) Delaytime,LCD_CLK (SYSCLK2) hightoLCD_AC_ENB_CS low 0 7 0 9 ns 7 td(LCD_E_I) Delaytime,LCD_CLK (SYSCLK2) hightoLCD_AC_ENB_CS high 0 7 0 9 ns 8 td(LCD_A_A) Delaytime,LCD_CLK (SYSCLK2) hightoLCD_VSYNC low 0 7 0 9 ns 9 td(LCD_A_I) Delaytime,LCD_CLK (SYSCLK2) hightoLCD_VSYNC high 0 7 0 9 ns 10 td(LCD_W_A) Delaytime,LCD_CLK (SYSCLK2) hightoLCD_HSYNC low 0 7 0 9 ns 11 td(LCD_W_I) Delaytime,LCD_CLK (SYSCLK2) hightoLCD_HSYNC high 0 7 0 9 ns 12 td(LCD_STRB_A) Delaytime,LCD_CLK (SYSCLK2) hightoLCD_PCLK active 0 7 0 9 ns 13 td(LCD_STRB_I) Delaytime,LCD_CLK (SYSCLK2) hightoLCD_PCLK inactive 0 7 0 9 ns 14 td(LCD_D_Z) Delaytime,LCD_CLK (SYSCLK2) hightoLCD_D[15:0]in3-state 0 7 0 9 ns 15 td(Z_LCD_D) Delaytime,LCD_CLK (SYSCLK2) hightoLCD_D15:0 0 7 0 9 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Figure5-55.CharacterDisplayHD44780 Write

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LCD_AC_ENB_CS LCD_PCLK LCD_VSYNC LCD_HSYNC R_SU R_STROBE R_HOLD (0–31) (1–63) (1–5) CS_DELAY (0−3) Not Used RS R/W LCD_CLK (SYSCLK2) 2 3 W_SU W_STROBE W_HOLD (0–31) (1–63) (1–15) CS_DELAY (0 − 3) 8 9 12 13 10 11 Not Used LCD_D[7:0] 14 1716 Read Data 15 4 5 (E1) 12 13 Data[7:0]Write Instruction (LCD_MCLK) OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-56.CharacterDisplayHD44780 Read Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 215 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

LCD_D[15:0] LCD_AC_ENB_CS (LCD_MCLK) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELAY (0−3) CS0 ( )CS1 R/W E Clock 2 3 W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELAY (0−3) 5 4 5 6 7 6 7 8 9 12 13 Write Address Write Data 12 13 10 11 10 11 Data[15:0] (async mode) OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-57.Micro-InterfaceGraphic Display6800 Write

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LCD_D[15:0] LCD_AC_ENB_CS (LCD_MCLK) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELAY (0−3) CS0 ( )CS1 R/W E Clock 2 3 R_SU R_STROBE R_HOLD (0−31) (1−63 (1−15) CS_DELAY (0−3) 5 14 15 6 7 6 7 8 9 12 13 1716 Write Address Read Data 10 11 1213 Data[15:0] (async mode) OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-58.Micro-InterfaceGraphic Display6800 Read Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 217 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

LCD_D[15:0] LCD_AC_ENB_CS (LCD_MCLK) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK R_SU R_STROBE R_HOLD (0−31) (1−63) (1−15) CS_DELAY (0−3) CS0 ( )CS1 R/W E Clock 2 3 R_STROBE R_HOLD (1−63) (1−15) CS_DELAY (0−3) 14 15 6 7 6 7 8 9 12 13 171614 1716 15 12 13 Data[15:0] R_SU (0−31) Read Status (async mode) OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-59.Micro-InterfaceGraphic Display6800 Status

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LCD_D[15:0] LCD_AC_ENB_CS (LCD_MCLK) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELAY (0−3) DATA[15:0] CS0 ( )CS1 WR RD Clock 2 3 W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELAY (0 − 3) 5 4 5 6 7 6 7 8 9 10 11 Write Address Write Data 10 11 (async mode) OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-60.Micro-InterfaceGraphic Display8080 Write Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 219 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

LCD_D[15:0] LCD_AC_ENB_CS (LCD_MCLK) LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK W_SU W_STROBE W_HOLD (0−31) (1−63) (1−15) CS_DELAY (0−3) CS0 ( )CS1 WR RD Clock 2 3 R_SU R_STROBE R_HOLD (0−31) (1−63) (1−15) CS_DELAY (0−3) 5 14 15 6 7 6 7 8 9 12 13 1716 Read Data 10 11 Data[15:0]Write Address (async mode) OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-61.Micro-InterfaceGraphic Display8080 Read

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LCD_D[15:0] LCD_AC_ENB_CS LCD_VSYNC LCD_HSYNC LCD_CLK (SYSCLK2) LCD_PCLK R_SU R_STROBE R_HOLD (0−31) (1−63) (1−15) CS_DELAY (0−3) CS0 ( )CS1 WR RD Clock R_STROBE R_HOLD (1−63) (1−15) CS_DELAY (0−3) 14 15 6 7 6 12 13 1716 Read Status 14 1716 Read Data 12 13 Data[15:0] R_SU (0−31) (LCD_MCLK) OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-62.Micro-InterfaceGraphic Display8080 Status Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 221 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.24.2 LCD RasterMode

Table5-112.SwitchingCharacteristicsOver Recommended OperatingConditionsforLCD RasterMode (1) See Figure5-63throughFigure5-67 NO. PARAMETER UNIT MIN MAX MIN MAX 1 tc(PIXEL_CLK) Cycletime,pixelclock 26.66 33.33 ns 2 tw(PIXEL_CLK_H) Pulseduration,pixelclockhigh 10 10 ns 3 tw(PIXEL_CLK_L) Pulseduration,pixelclocklow 10 10 ns 4 td(LCD_D_V) Delaytime,LCD_PCLK hightoLCD_D[15:0]valid(write) 0 7 0 9 ns Delaytime,LCD_PCLK hightoLCD_D[15:0]invalid5 td(LCD_D_IV) 0 7 0 9 ns(write) 6 td(LCD_AC_ENB_CS_A ) Delaytime,LCD_PCLK lowtoLCD_AC_ENB_CS high 0 7 0 9 ns 7 td(LCD_AC_ENB_CS_I) Delaytime,LCD_PCLK lowtoLCD_AC_ENB_CS low 0 7 0 9 ns 8 td(LCD_VSYNC_A) Delaytime,LCD_PCLK lowtoLCD_VSYNC high 0 7 0 9 ns 9 td(LCD_VSYNC_I) Delaytime,LCD_PCLK lowtoLCD_VSYNC low 0 7 0 9 ns 10 td(LCD_HSYNC_A) Delaytime,LCD_PCLK hightoLCD_HSYNC high 0 7 0 9 ns 11 td(LCD_HSYNC_I) Delaytime,LCD_PCLK hightoLCD_HSYNC low 0 7 0 9 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Frame-to-frametimingis derivedthroughthe followingparametersin the LCD (RASTER_TIMING_1) register:

Verticalfrontporch(VFP)
Verticalsyncpulsewidth(VSW)
Verticalback porch(VBP)
Linesperpanel(LPP) Line-to-linetimingisderivedthroughthefollowingparametersintheLCD (RASTER_TIMING_0) register:
Horizontalfrontporch(HFP)
Horizontalsyncpulsewidth(HSW)
Horizontalback porch(HBP)
Pixelsperpanel(PPL) LCD_AC_ENB_CS timingisderivedthroughthe followingparameterinthe LCD (RASTER_TIMING_2) register:
AC biasfrequency(ACB) The displayformatproducedinrastermode isshown inFigure5-63.An entireframeisdeliveredone line at a time.The firstlinedeliveredstartsat data pixel(1,1) and ends at data pixel(P,1).The lastline deliveredstartsat data pixel(1,L) and ends at data pixel(P,L).The beginningof each new frame is denotedby theactivationofI/OsignalLCD_VSYNC. The beginningofeach new lineisdenotedby the activationofI/OsignalLCD_HSYNC.

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1, 1 2, 1 3, 1 1, 2 2, 2 1, 3 P, 1P−1, P−2, P, 2P−1, P, 3 1, L L−1 L−2 3, L2, L L−1 P, L P−1, L−1 L−1 P−1, L L−2 P−2, L Data Pixels (From 1 to P) Data Lines (From 1 to L) OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-63.LCD Raster-Mode DisplayFormat Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 223 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

LCD_HSYNC Hsync LCD_VSYNC (1 to 64) VSW (1 to 64) VSW (0 to 255) VFP (1 to 1024) Frame Time 70 Hz~ LPP (0 to 255) LCD_D[15:0] 1, 1 P, 1 1, 2 P, 2 1, L P, L 1, L-1 P, L-1 Line Time Vsync Data Active TFT LCD_AC_ENB_CS VBP CLK LCD_HSYNC Hsync 10 11 LCD_PCLK PLL 16 × (1 to 1024) HBP (1 to 256) Line 1 (1 to 256) HFP (1 to 64) HSW PLL 16 × (1 to 1024) Line 2 Data LCD_AC_ENB_CS Enable OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-64.LCD Raster-Mode Active

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-65.LCD Raster-Mode Passive Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 225 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

LCD_HSYNC LCD_PCLK (active mode) LCD_D[15:0] (active mode) 1,□L P,□L2,□L PPL 16 ×(1□to□1024) HBP (1□to□256 Line□L (1□to□256) HFP (1□to□64) HSW PPL 16 ×(1□to□1024) Line□1□(Passive□Only) LCD_VSYNC LCD_PCLK (passive mode) LCD_AC_ENB_CS LCD_D[7:0] (passive mode) 1,□L 2,□1 P,□1P,□L2,□L 1,□1 10 11 2 3 2 3 VSW = 1 VFP =□0 VBP =□0 OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-66.LCD Raster-Mode ControlSignalActivation

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LCD_HSYNC LCD_PCLK (active mode) LCD_D[15:0] (active mode) PPL 16 ×(1□to□1024) HBP (1□to□256 Line□1□for□passive (1□to□256) HFP (1□to□64) HSW PPL 16 ×(1□to□1024) Line□1□for□active LCD_VSYNC LCD_PCLK (passive mode) LCD_AC_ENB_CS LCD_D[7:0] (passive mode) 1,□1 2,□2 P,□2P,□12,□1 1,□2 10 11 4 5 2 3 VSW = 1 VFP =□0 VBP =□0 P,□11,□1 2,□1 4 5 Line□2□for□passive OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-67.LCD Raster-Mode ControlSignalDeactivation Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 227 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.25 Host-PortInterface(UHPI)

5.25.1 HPI Device-SpecificInformation

The deviceincludesa user-configurable16-bitHost-portinterface(HPI16). The hostportinterface(UHPI)providesa parallelportinterfacethroughwhichan externalhostprocessor can directlyaccess the processor'sresources(configurationand program/datamemories).The external hostdeviceisasynchronoustotheCPU clockand functionsas a mastertotheHPI interface.The UHPI enables a host deviceand the processorto exchange informationvia internalor externalmemory. Dedicatedaddress(HPIA)and data(HPID)registerswithintheUHPI providethedatapathbetween the externalhostinterfaceand the processorresources.A UHPI controlregister(HPIC) isavailableto the hostand theCPU forvariousconfigurationand interruptfunctions.

5.25.2 HPI PeripheralRegisterDescription(s)

Table5-113.HPI ControlRegisters BYTE ADDRESS ACRONYM REGISTER DESCRIPTION COMMENTS 0x01E1 0000 PID PeripheralIdentificationRegister The CPU has read/writeaccessto0x01E1 0004 PWREMU_MGMT HPI power and emulationmanagement registerthePWREMU_MGMT register. 0x01E1 0008 - Reserved 0x01E1 000C GPIO_EN GeneralPurposeIO EnableRegister 0x01E1 0010 GPIO_DIR1 GeneralPurposeIO DirectionRegister1 0x01E1 0014 GPIO_DAT1 GeneralPurposeIO Data Register1 0x01E1 0018 GPIO_DIR2 GeneralPurposeIO DirectionRegister2 0x01E1 001C GPIO_DAT2 GeneralPurposeIO Data Register2 0x01E1 0020 GPIO_DIR3 GeneralPurposeIO DirectionRegister3 0x01E1 0024 GPIO_DAT3 GeneralPurposeIO Data Register3 01E1 0028 - Reserved 01E1 002C - Reserved The Hostand theCPU bothhave 01E1 0030 HPIC HPI controlregister read/writeaccesstotheHPIC register. HPIA The Hosthas read/writeaccessto01E1 0034 HPI addressregister(Write)(HPIAW) (1) theHPIA registers.The CPU has onlyreadaccesstotheHPIAHPIA01E1 0038 HPI addressregister(Read) registers.(HPIAR)(1) 01E1 000C -01E1 07FF - Reserved (1) Therearetwo 32-bitHPIA registers:HPIAR forreadoperationsand HPIAW forwriteoperations.The HPI can be configuredsuch that HPIAR and HPIAW actas a single32-bitHPIA (single-HPIAmode) oras two separate32-bitHPIAs (dual-HPIAmode) fromthe perspectiveoftheHost.The CPU can accessHPIAW and HPIAR independently.

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5.25.3 HPI ElectricalData/Timing

Table5-114.Timing Requirements forHost-PortInterface1.2V,1.1V(2)(3) NO. UNIT MIN MAX 1 tsu(SELV-HSTBL) Setuptime,selectsignals(4)validbeforeUHPI_HSTROBE low 5 ns 2 th(HSTBL-SELV) Holdtime,selectsignals(4)validafterUHPI_HSTROBE low 2 ns 3 tw(HSTBL) Pulseduration,UHPI_HSTROBE activelow 15 ns 4 tw(HSTBH) Pulseduration,UHPI_HSTROBE inactivehighbetween consecutiveaccesses 2M ns 9 tsu(SELV-HASL) Setuptime,selectssignalsvalidbeforeUHPI_HAS low 5 ns 10 th(HASL-SELV) Holdtime,selectsignalsvalidafterUHPI_HAS low 2 ns 11 tsu(HDV-HSTBH) Setuptime,hostdatavalidbeforeUHPI_HSTROBE high 5 ns 12 th(HSTBH-HDV) Holdtime,hostdatavalidafterUHPI_HSTROBE high 2 ns Holdtime,UHPI_HSTROBE highafterUHPI_HRDY low.UHPI_HSTROBE 13 th(HRDYL-HSTBH) shouldnotbe inactivateduntilUHPI_HRDY isactive(low);otherwise,HPI writes 2 ns willnotcompleteproperly. 16 tsu(HASL-HSTBL) Setuptime,UHPI_HAS lowbeforeUHPI_HSTROBE low 5 ns 17 th(HSTBL-HASH) Holdtime,UHPI_HAS lowafterUHPI_HSTROBE low 2 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) UHPI_HSTROBE referstothefollowinglogicaloperationon UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS. (3) M=SYSCLK2 periodinns. (4) Selectsignalsinclude:HCNTL[1:0],HR/W and HHWIL. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 229 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-115.SwitchingCharacteristicsOver Recommended OperatingConditionsforHost-PortInterface 1.3V,1.2V 1.1V NO. PARAMETER UNIT MIN MAX MIN MAX ForHPI Write,HRDY can go high(not ready)fortheseHPI Writeconditions; otherwise,HRDY stayslow(ready): Case 1:Back-to-backHPIA writes(can be eitherfirstorsecond half-word) Case 2:HPIA writefollowinga PREFETCH command (canbe either firstorsecond half-word) Case 3:HPID writewhen FIFO isfullor flushing(canbe eitherfirstorsecond half-word) Case 4:HPIA writeand WriteFIFO not empty ForHPI Read, HRDY can go high(not ready)fortheseHPI Read conditions: Case 1:HPID read(withauto-Delaytime,HSTROBE lowto5 td(HSTBL-HRDYV) 15 17 nsincrement)and datanotinRead FIFOHRDY valid (canonlyhappen tofirsthalf-wordof HPID access) Case 2:Firsthalf-wordaccessofHPID Read withoutauto-increment ForHPI Read, HRDY stayslow(ready) fortheseHPI Read conditions: Case 1:HPID readwithauto-increment and dataisalreadyinRead FIFO (appliestoeitherhalf-wordofHPID access) Case 2:HPID readwithoutauto- incrementand dataisalreadyinRead FIFO (alwaysappliestosecond half- word ofHPID access) Case 3:HPIC orHPIA read(appliesto eitherhalf-wordaccess) 5a td(HASL-HRDYV) Delaytime,HAS lowtoHRDY valid 15 17 ns 6 ten(HSTBL-HDLZ) Enabletime,HD drivenfromHSTROBE low 1.5 1.5 ns 7 td(HRDYL-HDV) Delaytime,HRDY lowtoHD valid 0 0 ns 8 toh(HSTBH-HDV) Outputholdtime,HD validafterHSTROBE high 1.5 1.5 ns 14 tdis(HSTBH-HDHZ) Disabletime,HD high-impedancefromHSTROBE high 15 17 ns ForHPI Read. Appliestoconditions where dataisalreadyresidingin HPID/FIFO: Case 1:HPIC orHPIA readDelaytime,HSTROBE lowto15 td(HSTBL-HDV) Case 2:Firsthalf-wordofHPID read 15 17 nsHD valid withauto-incrementand dataisalready inRead FIFO Case 3:Second half-wordofHPID read withorwithoutauto-increment ForHPI Write,HRDY can go high(not ready)fortheseHPI Writeconditions; otherwise,HRDY stayslow(ready): Case 1:HPID writewhen WriteFIFO is Delaytime,HSTROBE highto full(canhappen toeitherhalf-word)18 td(HSTBH-HRDYV) 15 17 nsHRDY valid Case 2:HPIA write(canhappen to eitherhalf-word) Case 3:HPID writewithoutauto- increment(onlyhappens tosecond half-word) (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) M=SYSCLK2 periodinns. (3) HSTROBE referstothefollowinglogicaloperationon HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. (4) By design,whenever HCS isdriveninactive(high),HPI willdriveHRDY active(low).

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-116.SwitchingCharacteristicsOver Recommended OperatingConditionsforHost-PortInterface 1.0V(2)(3)(4) 1.0V NO. PARAMETER UNIT MIN MAX ForHPI Write,HRDY can go high(notready)for theseHPI Writeconditions;otherwise,HRDY stayslow(ready): Case 1:Back-to-backHPIA writes(canbe either firstorsecond half-word) Case 2:HPIA writefollowinga PREFETCH command (canbe eitherfirstorsecond half- word) Case 3:HPID writewhen FIFO isfullorflushing (canbe eitherfirstorsecond half-word) Case 4:HPIA writeand WriteFIFO notempty ForHPI Read, HRDY can go high(notready)for theseHPI Read conditions:Delaytime,HSTROBE lowtoHRDY Case 1:HPID read(withauto-increment)and5 td(HSTBL-HRDYV) 22 nsvalid datanotinRead FIFO (canonlyhappen tofirst half-wordofHPID access) Case 2:Firsthalf-wordaccessofHPID Read withoutauto-increment ForHPI Read, HRDY stayslow(ready)forthese HPI Read conditions: Case 1:HPID readwithauto-incrementand data isalreadyinRead FIFO (appliestoeitherhalf- word ofHPID access) Case 2:HPID readwithoutauto-incrementand dataisalreadyinRead FIFO (alwaysappliesto second half-wordofHPID access) Case 3:HPIC orHPIA read(appliestoeither half-wordaccess) 5a td(HASL-HRDYV) Delaytime,HAS lowtoHRDY valid 22 ns 6 ten(HSTBL-HDLZ) Enabletime,HD drivenfromHSTROBE low 1.5 ns 7 td(HRDYL-HDV) Delaytime,HRDY lowtoHD valid 0 ns 8 toh(HSTBH-HDV) Outputholdtime,HD validafterHSTROBE high 1.5 ns 14 tdis(HSTBH-HDHZ) Disabletime,HD high-impedancefromHSTROBE high 22 ns ForHPI Read. Appliestoconditionswhere data isalreadyresidinginHPID/FIFO: Case 1:HPIC orHPIA readDelaytime,HSTROBE lowtoHD15 td(HSTBL-HDV) Case 2:Firsthalf-wordofHPID readwithauto- 22 nsvalid incrementand dataisalreadyinRead FIFO Case 3:Second half-wordofHPID readwithor withoutauto-increment ForHPI Write,HRDY can go high(notready)for theseHPI Writeconditions;otherwise,HRDY stayslow(ready): Case 1:HPID writewhen WriteFIFO isfull(canDelaytime,HSTROBE hightoHRDY18 td(HSTBH-HRDYV) happen toeitherhalf-word) 22 nsvalid Case 2:HPIA write(canhappen toeitherhalf- word) Case 3:HPID writewithoutauto-increment(only happens tosecond half-word) (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) M=SYSCLK2 periodinns. (3) HSTROBE referstothefollowinglogicaloperationon HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. (4) By design,whenever HCS isdriveninactive(high),HPI willdriveHRDY active(low). Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 231 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

UHPI_HCS UHPI_HAS (D) UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL UHPI_HSTROBE (A)(C) UHPI_HD[15:0] (output) UHPI_HRDY (B) 1st Half-Word 2nd Half-Word A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2)] OR UHPI_HCS. B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur. C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2 . UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE. D The diagram above assumes UHPI_HAS has been pulled high. OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-68.UHPI Read Timing (HAS Not Used, TiedHigh)

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UHPI_HAS (A) UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL UHPI_HSTROBE (B) UHPI_HCS UHPI_HD[15:0] (output) UHPI_HRDY 1st half-word 2nd half-word75a 815 10910 9 17 17 1616 OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 A. Forcorrectoperation,strobetheUHPI_HAS signalonlyonce perUHPI_HSTROBE activecycle. B. UHPI_HSTROBE refersto the followinglogicaloperationon UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS. Figure5-69.UHPI Read Timing (HAS Used) Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 233 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

UHPI_HAS (D) UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL UHPI_HSTROBE (A)(C) UHPI_HCS UHPI_HD[15:0] (input) UHPI_HRDY (B) 2 1 21 1 2 1 2 3 4 3 11 12 1813 185 11 12 2nd Half-Word1st Half-Word A. UHPI_HSTROBE refers to the following logical operation on UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(HDS1 XOR HDS2 )] OR UHPI_HCS . B. Depending on the type of write or read operation (HPID without auto-incrementing; HPIA, HPIC, or HPID with auto-incrementing) and the state of the FIFO, transitions on UHPI_HRDY may or may not occur. C. UHPI_HCS reflects typical UHPI_HCS behavior when UHPI_HSTROBE assertion is caused by UHPI_HDS1 or UHPI_HDS2. UHPI_HCS timing requirements are reflected by parameters for UHPI_HSTROBE. D The diagram above assumes UHPI_HAS has been pulled high. OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-70.UHPI WriteTiming (HAS Not Used, TiedHigh)

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1st half-word 2nd half-word 12111211 UHPI_HAS † UHPI_HCNTL[1:0] UHPI_HR/W UHPI_HHWIL UHPI_HSTROBE ‡ UHPI_HCS UHPI_HD[15:0] (input) UHPI_HRDY 1717 16 16 OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 A. Forcorrectoperation,strobetheUHPI_HAS signalonlyonce perUHPI_HSTROBE activecycle. B. UHPI_HSTROBE refersto the followinglogicaloperationon UHPI_HCS, UHPI_HDS1, and UHPI_HDS2: [NOT(UHPI_HDS1 XOR UHPI_HDS2)] OR UHPI_HCS. Figure5-71.UHPI WriteTiming (HAS Used) Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 235 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.26 UniversalParallelPort(uPP)

The UniversalParallelPort(uPP)peripheralisa multichannel,high-speedparallelinterfacewithdedicated datalinesand minimalcontrolsignals.Itisdesignedtointerfacecleanlywithhigh-speedanalog-to-digital converters(ADCs) ordigital-to-analogconverters(DACs) withup to16-bitdatawidth(perchannel).Itmay alsobe interconnectedwithfield-programmablegate arrays(FPGAs) or otheruPP devicesto achieve high-speeddigitaldatatransfer.Itcan operateinreceivemode, transmitmode, orduplexmode, inwhich itsindividualchannelsoperateinoppositedirections. The uPP peripheralincludesan internalDMA controllerto maximize throughputand minimizeCPU overheadduringhigh-speeddatatransmission.AlluPP transactionsuse theinternalDMA toprovidedata toorretrievedatafromtheI/Ochannels.The DMA controllerincludestwo DMA channels,whichtypically serviceseparateI/Ochannels.The uPP peripheralalsosupportsdatainterleavemode, inwhichallDMA resourcesservicea singleI/Ochannel.Inthismode, onlyone I/Ochannelmay be used. The featuresoftheuPP include:

Programmable datawidthperchannel(from8 to16 bitsinclusive)
Programmable datajustification – Right-justifywithzeroextend – Right-justifywithsignextend – Left-justifywithzerofill
SupportsmultiplexingofinterleaveddataduringSDR transmit
OptionalframeSTART signalwithprogrammablepolarity
OptionaldataENABLE signalwithprogrammablepolarity
OptionalsynchronizationWAIT signalwithprogrammablepolarity
SingleData Rate (SDR) orDoubledataRate (DDR, interleaved)interface – SupportsmultiplexingofinterleaveddataduringSDR transmit – Supportsdemultiplexingand multiplexingofinterleaveddataduringDDR transfers

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 5.26.1 uPP RegisterDescriptions Table5-117.UniversalParallelPort(uPP)Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E1 6000 UPPID uPP PeripheralIdentificationRegister 0x01E1 6004 UPPCR uPP PeripheralControlRegister 0x01E1 6008 UPDLB uPP DigitalLoopback Register 0x01E1 6010 UPCTL uPP ChannelControlRegister 0x01E1 6014 UPICR uPP InterfaceConfigurationRegister 0x01E1 6018 UPIVR uPP InterfaceIdleValueRegister 0x01E1 601C UPTCR uPP ThresholdConfigurationRegister 0x01E1 6020 UPISR uPP InterruptRaw StatusRegister 0x01E1 6024 UPIER uPP InterruptEnabledStatusRegister 0x01E1 6028 UPIES uPP InterruptEnableSetRegister 0x01E1 602C UPIEC uPP InterruptEnableClearRegister 0x01E1 6030 UPEOI uPP End-of-InterruptRegister 0x01E1 6040 UPID0 uPP DMA ChannelIDescriptor0 Register 0x01E1 6044 UPID1 uPP DMA ChannelIDescriptor1 Register 0x01E1 6048 UPID2 uPP DMA ChannelIDescriptor2 Register 0x01E1 6050 UPIS0 uPP DMA ChannelIStatus0 Register 0x01E1 6054 UPIS1 uPP DMA ChannelIStatus1 Register 0x01E1 6058 UPIS2 uPP DMA ChannelIStatus2 Register 0x01E1 6060 UPQD0 uPP DMA ChannelQ Descriptor0 Register 0x01E1 6064 UPQD1 uPP DMA ChannelQ Descriptor1 Register 0x01E1 6068 UPQD2 uPP DMA ChannelQ Descriptor2 Register 0x01E1 6070 UPQS0 uPP DMA ChannelQ Status0 Register 0x01E1 6074 UPQS1 uPP DMA ChannelQ Status1 Register 0x01E1 6078 UPQS2 uPP DMA ChannelQ Status2 Register Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 237 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com 5.26.2 uPP ElectricalData/Timing Table5-118.Timing Requirements foruPP (seeFigure5-72,Figure5-73,Figure5-74,Figure5-75)(1) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX SDR mode 13.33 20 26.66 1 tc(INCLK) Cycletime,CH n_CLK ns DDR mode 26.66 40 53.33 SDR mode 5 8 10 2 tw(INCLKH) Pulsewidth,CH n_CLK high ns DDR mode 10 16 20 SDR mode 5 8 10 3 tw(INCLKL) Pulsewidth,CH n_CLK low ns DDR mode 10 16 20 4 tsu(STV-INCLKH) Setuptime,CH n_START validbeforeCH n_CLK high 4 5.5 6.5 ns 5 th(INCLKH-STV) Holdtime,CH n_START validafterCH n_CLK high 0.8 0.8 0.8 ns 6 tsu(ENV-INCLKH) Setuptime,CH n_ENABLE validbeforeCH n_CLK high 4 5.5 6.5 ns 7 th(INCLKH-ENV) Holdtime,CH n_ENABLE validafterCH n_CLK high 0.8 0.8 0.8 ns Setuptime,8 tsu(DV-INCLKH) 4 5.5 6.5 nsCH n_DATA/XDATA validbeforeCH n_CLK high 9 th(INCLKH-DV) Holdtime,CH n_DATA/XDATA validafterCH n_CLK high 0.8 0.8 0.8 ns 10 tsu(DV-INCLKL) Setuptime,CH n_DATA/XDATA validbeforeCH n_CLK low 4 5.5 6.5 ns 11 th(INCLKL-DV) Holdtime,CH n_DATA/XDATA validafterCH n_CLK low 0.8 0.8 0.8 ns 19 tsu(WTV-INCLKL) Setuptime,CH n_WAIT validbeforeCH n_CLK high 10 12 14 ns 20 th(INCLKL-WTV) Holdtime,CH n_WAIT validafterCH n_CLK high 0.8 0.8 0.8 ns 21 tc(2xTXCLK) Cycletime,2xTXCLK inputclock(2) 6.66 10 13.33 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) 2xTXCLK isan alternatetransmitclocksourcethatmust be atleast2 timestherequireduPP transmitclockrate(asitisisdivideddown by 2 insidetheuPP).2xTXCLK has no specifiedskew relationshiptotheCH n_CLOCK and thereforeisnotshown inthetimingdiagram. Table5-119.SwitchingCharacteristicsOver Recommended OperatingConditionsforuPP (1) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX SDR mode 13.33 20 26.66 12 tc(OUTCLK) Cycletime,CH n_CLK ns DDR mode 26.66 40 53.33 SDR mode 5 8 10 13 tw(OUTCLKH) Pulsewidth,CH n_CLK high ns DDR mode 10 16 20 SDR mode 5 8 10 14 tw(OUTCLKL) Pulsewidth,CH n_CLK low ns DDR mode 10 16 20 15 td(OUTCLKH-STV) Delaytime,CH n_START validafterCH n_CLK high 2 11 2 15 2 21 ns 16 td(OUTCLKH-ENV) Delaytime,CH n_ENABLE validafterCH n_CLK high 2 11 2 15 2 21 ns 17 td(OUTCLKH-DV) Delaytime,CH n_DATA/XDATA validafterCH n_CLK high 2 11 2 15 2 21 ns 18 td(OUTCLKL-DV) Delaytime,CH n_DATA/XDATA validafterCH n_CLK low 2 11 2 15 2 21 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted.

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Q1 I2 I3 I4 I5 I6 I7 I8 I9Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 CHx_CLK CHx_ST ART CHx_ENABLE CHx_DA T A[n:0] CHx_XDA T A[n:0] CHx_WAIT CHx_CLK CHx_ST ART CHx_ENABLE CHx_DA T A[n:0] CHx_XDA T A[n:0] Data2Data1 Data3 Data4 CHx_WAIT Data5 Data6 Data7 Data8 Data9 OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-72.uPP SingleData Rate (SDR) Receive Timing Figure5-73.uPP Double Data Rate (DDR) Receive Timing Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 239 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

Q1 I2 I3 I4 I5 I6 I7 I8 I9Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 CHx_CLK CHx_ST ART CHx_ENABLE CHx_DA T A[n:0] CHx_XDA T A[n:0] CHx_WAIT Data2Data1 Data3 Data4 Data5 Data6 Data7 Data8 Data9 2019 CHx_CLK CHx_ST ART CHx_ENABLE CHx_DA T A[n:0] CHx_XDA T A[n:0] CHx_WAIT OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-74.uPP SingleData Rate (SDR) TransmitTiming Figure5-75.uPP Double Data Rate (DDR) TransmitTiming

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5.27 Video PortInterface(VPIF)

The VideoPortInterface(VPIF)allowsthecaptureand displayofdigitalvideostreams.Featuresinclude:

Up to2 VideoCaptureChannels(Channel0 and Channel1) – Two 8-bitStandard-Definition(SD)Videowithembedded timingcodes (BT.656) – Single16-bitHigh-Definition(HD) Videowithembedded timingcodes (BT.1120) – SingleRaw Video(8-/10-/12-bit)
Up to2 VideoDisplayChannels(Channel2 and Channel3) – Two 8-bitSD VideoDisplaywithembedded timingcodes (BT.656) – Single16-bitHD VideoDisplaywithembedded timingcodes (BT.1120) The VPIF capturechannelinputdataformatisselectablebased on thesettingsofthespecificChannel ControlRegister(Channels0–3).The VPIF Raw Videodata-buswidthisselectablebased on thesettings oftheChannel0 ControlRegister. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 241 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.27.1 VPIF RegisterDescriptions

Table5-120shows theVPIF registers. Table5-120.Video PortInterface(VPIF)Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E1 7000 PID Peripheralidentificationregister 0x01E1 7004 CH0_CTRL Channel0 controlregister 0x01E1 7008 CH1_CTRL Channel1 controlregister 0x01E1 700C CH2_CTRL Channel2 controlregister 0x01E1 7010 CH3_CTRL Channel3 controlregister 0x01E1 7014 -0x01E1 701F - Reserved 0x01E1 7020 INTEN Interruptenable 0x01E1 7024 INTENSET Interruptenableset 0x01E1 7028 INTENCLR Interruptenableclear 0x01E1 702C INTSTAT Interruptstatus 0x01E1 7030 INTSTATCLR Interruptstatusclear 0x01E1 7034 EMU_CTRL Emulationcontrol 0x01E1 7038 DMA_SIZE DMA sizecontrol 0x01E1 703C -0x01E1 703F - Reserved CAPTURE CHANNEL 0 REGISTERS 0x01E1 7040 CH0_TY_STRTADR Channel0 Top Fieldluma bufferstartaddress 0x01E1 7044 CH0_BY_STRTADR Channel0 BottomFieldluma bufferstartaddress 0x01E1 7048 CH0_TC_STRTADR Channel0 Top Fieldchroma bufferstartaddress 0x01E1 704C CH0_BC_STRTADR Channel0 BottomFieldchroma bufferstartaddress 0x01E1 7050 CH0_THA_STRTADR Channel0 Top Fieldhorizontalancillarydatabufferstartaddress 0x01E1 7054 CH0_BHA_STRTADR Channel0 BottomFieldhorizontalancillarydatabufferstartaddress 0x01E1 7058 CH0_TVA_STRTADR Channel0 Top Fieldverticalancillarydatabufferstartaddress 0x01E1 705C CH0_BVA_STRTADR Channel0 BottomFieldverticalancillarydatabufferstartaddress 0x01E1 7060 CH0_SUBPIC_CFG Channel0 sub-pictureconfiguration 0x01E1 7064 CH0_IMG_ADD_OFST Channel0 image dataaddressoffset 0x01E1 7068 CH0_HA_ADD_OFST Channel0 horizontalancillarydataaddressoffset 0x01E1 706C CH0_HSIZE_CFG Channel0 horizontaldatasizeconfiguration 0x01E1 7070 CH0_VSIZE_CFG0 Channel0 verticaldatasizeconfiguration(0) 0x01E1 7074 CH0_VSIZE_CFG1 Channel0 verticaldatasizeconfiguration(1) 0x01E1 7078 CH0_VSIZE_CFG2 Channel0 verticaldatasizeconfiguration(2) 0x01E1 707C CH0_VSIZE Channel0 verticalimage size CAPTURE CHANNEL 1 REGISTERS 0x01E1 7080 CH1_TY_STRTADR Channel1 Top Fieldluma bufferstartaddress 0x01E1 7084 CH1_BY_STRTADR Channel1 BottomFieldluma bufferstartaddress 0x01E1 7088 CH1_TC_STRTADR Channel1 Top Fieldchroma bufferstartaddress 0x01E1 708C CH1_BC_STRTADR Channel1 BottomFieldchroma bufferstartaddress 0x01E1 7090 CH1_THA_STRTADR Channel1 Top Fieldhorizontalancillarydatabufferstartaddress 0x01E1 7094 CH1_BHA_STRTADR Channel1 BottomFieldhorizontalancillarydatabufferstartaddress 0x01E1 7098 CH1_TVA_STRTADR Channel1 Top Fieldverticalancillarydatabufferstartaddress 0x01E1 709C CH1_BVA_STRTADR Channel1 BottomFieldverticalancillarydatabufferstartaddress 0x01E1 70A0 CH1_SUBPIC_CFG Channel1 sub-pictureconfiguration 0x01E1 70A4 CH1_IMG_ADD_OFST Channel1 image dataaddressoffset 0x01E1 70A8 CH1_HA_ADD_OFST Channel1 horizontalancillarydataaddressoffset 0x01E1 70AC CH1_HSIZE_CFG Channel1 horizontaldatasizeconfiguration

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-120.Video PortInterface(VPIF)Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E1 70B0 CH1_VSIZE_CFG0 Channel1 verticaldatasizeconfiguration(0) 0x01E1 70B4 CH1_VSIZE_CFG1 Channel1 verticaldatasizeconfiguration(1) 0x01E1 70B8 CH1_VSIZE_CFG2 Channel1 verticaldatasizeconfiguration(2) 0x01E1 70BC CH1_VSIZE Channel1 verticalimage size DISPLAY CHANNEL 2 REGISTERS 0x01E1 70C0 CH2_TY_STRTADR Channel2 Top Fieldluma bufferstartaddress 0x01E1 70C4 CH2_BY_STRTADR Channel2 BottomFieldluma bufferstartaddress 0x01E1 70C8 CH2_TC_STRTADR Channel2 Top Fieldchroma bufferstartaddress 0x01E1 70CC CH2_BC_STRTADR Channel2 BottomFieldchroma bufferstartaddress 0x01E1 70D0 CH2_THA_STRTADR Channel2 Top Fieldhorizontalancillarydatabufferstartaddress 0x01E1 70D4 CH2_BHA_STRTADR Channel2 BottomFieldhorizontalancillarydatabufferstartaddress 0x01E1 70D8 CH2_TVA_STRTADR Channel2 Top Fieldverticalancillarydatabufferstartaddress 0x01E1 70DC CH2_BVA_STRTADR Channel2 BottomFieldverticalancillarydatabufferstartaddress 0x01E1 70E0 CH2_SUBPIC_CFG Channel2 sub-pictureconfiguration 0x01E1 70E4 CH2_IMG_ADD_OFST Channel2 image dataaddressoffset 0x01E1 70E8 CH2_HA_ADD_OFST Channel2 horizontalancillarydataaddressoffset 0x01E1 70EC CH2_HSIZE_CFG Channel2 horizontaldatasizeconfiguration 0x01E1 70F0 CH2_VSIZE_CFG0 Channel2 verticaldatasizeconfiguration(0) 0x01E1 70F4 CH2_VSIZE_CFG1 Channel2 verticaldatasizeconfiguration(1) 0x01E1 70F8 CH2_VSIZE_CFG2 Channel2 verticaldatasizeconfiguration(2) 0x01E1 70FC CH2_VSIZE Channel2 verticalimage size 0x01E1 7100 CH2_THA_STRTPOS Channel2 Top Fieldhorizontalancillarydatainsertionstartposition 0x01E1 7104 CH2_THA_SIZE Channel2 Top Fieldhorizontalancillarydatasize 0x01E1 7108 CH2_BHA_STRTPOS Channel2 BottomFieldhorizontalancillarydatainsertionstartposition 0x01E1 710C CH2_BHA_SIZE Channel2 BottomFieldhorizontalancillarydatasize 0x01E1 7110 CH2_TVA_STRTPOS Channel2 Top Fieldverticalancillarydatainsertionstartposition 0x01E1 7114 CH2_TVA_SIZE Channel2 Top Fieldverticalancillarydatasize 0x01E1 7118 CH2_BVA_STRTPOS Channel2 BottomFieldverticalancillarydatainsertionstartposition 0x01E1 711C CH2_BVA_SIZE Channel2 BottomFieldverticalancillarydatasize 0x01E1 7120 -0x01E1 713F - Reserved DISPLAY CHANNEL 3 REGISTERS 0x01E1 7140 CH3_TY_STRTADR Channel3 Field0 luma bufferstartaddress 0x01E1 7144 CH3_BY_STRTADR Channel3 Field1 luma bufferstartaddress 0x01E1 7148 CH3_TC_STRTADR Channel3 Field0 chroma bufferstartaddress 0x01E1 714C CH3_BC_STRTADR Channel3 Field1 chroma bufferstartaddress 0x01E1 7150 CH3_THA_STRTADR Channel3 Field0 horizontalancillarydatabufferstartaddress 0x01E1 7154 CH3_BHA_STRTADR Channel3 Field1 horizontalancillarydatabufferstartaddress 0x01E1 7158 CH3_TVA_STRTADR Channel3 Field0 verticalancillarydatabufferstartaddress 0x01E1 715C CH3_BVA_STRTADR Channel3 Field1 verticalancillarydatabufferstartaddress 0x01E1 7160 CH3_SUBPIC_CFG Channel3 sub-pictureconfiguration 0x01E1 7164 CH3_IMG_ADD_OFST Channel3 image dataaddressoffset 0x01E1 7168 CH3_HA_ADD_OFST Channel3 horizontalancillarydataaddressoffset 0x01E1 716C CH3_HSIZE_CFG Channel3 horizontaldatasizeconfiguration 0x01E1 7170 CH3_VSIZE_CFG0 Channel3 verticaldatasizeconfiguration(0) 0x01E1 7174 CH3_VSIZE_CFG1 Channel3 verticaldatasizeconfiguration(1) 0x01E1 7178 CH3_VSIZE_CFG2 Channel3 verticaldatasizeconfiguration(2) 0x01E1 717C CH3_VSIZE Channel3 verticalimage size Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 243 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-120.Video PortInterface(VPIF)Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E1 7180 CH3_THA_STRTPOS Channel3 Top Fieldhorizontalancillarydatainsertionstartposition 0x01E1 7184 CH3_THA_SIZE Channel3 Top Fieldhorizontalancillarydatasize 0x01E1 7188 CH3_BHA_STRTPOS Channel3 BottomFieldhorizontalancillarydatainsertionstartposition 0x01E1 718C CH3_BHA_SIZE Channel3 BottomFieldhorizontalancillarydatasize 0x01E1 7190 CH3_TVA_STRTPOS Channel3 Top Fieldverticalancillarydatainsertionstartposition 0x01E1 7194 CH3_TVA_SIZE Channel3 Top Fieldverticalancillarydatasize 0x01E1 7198 CH3_BVA_STRTPOS Channel3 BottomFieldverticalancillarydatainsertionstartposition 0x01E1 719C CH3_BVA_SIZE Channel3 BottomFieldverticalancillarydatasize 0x01E1 71A0 -0x01E1 71FF - Reserved

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5.27.2 VPIF ElectricalData/Timing

Table5-121.Timing Requirements forVPIF VP_CLKINx Inputs(1)(2)(seeFigure5-76) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX Cycletime,VP_CLKIN0 13.3 20 37 ns 1 tc(VKI) Cycletime,VP_CLKIN1/2/3 13.3 20 37 ns 2 tw(VKIH) Pulseduration,VP_CLKINx high 0.4C 0.4C 0.4C ns 3 tw(VKIL) Pulseduration,VP_CLKINx low 0.4C 0.4C 0.4C ns 4 tt(VKI) Transitiontime,VP_CLKINx 5 5 5 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) C = VP_CLKINx periodinns. Figure5-76.Video PortCapture VP_CLKINx Timing Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 245 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

VP_CLKOUTx (Positive□Edge Clocking) VP_CLKOUTx (Negative□Edge Clocking) VP_DOUTx 11 12 VP_CLKIN0/1 VP_DINx/FIELD/ HSYNC/VSYNC OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-122.Timing Requirements forVPIF Channels 0/1Video Capture Data and ControlInputs (seeFigure5-77) 1.3V 1.2V 1.1V 1.0V NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX MIN MAX tsu(VDINV-1 Setuptime,VP_DINx validbeforeVP_OSCIN0/1 high 4 4 6 7 ns VKIH) 2 th(VKIH-VDINV) Holdtime,VP_DINx validafterVP_CLKIN0/1 high 0.5 0 0 0 ns Figure5-77.VPIF Channels 0/1Video Capture Data and ControlInputTiming Table5-123.SwitchingCharacteristicsOver Recommended OperatingConditionsforVideo Data Shown With Respect toVP_CLKOUT2/3 (1)(2) (seeFigure5-78) NO. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 1 tc(VKO) Cycletime,VP_CLKOUT2/3 13.3 20 37 ns 2 tw(VKOH) Pulseduration,VP_CLKOUT2/3 high 0.4C 0.4C 0.4C ns 3 tw(VKOL) Pulseduration,VP_CLKOUT2/3 low 0.4C 0.4C 0.4C ns 4 tt(VKO) Transitiontime,VP_CLKOUT2/3 5 5 5 ns Delaytime,11 td(VKOH-VPDOUTV) 8.5 12 17 nsVP_CLKOUT2/3 hightoVP_DOUTx valid Delaytime,12 td(VCLKOH-VPDOUTIV) 1.5 1.5 1.5 nsVP_CLKOUT2/3 hightoVP_DOUTx invalid (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) C = VP_CLKO2/3 periodinns. Figure5-78.VPIF Channels 2/3Video DisplayData Output Timing With Respect toVP_CLKOUT2/3

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5.28 Enhanced Capture (eCAP) Peripheral

The devicecontainsup tothreeenhanced capture(eCAP) modules.Figure5-79shows a functionalblock diagramofa module. Uses forECAP include:

Speed measurements ofrotatingmachinery(e.g.toothedsprocketssensed viaHallsensors)
Elapsedtimemeasurements between positionsensortriggers
Periodand dutycyclemeasurements ofpulsetrainsignals
Decodingcurrentorvoltageamplitudederivedfromdutycycleencoded current/voltagesensors The ECAP module describedinthisspecificationincludesthefollowingfeatures:
32 bittimebase
4 eventtime-stampregisters(each32 bits)
Edge polarityselectionforup to4 sequenced time-stampcaptureevents
Interrupton eitherofthe4 events
Singleshotcaptureofup to4 eventtime-stamps
Continuousmode captureoftime-stampsina 4 deep circularbuffer
Absolutetime-stampcapture
Differencemode time-stampcapture
Alltheabove resourcesarededicatedtoa singleinputpin The eCAP modules areclockedattheASYNC3 clockdomain rate. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 247 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

(counter−32 bit) RST CAP1 (APRD active) LD CAP2 (ACMP active) LD CAP3 (APRD shadow) LD CAP4 (ACMP shadow) LD Continuous / Oneshot Capture Control LD1 LD2 LD3 LD4 PRD [0−31] CMP [0−31] CTR [0−31] eCAPx Interrupt Trigger and Flag control to Interrupt Controller CTR=CMP ACMP shadow Event Pre-scale CTRPHS (phase register−32 bit) SYNCOut SYNCIn Event qualifier Polarity select Polarity select Polarity select Polarity select CTR=PRD CTR_OVF PWM compare logic CTR [0−31] PRD [0−31] CMP [0−31] CTR=CMP CTR=PRD CTR_OVFOVF APWM mode Delta−mode SYNC 4Capture events CEVT[1:4] APRD shadow MODE SELECT OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Figure5-79.eCAP FunctionalBlock Diagram

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-124isthelistoftheECAP registers. Table5-124.ECAPx ConfigurationRegisters ECAP0 ECAP1 ECAP2 ACRONYM DESCRIPTIONBYTE ADDRESS BYTE ADDRESS BYTE ADDRESS 0x01F0 6000 0x01F0 7000 0x01F0 8000 TSCTR Time-Stamp Counter 0x01F0 6004 0x01F0 7004 0x01F0 8004 CTRPHS CounterPhase OffsetValueRegister 0x01F0 6008 0x01F0 7008 0x01F0 8008 CAP1 Capture1 Register 0x01F0 600C 0x01F0 700C 0x01F0 800C CAP2 Capture2 Register 0x01F0 6010 0x01F0 7010 0x01F0 8010 CAP3 Capture3 Register 0x01F0 6014 0x01F0 7014 0x01F0 8014 CAP4 Capture4 Register 0x01F0 6028 0x01F0 7028 0x01F0 8028 ECCTL1 CaptureControlRegister1 0x01F0 602A 0x01F0 702A 0x01F0 802A ECCTL2 CaptureControlRegister2 0x01F0 602C 0x01F0 702C 0x01F0 802C ECEINT CaptureInterruptEnableRegister 0x01F0 602E 0x01F0 702E 0x01F0 802E ECFLG CaptureInterruptFlagRegister 0x01F0 6030 0x01F0 7030 0x01F0 8030 ECCLR CaptureInterruptClearRegister 0x01F0 6032 0x01F0 7032 0x01F0 8032 ECFRC CaptureInterruptForceRegister 0x01F0 605C 0x01F0 705C 0x01F0 805C REVID RevisionID Table 5-125 shows the eCAP timingrequirementand Table 5-126 shows the eCAP switching characteristics. Table5-125.Timing Requirements forEnhanced Capture (eCAP)(1) PARAMETER TEST CONDITIONS UNIT MIN MAX tw(CAP) Captureinputpulsewidth Asynchronous cycle2tc(SCO) s Synchronous cycle2tc(SCO) s (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Table5-126.SwitchingCharacteristicsOver Recommended OperatingConditionsforeCAP (1) PARAMETER UNIT MIN MAX MIN MAX MIN MAX tw(APWM) Pulseduration,APWMx 20 20 20 ns outputhigh/low (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 249 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

Peripheral□Bus ePWM0 module ePWM1 module EPWM0SYNCI EPWM1SYNCI EPWM1SYNCO GPIO MUX EPWMSYNCI EPWM1A EPWM1B EPWM0A EPWM0B EPWM0INT EPWM1INT TZ TZ EPWM0SYNCOInterrupt Controllers EPWMSYNCOTo□eCAP0 module (sync□in) OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com

5.29 Enhanced High-ResolutionPulse-WidthModulator(eHRPWM)

The devicecontainstwo enhanced PWM Modules (eHRPWM). Figure5-80 shows a blockdiagram of multipleeHRPWM modules.Figure5-80shows thesignalinterconnectionswiththeeHRPWM. Figure5-80.MultiplePWM Modules ina OMAPL138 System

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CTR=PRD TBPRD shadow (16) TBPRD active (16) Counter up/down (16 bit) TBCNT active (16) TBCTL[CNTLDE] TBCTL[SWFSYNC] (software forced sync) EPWMSYNCI CTR=ZERO CTR_Dir CTR=CMPB Disabled Sync in/out select Mux TBCTL[SYNCOSEL] EPWMSYNCO TBPHS active (24) 16 8 TBPHSHR (8) Phase control Time−base (TB) CTR=CMPA CMP A active (24) CMP A shadow (24) Action qualifier (AQ) Counter compare (CC) CMPB active (16) CTR=CMPB CMPB shadow (16) CMP AHR (8) EPWMA EPWMB Dead band (DB) (PC) chopper PWM zone (TZ) Trip CTR = ZERO EPWMxA EPWMxB EPWMxTZINT TZ HiRes PWM (HRPWM) CTR = PRD CTR = ZERO CTR = CMPB CTR = CMP A CTR_Dir Event trigger and interrupt (ET) EPWMxINT CTR=ZERO OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Figure5-81.eHRPWM Sub-Modules Showing CriticalInternalSignalInterconnections Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 251 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-127.eHRPWM Module Controland StatusRegistersGrouped by Submodule eHRPWM0 eHRPWM1 BYTE ADDRESS BYTE ADDRESS ACRONYM SHADOW REGISTER DESCRIPTION Time-Base Submodule Registers 0x01F0 0000 0x01F0 2000 TBCTL No Time-BaseControlRegister 0x01F0 0002 0x01F0 2002 TBSTS No Time-BaseStatusRegister 0x01F0 0004 0x01F0 2004 TBPHSHR No ExtensionforHRPWM Phase Register(1) 0x01F0 0006 0x01F0 2006 TBPHS No Time-BasePhase Register 0x01F0 0008 0x01F0 2008 TBCNT No Time-BaseCounterRegister 0x01F0 000A 0x01F0 200A TBPRD Yes Time-BasePeriodRegister Counter-Compare Submodule Registers 0x01F0 000E 0x01F0 200E CMPCTL No Counter-CompareControlRegister 0x01F0 0010 0x01F0 2010 CMPAHR No ExtensionforHRPWM Counter-CompareA Register(1) 0x01F0 0012 0x01F0 2012 CMPA Yes Counter-CompareA Register 0x01F0 0014 0x01F0 2014 CMPB Yes Counter-CompareB Register Action-QualifierSubmodule Registers 0x01F0 0016 0x01F0 2016 AQCTLA No Action-QualifierControlRegisterforOutputA (eHRPWMxA) 0x01F0 0018 0x01F0 2018 AQCTLB No Action-QualifierControlRegisterforOutputB (eHRPWMxB) 0x01F0 001A 0x01F0 201A AQSFRC No Action-QualifierSoftwareForceRegister 0x01F0 001C 0x01F0 201C AQCSFRC Yes Action-QualifierContinuousS/W ForceRegisterSet Dead-Band GeneratorSubmodule Registers 0x01F0 001E 0x01F0 201E DBCTL No Dead-Band GeneratorControlRegister 0x01F0 0020 0x01F0 2020 DBRED No Dead-Band GeneratorRisingEdge DelayCount Register 0x01F0 0022 0x01F0 2022 DBFED No Dead-Band GeneratorFallingEdge DelayCount Register PWM-Chopper Submodule Registers 0x01F0 003C 0x01F0 203C PCCTL No PWM-Chopper ControlRegister Trip-ZoneSubmodule Registers 0x01F0 0024 0x01F0 2024 TZSEL No Trip-ZoneSelectRegister 0x01F0 0028 0x01F0 2028 TZCTL No Trip-ZoneControlRegister 0x01F0 002A 0x01F0 202A TZEINT No Trip-ZoneEnableInterruptRegister 0x01F0 002C 0x01F0 202C TZFLG No Trip-ZoneFlagRegister 0x01F0 002E 0x01F0 202E TZCLR No Trip-ZoneClearRegister 0x01F0 0030 0x01F0 2030 TZFRC No Trip-ZoneForceRegister Event-TriggerSubmodule Registers 0x01F0 0032 0x01F0 2032 ETSEL No Event-TriggerSelectionRegister 0x01F0 0034 0x01F0 2034 ETPS No Event-TriggerPre-ScaleRegister 0x01F0 0036 0x01F0 2036 ETFLG No Event-TriggerFlagRegister 0x01F0 0038 0x01F0 2038 ETCLR No Event-TriggerClearRegister 0x01F0 003A 0x01F0 203A ETFRC No Event-TriggerForceRegister High-ResolutionPWM (HRPWM) Submodule Registers 0x01F0 1040 0x01F0 3040 HRCNFG No HRPWM ConfigurationRegister(1) (1) These registersareonlyavailableon eHRPWM instancesthatincludethehigh-resolutionPWM (HRPWM) extension;otherwise,these locationsarereserved.

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5.29.1 Enhanced Pulse Width Modulator(eHRPWM) Timing

PWM refersto PWM outputson eHRPWM1-6. Table 5-128 shows the PWM timingrequirementsand Table5-129,switchingcharacteristics. Table5-128.Timing Requirements foreHRPWM (1) PARAMETER TEST CONDITIONS 1.3V,1.2V,1.1V,1.0V UNIT MIN MAX tw(SYNCIN) Sync inputpulsewidth Asynchronous 2tc(SCO) cycles Synchronous 2tc(SCO) cycles (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Table5-129.SwitchingCharacteristicsOver Recommended OperatingConditionsforeHRPWM (1) PARAMETER TEST 1.3V,1.2V 1.1V 1.0V UNITCONDITIONS MIN MAX MIN MAX MIN MAX tw(PWM) Pulseduration,PWMx output ns20 20 26.6high/low tw(SYNCOUT) Sync outputpulsewidth 8tc(SCO) 8tc(SCO) 8tc(SCO) cycles td(PWM)TZA Delaytime,tripinputactiveto no pinload;no ns PWM forcedhigh additional 25 25 25Delaytime,tripinputactiveto programmable PWM forcedlow delay td(TZ-PWM)HZ Delaytime,tripinputactiveto no additional ns PWM Hi-Z programmable 20 20 20 delay (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 253 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

PWM (A) TZ tw(TZ) td(TZ-PWM)HZ OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com

5.29.2 Trip-ZoneInputTiming

A. PWM referstoallthePWM pinsinthedevice.The stateofthePWM pinsafterTZ istakenhighdepends on thePWM recoverysoftware. Figure5-82.PWM Hi-ZCharacteristics Table5-130.Trip-ZoneinputTiming Requirements(1) PARAMETER TEST CONDITIONS 1.3V,1.2V,1.1V,1.0V UNIT MIN MAX tw(TZ) Pulseduration,TZx inputlow Asynchronous 1tc(SCO) cycles Synchronous 2tc(SCO) cycles (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Table5-131shows thehigh-resolutionPWM switchingcharacteristics. Table5-131.High ResolutionPWM CharacteristicsatSYSCLKOUT = (60-100 MHz) (1) PARAMETER 1.3V,1.2V 1.1V 1.0V UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX MicroEdge Positioning(MEP) stepsize(2) 200 200 200 ps (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) MEP stepsizewillincreasewithlowvoltageand hightemperatureand decreasewithhighvoltageand coldtemperature.

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5.30 Timers

The timerssupportthefollowingfeatures:

Configurableas single64-bittimerortwo 32-bittimers
Periodtimeoutsgenerateinterrupts,DMA eventsorexternalpinevents
8 32-bitcompare registers
Compare matches generateinterruptevents
Capturecapability
64-bitWatchdog capability(Timer64P1only) Table5-132liststhetimerregisters. Table5-132.Timer Registers TIMER64P 0 TIMER64P 1 TIMER64P 2 TIMER64P 3 ACRONYM REGISTER DESCRIPTION BYTE BYTE BYTE BYTE ADDRESS ADDRESS ADDRESS ADDRESS 0x01C2 0000 0x01C2 1000 0x01F0 C000 0x01F0 D000 REV RevisionRegister 0x01C2 0004 0x01C2 1004 0x01F0 C004 0x01F0 D004 EMUMGT EmulationManagement Register 0x01C2 0008 0x01C2 1008 0x01F0 C008 0x01F0 D008 GPINTGPEN GPIO Interruptand GPIO EnableRegister 0x01C2 000C 0x01C2 100C 0x01F0 C00C 0x01F0 D00C GPDATGPDIR GPIO Data and GPIO DirectionRegister 0x01C2 0010 0x01C2 1010 0x01F0 C010 0x01F0 D010 TIM12 TimerCounterRegister12 0x01C2 0014 0x01C2 1014 0x01F0 C014 0x01F0 D014 TIM34 TimerCounterRegister34 0x01C2 0018 0x01C2 1018 0x01F0 C018 0x01F0 D018 PRD12 TimerPeriodRegister12 0x01C2 001C 0x01C2 101C 0x01F0 C01C 0x01F0 D01C PRD34 TimerPeriodRegister34 0x01C2 0020 0x01C2 1020 0x01F0 C020 0x01F0 D020 TCR TimerControlRegister 0x01C2 0024 0x01C2 1024 0x01F0 C024 0x01F0 D024 TGCR TimerGlobalControlRegister 0x01C2 0028 0x01C2 1028 0x01F0 C028 0x01F0 D028 WDTCR Watchdog TimerControlRegister 0x01C2 0034 0x01C2 1034 0x01F0 C034 0x01F0 D034 REL12 TimerReloadRegister12 0x01C2 0038 0x01C2 1038 0x01F0 C038 0x01F0 D038 REL34 TimerReloadRegister34 0x01C2 003C 0x01C2 103C 0x01F0 C03C 0x01F0 D03C CAP12 TimerCaptureRegister12 0x01C2 0040 0x01C2 1040 0x01F0 C040 0x01F0 D040 CAP34 TimerCaptureRegister34 0x01C2 0044 0x01C2 1044 0x01F0 C044 0x01F0 D044 INTCTLSTAT TimerInterruptControland StatusRegister 0x01C2 0060 0x01C2 1060 0x01F0 C060 0x01F0 D060 CMP0 Compare Register0 0x01C2 0064 0x01C2 1064 0x01F0 C064 0x01F0 D064 CMP1 Compare Register1 0x01C2 0068 0x01C2 1068 0x01F0 C068 0x01F0 D068 CMP2 Compare Register2 0x01C2 006C 0x01C2 106C 0x01F0 C06C 0x01F0 D06C CMP3 Compare Register3 0x01C2 0070 0x01C2 1070 0x01F0 C070 0x01F0 D070 CMP4 Compare Register4 0x01C2 0074 0x01C2 1074 0x01F0 C074 0x01F0 D074 CMP5 Compare Register5 0x01C2 0078 0x01C2 1078 0x01F0 C078 0x01F0 D078 CMP6 Compare Register6 0x01C2 007C 0x01C2 107C 0x01F0 C07C 0x01F0 D07C CMP7 Compare Register7 Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 255 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

TM64P0_OUT12 5 6 TM64P0_IN12 OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com

5.30.1 Timer ElectricalData/Timing

Table5-133.Timing Requirements forTimer Input(1)(2)(3)(seeFigure5-83) NO. PARAMETER UNIT MIN MAX 1 tc(TM64Px_IN12) Cycletime,TM64Px_IN12 4P ns 2 tw(TINPH) Pulseduration,TM64Px_IN12 high 0.45C 0.55C ns 3 tw(TINPL) Pulseduration,TM64Px_IN12 low 0.45C 0.55C ns 0.25Por104 tt(TM64Px_IN12) Transitiontime,TM64Px_IN12 ns(4) (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) P = OSCIN cycletimeinns. (3) C = TM64P0_IN12 cycletimeinns. (4) Whicheverissmaller.P = theperiodoftheappliedsignal.Maintainingtransitiontimesas fastas possibleisrecommended toimprove noiseimmunityon inputsignals. Figure5-83.Timer Timing Table5-134.SwitchingCharacteristicsOver Recommended OperatingConditionsforTimer Output(1)(2) NO. PARAMETER UNIT MIN MAX 5 tw(TOUTH) Pulseduration,TM64P0_OUT12 high 4P ns 6 tw(TOUTL) Pulseduration,TM64P0_OUT12 low 4P ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) P = OSCIN cycletimeinns.Forexample,when OSCIN frequencyis27 MHz, use P = 37.037 ns. Figure5-84.Timer Timing

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Seconds Minutes Hours Days Months Years Alarm Timer Alarm Interrupts Periodic Interrupts Counter 32□kHz Oscillator Compensation Week Days Oscillator RTC_XI XTAL RTC_XO OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013

5.31 Real Time Clock (RTC)

The RTC providesa timereferencetoan applicationrunningon thedevice.The currentdateand timeis trackedina setofcounterregistersthatupdateonce persecond.The timecan be representedin12-hour or24-hourmode. The calendarand timeregistersarebufferedduringreadsand writesso thatupdatesdo notinterferewiththeaccuracyofthetimeand date. Alarms are availabletointerrupttheCPU ata particulartime,or atperiodictimeintervals,such as once perminuteoronce perday.Inaddition,theRTC can interrupttheCPU everytimethecalendarand time registersareupdated,oratprogrammableperiodicintervals. The real-timeclock(RTC) providesthefollowingfeatures:

100-yearcalendar(xx00toxx99)
Countsseconds,minutes,hours,day oftheweek,date,month,and yearwithleapyearcompensation
Binary-coded-decimal(BCD) representationoftime,calendar,and alarm
12-hourclockmode (withAM and PM) or24-hourclockmode
Alarminterrupt
Periodicinterrupt
SingleinterrupttotheCPU
Supportsexternal32.768-kHzcrystalorexternalclocksourceofthesame frequency
Separateisolatedpower supply Figure5-85shows a blockdiagramoftheRTC. Figure5-85.Real-TimeClock Block Diagram Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 257 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

32.768 kHz RTC_XI RTC_XO RTC_VSS 32K OSC Real Time Clock (RTC) Module Isolated RTC Power Domain CVDD RTC_CVDD RTC Power Source OMAPL138B-EP SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com

5.31.1 Clock Source

The clockreferencefortheRTC isan external32.768-kHzcrystaloran externalclocksourceofthesame frequency.The RTC alsohas a separatepower supplythatisisolatedfromtherestofthesystem.When theCPU and otherperipheralsare withoutpower,theRTC can remainpowered topreservethecurrent timeand calendarinformation.Even iftheRTC isnotused,itmust remainpowered when therestofthe deviceispowered. The sourcefortheRTC referenceclockmay be providedby a crystalorby an externalclocksource.The RTC has an internaloscillatorbuffertosupportdirectoperationwitha crystal.The crystalisconnected between pinsRTC_XI and RTC_XO. RTC_XI isthe inputto the on-chiposcillatorand RTC_XO isthe outputfromtheoscillatorback tothecrystal. An external32.768-kHzclocksourcemay be used insteadofa crystal.Insuch a case,theclocksourceis connectedtoRTC_XI, and RTC_XO isleftunconnected. Ifthe RTC is not used, the RTC_XI pin should be held eitherlow or high,RTC_XO should be left unconnected,RTC_CVDD should be connected to the deviceCVDD and RTC_VSS should remain grounded. Figure5-86.Clock Source

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5.31.2 Real-TimeClock RegisterDescriptions

Table5-135.Real-TimeClock (RTC) Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C2 3000 SECOND Seconds Register 0x01C2 3004 MINUTE MinutesRegister 0x01C2 3008 HOUR Hours Register 0x01C2 300C DAY Day oftheMonth Register 0x01C2 3010 MONTH Month Register 0x01C2 3014 YEAR Year Register 0x01C2 3018 DOTW Day oftheWeek Register 0x01C2 3020 ALARMSECOND AlarmSeconds Register 0x01C2 3024 ALARMMINUTE AlarmMinutesRegister 0x01C2 3028 ALARMHOUR AlarmHours Register 0x01C2 302C ALARMDAY AlarmDays Register 0x01C2 3030 ALARMMONTH AlarmMonths Register 0x01C2 3034 ALARMYEAR AlarmYearsRegister 0x01C2 3040 CTRL ControlRegister 0x01C2 3044 STATUS StatusRegister 0x01C2 3048 INTERRUPT InterruptEnableRegister 0x01C2 304C COMPLSB Compensation(LSB)Register 0x01C2 3050 COMPMSB Compensation(MSB) Register 0x01C2 3054 OSC OscillatorRegister 0x01C2 3060 SCRATCH0 Scratch0 (General-Purpose)Register 0x01C2 3064 SCRATCH1 Scratch1 (General-Purpose)Register 0x01C2 3068 SCRATCH2 Scratch2 (General-Purpose)Register 0x01C2 306C KICK0 Kick0 (WriteProtect)Register 0x01C2 3070 KICK1 Kick1 (WriteProtect)Register Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 259 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.32 General-PurposeInput/Output(GPIO)

The GPIO peripheralprovidesgeneral-purposepinsthatcan be configuredas eitherinputsor outputs. When configuredas an output,a writetoan internalregistercan controlthestatedrivenon theoutputpin. When configuredas an input,the stateof the inputisdetectableby readingthe stateof an internal register.In addition,the GPIO peripheralcan produce CPU interruptsand EDMA events in different interrupt/eventgenerationmodes. The GPIO peripheralprovidesgenericconnectionstoexternaldevices. The GPIO pinsaregroupedintobanks of16 pinsperbank (i.e.,bank 0 consistsofGPIO [0:15]). The deviceGPIO peripheralsupportsthefollowing:

Up to144 Pinsconfigurableas GPIO
ExternalInterruptand DMA requestCapability – Every GPIO pinmay be configuredtogeneratean interruptrequeston detectionofrisingand/or fallingedges on thepin. – The interruptrequestswithineach bank arecombined (logicalor)tocreateeightuniquebank level interruptrequests. – The bank levelinterruptserviceroutinemay polltheINTSTATx registerforitsbank todetermine whichpin(s)have triggeredtheinterrupt. – GPIO Banks 0,1,2,3,4,5,6,7,and 8 InterruptsassignedtoARM INTC InterruptRequests 42, 43,44,45,46,47,48,49,and 50 respectively – GPIO Banks 0,1,2,3,4,5,6,7,and 8 InterruptsassignedtoDSP Events65,41,49,52,54,59, 62,72,and 75 respectively – GPIO Banks 0, 1, 2, 3, 4, and 5 are assignedto EDMA events6, 7, 22, 23, 28, 29, and 29 respectivelyon Channel Controller0 and GPIO Banks 6,7,and 8 are assignedtoEDMA events 16,17,and 18 respectivelyon ChannelController1.
Set/clearfunctionality:Firmware writes1 to correspondingbitposition(s)to set or to clearGPIO signal(s).ThisallowsmultiplefirmwareprocessestotoggleGPIO outputsignalswithoutcriticalsection protection(disableinterrupts,program GPIO, re-enableinterrupts,to preventcontextswitchingto antherprocessduringGPIO programming).
SeparateInput/Outputregisters
Outputregisterinadditiontoset/clearso that,ifpreferredby firmware,some GPIO outputsignalscan be toggledby directwritetotheoutputregister(s).
Outputregister,when read,reflectsoutputdrivestatus.This,inadditiontotheinputregisterreflecting pinstatusand open-drainI/Ocell,allowswiredlogicbe implemented. The memory map fortheGPIO registersisshown inTable5-136.

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5.32.1 GPIO RegisterDescription(s)

Table5-136.GPIO Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01E2 6000 REV PeripheralRevisionRegister 0x01E2 6004 RESERVED Reserved 0x01E2 6008 BINTEN GPIO InterruptPer-BankEnableRegister GPIO Banks 0 and 1 0x01E2 6010 DIR01 GPIO Banks 0 and 1 DirectionRegister 0x01E2 6014 OUT_DATA01 GPIO Banks 0 and 1 OutputData Register 0x01E2 6018 SET_DATA01 GPIO Banks 0 and 1 SetData Register 0x01E2 601C CLR_DATA01 GPIO Banks 0 and 1 ClearData Register 0x01E2 6020 IN_DATA01 GPIO Banks 0 and 1 InputData Register 0x01E2 6024 SET_RIS_TRIG01 GPIO Banks 0 and 1 SetRisingEdge InterruptRegister 0x01E2 6028 CLR_RIS_TRIG01 GPIO Banks 0 and 1 ClearRisingEdge InterruptRegister 0x01E2 602C SET_FAL_TRIG01 GPIO Banks 0 and 1 SetFallingEdge InterruptRegister 0x01E2 6030 CLR_FAL_TRIG01 GPIO Banks 0 and 1 ClearFallingEdge InterruptRegister 0x01E2 6034 INTSTAT01 GPIO Banks 0 and 1 InterruptStatusRegister GPIO Banks 2 and 3 0x01E2 6038 DIR23 GPIO Banks 2 and 3 DirectionRegister 0x01E2 603C OUT_DATA23 GPIO Banks 2 and 3 OutputData Register 0x01E2 6040 SET_DATA23 GPIO Banks 2 and 3 SetData Register 0x01E2 6044 CLR_DATA23 GPIO Banks 2 and 3 ClearData Register 0x01E2 6048 IN_DATA23 GPIO Banks 2 and 3 InputData Register 0x01E2 604C SET_RIS_TRIG23 GPIO Banks 2 and 3 SetRisingEdge InterruptRegister 0x01E2 6050 CLR_RIS_TRIG23 GPIO Banks 2 and 3 ClearRisingEdge InterruptRegister 0x01E2 6054 SET_FAL_TRIG23 GPIO Banks 2 and 3 SetFallingEdge InterruptRegister 0x01E2 6058 CLR_FAL_TRIG23 GPIO Banks 2 and 3 ClearFallingEdge InterruptRegister 0x01E2 605C INTSTAT23 GPIO Banks 2 and 3 InterruptStatusRegister GPIO Banks 4 and 5 0x01E2 6060 DIR45 GPIO Banks 4 and 5 DirectionRegister 0x01E2 6064 OUT_DATA45 GPIO Banks 4 and 5 OutputData Register 0x01E2 6068 SET_DATA45 GPIO Banks 4 and 5 SetData Register 0x01E2 606C CLR_DATA45 GPIO Banks 4 and 5 ClearData Register 0x01E2 6070 IN_DATA45 GPIO Banks 4 and 5 InputData Register 0x01E2 6074 SET_RIS_TRIG45 GPIO Banks 4 and 5 SetRisingEdge InterruptRegister 0x01E2 6078 CLR_RIS_TRIG45 GPIO Banks 4 and 5 ClearRisingEdge InterruptRegister 0x01E2 607C SET_FAL_TRIG45 GPIO Banks 4 and 5 SetFallingEdge InterruptRegister 0x01E2 6080 CLR_FAL_TRIG45 GPIO Banks 4 and 5 ClearFallingEdge InterruptRegister 0x01E2 6084 INTSTAT45 GPIO Banks 4 and 5 InterruptStatusRegister Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 261 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-136.GPIO Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION GPIO Banks 6 and 7 0x01E2 6088 DIR67 GPIO Banks 6 and 7 DirectionRegister 0x01E2 608C OUT_DATA67 GPIO Banks 6 and 7 OutputData Register 0x01E2 6090 SET_DATA67 GPIO Banks 6 and 7 SetData Register 0x01E2 6094 CLR_DATA67 GPIO Banks 6 and 7 ClearData Register 0x01E2 6098 IN_DATA67 GPIO Banks 6 and 7 InputData Register 0x01E2 609C SET_RIS_TRIG67 GPIO Banks 6 and 7 SetRisingEdge InterruptRegister 0x01E2 60A0 CLR_RIS_TRIG67 GPIO Banks 6 and 7 ClearRisingEdge InterruptRegister 0x01E2 60A4 SET_FAL_TRIG67 GPIO Banks 6 and 7 SetFallingEdge InterruptRegister 0x01E2 60A8 CLR_FAL_TRIG67 GPIO Banks 6 and 7 ClearFallingEdge InterruptRegister 0x01E2 60AC INTSTAT67 GPIO Banks 6 and 7 InterruptStatusRegister GPIO Bank 8 0x01E2 60B0 DIR8 GPIO Bank 8 DirectionRegister 0x01E2 60B4 OUT_DATA8 GPIO Bank 8 OutputData Register 0x01E2 60B8 SET_DATA8 GPIO Bank 8 SetData Register 0x01E2 60BC CLR_DATA8 GPIO Bank 8 ClearData Register 0x01E2 60C0 IN_DATA8 GPIO Bank 8 InputData Register 0x01E2 60C4 SET_RIS_TRIG8 GPIO Bank 8 SetRisingEdge InterruptRegister 0x01E2 60C8 CLR_RIS_TRIG8 GPIO Bank 8 ClearRisingEdge InterruptRegister 0x01E2 60CC SET_FAL_TRIG8 GPIO Bank 8 SetFallingEdge InterruptRegister 0x01E2 60D0 CLR_FAL_TRIG8 GPIO Bank 8 ClearFallingEdge InterruptRegister 0x01E2 60D4 INTSTAT8 GPIO Bank 8 InterruptStatusRegister

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5.32.2 GPIO PeripheralInput/OutputElectricalData/Timing

Table5-137.Timing Requirements forGPIO Inputs(1)(2)(seeFigure5-87) NO. PARAMETER UNIT MIN MAX 1 tw(GPIH) Pulseduration,GP n[m ]as inputhigh 2C (2)(3) ns 2 tw(GPIL) Pulseduration,GP n[m ]as inputlow 2C (2)(3) ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) The pulsewidthgivenissufficienttogeneratea CPU interruptoran EDMA event.However,ifa userwantstohave thedevice recognizetheGPIx changes throughsoftwarepollingoftheGPIO register,theGPIx durationmust be extendedtoallowthedevice enough timetoaccesstheGPIO registerthroughtheinternalbus. (3) C=SYSCLK4 periodinns. Table5-138.SwitchingCharacteristicsOver Recommended OperatingConditionsforGPIO Outputs(1) (seeFigure5-87) NO. PARAMETER UNIT MIN MAX 3 tw(GPOH) Pulseduration,GP n[m ]as outputhigh 2C (2)(3) ns 4 tw(GPOL) Pulseduration,GP n[m ]as outputlow 2C (2)(3) ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) Thisparametervalueshouldnotbe used as a maximum performancespecification.Actualperformanceofback-to-backaccessesofthe GPIO isdependentupon internalbus activity. (3) C=SYSCLK4 periodinns. Figure5-87.GPIO PortTiming

5.32.3 GPIO PeripheralExternalInterruptsElectricalData/Timing

Table5-139.Timing Requirements forExternalInterrupts(1)(2)(seeFigure5-88) NO. PARAMETER UNIT MIN MAX 1 tw(ILOW) Widthoftheexternalinterruptpulselow 2C (2)(3) ns 2 tw(IHIGH) Widthoftheexternalinterruptpulsehigh 2C (2)(3) ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. (2) The pulsewidthgivenissufficienttogeneratean interruptoran EDMA event.However,ifa userwantstohave thedevicerecognizethe GPIO changes throughsoftwarepollingoftheGPIO register,theGPIO durationmust be extendedtoallowthedeviceenough timeto accesstheGPIO registerthroughtheinternalbus. (3) C=SYSCLK4 periodinns. Figure5-88.GPIO ExternalInterruptTiming Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 263 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.33 Programmable Real-TimeUnitSubsystem (PRUSS)

The Programmable Real-TimeUnitSubsystem (PRUSS) consistsof

Two Programmable Real-TimeUnits(PRU0 and PRU1) and theirassociatedmemories
An InterruptController(INTC)forhandlingsystem interruptevents.The INTC alsosupportsposting eventsback tothedevicelevelhostCPU.
A SwitchedCentralResource (SCR) forconnectingthe variousinternaland externalmastersto the resourcesinsidethePRUSS. The two PRUs can operatecompletelyindependentlyor incoordinationwitheach other.The PRUs can alsowork incoordinationwiththedevicelevelhostCPU. Thisisdeterminedby thenatureoftheprogram which isloadedintothePRUs instructionmemory. Severaldifferentsignalingmechanisms are available between thetwo PRUs and thedevicelevelhostCPU. The PRUs are optimizedforperformingembedded tasksthatrequiremanipulationof packed memory mapped datastructures,handlingofsystemeventsthathave tightrealtimeconstraintsand interfacingwith systemsexternaltothedevice. The PRUSS comprisesvariousdistinctaddressableregions.Externallythesubsystem presentsa single 64Kbyterangeofaddresses.The internalinterconnectbus (alsocalledswitchedcentralresource,orSCR) of the PRUSS decodes accesses foreach of the individualregions.The PRUSS memory map is documented in Table 5-140 and in Table 5-141. Note thatthese two memory maps are implemented insidethePRUSS and arelocaltothecomponents ofthePRUSS. Table5-140.Programmable Real-TimeUnitSubsystem (PRUSS) LocalInstructionSpace Memory Map BYTE ADDRESS PRU0 PRU1 0x0000 0000 -0x0000 0FFF PRU0 InstructionRAM PRU1 InstructionRAM Table5-141.Programmable Real-TimeUnitSubsystem (PRUSS) LocalData Space Memory Map BYTE ADDRESS PRU0 PRU1 0x0000 0000 -0x0000 01FF Data RAM 0(1) Data RAM 1(1) 0x0000 0200 -0x0000 1FFF Reserved Reserved 0x0000 2000 -0x0000 21FF Data RAM 1(1) Data RAM 0(1) 0x0000 2200 -0x0000 3FFF Reserved Reserved 0x0000 4000 -0x0000 6FFF INTC Registers INTC Registers 0x0000 7000 -0x0000 73FF PRU0 ControlRegisters PRU0 ControlRegisters 0x0000 7400 -0x0000 77FF Reserved Reserved 0x0000 7800 -0x0000 7BFF PRU1 ControlRegisters PRU1 ControlRegisters 0x0000 7C00 -0xFFFF FFFF Reserved Reserved (1) Note thatPRU0 accessesData RAM 0 ataddress0x0000 0000,alsoPRU1 accessesData RAM 1 ataddress0x0000 0000.Data RAM0 isintendedtobe theprimarydatamemory forPRU0 and Data RAM1 isintendedtobe theprimarydatamemory forPRU1. However for passinginformationbetween PRUs, each PRU can accessthedataram ofthe‘other’PRU throughaddress0x0000 2000. The globalview ofthePRUSS internalmemories and controlportsisdocumented inTable5-142.The offsetaddresses of each regionare implemented insidethe PRUSS but the globaldevicememory mapping placesthePRUSS slaveportintheaddressrange0x01C3 0000-0x01C3 FFFF. The PRU0 and PRU1 can use eitherthelocalor globaladdressestoaccess theirinternalmemories,butusingthelocal addresseswillprovideaccesstimeseveralcyclesfasterthanusingtheglobaladdresses.Thisisbecause when accessingviatheglobaladdresstheaccess needs tobe routedthroughtheswitchfabricoutside PRUSS and back inthroughthePRUSS slaveport.

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-142.Programmable Real-TimeUnitSubsystem (PRUSS) GlobalMemory Map BYTE ADDRESS REGION 0x01C3 0000 -0x01C3 01FF Data RAM 0 0x01C3 0200 -0x01C3 1FFF Reserved 0x01C3 2000 -0x01C3 21FF Data RAM 1 0x01C3 2200 -0x01C3 3FFF Reserved 0x01C3 4000 -0x01C3 6FFF INTC Registers 0x01C3 7000 -0x01C3 73FF PRU0 ControlRegisters 0x01C3 7400 -0x01C3 77FF PRU0 Debug Registers 0x01C3 7800 -0x01C3 7BFF PRU1 ControlRegisters 0x01C3 7C00 -0x01C3 7FFF PRU1 Debug Registers 0x01C3 8000 -0x01C3 8FFF PRU0 InstructionRAM 0x01C3 9000 -0x01C3 BFFF Reserved 0x01C3 C000 -0x01C3 CFFF PRU1 InstructionRAM 0x01C3 D000 -0x01C3 FFFF Reserved Each ofthePRUs can access therestofthedevicememory (includingmemory mapped peripheraland configurationregisters)usingtheglobalmemory space addresses

5.33.1 PRUSS RegisterDescriptions

Table5-143.Programmable Real-TimeUnitSubsystem (PRUSS) Control/StatusRegisters PRU0 BYTE ADDRESS PRU1 BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C3 7000 0x01C3 7800 CONTROL PRU ControlRegister 0x01C3 7004 0x01C3 7804 STATUS PRU StatusRegister 0x01C3 7008 0x01C3 7808 WAKEUP PRU Wakeup EnableRegister 0x01C3 700C 0x01C3 780C CYCLCNT PRU CycleCount 0x01C3 7010 0x01C3 7810 STALLCNT PRU StallCount 0x01C3 7020 0x01C3 7820 CONTABBLKIDX0 PRU ConstantTableBlockIndexRegister0 0x01C3 7028 0x01C3 7828 CONTABPROPTR0 PRU ConstantTableProgrammable PointerRegister0 0x01C3 702C 0x01C3 782C CONTABPROPTR1 PRU ConstantTableProgrammable PointerRegister1 0x01C37400 - 0x01C3 7C00 - INTGPR0 – INTGPR31 PRU InternalGeneralPurposeRegister0 (forDebug)0x01C3747C 0x01C3 7C7C 0x01C37480 - 0x01C3 7C80 - INTCTER0 – INTCTER31 PRU InternalGeneralPurposeRegister0 (forDebug)0x01C374FC 0x01C3 7CFC Table5-144.Programmable Real-TimeUnitSubsystem InterruptController(PRUSS INTC) Registers BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C3 4000 REVID RevisionID Register 0x01C3 4004 CONTROL ControlRegister 0x01C3 4010 GLBLEN GlobalEnableRegister 0x01C3 401C GLBLNSTLVL GlobalNestingLevelRegister 0x01C3 4020 STATIDXSET System InterruptStatusIndexedSetRegister 0x01C3 4024 STATIDXCLR System InterruptStatusIndexedClearRegister 0x01C3 4028 ENIDXSET System InterruptEnableIndexedSetRegister 0x01C3 402C ENIDXCLR System InterruptEnableIndexedClearRegister 0x01C3 4034 HSTINTENIDXSET HostInterruptEnableIndexedSetRegister 0x01C3 4038 HSTINTENIDXCLR HostInterruptEnableIndexedClearRegister 0x01C3 4080 GLBLPRIIDX GlobalPrioritizedIndexRegister 0x01C3 4200 STATSETINT0 System InterruptStatusRaw/Set Register0 Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 265 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-144.Programmable Real-TimeUnitSubsystem InterruptController(PRUSS INTC) Registers(continued) BYTE ADDRESS ACRONYM REGISTER DESCRIPTION 0x01C3 4204 STATSETINT1 System InterruptStatusRaw/Set Register1 0x01C3 4280 STATCLRINT0 System InterruptStatusEnabled/ClearRegister0 0x01C3 4284 STATCLRINT1 System InterruptStatusEnabled/ClearRegister1 0x01C3 4300 ENABLESET0 System InterruptEnableSetRegister0 0x01C3 4304 ENABLESET1 System InterruptEnableSetRegister1 0x01C3 4380 ENABLECLR0 System InterruptEnableClearRegister0 0x01C3 4384 ENABLECLR1 System InterruptEnableClearRegister1 0x01C3 4400 -0x01C3 4440 CHANMAP0 -CHANMAP15 ChannelMap Registers0-15 0x01C3 4800 -0x01C3 4808 HOSTMAP0 -HOSTMAP2 HostMap Register0-2 HOSTINTPRIIDX0 -0x01C3 4900 -0x01C3 4928 HostInterruptPrioritizedIndexRegisters0-9HOSTINTPRIIDX9 0x01C3 4D00 POLARITY0 System InterruptPolarityRegister0 0x01C3 4D04 POLARITY1 System InterruptPolarityRegister1 0x01C3 4D80 TYPE0 System InterruptType Register0 0x01C3 4D84 TYPE1 System InterruptType Register1 HOSTINTNSTLVL0-0x01C3 5100 -0x01C3 5128 HostInterruptNestingLevelRegisters0-9HOSTINTNSTLVL9 0x01C3 5500 HOSTINTEN HostInterruptEnableRegister

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5.34 EmulationLogic

Thissectiondescribesthestepstouse a thirdpartydebuggeron theARM926EJ-S withinthedevice.The debug capabilitiesand featuresforDSP and ARM areas shown below. DSP:

BasicDebug – ExecutionControl – System Visibility
Real-TimeDebug – Interruptsservicedwhilehalted – Low/non-intrusivesystemvisibilitywhilerunning
Advanced Debug – GlobalStart – GlobalStop – Specifytargetedmemory level(s)duringmemory accesses – HSRTDX (HighSpeed RealTime Data eXchange)
Advanced System Control – Subsystem resetviadebug – Peripheralnotificationofdebug events – Cache-coherentdebug accesses
AnalysisActions – Stopprogramexecution – Generatedebug interrupt – Benchmarkingwithcounters – Externaltriggergeneration – Debug statemachine statetransition – Combinationaland Sequentialeventgeneration
AnalysisEvents – Program eventdetection – Data eventdetection – ExternaltriggerDetection – System eventdetection(i.e.cache miss) – Debug statemachine statedetection
AnalysisConfiguration – Applicationaccess – Debugger access Table5-145.DSP Debug Features Category Hardware Feature Availability Softwarebreakpoint Unlimited Up to10 HWBPs, including: BasicDebug 4 precise(1)HWBPs insideDSP coreand one ofthem isassociatedwitha counter. Hardware breakpoint 2 imprecise(1)HWBPs fromAET. 4 imprecise(1)HWBPs fromAET whicharesharedforwatchpoint. (1) Precisehardwarebreakpointswillhalttheprocessorimmediatelypriortotheexecutionoftheselectedinstruction.Imprecisebreakpoints willhalttheprocessorsome number ofcyclesaftertheselectedinstructiondependingon deviceconditions. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 267 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-145.DSP Debug Features(continued) Category Hardware Feature Availability Up to4 watchpoints,whicharesharedwithHWBPs, and can alsobe used as 2 watchWatch point pointswithdata(32bits) Watch pointwithData Up to2,Which can alsobe used as 4 watchpoints. Analysis Counters/timers 1x64-bits(cycleonly)+ 2x32-bits(watermark counters) ExternalEventTriggerIn 1 ExternalEventTriggerOut 1 ARM:

BasicDebug – ExecutionControl – System Visibility
Advanced Debug – GlobalStart – GlobalStop
Advanced System Control – Subsystem resetviadebug – Peripheralnotificationofdebug events – Cache-coherentdebug accesses
Program Trace – Program flowcorruption – Code coverage – Pathcoverage – Thread/interruptsynchronizationproblems
Data Trace – Memory corruption
TimingTrace – Profiling
AnalysisActions – Stopprogramexecution – Controltracestreams – Generatedebug interrupt – Benchmarkingwithcounters – Externaltriggergeneration – Debug statemachine statetransition – Combinationaland Sequentialeventgeneration
AnalysisEvents – Program eventdetection – Data eventdetection – ExternaltriggerDetection – System eventdetection(i.e.cache miss) – Debug statemachine statedetection
AnalysisConfiguration – Applicationaccess – Debugger access

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www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 Table5-146.ARM Debug Features Category Hardware Feature Availability Softwarebreakpoint Unlimited Up to14 HWBPs, including: 2 precise(1)HWBP insideARM corewhicharesharedwithwatchpoints.BasicDebug Hardware breakpoint 8 imprecise(1)HWBPs fromETM ’s addresscomparators,whicharesharedwithtrace function,and can be used as watchpoints. 4 imprecise(1)HWBPs fromICECrusher. Up to6 watchpoints,including: 2 fromARM corewhichissharedwithHWBPs and can be associatedwitha data.Watch point 8 fromETM ’s addresscomparators,whicharesharedwithtracefunction,and HWBPs. 2 fromARM corewhichissharedwithHWBPs. Watch pointwithDataAnalysis 8 watchpointsfromETM can be associatedwitha datacomparator,and ETM has total4 datacomparators. Counters/timers 3x32-bit(1cycle;2 event) ExternalEventTriggerIn 1 ExternalEventTriggerOut 1 InternalCross-TriggeringSignals One between ARM and DSP Addressrangefortrace 4 Data qualificationfortrace 2 System eventsfortracecontrol 20 TraceControl Counters/Timersfortracecontrol 2x16-bit StateMachines/Sequencers 1x3-StateStateMachine Context/ThreadID Comparator 1 Independenttriggercontrolunits 12 CapturedepthPC 4k bytesETB On-chipTrace CapturedepthPC + Timing 4k bytesETBCapture Applicationaccessible Y (1) Precisehardwarebreakpointswillhalttheprocessorimmediatelypriortotheexecutionoftheselectedinstruction.Imprecisebreakpoints willhalttheprocessorsome number ofcyclesaftertheselectedinstructiondependingon deviceconditions.

5.34.1 JTAG PortDescription

The devicetargetdebug interfaceuses thefivestandardIEEE 1149.1(JTAG)signals(TRST, TCK, TMS, TDI, and TDO) , a returnclock(RTCK) due to the clockingrequirementsof the ARM926EJ-S and emulationsignalsEMU0 and EMU1. TRST holdsthe debug and boundary scan logicinreset(normalDSP operation)when pulledlow (its defaultstate).Since TRST has an internalpull-downresistor,thisensuresthatat power up the device functionsinitsnormal(non-test)operationmode ifTRST isnotconnected.Otherwise,TRST shouldbe driveninactiveby the emulatoror boundary scan controller.Boundary scan testcannotbe performed whiletheTRST pinispulledlow. Table5-147.JTAG PortDescription PIN TYPE NAME DESCRIPTION When asserted(activelow)causesalltestand debug logicinthedevicetobe resetTRST I TestLogicReset alongwiththeIEEE 1149.1interface Thisisthetestclockused todrivean IEEE 1149.1TAP statemachine and TCK I TestClock logic.Dependingon theemulatorattachedto,thisisa freerunningclockora gated clockdependingon RTCK monitoring. SynchronizedTCK. Dependingon theemulatorattachedto,theJTAG signalsareRTCK O ReturnedTestClock clockedfromRTCK orRTCK ismonitoredby theemulatortogateTCK. TMS I TestMode Select DirectsthenextstateoftheIEEE 1149.1testaccessportstatemachine Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 269 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com Table5-147.JTAG PortDescription(continued) PIN TYPE NAME DESCRIPTION TDI I TestData Input Scan datainputtothedevice TDO O TestData Output Scan dataoutputofthedevice EMU0 I/O Emulation0 Channel0 trigger+ HSRTDX EMU1 I/O Emulation1 Channel1 trigger+ HSRTDX

5.34.2 Scan Chain ConfigurationParameters

Table5-148shows theTAP configurationdetailsrequiredtoconfiguretherouter/emulatorforthisdevice. Table5-148.JTAG PortDescription Router PortID DefaultTAP TAP Name Tap IR Length

17 No C674x 38

18 No ARM926 4

19 No ETB 4

The routerisrevisionC and has a 6-bitIR length.

5.34.3 InitialScan Chain Configuration

The firstlevelofdebug interfacethatsees thescan controlleristheTAP routermodule.The debugger can configuretheTAP routerforseriallylinkingup to16 TAP controllersor individuallyscanningone of theTAP controllerswithoutdisruptingtheIR stateoftheotherTAPs. 5.34.3.1Adding TAPS totheScan Chain The TAP routermust be programmed toadd additionalTAPs tothescan chain.The followingJTAG scans must be completedtoadd theARM926EJ-S tothescan chain. A Power-On Reset (POR) or theJTAG Test-LogicReset stateconfigurestheTAP routertocontainonly therouter’s TAP. Figure5-89.Adding ARM926EJ-S tothescan chain Pre-amble:The devicewhose datareachestheemulatorfirstislistedfirstintheboardconfigurationfile. Thisdeviceisa pre-ambleforalltheotherdevices.Thisdevicehas thelowestdeviceID. Post-amble:The devicewhose datareachestheemulatorlastislistedlastintheboardconfigurationfile. Thisdeviceisa post-ambleforalltheotherdevices.Thisdevicehas thehighestdeviceID.

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Function:Update theJTAG preambleand post-amblecounts. – Parameter:The IR pre-amblecountis'0'. – Parameter:The IR post-amblecountis'0'. – Parameter:The DR pre-amblecountis'0'. – Parameter:The DR post-amblecountis'0'. – Parameter:The IR main countis'6'. – Parameter:The DR main countis'1'.
Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-ir'. – Parameter:The JTAG destinationstateis'pause-ir'. – Parameter:The bitlengthofthecommand is'6'. – Parameter:The send datavalueis'0x00000007'. – Parameter:The actualreceivedatais'discarded'.
Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-dr'. – Parameter:The JTAG destinationstateis'pause-dr'. – Parameter:The bitlengthofthecommand is'8'. – Parameter:The send datavalueis'0x00000089'. – Parameter:The actualreceivedatais'discarded'.
Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-ir'. – Parameter:The JTAG destinationstateis'pause-ir'. – Parameter:The bitlengthofthecommand is'6'. – Parameter:The send datavalueis'0x00000002'. – Parameter:The actualreceivedatais'discarded'.
Function:Embed theportaddressinnextcommand. – Parameter:The portaddressfieldis'0x0f000000'. – Parameter:The portaddressvalueis'3'.
Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-dr'. – Parameter:The JTAG destinationstateis'pause-dr'. – Parameter:The bitlengthofthecommand is'32'. – Parameter:The send datavalueis'0xa2002108'. – Parameter:The actualreceivedatais'discarded'.
Function:Do a send-onlyall-onesJTAG IR/DR scan. – Parameter:The JTAG shiftstateis'shift-ir'. – Parameter:The JTAG destinationstateis'run-test/idle'. – Parameter:The bitlengthofthecommand is'6'. – Parameter:The send datavalueis'all-ones'. – Parameter:The actualreceivedatais'discarded'.
Function:Waitfora minimum number ofTCLK pulses. – Parameter:The countofTCLK pulsesis'10'. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 271 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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Function:Update theJTAG preambleand post-amblecounts. – Parameter:The IR pre-amblecountis'0'. – Parameter:The IR post-amblecountis'6'. – Parameter:The DR pre-amblecountis'0'. – Parameter:The DR post-amblecountis'1'. – Parameter:The IR main countis'4'. – Parameter:The DR main countis'1'. The initialscan chaincontainsonlythe TAP routermodule.The followingstepsmust be completedin ordertoadd ETB TAP tothescan chain. Figure5-90.Adding ETB tothescan chain
Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-ir'. – Parameter:The JTAG destinationstateis'pause-ir'. – Parameter:The bitlengthofthecommand is'6'. – Parameter:The send datavalueis'0x00000007'. – Parameter:The actualreceivedatais'discarded'.
Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-dr'. – Parameter:The JTAG destinationstateis'pause-dr'. – Parameter:The bitlengthofthecommand is'8'. – Parameter:The send datavalueis'0x00000089'. – Parameter:The actualreceivedatais'discarded'.
Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-ir'. – Parameter:The JTAG destinationstateis'pause-ir'. – Parameter:The bitlengthofthecommand is'6'. – Parameter:The send datavalueis'0x00000002'. – Parameter:The actualreceivedatais'discarded'.
Function:Embed theportaddressinnextcommand. – Parameter:The portaddressfieldis'0x0f000000'. – Parameter:The portaddressvalueis'3'.

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Function:Do a send-onlyJTAG IR/DR scan. – Parameter:The routetoJTAG shiftstateis'shortesttransition'. – Parameter:The JTAG shiftstateis'shift-dr'. – Parameter:The JTAG destinationstateis'pause-dr'. – Parameter:The bitlengthofthecommand is'32'. – Parameter:The send datavalueis'0xa3302108'. – Parameter:The actualreceivedatais'discarded'.
Function:Do a send-onlyall-onesJTAG IR/DR scan. – Parameter:The JTAG shiftstateis'shift-ir'. – Parameter:The JTAG destinationstateis'run-test/idle'. – Parameter:The bitlengthofthecommand is'6'. – Parameter:The send datavalueis'all-ones'. – Parameter:The actualreceivedatais'discarded'.
Function:Waitfora minimum number ofTCLK pulses. – Parameter:The countofTCLK pulsesis'10'.
Function:Update theJTAG preambleand post-amblecounts. – Parameter:The IR pre-amblecountis'0'. – Parameter:The IR post-amblecountis'6+ 4'. – Parameter:The DR pre-amblecountis'0'. – Parameter:The DR post-amblecountis'1+ 1'. – Parameter:The IR main countis'4'. – Parameter:The DR main countis'1'. 5.34.4 IEEE 1149.1JTAG The JTAG (1)interfaceisused forBSDL testingand emulationofthedevice. The devicerequiresthatboth TRST and RESET be assertedupon power up to be properlyinitialized. WhileRESET initializesthedevice,TRST initializesthedevice'semulationlogic.Both resetsarerequired forproperoperation. WhilebothTRST and RESET need tobe assertedupon power up,onlyRESET needs tobe releasedfor thedevicetobootproperly.TRST may be assertedindefinitelyfornormaloperation,keepingtheJTAG portinterfaceand device'semulationlogicintheresetstate. TRST onlyneeds tobe releasedwhen itisnecessarytouse a JTAG controllertodebug thedeviceor exercisethedevice'sboundaryscan functionality.Note:TRST issynchronousand must be clockedby TCK; otherwise,theboundaryscan logicmay notrespondas expectedafterTRST isasserted. RESET must be releasedonlyin orderforboundary-scanJTAG to read the variantfieldof IDCODE correctly.Otherboundary-scaninstructionswork correctlyindependentofcurrentstateofRESET. For maximum reliability,the deviceincludesan internalpulldown(IPD)on the TRST pinto ensure that TRST willalways be assertedupon power up and the device'sinternalemulationlogicwillalways be properlyinitialized. JTAG controllersfrom Texas InstrumentsactivelydriveTRST high.However, some third-partyJTAG controllersmay notdriveTRST highbutexpecttheuse ofa pullupresistoron TRST. When usingthistypeofJTAG controller,assertTRST toinitializethedeviceafterpowerup and externally driveTRST highbeforeattemptingany emulationorboundaryscan operations. (1) IEEE Standard1149.1-1990Standard-Test-AccessPortand BoundaryScan Architecture. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 273 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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5.34.4.1 JTAG PeripheralRegisterDescription(s)– JTAG ID Register(DEVIDR0)

Table5-149.DEVIDR0 Register BYTE ADDRESS ACRONYM REGISTER DESCRIPTION COMMENTS Read-only.Provides32-bit0x01C1 4018 DEVIDR0 JTAG IdentificationRegister JTAG ID ofthedevice. The JTAG ID registerisa read-onlyregisterthatidentifiestheJTAG/DeviceID.For thedevice,theJTAG ID registerresidesataddresslocation0x01C1 4018.The registerhex valueforeach siliconrevisionis:

0x0B7D 102F forsiliconrevision1.0
0x0B7D 102F forsiliconrevision1.1
0x1B7D 102F forsiliconrevision2.0 For theactualregisterbitnames and theirassociatedbitfielddescriptions,see Figure5-91and Table5- 150. 31-28 27-12 11-1 0 VARIANT (4-Bit) PART NUMBER (16-Bit) MANUFACTURER (11-Bit) LSB R-xxxx R-1011 0111 1101 0001 R-0000 0010 111 R-1 LEGEND: R = Read, W = Write,n = valueatreset Figure5-91.JTAG ID (DEVIDR0) RegisterDescription-RegisterValue Table5-150.JTAG ID RegisterSelectionBitDescriptions BIT NAME DESCRIPTION 31:28 VARIANT Variant(4-Bit)value 27:12 PART NUMBER PartNumber (16-Bit)value 11-1 MANUFACTURER Manufacturer(11-Bit)value 0 LSB LSB. Thisbitisreadas a "1".

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5.34.4.2 JTAG Test-PortElectricalData/Timing

Table5-151.Timing Requirements forJTAG TestPort(1)(seeFigure5-92) No. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 1 tc(TCK) Cycletime,TCK 40 50 66.6 ns 2 tw(TCKH) Pulseduration,TCK high 16 20 26.6 ns 3 tw(TCKL) Pulseduration,TCK low 16 20 26.6 ns 4 tc(RTCK) Cycletime,RTCK 40 50 66.6 ns 5 tw(RTCKH) Pulseduration,RTCK high 16 20 26.6 ns 6 tw(RTCKL) Pulseduration,RTCK low 16 20 26.6 ns 7 tsu(TDIV-RTCKH) Setuptime,TDI/TMS/TRST validbeforeRTCK high 4 4 4 ns 8 th(RTCKH-TDIV) Holdtime,TDI/TMS/TRST validafterRTCK high 4 6 8 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Table5-152.SwitchingCharacteristicsOver Recommended OperatingConditionsforJTAG TestPort(1) (seeFigure5-92) No. PARAMETER UNIT MIN MAX MIN MAX MIN MAX 9 td(RTCKL-TDOV) Delaytime,RTCK lowtoTDO valid 18 23 31 ns (1) Parametersarecharacterizedfrom-40°C to105°C unlessotherwisenoted. Figure5-92.JTAG Test-PortTiming 5.34.5 JTAG 1149.1Boundary Scan Considerations To use boundaryscan,thefollowingsequence shouldbe followed:

Executea validresetsequence and exitreset
Waitatleast6000 OSCIN clockcycles
Enterboundaryscan mode usingtheJTAG pins No specificvalueisrequiredon theEMU0 and EMU1 pinsforboundaryscan testing.IfTRST isnotdriven by theboundaryscan toolortester,TRST shouldbe externallypulledhighduringboundaryscan testing. Copyright© 2011–2013,Texas InstrumentsIncorporated PeripheralInformationand ElectricalSpecifications 275 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

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6 Device and Documentation Support

6.1 Device Support

6.1.1 Development Support

TI offersan extensivelineof developmenttoolsforthe deviceplatform,includingtoolsto evaluatethe performanceoftheprocessors,generatecode,developalgorithmimplementations,and fullyintegrateand debug softwareand hardwaremodules.The tool'ssupportdocumentationiselectronicallyavailablewithin theCode Composer Studio™ IntegratedDevelopmentEnvironment(IDE). The followingproductssupportdevelopmentofthedeviceapplications: SoftwareDevelopment Tools: Code Composer Studio™ IntegratedDevelopmentEnvironment(IDE):includingEditor C/C++/AssemblyCode Generation,and Debug plusadditionaldevelopmenttools Scalable,Real-TimeFoundationSoftware(DSP/BIOS™ ),which providesthe basicrun-timetarget softwareneeded tosupportany application. Hardware Development Tools: ExtendedDevelopmentSystem (XDS ™ )Emulator For a completelistingofdevelopment-supporttoolsforthedevice,visittheTexas Instrumentsweb site on theWorldwideWeb athttp://www.ti.comuniformresourcelocator(URL).For informationon pricing and availability,contactthenearestTIfieldsalesofficeorauthorizeddistributor.

6.1.2 Device Nomenclature

To designatethestagesintheproductdevelopmentcycle,TI assignsprefixestothepartnumbers ofall DSP devicesand supporttools.Each DSP commercialfamilymember has one ofthreeprefixes:X, P or NULL (e.g.,OMAPL138). Texas Instrumentsrecommends two ofthreepossibleprefixdesignatorsforits supporttools:TMDX and TMDS. These prefixesrepresentevolutionarystagesof productdevelopment fromengineeringprototypes(TMX/TMDX) throughfullyqualifiedproductiondevices/tools(TMS/TMDS). Devicedevelopmentevolutionaryflow: X Experimentaldevicethatis not necessarilyrepresentativeof the finaldevice'selectrical specifications. P Finalsilicondiethatconformstothedevice'selectricalspecificationsbuthas notcompleted qualityand reliabilityverification. NULL Fully-qualifiedproductiondevice. Supporttooldevelopmentevolutionaryflow: TMDX Development-supportproduct that has not yet completed Texas Instrumentsinternal qualificationtesting. TMDS Fullyqualifieddevelopment-supportproduct. X and P devicesand TMDX development-supporttoolsareshippedagainstthefollowingdisclaimer: "Developmentalproductisintendedforinternalevaluationpurposes." Nulldevicesand TMDS development-supporttoolshave been characterizedfully,and the qualityand reliabilityofthedevicehave been demonstratedfully.TI'sstandardwarrantyapplies. Predictionsshow thatprototypedevices(X orP) have a greaterfailureratethanthestandardproduction devices.Texas Instrumentsrecommends thatthese devicesnot be used in any productionsystem because theirexpectedend-usefailureratestillisundefined.Only qualifiedproductiondevicesaretobe used.

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X OMAPL138 (B) GWT M PREFIX DEVICE SILICON REVISION PACKAGE TYPE TEMPERATURE RANGE (JUNCTION) B = Silicon Revision 2.1 Blank = Production Device X = Experimental Device P = Prototype Device

361 Pin Plastic BGA, with SnPb

Soldered Balls, 0.8 mm Ball Pitch GWT =OMAPL138 M = -55°C to 125°C (Military Range) (A) (C) EP Enhanced Plastic OMAPL138B-EP www.ti.com SPRS815C –DECEMBER 2011–REVISED APRIL 2013 TI devicenomenclaturealso includesa suffixwiththe devicefamilyname. This suffixindicatesthe package type(GWT) and thetemperaturerange(M). Figure6-1providesa legendforreadingthecompletedevice. A. BGA = BallGridArray B. The devicespeed rangesymbolizationindicatesthemaximum CPU frequencywhen thecorevoltageCV DD issetto 1.2V. C. Partsmarked revisionB aresiliconrevision2.1. Figure6-1.Device Nomenclature

6.2 Documentation Support

The followingdocuments are availableon theInternetatwww.ti.com.Tip:Entertheliteraturenumber in thesearchbox. DSP ReferenceGuides SPRUG82 TMS320C674x DSP Cache User's Guide. Explainsthe fundamentalsof memory caches and describeshow the two-levelcache-based internalmemory architecturein the TMS320C674x digitalsignalprocessor(DSP) can be efficientlyused inDSP applications. Shows how to maintaincoherence withexternalmemory, how to use DMA to reduce memory latencies,and how tooptimizeyourcode toimprovecache efficiency.The internal memory architectureintheC674x DSP isorganizedina two-levelhierarchyconsistingofa dedicatedprogram cache (L1P) and a dedicateddata cache (L1D) on the firstlevel. Accesses by the CPU to the thesefirstlevelcaches can completewithoutCPU pipeline stalls.Ifthedatarequestedby theCPU isnotcontainedincache,itisfetchedfromthenext lowermemory level,L2 orexternalmemory. SPRUFE8 TMS320C674x DSP CPU and InstructionSet Reference Guide. Describesthe CPU architecture,pipeline,instructionset,and interruptsforthe TMS320C674x digitalsignal processors(DSPs).The C674x DSP isan enhancement oftheC64x+ and C67x+ DSPs with added functionalityand an expanded instructionset. SPRUFK5 TMS320C674x DSP Megamodule Reference Guide. Describesthe TMS320C674x digital signalprocessor(DSP) megamodule. Includedisa discussionon theinternaldirectmemory access (IDMA) controller,the interruptcontroller,the power-down controller,memory protection,bandwidthmanagement, and thememory and cache. SPRUFK9 TMS320C674x/OMAP-L1x Processor PeripheralsOverview Reference Guide. Provides an overviewand brieflydescribestheperipheralsavailableon thedevice. SPRUH77 OMAPL138 C6-IntegraDSP+ARM TechnicalReference Manual. Describesthe System- on-Chip(SoC) system.The SoC system includesTI’s standardTMS320C674x Megamodule and severalblocksofinternalmemory (L1P,L1D, and L2). Copyright© 2011–2013,Texas InstrumentsIncorporated Deviceand DocumentationSupport 277 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com SPRUGQ9 TMS320C674x/OMAP-L1x Processor SecurityUser'sGuide.Providesan overviewofthe securityconceptsimplementedon TIBasicSecureBootdevices.

6.3 Community Resources

The followinglinksconnectto TI community resources.Linkedcontentsare provided"AS IS"by the respectivecontributors.They do notconstituteTI specificationsand do notnecessarilyreflectTI'sviews; see TI'sTerms ofUse. TIE2E Community TI's Engineer-to-Engineer(E2E) Community. Created to fostercollaboration among engineers.Ate2e.ti.com,you can ask questions,shareknowledge,exploreideasand helpsolveproblemswithfellowengineers. TIEmbedded Processors Wiki Texas InstrumentsEmbedded Processors Wiki.Establishedto help developersget startedwithEmbedded Processorsfrom Texas Instrumentsand to foster innovationand growthofgeneralknowledge aboutthehardwareand softwaresurrounding thesedevices.

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7 MechanicalPackaging and OrderableInformation

Thissectiondescribestheorderablepartnumbers,packagingoptions,materials,thermaland mechanical parameters.

7.1 Thermal Data forGWT Package

The followingtable(s)show the thermalresistancecharacteristicsfor the PBGA –GWT mechanical package. Table7-1.Thermal ResistanceCharacteristics(PBGA Package) [GWT] NO. °C/W (1) AIR FLOW (m/s)(2) 1 R ΘJC Junction-to-case 7.3 N/A 2 R ΘJB Junction-to-board 12.4 N /A 3 R ΘJA Junction-to-freeair 23.7 0.00 4 21.0 0.50 5 20.1 1.00 R ΘJMA Junction-to-movingair 6 19.3 2.00 7 18.4 4.00 8 0.2 0.00 9 0.3 0.50 10 PsiJT Junction-to-packagetop 0.3 1.00 11 0.4 2.00 12 0.5 4.00 13 12.3 0.00 14 12.2 0.50 15 PsiJB Junction-to-board 12.1 1.00 16 12.0 2.00 17 11.9 4.00 (1) These measurements were conductedina JEDEC defined2S2P systemand willchange based on environmentas wellas application. Formore information,see theseEIA/JEDEC standards– EIA/JESD51-2,IntegratedCircuitsThermalTestMethod Environment Conditions-NaturalConvection(StillAir)and JESD51-7,HighEffectiveThermalConductivityTestBoard forLeaded SurfaceMount Packages.Power dissipationof1W and ambienttemp of70C assumed. PCB with2oz (70um)topand bottomcopperthicknessand 1.5oz(50um)innercopperthickness (2) m/s = meterspersecond Copyright© 2011–2013,Texas InstrumentsIncorporated MechanicalPackagingand OrderableInformation 279 SubmitDocumentationFeedback ProductFolderLinks:OMAPL138B-EP

SPRS815C –DECEMBER 2011–REVISED APRIL 2013 www.ti.com RevisionHistory NOTE: Page numbers forpreviousrevisionsmay differfrompage numbers inthecurrentversion. Changes from RevisionB (March,2012)toRevisionC Page

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www.ti.com 25-Oct-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples OMAPL138BGWTMEP ACTIVE NFBGA GWT 361 90 TBD SNPB Level-3-220C-168 HR -55 to 125 OMAPL138B GWTMEP V62/12605-01XE ACTIVE NFBGA GWT 361 90 TBD SNPB Level-3-220C-168 HR -55 to 125 OMAPL138B GWTMEP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

www.ti.com 25-Oct-2016 Addendum-Page 2 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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Product Information

V6212605-01XE specifications and overview.

Summary

OMAPL138B C6-Integra DSP ARM Processor

Description

OMAPL138B C6-Integra DSP ARM Processor

Source title V6212605-01XE Datasheet(PDF) - Texas Instruments

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