V6209626-01XE

Texas Instruments

16-CHANNEL, 24-BIT ANALOG-TO-DIGITAL CONVERTER

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ADS1258-EP_14 TI1 | Alldatasheet

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www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 16-CHANNEL,24-BITANALOG-TO-DIGITALCONVERTER Check forSamples: ADS1258-EP 1FEATURES 23• 24 Bits,No MissingCodes APPLICATIONS

Fixed-Channelor Automatic Channel Scan • Medical,Avionics,and Process Control
Fixed-ChannelData Rate:125 kSPS • Machine and System Monitoring
Auto-Scan Data Rate:23.7kSPS/Channel • FastScan Multi-ChannelInstrumentation
Single-ConversionSettledData • IndustrialSystems
16 Single-Endedor 8 DifferentialInputs • Testand Measurement Systems
Unipolar(5V) or Bipolar(±2.5V) Operation
One FabricationSite• Open-Sensor Detection
AvailableinMilitary(–55°C/125°C) and• Conversion ControlPin Industrial(–40°C/105°C) Temperature Ranges (1)
MultiplexerOutput forExternalSignal • Extended Product LifeCycleConditioning
Extended Product-Change Notification• On-Chip Temperature,Reference,Offset,Gain,
Product Traceabilityand Supply VoltageReadback
42-mW Power Dissipation
Standby,Sleep,and Power-Down Modes
8 General-PurposeInputs/Outputs(GPIO)
32.768-kHzCrystalOscillatoror ExternalClock (1) Custom temperaturerangesavailable

DESCRIPTION

The ADS1258 isa 16-channel(multiplexed),low-noise,24-bit,delta-sigma(ΔΣ)analog-to-digitalconverter(ADC) thatprovidessingle-cyclesettleddataatchannelscan ratesfrom 1.8kto23.7ksamples per second (SPS) per channel.A flexibleinputmultiplexeracceptscombinationsofeightdifferentialor 16 single-endedinputswitha full-scaledifferentialrange of 5 V or truebipolarrange of ±2.5 V when operatingwitha 5-V reference.The fourth-orderdelta-sigmamodulator is followedby a fifth-ordersinc digitalfilteroptimizedfor low-noise performance. The differentialoutputofthemultiplexerisaccessibletoallowsignalconditioningpriortotheinputoftheADC. Internalsystemmonitorregistersprovidesupplyvoltage,temperature,referencevoltage,gain,and offsetdata. An onboard PLL generatesthe system clockfrom a 32.768-kHzcrystal,or can be overriddenby an external clocksource.A bufferedsystem clockoutput(15.7MHz) isprovidedto drivea microcontrolleror additional converters. Serialdigitalcommunicationishandledviaan SPI™ -compatibleinterface.A simplecommand word structure controlschannelconfiguration,datarates,digitalI/O,monitorfunctions,etc. Programmable sensorbiascurrentsourcescan be used tobiassensorsorverifysensorintegrity. The ADS1258 operatesfroma unipolar5-V orbipolar±2.5-Vanalogsupplyand a digitalsupplycompatiblewith interfacesrangingfrom2.7V to5.25V.The ADS1258 isavailableinQFN-48 and QFP-48 packages. Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2SPI isa trademarkofMotorola,Inc. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2009–2011,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

24− Bit ADC Digital Filter Internal Monitoring 16:1 Analog Input MUX AINCOM ADC IN Extclk In/Out AVSS DGND32.768kHz AVDD DVDD MUX OUT SPI Interface CS DRDY SCLK DIN DOUT ControlOscillator GPIO START RESET PWDN GPIO[7:0]VREF ADS1258 Analog Inputs ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com This integratedcircuitcan be damaged by ESD. Texas Instrumentsrecommends thatallintegratedcircuitsbe handled with appropriateprecautions.Failuretoobserveproperhandlingand installationprocedurescan cause damage. ESD damage can rangefromsubtleperformancedegradationtocompletedevicefailure.Precisionintegratedcircuitsmay be more susceptibletodamage because verysmallparametricchanges couldcause thedevicenottomeet itspublishedspecifications. ORDERING INFORMATION (1) NUMBER 48/RTC Tape & Reelof250 ADS1258MRTCTEP 1258MEP –55°C to125°C 48/PHP Trayof250 ADS1258MPHPTEP ADS1258MEP –40°C to105°C 48/PHP Tape & Reel1000 ADS1258IPHPREP ADS1258IEP (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTI Web siteatwww.ti.com. (2) Package drawings,standardpackingquantities,thermaldata,symbolization,and PCB designguidelinesareavailableat www.ti.com/sc/package. ABSOLUTE MAXIMUM RATINGS Over operatingfree-airtemperaturerange(unlessotherwisenoted).(1) ADS1258 UNIT AVDD toAVSS –0.3to5.5 V AVSS toDGND –2.8to0.3 V DVDD toDGND –0.3to5.5 V InputCurrent 100,Momentary mA InputCurrent 10,Continuous mA AnalogInputVoltage AVSS – 0.3toAVDD + 0.3 V DigitalInputVoltagetoDGND –0.3toDVDD + 0.3 V Maximum JunctionTemperature 150 °C StorageTemperatureRange –60 to150 °C (1) Stressesabove theseratingsmay cause permanentdamage. Exposuretoabsolutemaximum conditionsforextendedperiodsmay degradedevicereliability.These arestressratingsonly,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thosespecifiedisnotimplied.

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www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011

ELECTRICAL CHARACTERISTICS

AllspecificationsatTA = –55°C to125°C, AVDD = 2.5V,AVSS = –2.5V,DVDD = 3.3V,fCLK = 16 MHz (externalclock)orfCLK = 15.729 MHz (internalclock),OPA227 bufferbetween MUX outputsand ADC inputs,VREF = 4.096V,and VREFN = –2.5V,unlessotherwisenoted. PARAMETER CONDITIONS MIN TYP (1) MAX UNIT Analog MultiplexerInputs AIN0–AIN15, AVSS – AVDD +AbsoluteInputVoltage AINCOM withrespectto V100 mV 100mVDGND On-ChannelResistance 80 Ω Crosstalk fIN = 1 kHz –110 dB SBCS[1:0]= 01 1.5 SensorBias(CurrentSource) μA SBCS[1:0]= 11 24 1.5μA:24μA RatioError 1 % ADC Input Full-ScaleInputVoltage (VIN = ADCINP – ADCINN) ±1.06 VREF V AVSS – AVDD +AbsoluteInputVoltage (ADCINP, ADCINN) V100 mV 100mV DifferentialInputImpedance 65 kΩ System Performance Resolution No MissingCodes 24 Bits Data Rate,Fixed-ChannelMode 1.953 125 kSPS Data Rate,Auto-ScanMode 1.805 23.739 kSPS % ofIntegralNonlinearity(INL)(2) DifferentialInput 0.0003 0.0010 FSR (3) ChoppingOff 20 OffsetError Shorted TA = –40°C to105°C 1 10 μV ChoppingOn Inputs TA = –55°C to125°C -650 650 ChoppingOff 0.5 OffsetDrift ShortedInputs μV/°C ChoppingOn 0.02 0.1 TA = –40°C to105°C 0.1 0.5 Gain Error % TA = –40°C to105°C 0.4 2 Gain Drift ppm/°C TA = –55°C to125°C 0.4 Noise (seeTable4) Common-Mode Rejection fCM = 60 Hz 90 100 dB AVDD, AVSS 70 85 Power-SupplyRejection fPS = 60 Hz dB DVDD 80 95 VoltageReferenceInput AVDD –ReferenceInputVoltage (VREF = VREFP – VREFN) 0.5 4.096 VAVSS NegativeReferenceInput(VREFN) AVSS – 0.1V VREFP – 0.5 V PositiveReferenceInput(VREFP) VREFN + 0.5 AVDD + 0.1V V ReferenceInputImpedance 40 kΩ System Parameters ExternalReferenceReadingError 1 3 % AnalogSupplyReadingError 1 3 % Voltage TA = 25°C 168 mV OnlyADS1258-EP temperature 394TemperatureSensorReading forced;testPCB infree-air. Coefficient μV/°C ADS1258-EP and testPCB 563temperaturesforcedtogether. (1) TA = 25°C fortypicalparameters. (2) Beststraightlinefitmethod. (3) FSR = Full-scalerange= 2.13VREF . Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):ADS1258-EP

SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) AllspecificationsatTA = –55°C to125°C, AVDD = 2.5V,AVSS = –2.5V,DVDD = 3.3V,fCLK = 16 MHz (externalclock)or fCLK = 15.729MHz (internalclock),OPA227 bufferbetween MUX outputsand ADC inputs,VREF = 4.096V,and VREFN = –2.5V,unlessotherwisenoted. PARAMETER CONDITIONS MIN TYP (1) MAX UNIT DigitalInput/Output VIH 0.7DVDD DVDD V VIL DGND 0.3DVDD V LogicLevels VOH IOH = 2 mA 0.8DVDD DVDD V VOL IOL = 2 mA DGND 0.2DVDD V InputLeakage VIN = DVDD, GND 10 μA Frequency 0.1 16 MHz MasterClockInput(CLKIO) DutyCycle 40 60 % CrystalFrequency 32.768 kHz ClockOutputFrequency 15.729 MHzCrystalOscillator (seetheCrystalOscillator Start-UpTime (ClockOutput 150 mS section) Valid) ClockOutputDutyCycle 40 60 % Power Supply DVDD 2.7 5.25 V AVSS –2.6 0 V AVDD AVSS + 4.75 AVSS + 5.25 V External TA = –40°C to105°C 0.25 0.6 Clock mA TA = –55°C to125°C 0.25 0.75Operation InternalOscillatorOperation, 0.04 mADVDD SupplyCurrent ClockOutputDisabled InternalOscillatorOperation, 1.4 mAClockOutputEnabled(4) Power-Down (5) 1 25 µA Converting 8.2 12 mA Standby 5.6 mA AVDD, AVSS SupplyCurrent Sleep 2.1 mA Power-Down 2 85 µA Converting 42 62 mW Standby 29 mW Power Dissipation Sleep 11 mW Power-Down 14 μW (4) CLKIO load= 20 pF. (5) No clockappliedtoCLKIO.

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13 14 15 16 17 18 19 20 21 22 23 ADS1258 AIN12 AIN13 AIN14 AIN15 AINCOM VREFP VREFN D GND D VDD C S START D RDY AIN4 AIN5 AIN6 AIN7 M UXOUTP M UXOUTN ADCINP ADCINN AIN8 AIN9 AIN10 AIN11 CLKIO G PIO0 G PIO1 G PIO2 G PIO3 G PIO4 G PIO5 G PIO6 G PIO7 SCLK DIN DO UT AIN3 AIN2 AIN1 AIN0 AVSS AVDD PLLCAP XTAL1 XTAL2 PWDN RESET CLKSEL 48 47 46 45 44 43 42 41 40 39 38 13 14 15 16 17 18 19 20 21 22 23 ADS1258 Top View QFP ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 PIN CONFIGURATION Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):ADS1258-EP

SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com PIN ASSIGNMENTS ANALOG/DIGITAL PIN # NAME INPUT/OUTPUT DESCRIPTION

1 AIN3 AnalogInput AnalogInput3:Single-EndedChannel3,DifferentialChannel1 (–)

2 AIN2 AnalogInput AnalogInput2:Single-EndedChannel2,DifferentialChannel1 (+)

3 AIN1 AnalogInput AnalogInput1:Single-EndedChannel1,DifferentialChannel0 (–)

4 AIN0 AnalogInput AnalogInput0:Single-EndedChannel0,DifferentialChannel0 (+)

NegativeAnalogPower Supply:0V forunipolaroperation,–2.5V forbipolaroperation.5 AVSS Analog (Internallyconnectedtoexposed thermalpad ofQFN package.) 6 AVDD Analog PositiveAnalogPower Supply:5 V forunipolaroperation,2.5V forbipolaroperation. 7 PLLCAP Analog PLL Bypass Capacitor:Connect22nF capacitortoAVSS when usingcrystaloscillator. 8 XTAL1 Analog 32.768-kHzCrystalOscillatorInput1;see theChrystalOscillatorsection. 9 XTAL2 Analog 32.768-kHzCrystalOscillatorInput2;see theChrystalOscillatorsection. 10 PWDN DigitalInput Power-Down Input:Holdlowforminimum oftwo fCLK cyclestoengage low-powermode. 11 RESET DigitalInput ResetInput:Holdlowforminimum oftwo fCLK cyclestoresetthedevice. ClockSelectInput:Low = ActivatesCrystalOscillator,fCLK outputon CLKIO.12 CLKSEL DigitalInput High= DisablesCrystalOscillator,applyfCLK toCLKIO. 13 CLKIO DigitalI/O System ClockInput/Output(See CLKSEL pin.)

14 GPIO0 DigitalI/O General-PurposeDigitalInput/Output0

15 GPIO1 DigitalI/O General-PurposeDigitalInput/Output1

16 GPIO2 DigitalI/O General-PurposeDigitalInput/Output2

17 GPIO3 DigitalI/O General-PurposeDigitalInput/Output3

18 GPIO4 DigitalI/O General-PurposeDigitalInput/Output4

19 GPIO5 DigitalI/O General-PurposeDigitalInput/Output5

20 GPIO6 DigitalI/O General-PurposeDigitalInput/Output6

21 GPIO7 DigitalI/O General-PurposeDigitalInput/Output7

22 SCLK DigitalInput SPI InterfaceClockInput:Data clockedinon risingedge,clockedouton fallingedge. 23 DIN DigitalInput SPI InterfaceData Input:Data isinputtothedevice. 24 DOUT DigitalOutput SPI InterfaceData Output:Data isoutputfromthedevice. 25 DRDY DigitalOutput Data Ready Output:Activelow. 26 START DigitalInput StartConversionInput:Activehigh. 27 CS DigitalInput SPI InterfaceChipSelectInput:Activelow. 28 DVDD Digital DigitalPower Supply:2.7V to5.25V

29 DGND Digital DigitalGround

30 VREFN AnalogInput ReferenceInputNegative

31 VREFP AnalogInput ReferenceInputPositive

32 AINCOM AnalogInput AnalogInputCommon: Common inputpintoallsingle-endedinputs.

33 AIN15 AnalogInput AnalogInput15:Single-EndedChannel15,DifferentialChannel7 (–)

34 AIN14 AnalogInput AnalogInput14:Single-EndedChannel14,DifferentialChannel7 (+)

35 AIN13 AnalogInput AnalogInput13:Single-EndedChannel13,DifferentialChannel6 (–)

36 AIN12 AnalogInput AnalogInput12:Single-EndedChannel12,DifferentialChannel6 (+)

37 AIN11 AnalogInput AnalogInput11:Single-EndedChannel11,DifferentialChannel5 (–)

38 AIN10 AnalogInput AnalogInput10:Single-EndedChannel10,DifferentialChannel5 (+)

39 AIN9 AnalogInput AnalogInput9:Single-EndedChannel9,DifferentialChannel4 (–)

40 AIN8 AnalogInput AnalogInput8:Single-EndedChannel8,DifferentialChannel4 (+)

41 ADCINN AnalogInput ADC DifferentialInput(–)

42 ADCINP AnalogInput ADC DifferentialInput(+)

43 MUXOUTN AnalogOutput MultiplexerDifferentialOutput(–)

44 MUXOUTP AnalogOutput MultiplexerDifferentialOutput(+)

45 AIN7 AnalogInput AnalogInput7:Single-EndedChannel7,DifferentialChannel3 (–)

46 AIN6 AnalogInput AnalogInput6 :Single-EndedChannel6,DifferentialChannel3 (+)

47 AIN5 AnalogInput AnalogInput5:Single-EndedChannel5,DifferentialChannel2 (–)

48 AIN4 AnalogInput AnalogInput4:Single-EndedChannel4,DifferentialChannel2 (+)

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CS(1) DIN DOUT tSCLKtCSSC tSPW tDIST tDIHD tSPW tCSDO Hi-ZHi-Z tCSPW tDOPD tDOHDNOTE:□(1) can□be□tied□low.CS DRDY DOUT tDRDY tDDO ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 PARAMETER MEASUREMENT INFORMATION Figure1. SerialInterfaceTiming SERIAL INTERFACE TIMING CHARACTERISTICS AtTA= –40°C to+105°C (1)and DVDD = 2.7V to5.25V,unlessotherwisenoted. SYMBOL DESCRIPTION MIN MAX UNITS tSCLK SCLK Period 2 τCLK (2) tSPW SCLK HighorLow PulseWidth(exceedingmax resetsSPI interface) 0.8 4096(3) τCLK tCSSC CS Low toFirstSCLK: SetupTime(4) 2.5 τCLK tDIST ValidDIN toSCLK RisingEdge:SetupTime 10 ns tDIHD ValidDIN toSCLK RisingEdge:HoldTime 5 ns tDOPD SCLK FallingEdge toValidNew DOUT: PropagationDelay(5) 20 ns tDOHD SCLK FallingEdge toOld DOUT Invalid:HoldTime 0 ns tCSDO CS HightoDOUT Invalid(tri-state) 5 τCLK tCSPW CS PulseWidthHigh 2 τCLK (1) Ensuredby characterizationonly. (2) τCLK = masterclockperiod= 1/fCLK . (3) Programmable to256 τCLK . (4) CS can be tiedlow. (5) DOUT load= 20 pF ||100kΩ toDGND. Figure2. DRDY Update Timing DRDY UPDATE TIMING CHARACTERISTICS SYMBOL DESCRIPTION TYP UNITS tDRDY DRDY HighPulseWidthWithoutData Read 1 τCLK tDDO ValidDOUT toDRDY FallingEdge (CS = 0) 0.5 τCLK Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):ADS1258-EP

8 0 9 0 1 0 0 1 1 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 Y ears of Estimaed Life Continuous T (°C)J Electromigration Fail Mode Wirebond Voiding Fail Mode ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com ADS1258 48/RTC Package OperatingLifeDeratingChart Figure3. Notes: 1. See datasheetforabsolutemaximum and minimum recommended operatingconditions. 2. Siliconoperatinglifedesigngoal is10 years at 105°C junctiontemperature(does not includepackage interconnectlife).

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Offset (µV) 3000 2500 2000 1500 1000 500 −50 −45 −40 −35 −30 −25 −20 −15 −10 DRATE[1:0] = 11

16384 Points

Offset (µV) 4500 4000 3500 3000 2500 2000 1500 1000 500 −35 −30 −25 −20 −15 −10 DRATE[1:0] = 10 Offset (µV) 3500 3000 2500 2000 1500 1000 500 −20 −16 −12 DRATE[1:0] = 01 Offset (µV) 2500 2000 1500 1000 500 −12 −10 DRATE[1:0] = 00 RMS Noise (µV) Input Voltage (%FS) −100 −75 10075 −50 −25 50 250 DRATE[1:0] = 11 DRATE[1:0] = 10 DRATE[1:0] = 01 DRATE[1:0] = 00 Number of Occurrences RMS Noise (µV) 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 14.5 15.0 50 units from two production lots. DRATE[1:0] = 11 ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 TYPICAL CHARACTERISTICS AtTA = +25°C, AVDD = +2.5V,AVSS = –2.5V,DVDD = +3.3V,fCLK = 16MHz (externalclock)orfCLK = 15.729MHz (internalclock),OPA227 bufferbetween MUX outputsand ADC inputs,VREFP = +2.048V,and VREFN = –2.048V,unlessotherwisenoted. READING HISTOGRAM READING HISTOGRAM Figure4. Figure5. READING HISTOGRAM READING HISTOGRAM Figure6. Figure7. NOISE HISTOGRAM NOISE vs INPUT VOLTAGE Figure8. Figure9. Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9 ProductFolderLink(s):ADS1258-EP

RMS Noise (µV) VREF (V) DRATE[1:0] = 11 DRATE[1:0] = 10 DRATE[1:0] = 01 DRATE[1:0] = 00 RMS Noise (µV) DVDD, AVDD−AVSS (V) DRATE[1:0] = 11 from DVDD from AVDD−AVSS RMS Noise (µV) Temperature (/C0095C) −40 −20 0 20 40 60 80 100 DRATE[1:0] = 11 RMS Noise (µV) Common−Mode Input Voltage (V) Offset (µV) −10 −15 −3 −2 3−1 0 1 2 OFFSET CHOP = 1 OFFSET CHOP = 0 NOISE Number of Occurrences Offset (µV) 200 180 160 140 120 100 −10 311 units from one production lot. CHOP = 1 Number of Occurrences Offset Drift (µV//C0095C) −0.10 −0.09 −0.08 −0.07 −0.06 −0.05 −0.04 −0.03 −0.02 −0.01 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 50 units from two production lots. Based on 20/C0095C intervals over the range of −40/C0095C to +105/C0095C. CHOP = 1 ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, AVDD = +2.5V,AVSS = –2.5V,DVDD = +3.3V,fCLK = 16MHz (externalclock)orfCLK = 15.729MHz (internal clock),OPA227 bufferbetween MUX outputsand ADC inputs,VREFP = +2.048V,and VREFN = –2.048V,unlessotherwise noted. NOISE vs VREF NOISE vs SUPPLY VOLTAGE Figure10. Figure11. NOISE AND OFFSET vs NOISE vs TEMPERATURE COMMON-MODE INPUT VOLTAGE Figure12. Figure13. OFFSET HISTOGRAM OFFSET DRIFT HISTOGRAM Figure14. Figure15.

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Normalized Offset (µV) Temperature (/C0095C) −20 −40 −60 −40 −20 1000 20 80 6040 CHOP = 1 CHOP = 1, No Buffer CHOP = 0, No Buffer 50 units from two production lots. Normalized Offset (µV) VREF (V) 0.5 1.0 −10 Normalized Offset (µV) Time After Power−On (s) −10 0 10 6020 30 40 50 Free−Air Number of Occurrences Absolute Gain Error (ppm) 100 300 500 700 900 1100 1300 1500 1700 1900 320 units from one production lot. Normalized Gain Error (ppm) Temperature (/C0095C) −10 −40 −20 100 0 20 80 6040 Number of Occurrences Gain Drift (ppm//C0095C) −1.8 −1.6 −1.4 −1.2 −1.0 −0.8 −0.6 −0.4 −0.2 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 50 units from two production lots. Based on 20/C0095C intervals over the range of−40/C0095C to +105/C0095C. ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, AVDD = +2.5V,AVSS = –2.5V,DVDD = +3.3V,fCLK = 16MHz (externalclock)orfCLK = 15.729MHz (internal clock),OPA227 bufferbetween MUX outputsand ADC inputs,VREFP = +2.048V,and VREFN = –2.048V,unlessotherwise noted. OFFSET vs TEMPERATURE OFFSET vs VREF Figure16. Figure17. OFFSET POWER-ON WARMUP GAIN ERROR HISTOGRAM Figure18. Figure19. GAIN DRIFT HISTOGRAM GAIN ERROR vs TEMPERATURE Figure20. Figure21. Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11 ProductFolderLink(s):ADS1258-EP

Normalized Gain Error (ppm) VREF (V) −10 −15 −20 Normalized Gain Error (ppm) Time After Power−On (s) −10 0 10 6020 30 40 50 Free−Air Linearity Error (ppm) VREF (V) Linearity Error (ppm) VIN (V) −5 −4 −10 5−3 −2 −1 0 1 2 3 4 VREF = 5V TA = −40/C0095C, −10/C0095C, +25/C0095C, +55/C0095C, +85/C0095C, +105/C0095C INL (ppm) Temperature (/C0095C) −40 −20 120100 0 20 80 6040 Level□(dBFS) Frequency□(Hz) /c4520 /c4540 /c4560 /c4580 /c45100 /c45120 /c45140 /c45160 /c45180 1 10 100k100 1k 10k f□=□1kHz, 0.5dBFS/c45 DRATE[1:0]□=□11 65536□Points ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, AVDD = +2.5V,AVSS = –2.5V,DVDD = +3.3V,fCLK = 16MHz (externalclock)orfCLK = 15.729MHz (internal clock),OPA227 bufferbetween MUX outputsand ADC inputs,VREFP = +2.048V,and VREFN = –2.048V,unlessotherwise noted. GAIN ERROR vs VREF GAIN ERROR POWER-ON WARMUP Figure22. Figure23. INTEGRAL NONLINEARITY vs VREF INTEGRAL NONLINEARITY vs INPUT LEVEL Figure24. Figure25. INTEGRAL NONLINEARITY vs TEMPERATURE OUTPUT SPECTRUM Figure26. Figure27.

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T emperature□Sensor□Voltage□(mV) /c45 40 T emperature□( C)/c176 120/c45 20 0 20 60 40 100 80 Only□ADS1258 T emperature□Forced; T est□PCB□in□Free-Air ADS1258□and□T est□PCB T emperatures□Forced□T ogether Number of Occurrences Temperature Reading (/C0095C) 50 units from two production lots. TA = +25/C0095C Ratio (µA/µA) Temperature (/C0095C) −40 −20 120100 0 20 80 6040 Number of Occurrences Ratio (µA/µA) 14.0 14.5 15.0 15.5 16.0 16.5 17.0 17.5 18.0 18.5 19.0 50 units from two production lots. AVDD, AVSS Current (mA) Temperature (/C0095C) DVDD Current (mA) 1.0 0.8 0.6 0.4 0.2 −40 −20 120 0 20 40 60 80 100 AVDD, AVSS DVDD RMS Noise (µV) Master Clock (MHz) Linearity Error (ppm) 0.1 1 10010 DRATE[1:0] = 11 Noise Linearity ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 TYPICAL CHARACTERISTICS (continued) AtTA = +25°C, AVDD = +2.5V,AVSS = –2.5V,DVDD = +3.3V,fCLK = 16MHz (externalclock)orfCLK = 15.729MHz (internal clock),OPA227 bufferbetween MUX outputsand ADC inputs,VREFP = +2.048V,and VREFN = –2.048V,unlessotherwise noted. TEMPERATURE SENSOR VOLTAGE vs TEMPERATURE TEMPERATURE SENSOR READING HISTOGRAM Figure28. Figure29. SENSOR BIAS CURRENT SOURCE RATIO SENSOR BIAS CURRENT SOURCE RATIO HISTOGRAM vs TEMPERATURE Figure30. Figure31. SUPPLY CURRENT vs TEMPERATURE NOISE AND INL vs MASTER CLOCK Figure32. Figure33. Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13 ProductFolderLink(s):ADS1258-EP

16−Channel MUX AVDD Sensor Bias M UXOUTP MUX OUTN ADCINP GNDAD CINN ADC Channel Control Supply Monitor GPIO G PIO[7:0]DVDD Temperature Ext Ref Monitor Internal Ref ADC CLKSELCLKIO ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com OVERVIEW The ADS1258 is a flexible,24-bit,low-noiseADC VIN = (ADCINP – ADCINN), againstthe differential optimized for fast multi-channel,high-resolution referenceinput,VREF = (VREFP – VREFN). The measurement systems. The converterprovidesa digitalfilterreceives the modulator signal and maximum channelscan rateof23.7kSPS,providinga providesa low-noisedigitaloutput.The ADC channel complete16-channelscan inlessthan700μs. block controlsthe multiplexerAuto-Scan feature. Channel Auto-Scan occurs at a maximum rateofFigure34 shows theblockdiagramoftheADS1258. 23.7kSPS. Slower scan rates can be used withThe inputmultiplexerselectsthe analog inputpins correspondingincreasesinresolution.connected to the multiplexer output pins (MUXOUTP/MUXOUTN). Externalsignalconditioning Communication is handled over an SPI-compatible can be used between themultiplexeroutputpinsand serialinterfacewith a set of simple commands the ADC input pins (ADCINP/ADCINN) or the providingcontroloftheADS1258. Onboard registers multiplexeroutputcan be routedinternallytotheADC storethe varioussettingsforthe inputmultiplexer, inputswithoutexternalcircuitry.Selectablecurrent sensordetectbias,datarateselection,etc.Eitheran sourceswithinthe inputmultiplexercan be used to external32.768kHzcrystal,connectedtopinsXTAL1 biassensorsor detectfora failedsensor.On-chip and XTAL2, oran externalclockappliedtopinCLKIO system functionreadings provide readback of can be used as the clocksource.When usingthe temperature,supplyvoltage,gain,offset,and external externalcrystaloscillator,the system clock is reference. availableas an outputfordrivingotherdevicesor controllers.General-purpose digitalI/Os (GPIO)The ADS1258 convertercomprises a fourth-order, provideinputand outputcontrolofeightpins.delta-sigmamodulatorfollowedby a programmable digital filter. The modulator measures the differentialinput signal, Figure34. ADS1258 Block Diagram

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3pF R eff= 40kΩ (fCLK = 16MHz) AVDD AVSS VREFP VREFN AVSS /C0042100mV /C0116/C0466VREFP or VREFN /C0467/C0116AVDD /C0041100mV ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 MULTIPLEXER INPUTS A simplifieddiagram of the input multiplexeris illustratedinFigure36.The multiplexerconnectsone of 16 single-endedexternalinputs,one of eight differentialexternalinputs,or one of the on-chip internalvariablestotheADC inputs.The outputofthe channel multiplexercan be routedto externalpins and then to the inputof the ADC. This flexibility allowsforuse ofexternalsignalconditioning.See the ExternalMultiplexerLoop section. ESD diodesprotecttheanaloginputs.To keep these diodesfrom turningon, make sure the voltageson the inputpinsdo not go below AVSS by more than 100 mV, and likewisedo notexceed AVDD by more than100 mV: AVSS – 100mV < (AnalogInputs)< AVDD + 100 mV. Overdrivingthe multiplexerinputsmay affectthe conversions of other channels. See the Input Overload Protectiondescriptionin the Hardware Figure35. SimplifiedReferenceInputCircuitConsiderationssegment oftheApplicationssection. ESD diodes protectthe referenceinputs.To keepThe convertersupportstwo modes ofchannelaccess thesediodesfromturningon,make surethevoltagesthroughthemultiplexer:theAuto-Scanmode and the on thereferencepinsdo notgo below AVSS by moreFixed-Channelmode. These modes are selectedby than 100mV, and likewisedo not exceed AVDD bythe MUXMOD bit of registerCONFIG0. The 100mV, as describedinEquation1:Auto-Scan mode scans through the selected channels automatically,with break-before-make (1) switching.The Fixed-Channelmode requirestheuser A high-qualityreferencevoltage is essentialforto set the channel address for each channel achievingthe best performancefrom the ADS1258.measured. Noise and drifton the referencedegrade overall system performance.It is especiallycriticalthatVOLTAGE REFERENCE INPUTS specialcare be givento the circuitrythatgenerates(VREFP, VREFN) thereferencevoltagesand thelayoutwhen operating The voltagereferenceforthe ADS1258 ADC isthe inthelow-noisesettings(thatis,withlow datarates) differentialvoltagebetween VREFP and VREFN: to prevent the voltage reference from limiting VREF = VREFP – VREFN. The referenceinputsuse a performance.See theReferenceInputsdescriptionin structuresimilartothatoftheanaloginputswiththe the Hardware Considerationssegment of the circuitryon thereferenceinputsshown inFigure35. Applicationssection. The loadpresentedby theswitchedcapacitorcan be modeled withan effectiveresistance(Reff) of 40 kΩ forfCLK = 16 MHz. Note thattheeffectiveimpedance of the referenceinputsloadsan externalreference witha non-zerosourceimpedance. Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15 ProductFolderLink(s):ADS1258-EP

NOTE: ESD diodes not shown. Supply Monitor AVDD AVSS AVDD AVSS Temperature Sensor Monitor 1x 2x 8x 1x AVDD (AVDD − AVSS)/2AVSS Sensor Bias Offset Monitor MUXOUTP MUXOUTN ADCINP ADCINN Internal ReferenceAVSS ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com Figure36. InputMultiplexer

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NOTE: ESD input diodes not shown. Figure 38. S1 switches close during the input witha periodoftSAMPLE = 2/fCLK .

50Ω 32.768kHz(1) 4.7pF 4.7pF 22nF CLKSEL XTAL1 XTAL2 PLLCAP AVSS CLKIO Clock Output (15.729MHz) 0V to−2.5V NOTE: (1) Parallel resonant type, CL = 12.5pF , ESR = 35kΩ (max). Place the crystal and load capacitors as close as possible tothe device pins. Oscillator and□PLL MUX CLKENB Bit Internal□Master□Clock□(f )CLK CLKSEL CLKIO XTAL1 XTAL2 PLL 50Ω CLKSEL XTAL1 XTAL2 PLLCAP DVDD CLKIO Clock Input (16MHz) 2.7V to 5V No Connection ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com MASTER CLOCK (fCLK ) The ADS1258 oversamplestheanaloginputata high rate.Thisrequiresa high-frequencymaster clockto be suppliedtotheconverter.As shown inFigure39, theclockcomes fromeitheran internaloscillator(with externalcrystal),oran externalclocksource. Figure40. CrystalOscillatorConnection Table1.System Clock Source CLKSEL CLKENB PIN CLOCK SOURCE BIT CLKIO FUNCTION 32.768kHz Disabled0 0CrystalOscillator (internallygrounded)Figure39. Clock GenerationBlock Diagram 32.768kHz0 1 Output(15.729MHz)CrystalOscillator The CLKSEL pin determines the source of the 1 ExternalClockInput X Input(16MHz) system clock,as shown inTable 1. The CLKIO pin functionsas an inputor as an output.When the Table2.Approved CrystalVendorsCLKSEL pinissetto'1',CLKIO isconfiguredas an inputtoreceivethemasterclock.When theCLKSEL VENDOR CRYSTAL PRODUCT pin isset to '0',the crystaloscillatorgeneratesthe C-001R clock.The CLKIO pin can then be configuredto Epson MC-306 32.7680K-A0outputthemasterclock.When theclockoutputisnot FC-135 32.7680KA-A0needed, itcan be disabledto reduce devicepower ECS ECS-.327-12.5-17-TRconsumption. CrystalOscillator ExternalClock Input An on-chiposcillatorand Phase-Locked Loop (PLL) When usingan externalclocktooperatethedevice, togetherwith an externalcrystalcan be used to apply the master clockto the CLKIO pin.For this generatethe system clock.For thismode, tiethe mode, the CLKSEL pin is tiedhigh.CLKIO then CLKSEL pin low. A 22nF PLL filtercapacitor, becomes an input,as shown inFigure41. connectedfrom thePLLCAP pintotheAVSS pin,is required.The internalclockofthePLL can be output totheCLKIO todriveotherconvertersor controllers. Ifnotused,disabletheclockoutputtoreducedevice power consumption;see Table 1 forsettings.The clock output is enabled by a registerbitsetting (defaultis ON). Figure 40 shows the oscillator connections.Placethesecomponents as closetothe pinsas possibleto avoidinterferenceand coupling. Do notconnectXTAL1 or XTAL2 toany otherlogic. The oscillatorstart-uptimemay vary,dependingon thecrystaland ambienttemperature.The usershould Figure41. ExternalClock Connectionverifytheoscillatorstart-uptime.

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128(411b/C0042DR /C00414.265625/C0041TD )/C00322CHOP fCLK 128(411b/C0042DR /C0041CHOP (4.265625/C0041TD ))/C00322CHOP Analog Modulator sinc5 Filter Programmable Averager Data Rate = fCLK /128Modulator Rate = fCLK /2 Num_Ave Data Rate(1)= fCLK /(128× Num_Ave) NOTE: (1) Data rate for Fixed−Channel Mode, Chop = 0, Delay = 0. ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 Make suretouse a clocksourcecleanfrom jitteror rate—filtermore forhigherresolution,filterlessfor interference.Ringingor under/overshootshould be higher data rate.The filteris comprised of two avoided.A 50 Ω resistorinserieswiththeCLKIO pin sections,a fixedfilterfollowedby a programmable (placedclosetothesource)can oftenhelp. filter.Figure42 shows theblockdiagramofthefilter. Data is suppliedto the filterfrom the analog modulatorat a rateof fCLK /2.The fixedfilteris aADC fifth-ordersincfilterwitha decimationvalueof64 thatThe ADC blockoftheADS1258 iscomposed oftwo outputsdataata rateoffCLK /128.The second stageblocks:a modulatorand a digitalfilter. of the filterisa programmable averager(first-order sincfilter)withthe number of averages set by theModulator DRATE[1:0]bits. The modulatorconvertstheanaloginputvoltageinto The data rate depends upon the system clocka Pulse Code Modulated(PCM) data stream.When frequency(fCLK ) and theconverterconfiguration.Thethe levelof differentialanalog input(ADCINP – data rate can be computed by Equation 2 orADCINN) isnear the levelof the referencevoltage, Equation3:the '1'densityof the PCM data stream is at its Data Rate (Auto-Scan):highest.When thelevelofthedifferentialanaloginput isnear zero,thePCM '0'and '1'densitiesare nearly equal. The fourth-ordermodulator shifts the (2)quantizationnoise to a high frequency(outof the passband)where thedigitalfiltercan easilyremove it. Data Rate (Fixed-ChannelMode): The modulatorcontinuouslychops theinput,resulting in excellentoffsetand offsetdriftperformance.Itis (3) importanttonotethatoffsetor offsetdriftoriginating Where:from the externalcircuitryis not removed by the DR = DRATE[1:0]registerbits(binary).modulatorchopping.These errorscan be effectively removed by using the externalchopping featureof CHOP = Chop registerbit. theADS1258 (seetheExternalChoppingsection). TD = timedelayvaluegiveninTable5 from the DLY[2:0]registerbits(128/fCLK periods).DigitalFilter The programmable low-passdigitalfilterreceivesthe modulator output and produces a high-resolution digitaloutput.By adjustingthe amount of filtering, tradeoffscan be made between resolutionand data Figure42. Block Diagram ofDigitalFilter Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19 ProductFolderLink(s):ADS1258-EP

/C0356H /C0466f/C0467/C0356/C0043/C0356H sinc 5 /C0466f/C0467/C0356/C0032/C0356H Averager/C0466f/C0467/C0356/C0043 /C0551 /C0551 /C0551 /C0551 sin/C0466128/C0112/C0032f fCLK /C0467 64 /C0032sin/C04662/C0112/C0032f fCLK /C0467 /C0551 /C0551 /C0551 /C0551 /C0032 /C0551 /C0551 /C0551 /C0551 sin/C0466128/C0112/C0032Num_Ave /C0032f fCLK /C0467 Num_Ave /C0032sin/C0466128/C0112/C0032f fCLK /C0467 /C0551 /C0551 /C0551 /C0551 −20 −40 −60 −80 −100 −120 −140 Frequency (kHz) Gain (dB) 125 2500 375 500 625 Data Rate Auto−Scan Mode (23.739kSPS) Data Rate Fixed−Channel Mode (125kSPS) −20 −40 −60 −80 −100 −120 −140 Frequency (kHz) Gain (dB) 125 2500 375 500 625 Data Rate Auto−Scan Mode (15.123kSPS) Data Rate Fixed−Channel Mode (31.25kSPS) ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com Table 3 shows a listingof the averagingand data Figure44 shows theresponsewithaveragingsetto4 rates for each of the four DRATE[1:0] register (DRATE[1:0] = 10). 4-reading, post-averaging settingsfortheAuto-Scanand Fixed-Channelmodes, produces three equally-spacednotches between withCHOP, DLY = 0.Note thatthedataratescales each main notch of the sinc5 filter.The frequency directlywithfCLK . For example,reducingfCLK by 2x responseofDRATE[1:0]= 01 and 00 followsa similar reducesthemaximum datarateby 2x. pattern,but with15 and 63 equally-spacednotches between themain sinc5 notches,respectively. FREQUENCY RESPONSE The low-passdigitalfiltersetsthe overallfrequency responsefortheADS1258. The filterresponseisthe product of the responses of the fixed and programmable filtersections and is given by Equation4: (4) The digitalfilterattenuatesnoise on the modulator outputincludingnoisefrom withinthe ADS1258 and externalnoise present withinthe ADS1258 input signal.Adjustingthefilteringby changingthenumber Figure43. Frequency Response, DRATE[1:0] = 11 ofaveragesused intheprogrammable filterchanges the filterbandwidth. With a higher number of averages,the bandwidthisreduced and more noise isattenuated. The low-passfilterhas notches(orzeros)atthedata outputrateand multiplesthereof.The sinc5 partof the filterproduces wide notches at fCLK /128 and multiplesthereof.At thesefrequencies,thefilterhas zerogain.Figure43 shows theresponsewithno post averaging.Note thatin Auto-Scan mode, the data rateisreduced whileretainingthe same frequency responseas inFixed-Channelmode. With programmable averaging,the wide notches produced by the sinc5 filterremain,but a number of narrow notchesare superimposedin the response. The number of the superimposed notches is determined by the number of readings averaged(minusone). Figure44. Frequency Response, DRATE[1:0] = 10 Table3.Data Rates(1) DATA RATE AUTO-SCAN DATA RATE FIXED-CHANNEL –3dB BANDWIDTH DRATE[1:0] Num_Ave (2) MODE (SPS)(3) MODE (SPS) (Hz) 11 1 23739 125000 25390 10 4 15123 31250 12402 01 16 6168 7813 3418 00 64 1831 1953 869 (1) fCLK = 16 MHz, Chop = 0,and Delay= 0. (2) Num_Ave isthenumber ofaveragesperformedby thedigitalfiltersecond stage. (3) InAuto-Scanmode, thedataratelistedisfora singlechannel;theeffectivedatarateformultiplechannels(ona per-channelbasis)is thevalueshown inFigure43 and Figure44 dividedby thenumber ofactivechannelsina scan loop.

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Data Not Settled Settled Data DRDY 1 2 6 Step Input Data Not Settled Settled Data −20 −40 −60 −80 −100 −120 −140 Frequency (MHz) Gain (dB) 4 80 12 16 DRATE[1:0] = 11 125kSPS Fixed−Channel Mode ENOB /C0043ln/C0466FSR /C0324RMS Noise/C0467 ln(2) ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 ALIASING input.For most modes ofoperation,theanaloginput must be stableforone completeconversioncycletoThe digitalfilterlow-passcharacteristicrepeatsat provide settled data. In Fixed-Channel modemultiplesof the modulatorrateof fCLK /2.Figure45 (DRATE[1:0]= 11),the inputmust be stableforfiveshows theresponseplottedoutto16MHz atthedata completeconversioncycles.rateof125 kSPS (Fixed-Channelmode). Noticehow theresponsesnear DC, 8 MHz, and 16 MHz are the same. The digitalfilterattenuateshigh-frequency noise on the ADS1258 inputsup to the frequency where the response repeats.However, noise or frequencycomponents presenton the analog input where theresponserepeatsaliasintothepassband. For most applications,an anti-aliasfilteris recommended to remove the noise. A simple first-orderinput filterwith a pole at 200kHz provides–34dB rejectionatthefirstimage frequency. Figure46. Asynchronous Step-InputSettling Time (DRATE[1:0]= 10,01,00) Figure47. Asynchronous Step-InputSettling Time (Fixed-ChannelMode, DRATE[1:0] = 11) NOISE PERFORMANCE Figure45. Frequency Response Out to16MHz The ADS1258 offersoutstandingnoiseperformance thatcan be optimizedby adjustingthedatarate.As theaveragingisincreasedby reducingthedatarate,Referringto Figure43 and Figure44, frequencies noise drops correspondingly.See Table 4 forpresenton the analoginputabove the Nyquistrate Input-ReferredNoise, Noise-Free Resolution,and(samplerate/2)arefirstattenuatedby thedigitalfilter EffectiveNumber of Bits (ENOB). The noiseand thenaliasintothepassband. performanceof low-levelsignalscan be improved substantiallyby usingexternalgain.Note thatwhenSETTLING TIME Chop = 1, the data rateisreduced by 2x and the The design of the ADS1258 providesfully-settled noiseisreducedby 1.4x. data when scanningthroughthe inputchannelsin ENOB isdefinedinEquation5:Auto-Scanmode. The DRDY flagassertslow when the data for each channel is ready. It may be necessary to use the automaticswitchtime delay (5)featureto providetime forsettlingof the external where FSR isthefull-scalerange.bufferand associatedcomponents afterchannel switching.When theconverterisstarted(START pin The data for the Noise-FreeResolution(bits)istransitionshighorStartCommand) withstableinputs, calculatedin the same way as ENOB, exceptthe firstconverteroutput is fullysettled.When peak-to-peaknoiseisused.applyingasynchronousstepinputs,the settlingtime is somewhat different.The step-inputsettlingtime As seen in the illustrationof Noise vs VREF diagrams (Figure 46 and Figure 47) show the (Figure10),theconverternoiseisrelativelyconstant converterstepresponsewithan asynchronousstep versus the reference voltage. Optimum signal-to-noiseratioof the converterisachievedby usinghigherreferencevoltages(VREF MAX = AVDD – AVSS). Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21 ProductFolderLink(s):ADS1258-EP

SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com Table4.Noise Performance(1) DATA RATE EFFECTIVE DATA RATE FIXED-CHANNEL INPUT-REFERRED NOISE-FREE NUMBER AUTO-SCAN MODE MODE NOISE RESOLUTION OF BITS DRATE[1:0] (SPS) (SPS) (µVRMS ) (Bits) (ENOB) 11 23739 125000 12 16.8 19.5 10 15123 31250 7.9 17.4 20.1 01 6168 7813 4.5 18.2 20.9 00 1831 1953 2.8 18.9 21.6 (1) VREF = 4.096V,fCLK = 16MHz, Chop = 0,Delay= 0,Inputsshorted,and 2048 sample size. Table5.EffectiveData Rates withSwitch-TimeDelay (Auto-ScanMode) (1) TIME DELAY TIME DELAY DLY[2:0] (128/fCLK periods) (μS) DRATE[1:0] = 11 DRATE[1:0] = 10 DRATE[1:0] = 01 DRATE[1:0] = 00 000 0 0 23739 15123 6168 1831 001 1 8 19950 13491 5878 1805 010 2 16 17204 12177 5614 1779 011 4 32 13491 10191 5151 1730 100 8 64 9423 7685 4422 1639 101 16 128 5878 5151 3447 1483 110 32 256 3354 3104 2392 1247 111 48 384 2347 2222 1831 1075 (1) Time delayand dataratesscalewithfCLK .IfChop = 1,thedataratesarehalfthoseshown.fCLK = 16MHz, Auto-ScanMode. Use of the switchtime delay registerreduces theEXTERNAL MULTIPLEXER LOOP effectivechanneldatarate.Table5 shows theactual data ratesderivedfrom Equation2, when usingtheThe externalmultiplexerloop consists of two switchtimedelayfeature.differentialmultiplexeroutputpinsand two differential necessarytoallowforsettling.To bypass theexternalmultiplexerloop,connectthe ADC inputpinsdirectlytothemultiplexeroutputpins, In estimatingthe time delay thatmay be required,orselectinternalbypass connection(BYPASS = 0 of Table6 liststhetimedelay-to-timeconstantratio(t/τ)CONFIG0). Note thatthemultiplexeroutputpinsare and the correspondingfinalsettleddata in % andactiveregardlessofthebypasssetting. number ofbits. SWITCH TIME DELAY Table6.SettlingTime When using the ADS1258 in the Auto-Scan mode, FINAL SETTLING FINAL SETTLING where theconverterautomaticallyswitchesfrom one t/τ(1) (%) (Bits) channelto the next,the settlingtimeof the external 1 63 2 signalconditioningcircuitbecomes important.Ifthe 3 95 5channel does not fullysettleafterthe multiplexer 5 99.3 7channelisswitched,thedatamay notbe correct.The 7 99.9 10ADS1258 providesa switchtimedelayfeaturewhich automaticallyprovidesa delayafterchannelswitching 10 99.995 14 toallowthechanneltosettlebeforetakinga reading. 15 99.9999 20 The amount oftimedelayrequireddepends primarily 17 99.999994 24on thesettlingtimeoftheexternalsignalconditioning. Additionalconsiderationmay be needed to account forthe settlingof the inputsource arisingfrom the transientgeneratedfromchannelswitching. (1) Multipletimeconstantscan be approximatedby: (τ1 2 + τ2 2+…).

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C 80Ω AVDD R LR S ADCINP 80Ω AVSS ADCINN MUXOUTP MUXOUTN ISDC ISDC ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 SENSOR BIAS The currentsourceisconnectedtotheoutputofthe Figure48 shows a simplifieddiagram of ADS1258 The timetochargetheexternalcapacitanceisgiveninputstructurewiththeexternalsensormodeled as a inEquation6:resistanceR S between two inputpins.The two 80Ω seriesresistors,R MUX , model the ADS1258 internal resistances.R L represents the effectiveinput (6) thesensorisa directshort(thatis,R S = 0),thereis OPEN-SENSOR DETECTIONstilla smallsignalmeasured by the ADS1258 when thebiasingisenabled:ISDC [2RMUX׀׀R L]. For open-sensordetection,set the biasingto either 1.5μA or24μA. Then selectthechanneland readthe outputcode.When a sensoropens,thepositiveinput ispulledtoAVDD and thenegativeinputispulledto AVSS. Because ofthisconfiguration,theoutputcode trends toward positivefull-scale.Note that the interactionof the multiplexerresistancewith the currentsourcemay leadto degradationinconverter linearity.Itis recommended to enable the current sourceonlyperiodicallytocheck foropen inputsand discardtheassociateddata. EXTERNAL DIODE BIASING The currentsource can be used to bias external diodesfortemperaturesensing.Scan theappropriate channels with the currentsource set to 24µA. Re-scan the same channelswiththe currentsource setto1.5µA. The differenceindiodevoltagereadings resultingfrom the two bias currentsis directly proportionaltotemperature. Note thaterrorsin currentratio,diode and cableFigure48. Sensor Bias Structure resistance,or thenon-idealityfactorofthediodecan leadtoerrorsintemperaturereadings.These effects can be compensated by characterizationor by calibratingthediodeatknown temperatures. Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23 ProductFolderLink(s):ADS1258-EP

(chopping) AINn AINn MUXOUTP MUXOUTN ADCINP Optional Signal Conditioning ADCINN GPIO Pin GPIO Data (read) GPIO Data (write) GPIO Control ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com EXTERNAL CHOPPING GPIO DIGITAL PORT (GPIOx) The modulator of the ADS1258 incorporatesa The ADS1258 has eight dedicated pins for chopping front-endwhich removes offseterrors, General-PurposeDigitalI/O (GPIO).The digitalI/O providingexcellentoffsetand offsetdriftperformance. pinsare individuallyconfigurableas eitherinputsor However, offsetand offsetdriftoriginatingfrom as outputs through the GPIOC (GPIO-Configure) externalsignalconditioningare not removed by the register.The GPIOD (GPIO-Data)registercontrols modulator.The ADS1258 has an additionalchopping the levelof the pins.When reading the GPIOD featurethatremoves externaloffseterrors(CHOP = register,the data returnedis the levelof the pins, 1). whethertheyare programmed as inputsor outputs. As inputs,a writeto the GPIOD has no effect.AsWith externalchoppingenabled,the convertertakes outputs,a writetotheGPIOD setstheoutputvalue.two readingsinsuccessionon thesame channel.The firstreadingistakenwithone polarityand thesecond DuringStandby and Power-Down modes, the GPIO reading is taken with the oppositepolarity.The remainsactive.Ifconfiguredas inputs,theymust be converteraverages the two readings,cancelingthe driven(do not float).Ifconfiguredas outputs,they offset,as shown inFigure49.Withchoppingenabled, continuetodrivethepins.The GPIO pinsare setas theeffectivereadingisreducedtohalfofthenominal inputsafterpower-on or aftera reset.Figure 50 readingrate. shows theGPIO portstructure. Figure49. ExternalChopping Figure50. GPIO PortPinNote thatsincetheinputsarereversedundercontrol of the ADS1258, a delaytimemay be necessaryto providetime forexternalsignalconditioningto fully POWER-DOWN INPUT (PWDN)settlebefore the second phase of the reading The PWDN pin is used to controlthe power-downsequence starts(seetheSwitchtimeDelaysection). timebeforereadingscan be taken,as shown inthe Power-Up Timing section.Note thatin power-down mode, theinputsoftheADS1258 must stillbe driven and thedevicecontinuestodrivetheoutputs.

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3.2V, typical CLKSEL or AVDD − AVSS (1) or PWDN NOTE: (1) Shown with DVDD stable. CLKIO Device Ready tWAKE 3.2V, typical or AVDD − AVSS (1) PWDN, CLKSEL NOTE: (1) Shown with DVDD stable. ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 Table7.Wake-Up TimesPOWER-UP TIMING tWAKEWhen poweringup the deviceor takingthe PWDN INTERNAL tWAKEpin high to wake the device,a wake-up time is CONDITION OSCILLATOR (1) EXTERNAL CLOCKrequiredbeforereadingscan be taken.When using PWDN orCLKSEL tOSC 2/fCLKtheinternaloscillator,thewake-up timeiscomposed AVDD – AVSS tOSC + 218/fCLK 218/fCLKoftheoscillatorstart-uptimeand thePLL locktime, and ifthesuppliesarealsobeingpowered,thereisa resetintervaltimeof218 fCLK cycles.Note thatCLKIO POWER-UP SEQUENCE isnot validduringthe wake-up period,as shown in The analog and digitalsuppliesshould be appliedFigure51. beforeany analogordigitalinputisdriven.The power suppliesmay be sequenced inany order.The internal master resetsignalis generated from the analog power supply (AVDD – AVSS), when the level reaches approximately3.2 V. The power-up master resetsignalis functionallythe same as the Reset Command and theRESET inputpin. Reset Input(RESET) When RESET isheldlow foratleasttwo fCLK cycles, allregistersare resettotheirdefaultvaluesand the digitalfilteriscleared.When RESET isreleasedhigh, thedeviceisreadytoconvertdata. Clock SelectInput(CLKSEL) Thispinselectsthe sourceof the system clock:the crystaloscillatoror an externalclock.Tie CLKSELFigure51. Device Wake Time with low to selectthe crystaloscillator.When using anInternalOscillator externalclock(appliedtotheCLKIO pin),tieCLKSEL high.When using the devicewithan externalclock,the wake-up timeis2/fCLK periodswhen waking up with Clock Input/Output(CLKIO)the PWDN pin and 218/fCLK periodswhen powering Thispinserveseitheras a clockoutputorclockinput,the supplies,allaftera validCLKIO is applied,as depending on the stateof the CLKSEL pin.Whenshown inFigure52. usingan externalclock,applythe clockto thispin and set the CLKSEL pin high.When using the internaloscillator,thispinhas theoptionofproviding a clockoutput.The CLKENB bitofregisterCONFIG0 enablestheclockoutput(defaultisenabled). StartInput(START) The START pin is an inputthatcontrolsthe ADC process.When the START pin is taken high,the converter starts converting the selected input channels.When the START pin is taken low, the conversionin progressruns to completionand the converterisstopped.The devicethen entersone of the two idlemodes (see the IdleModes sectionfor more details).See theConversionControlsectionfor detailsofusingtheSTART pin.Figure52. Device Wake Time withExternalClock Table 7 summarizes the wake-up times using the internaloscillatorand theexternalclockoperations. (1) Wake-up timesfortheinternaloscillatoroperationaretypical and may varydependingon crystalcharacteristicsand layout capacitance.The usershouldverifytheoscillatorstart-up times(tOSC = oscillatorstart-uptime). Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25 ProductFolderLink(s):ADS1258-EP

tDRDYPLS = 1 fCLK ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com Data Ready Output (DRDY) DRDY is usuallyconnected to an interruptof a availableonce again.DRDY then pulseshigh,then Output Data Scalingand Over-Rangelowtoindicatenew dataisavailable;see Figure53. The ADS1258 is scaledsuch thatthe outputdata code resultingfrom an inputvoltageequalto ±VREF has a margin of 6.6% before clipping.This architectureallowsoperationofappliedinputsignals atornearfull-scalewithoutoverloadingtheconverter. Specifically,thedeviceiscalibratedso that: 1LSB = VREF /780000h, and theoutputclipswhen: |VIN|≥ 1.06 × VREF . Table 8 summarizes the idealoutputcodes versus inputsignals. Figure53. DRDY Timing (See Figure2 fortheDRDY Pulse) Table8.IdealOutput Code vs InputSignal INPUT SIGNAL VIN (ADCINP – ADCINN) IDEAL OUTPUT CODE (1) DESCRIPTION ≥ +1.06 VREF 7FFFFFh Maximum PositiveFull-ScaleBeforeOutputClipping +VREF 780000h VIN = +VREF +1.06 VREF /(223 – 1) 000001h +1LSB 0 000000h BipolarZero –1.06 VREF /(223 – 1) FFFFFFh –1LSB –VREF 87FFFFh VIN = –VREF ≤ –1.06 VREF × (223/223 – 1) 800000h Maximum NegativeFull-ScaleBeforeOutputClipping (1) Excludeseffectsofnoise,linearity,offset,and gainerrors.

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External Reference(V)/C0043Code 786432 Total Analog Supply Voltage(V)/C0043Code 786432 T emperature( C)□=/c176 T emp□Reading( V) 168,000 V/c45 /c109/c109 T emp□Sensor□Coefficient +□25 C/c176 Device Gain/C0466V/C0324V/C0467/C0043Code 7864320 ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 INTERNAL SYSTEM READINGS The scale factorof Equation9 convertsthe code valuetoexternalreferencevoltage: Analog Power-Supply Reading (VCC) (9)The analog power-supplyvoltageof the ADS1258 the referencehas settledto ensure an accurateThe scale factorof Equation7 convertsthe code reading.Note thatitisrequiredto disablechoppingvaluetovolts: (CHOP = 0)priortotakingthisreading. (7) Temperature Reading (TEMP) approximately50 mV higherthanthelowertrippoint. As a resultof the low thermalresistanceof the package to the printedcircuitboard (PCB), theThe digitalsupply (DVDD) may be monitoredby internaldevice temperature tracks the PCBlooping-backthesupplyvoltagetoan inputchannel. temperatureclosely.Note alsothatself-heatingoftheA resistordividermay be requiredforbipolarsupply ADS1258 causes a higher reading than theoperationto reduce the DVDD levelto withinthe temperatureof the surroundingPCB. Note thatitisrangeoftheanalogsupply. requiredto disablechopping (CHOP = 0) priorto takingthisreading.Gain Reading (GAIN) The scale factorof Equation 10 converts theIn this configuration,the externalreference is temperaturereadingto°C. Beforeusingtheequation,connected both to the analog input and to the thetemperaturereadingcode must firstbe scaledtoreferenceinputof the ADC. The data from this μV.registerindicatesthegainofthedevice. The followingscalefactor(Equation8) convertsthe code valuetodevicegain: (10) (8) Where Temp Sensor Coefficient= 563µV/°C (ifthe ADS1258 and testPCB temperaturesare forcedTo correctthe devicegain error,the user software together),or 394µV/°C (if only the ADS1258can divideeach converterdata valueby the device temperatureisforcedand thetestPCB isinfree-air).gain.Note thatthiscorrectsonly for gain errors originatingwithinthe ADC; system gain errors OffsetReading (OFFSET)because ofan externalgainstageerrororbecause of referenceerrorsare notcompensated.Note thatitis The differentialoutputof the multiplexeris shortedrequiredtodisablechopping(CHOP = 0)alsopriorto togetherand set to a common-mode voltageoftakingthisreading. (AVDD – AVSS)/2.Ideally,thecode fromthisregister functionis0h,butvariesbecause ofthenoiseoftheReferenceReading (REF) ADC and offsetsstemming from the ADC and externalsignalconditioning.Thisregistercan be usedIn this configuration,the externalreference is to calibrateor trackthe offsetof the ADS1258 andconnected to the analog input and an internal externalsignalconditioning.The chop featureof thereferenceisconnectedto the referenceof the ADC. ADC can automaticallyremove offsetand offsetdriftThe datafromthisregisterindicatesthemagnitudeof fromtheexternalsignalconditioning;see theExternaltheexternalreferencevoltage. Choppingsection. Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27 ProductFolderLink(s):ADS1258-EP

Data Ready, Index to Next Channel or DRDY START□Pin tSDSU tDRHD SYMBOL DESCRIPTION MIN UNIT tSDSU 8 /c116CLK 8 /c116CLKtDRHD START□to Setup□TimeDRDY to□Halt□Further□Conversions DRDY to□START□Hold□Time to□Complete□Current□Conversion DRDY START Pin Data Ready, Index to Next Channel IdleIdle Mode Converting ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com Pulse Convert CommandCONVERSION CONTROL Figure55 alsoshows thestartofconversionswiththeThe conversionsof the ADS1258 are controlledby risingedge of the START pin.Ifthe START pin istheSTART pin.Conversionsbeginwhen theSTART taken high,and then low priorto completionof thepinistakenhighand conversionsare stoppedwhen conversioncycle(8 τCLK beforeDRDY assertslow),the START pin is taken low. For continuous onlythecurrentchannelisconvertedand thedeviceconversions,tietheSTART pinhigh.The START pin entersthestandbyor sleepmodes waitingfora newcan alsobe tiedlow and the conversionscontrolled startcondition.Figure56 shows the START pin toby the PULSE convert command. The PULSE DRDY timing.The same functionof conversionconvertcommand convertsone channel (only)for controlispossibleusingthePulseConvertcommandeach command sent. In this way, channel (withtheSTART pinlow).Inthisoperation,thedataconversionscan be stepped withoutthe need to from one channel is convertedwith each PulsetoggletheSTART pin. Convert command. The Pulse convert command takeseffectwhen the command byte iscompletelySTART Pin shiftedin (eighthfallingedge of SCLK). AfterAs shown inFigure54,when theSTART pinistaken conversion,ifmore than one channel is enabledhigh,conversionsstartbeginningwith the current (Auto-Scanmode), theconverterindexestothenextchannel.The devicecontinuesto convertallof the selectedchannelaftercompletingtheconversion.programmed channels,ina continuousloop,untilthe START pin is taken low. When thisoccurs,the conversionin process completes,and the device entersthe standbyor sleepmode waitingfora new start condition.When DRDY asserts low, the conversiondata is ready. Figure 56 shows the START pin to DRDY timing.The order in which channeldata isconvertedisdescribedinTable 10. When the lastselectedchannelin the program list has been converted, the device continues conversionsstartingwiththehighestprioritychannel. Ifthereisonlyone channelselectedintheAuto-Scan mode, theconverterremainsfixedon one channel.A Figure55. Pulse Conversion,Auto-Scan Modewriteoperationto any of the multiplexerchannel selectregisterssets the channel pointerto the highest prioritychannel (see Table 11). In Fixed-Channelmode, the channel pointerremains fixed. Figure56. START Pin and DRDY Timing Figure54. Conversion Control,Auto-Scan Mode

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Fully−Settled Data DRDY Start Condition ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 GPIO Linked START Pin Control OPERATING MODES The START pincan be contolleddirectlyby software The operatingmodes oftheADS1258 are definedin by connectingexternallya GPIO port pin to the threebasicstates:ConvertingMode, IdleMode, and START pin.(Notethatan externalpull-downresistor Power-Down mode. In Convertingmode, the device isrecommended tokeep theGPIO fromfloatinguntil isactivelyconvertingchanneldata.The devicepower theGPIO isconfiguredas an output).For thismode dissipationisthehighestinthismode. Thismode is ofcontrol,theSTART piniseffectivelycontrolledby divided into two sub-modes: Auto-Scan and writingtotheGPIO Data Register(GPIOD),withthe Fixed-Channel. Converting mode. This mode also has twoInitialDelay sub-modes:Standbyand Sleep. As seen inFigure57,when a startconvertcondition The lastmode isPower-Down mode. Inthismode, alloccurs,thefirstreadingfromADS1258 isdelayedfor functionsof the converterare disabledto reducea number of clockcycles.This delay allowsfully power consumptiontoa minimum.settleddatatooccuratthefirstdataread.Data reads thereafterare availableat the fulldata rate.The CONVERTING MODESnumber of clock cycles delayed before the first readingisvaliddepends on thedataratesetting,and The ADS1258 has two convertingmodes: Auto-Scan whetherexitingtheStandby or Sleep Mode. Table9 and Fixed-Channel.InAuto-Scanmode, thechannels liststhedelayedclockcyclesversusdatarate. to be measured are pre-selectedin the address registersettings.When a convertconditionispresent, theconverterautomaticallymeasures and sequences throughthe channelseitherina continuousloopor pulse-step fashion, depending on the trigger condition. In Fixed-Channelmode, the channel address is selectedin the address registersettingspriorto acquiringchanneldata.When a convertconditionis present,thedeviceconvertsa singlechannel,either continuouslyor inpulse-stepfashion,dependingon the triggercondition.The data ratein thismode is higher than in Auto-Scan Mode since the inputFigure57. StartConditiontoFirstData channelsarenotindexedforeach reading. The selectionof convertingmodes is set with bit MUXMOD ofregisterCONFIG0. Table9. StartConditiontoDRDY Delay,Chop = 0,DLY[2:0]= 000 INITIALDELAY (StandbyMode) INITIALDELAY (SleepMode) (fCLK cycles) (fCLK cycles) DRATE[1:0] Fixed-Channel Auto-Scan Fixed-Channel Auto-Scan 11 802 708 866 772 10 1186 1092 1250 1156 01 2722 2628 2786 2692 00 8866 8772 8930 8836 Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29 ProductFolderLink(s):ADS1258-EP

SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com Auto-Scan Mode registerpriorto convertinga differentchannel.Note that the AINCOM inputand the internalsystemThe ADS1258 provides16 analoginputs,which can registerscannotbe referencedinthismode.be configuredin combinationsof eightdifferential inputsor 16 single-endedinputs,and providesan IdleModesadditionalfiveinternalsystem measurements.Taken together,the device allowsa totalof 29 possible When the START pin is taken low, the device channel combinations.The converterautomatically completestheconversionofthecurrentchanneland scans and measures theselectedchannels,eitherin thenentersone oftheIdlemodes, StandbyorSleep. a continuousloop or pulse-stepfashion,under the In the Standby mode, the internalbiasingof the controloftheSTART pinorStartcommand software. converterisreduced.Thisstateprovidesthe fastest The channels are selectedfor measurement in wake-up responsewhen re-enteringtherun state.In registers MUXDIF, MUXSG0, MUXSG1, and Sleepmode, theinternalbiasingisreducedfurtherto SYSRED. When any of these registersare written, providelowerpower consumptionthan the Standby the internalchannel pointeris set to the channel mode. This mode has a slowerwake-up response addresswiththehighestpriority(seeTable11). when re-enteringtheConvertingmode (seeTable9). Selectionofthesemodes issetunderbitIDLMOD ofDRDY assertslow when the channeldata isready; registerCONFIG1.see Figure55 and Figure54. At the same time,the converterindexestothenextselectedchanneland,if POWER-DOWN MODEthe START pin is high, startsa new channel conversion.Otherwise,ifpulseconverting,thedevice In power-down mode, both the analog and digital enterstheIdlemode. circuitryarecompletelydisabled. For example,ifchannels3,4,7,and 8 are selected SERIAL INTERFACEformeasurement in the list,the ADS1258 converts the channels in that order, skipping all other The ADS1258 is operated via an SPI-compatiblechannels.Afterchannel 8 is converted,the device serialinterfaceby writingdata to the configurationstartsover,beginningat the top of the channellist, registers,using commands to controlthe converterchannel3. and finallyreading back the channel data. The interfaceconsistsof foursignals:CS, SCLK, DIN,The followingguidelinescan be used when selecting and DOUT.inputchannelsforAuto-Scanmeasurement: 1. For differentialmeasurements, adjacent input Chip Select(CS)pins(AIN0/AIN1,AIN2/AIN3,AIN4/AIN5,etc.)are pre-set as differentialpairs. Even number CS isan inputthatisused to selectthe devicefor channelsfrom each pairrepresentthe positive serialcommunication.CS isactivelow.When CS is inputtotheADC and odd number channelswithin high,readorwritecommands inprogressareaborted a pairrepresentthenegativeinput(forexample, and the serialinterfaceisreset.Additionally,DOUT AIN0/AIN1:AIN0 isthepositivechannel,AIN1 is tri-statesand inputson DIN are ignored.DRDY thenegativechannel.) indicateswhen dataisready,independentofCS. 3. Combinationsof differential,single-endedinputs, SerialClock (SCLK) Operation and internalsystem registerscan be used in a The serialclock(SCLK) isan inputwhich isused toscan. clock data into (DIN) and out of (DOUT) the ADS1258. This inputis a Schmitt-triggerinputthatFixed-ChannelMode has a highdegree of noiseimmunity.However, itis In thismode, any of the 16 analog inputchannels recommended tokeep SCLK as cleanas possibleto (AIN0–AIN15) can be selectedforthe positiveADC preventglitchesfrom inadvertentlyshiftingthe data. inputand any analoginputchannelscan be selected Data isshiftedintoDIN on the risingedge of SCLK for the negative ADC input. New channel and dataisshiftedoutofDOUT on thefallingedge of configurationsmust be selectedby the MUXSCH SCLK. IfSCLK isheldinactivefor4096 or 256 fCLK cycles(SPIRST bitof registerCONFIG0), read or

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1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 NOTES: (1)□Optional□for□Auto-Scan□mode,□disabled□for□Fixed-Channel□mode.□See□T able□13,□Status□Byte. (2)□After□the□channel□data□read□operation, must□be□toggled□or□an□SPI□timeout□must□occur□before□sending□commands. (3)□No□SCLK□activity. CS (3) DRDY CS SCLK DOUT DIN (hold□inactive) Status□Byte (1) Data□Byte□1□(MSB) Data□Byte□3□(MSB) (2) ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 writeoperationsin progresswillterminateand the may be read at any timewithoutconcernto DRDY. SPI interfaceresets.This timeoutfeaturecan be The NEW bitof the STATUS byteindicatesthatthe used to recoverlostcommunicationwhen a serial dataregisterhas been refreshedwithnew converter interfacetransmissionisinterruptedor inadvertently datasincethelastreadoperation.The dataisshifted glitched. outMSB firstaftertheSTATUS byte. Itshouldbe noted thaton system power-up,iftheData Input(DIN)and Data Output (DOUT) ADS1258 interfacesignalsare floatingor undefined,Operation the interfacecouldwake inan unknown state.This The datainputpin(DIN)isused toinputdatatothe conditionis remedied by resettingthe interfacein ADS1258. The data outputpin (DOUT) is used to threeways: togglethe RESET pin low then high; outputdatafromtheADS1258. Data on DIN isshifted togglethe CS pin high then low; or hold SCLK intothe converteron the risingedge of SCLK while inactivefor218 + 4096 fCLK cycles. data isshiftedout on DOUT on the fallingedge of SCLK. DOUT istri-statedwhen CS ishighto allow Channel Data Read Direct multipledevicestosharetheline. Channel datacan be accessedfromtheADS1258 in two ways: Directdataread or dataread withregisterSPI Bus Sharing format.With Directread,the DIN inputpin is held The ADS1258 can be connectedtoa sharedSPI bus. inactive(highorlow)foratleastthefirstthreeSCLK DOUT tri-stateswhen CS isdeselected(high).When transitions.When thefirstthreebitsare 000 or 111, theADS1258 isconnectedtoa sharedbus,datacan the devicedetectsa directdata read and channel be read onlyby the Channel Data Read command data is output.Afterthe device defectsthisread format. format,commands are ignoreduntileitherCS is toggled,an SPI timeoutoccursorthedeviceisreset. COMMUNICATION PROTOCOL The Channel Data Read command does not have thisrequirement.CommunicatingtotheADS1258 involvesshiftingdata intothedevice(viatheDIN pin)orshiftingdataoutof Concurrentwith the firstSCLK transition,channel the device(viathe DOUT pin)under controlof the dataisoutputon theDOUT outputpin.A totalof24 SCLK input. or 32 SCLK transitionscomplete the data read operation.The number of shiftsdepend on whether Reading DATA the status byte is enabled. The data must be Figure58. Channel Data Read Direct(No Command) Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31 ProductFolderLink(s):ADS1258-EP

DIN Command Byte 1 Don't Care Don't Care (1) DOUT (1) After the prescribed number of registers are read, then one or more additional commands can be issued in succession. (2) Four bytes for channel data register read. See Table 13, Status Byte. One or more bytes for register data read, depending on MUL bit. NOTE: Don't Care Data (2) Data(2) 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com COMMAND DESCRIPTION SCLK fallingedge (command byte completed),the when DRDY isnot used and the data ispolledtoChannel Data Read Command detectfortheoccurrenceofnew dataor when CS is tiedlow toavoidthenecessityforan SPI timeoutthatTo read channeldata inthismode (registerformat), otherwiseoccurs when readingdata directly.Thisthefirstthreebitsofthecommand bytetobe shifted optionavoids conflictswith DRDY, as shown inintothe deviceare 001. The MUL bitmust be set Figure59.because thiscommand isa multiplebyteread.The remainingbitsaredon’tcarebutstillmust be clocked to the device.Duringthistime,ignoreany data that appear on DOUT untilthecommand completes.This data should be ignored.Beginningwiththe eighth Figure59. Registerand Channel Data (RegisterFormat)Read

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1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 CS SCLK DIN Command Byte Register Data (1) Register Data(1)(2) (1) One or more bytes depending on MUL bit. (2) After the prescribed number of registers are read, then one or more additional commands can be issued in succession. NOTE: 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 CS SCLK DIN Command 1 Command 2 (1) Command 3 (1) NOTE: (1) One or more commands can be issued in succession. ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 RegisterRead Command Beginning with the eighth SCLK risingedge thebeginningregisteraddressbits.Duringthistime, CONTROL COMMANDSthe invaliddata may appear on DOUT untilthe command iscompleted.Thisdatashouldbe ignored. Pulse Convert CommandBeginning with the eighth fallingedge of SCLK (command bytecompleted),the MSB of the register (See ConversionControlsection) data isoutputon DOUT. The remainingeightSCLK transitionscompletethe read of a singleregister.If Reset Command discarded.Note thatthe SPI interfacemay requireRegisterWriteCommand resetforthiscommand, orany command, tofunction. To writeregisterdata,the firstthree bitsof the To ensure deviceresetunder a possiblelockedSPI command bytetobe shiftedintothedeviceare 011. interfacecondition,do one ofthefollowing:1) toggle These bitsare followedby themultipleregisterread CS highthenlow and send theresetcommand; or2) bit(MUL).IfMUL = '1',thenmultipleregisterscan be holdSCLK inactivefor256/fCLK or4096/fCLK and send writtenin sequence beyond the desiredregister.If the reset command. The controlcommands are MUL = '0',onlydatatotheaddressedregistercan be illustratedinFigure61. written.The remainingfourbitsofthecommand word are the beginningregisteraddress bits.Duringthis time,theinvaliddatamay appear on DOUT untilthe command iscompleted.Thisdatashouldbe ignored. Figure60. RegisterWriteOperation Figure61. ControlCommand Operation Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33 ProductFolderLink(s):ADS1258-EP

(register format) ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com CHANNEL DATA The datareadoperationoutputseitherfourbytes(onebyteforstatusand threebytesfordata),orthreebytesfor dataonly.The selectionof4-byteor3-bytedatareadissetby thebitSTAT inregisterCONFIG0 (seeTable13, StatusByte,foroptions).Inthe4-byteread,thefirstbyteisthestatusbyteand thefollowingthreebytesarethe databytes.The MSB (Data23)ofthedataisshiftedoutfirst. Table10.CHANNEL DATA FORMAT BYTE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

1 STATUS NEW OVF SUPPLY CHID4 CHID3 CHID2 CHID1 CHID0

2 MSB Data23 Data22 Data21 Data20 Data19 Data18 Data17 Data16

3 MSB-1 Data15 Data14 Data13 Data12 Data11 Data10 Data9 Data8

4 LSB Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data0

BIT STATUS.7, NEW The NEW bitissetwhen the resultsof a Channel Data Read Command returnsnew channeldata.The bit remainssetindefinitelyuntilthechanneldataisread.When thechanneldataisreadagainbeforetheconverter updateswithnew data,thepreviousdataisoutputand theNEW bitiscleared.Ifthechanneldataisnotread beforethe nextconversionupdate,the data from the previousconversionislost.As shown inFigure62, the NEW bitemulatesthe operationof the DRDY outputpin.To emulatethe functionof the DRDY outputpinin software,theuserreadsdataata ratefasterthantheconverter'sdatarate.The userthenpollstheNEW bitto detectfornew channeldata. 0 = Channeldatahas notbeen updatedsincethelastreadoperation. 1 = Channeldatahas been updatedsincethelastreadoperation. Figure62. NEW BitOperation BIT STATUS.6 OVF When thisbitisset,thisindicatesthedifferentialvoltageappliedtotheADC inputshave exceeded therangeof theconverter|VIN|> 1.06 VREF .Duringover-range,theoutputcode oftheconverterclipstoeitherpositiveFS (VIN ≥ 1.06 × VREF ) or negativeFS (VIN ≤ –1.06 × VREF ).Thisbit,withtheMSB ofthedata,can be used to detectpositiveornegativeover-rangeconditions.Note thatbecause ofaveragingincorporatedwithinthedigital filter,theabsence ofthisbitdoes notassurethatthemodulatoroftheADC has notsaturateddue topossible transientinputoverloadconditions. BIT STATUS.5 SUPPLY Thisbitindicatesthattheanalogpower-supplyvoltage(AVDD – AVSS) isbelow a presetlimit.The SUPPLY bit issetwhen thevaluefallsbelow 4.3V (typically)and isresetwhen thevaluerises50mV higher(typically)than thelowertrippoint.The outputdataoftheADC may notbe validunderlowpower-supplyconditions. BITS CHID[4:0]CHANNEL ID BITS The Channel ID bitsindicatethemeasurement channeloftheacquireddata.Note thatforFixed-Channelmode, theChannel ID bitsareundefined.See Table11 forthechannelID,themeasurement priority,and thechannel descriptionforAuto-ScanMode.

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www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 BITS DATA[23:0] OF DATA BYTES The ADC outputdataare24 bitswide (DATA[23:0]).DATA23 isthemost significantbit(MSB) and DATA0 isthe leastsignificantbit(LSB).The dataiscoded inbinarytwoscomplement format. Table11.Channel ID and Measurement Order (Auto-ScanMode) BITS CHID[4:0] PRIORITY CHANNEL DESCRIPTION 00h 1 (Highest) DIFF0 (AIN0–AIN1) Differential0 01h 2 DIFF1 (AIN2–AIN3) Differential1 02h 3 DIFF2 (AIN4–AIN5) Differential2 03h 4 DIFF3 (AIN6–AIN7) Differential3 04h 5 DIFF4 (AIN8– AIN9) Differential4 05h 6 DIFF5 (AIN10–AIN11) Differential5 06h 7 DIFF6 (AIN12–AIN13) Differential6 07h 8 DIFF7 (AIN14–AIN15) Differential7 08h 9 AIN0 Single-Ended0 09h 10 AIN1 Single-Ended1 0Ah 11 AIN2 Single-Ended2 0Bh 12 AIN3 Single-Ended3 0Ch 13 AIN4 Single-Ended4 0Dh 14 AIN5 Single-Ended5 0Eh 15 AIN6 Single-Ended6 0Fh 16 AIN7 Single-Ended7 10h 17 AIN8 Single-Ended8 11h 18 AIN9 Single-Ended9 12h 19 AIN10 Single-Ended10 13h 20 AIN11 Single-Ended11 14h 21 AIN12 Single-Ended12 15h 22 AIN13 Single-Ended13 16h 23 AIN14 Single-Ended14 17h 24 AIN15 Single-Ended15 18h 25 OFFSET OFFSET 1Ah 26 VCC AVDD – AVSS Supplies 1Bh 27 TEMP Temperature 1Ch 28 GAIN Gain 1Dh 29 (Lowest) REF ExternalReference Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35 ProductFolderLink(s):ADS1258-EP

SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com COMMAND AND REGISTER DEFINITIONS Commands are used to read channel data,access the configurationregisters,and controlthe conversion process.Ifthecommand isa registerreadorwriteoperation,one ormore databytesfollowthecommand byte. IfbitMUL = 1 inthecommand byte,thenmultipleregisterscan be read or writteninone command operation (see the MUL bit).Commands can be sentback-to-backwithouttogglingCS; however,aftera channelData Read Directoperation,CS must be toggledoran SPI timeoutmust occurbeforesendinga command. The data readby command does notrequireCS tobe toggled. The command byteconsistsofthreefields:theCommand Bits(C[2:0]),multipleregisteraccess bit(MUL),and theRegisterAddressBits(A[3:0]);see theCommand Byteregister. Command Byte 7 6 5 4 3 2 1 0 C2 C1 C0 MUL A3 A2 A1 A0 BitsC[2:0]— Command Bits These bitscode thecommand withinthecommand byte. C[2:0] DESCRIPTION COMMENTS

000 ChannelData Read Direct(nocommand) ToggleCS orallowSPI timeoutbeforesendingcommand

001 ChannelData Read Command (registerformat) SetMUL = 1;statusbytealwaysincludedindata

010 RegisterRead Command

011 RegisterWriteCommand

100 PulseConvertCommand MUL, A[3:0]aredon'tcare

101 Reserved

110 ResetCommand MUL, A[3:0]don'tcare

111 ChannelData Read Direct(nocommand) ToggleCS orallowSPI timeoutbeforesendingcommand

Bit4 MUL: MultipleRegisterAccess 0 = DisableMultipleRegisterAccess 1 = EnableMultipleRegisterAccess Thisbitenablesthemultipleregisteraccess.Thisoptionallowswritingor readingmore thanone registerina singlecommand operation.Ifonlyone registeristo be read or written,set MUL = '0'.For multipleregister access,setMUL = '1'.The readorwriteoperationbeginsattheaddressedregister.The ADS1258 automatically incrementstheregisteraddressforeach registerdatabytesubsequentlyread or written.The multipleregister readorwriteoperationscompleteafterregisteraddress= 09h (deviceID register)has been accessed. The multipleregisteraccessisterminatedinone ofthreeways: 1. The usertakesCS high.ThisactionresetstheSPI interface. 2. The userholdsSCLK inactivefor4096 fCLK cycles.ThisactionresetstheSPI interface. 3. Registeraddress= 09h has been accessed.Thiscompletesthecommand and theADS1258 isthenready fora new command. Note fortheChannel Data Read command, thisbitmust be settoread thefourdata bytes(onestatusbyteand threedatabytes). A[3:0]RegisterAddress Bits These bitsaretheregisteraddressesfora registerreadorwriteoperation;see Table12.

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www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 REGISTERS Table12.RegisterMap ADDRESS REGISTER DEFAULT BitsA[3:0] NAME VALUE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00h CONFIG0 0Ah 0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0 01h CONFIG1 83h IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0 02h MUXSCH 00h AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0 03h MUXDIF 00h DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0 04h MUXSG0 FFh AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 05h MUXSG1 FFh AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8 06h SYSRED 00h 0 0 REF GAIN TEMP VCC 0 OFFSET 07h GPIOC FFh CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0 08h GPIOD 00h DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 09h ID 8Bh ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 CONFIG0: CONFIGURATION REGISTER 0 (Address = 00h) 7 6 5 4 3 2 1 0

0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0

Default= 0Ah. Bit7 Must be 0 (default) Bit6 SPIRST SPI InterfaceReset Timer Thisbitsetsthenumber offCLK cyclesinwhichSCLK isinactivetheSPI interfacewillreset.This placesa lowerlimiton thefrequencyofSCLK inwhichtoreadorwritedatatothedevice.The SPI interfaceonlyisresetand notthedeviceitself.When theSPI interfaceisreset,itisreadyfora new command. 0 = Resetwhen SCLK inactivefor4096fCLK cycles(256µs,fCLK = 16MHz) (default). 1 = Resetwhen SCLK inactivefor256fCLK cycles(16µs,fCLK = 16MHz). Bit5 MUXMOD ThisbitsetseithertheAuto-ScanorFixed-Channelmode ofoperation. 0 = Auto-ScanMode (default) InAuto-Scanmode, theinputchannelselectionsareeightdifferentialchannels(DIFF0–DIFF7)and 16 single-endedchannels(AIN0–AIN15).Additionally,fiveinternalmonitorreadingscan be selected. These selectionsaremade inregistersMUXDIF, MUXSG0, MUXSG1, and SYSRED. Inthismode, settingsinregisterMUXSCH have no effect.See theAuto-ScanMode sectionformore details. 1 = Fixed-ChannelMode InFixed-Channelmode, any oftheanaloginputchannelsmay be selectedforthepositive measurement and thenegativemeasurement channels.The inputsareselectedinregisterMUXSCH. Inthismode, registersMUXDIF, MUXSG0, MUXSG1, and SYSRED have no effect.Note thatitisnot possibletoselecttheinternalmonitorreadingsinthismode. Bit4 BYPAS ThisbitselectseithertheinternalorexternalconnectionfromthemultiplexeroutputtotheADC input. 0 = ADC inputsuse internalmultiplexerconnection(default). 1 = ADC inputsuse externalADC inputs(ADCINP and ADCINN). Note thattheTemperature,VCC ,Gain,and Referenceinternalmonitorreadingsautomaticallyuse the internalconnection,regardlessoftheBYPAS setting.The Offsetreadinguses thesettingofBYPAS. Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37 ProductFolderLink(s):ADS1258-EP

SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com Bit3 CLKENB Thisbitenablestheclockoutputon pinCLKIO. The clockoutputoriginatesfromthedevicecrystal oscillatorand PLL circuit. 0 = Clockoutputon CLKIO disabled. 1 = Clockoutputon CLKIO enabled(default). Note:IftheCLKSEL pinissetto'1',theCLKIO pinisa clockinputonly.Inthiscase,settingthisbit has no effect. Bit2 CHOP Thisbitenablesthechoppingfeatureon theexternalmultiplexerloop. 0 = ChoppingDisabled(default) 1 = ChoppingEnabled The choppingfeaturecorrectsforoffsetoriginatingfromcomponents used intheexternalmultiplexer loop;see theExternalChoppingsection. Note thatforInternalSystem readings(Temperature,VCC, Gain,and Reference),theCHOP bitmust be 0. Bit1 STAT StatusByteEnable When readingchanneldatafromtheADS1258, a statusbyteisnormallyincludedwiththeconversion data.However,insome ADS1258 operatingmodes, thestatusbytecan be disabled.Table13,Status Byte,shows themodes ofoperationand thedatareadformatsinwhichthestatusbytecan be disabled. 0 = StatusByteDisabled 1 = StatusByteEnabled(default) Table13.StatusByte CHANNEL DATA CHANNEL DATA MODE READ COMMAND READ DIRECT Auto-Scan AlwaysEnabled Enabled/Disabledby STAT Bit Fixed-Channel AlwaysEnabled(ByteisUndefined) AlwaysDisabled Bit0 Must be 0

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www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 CONFIG1: CONFIGURATION REGISTER 1 (Address = 01h) 7 6 5 4 3 2 1 0 IDLMOD DLY2 DLY1 DLY0 SBCS1 SBCS0 DRATE1 DRATE0 Default= 83h. Bit7 IDLMOD ThisbitselectstheIdlemode when thedeviceisnotconverting,StandbyorSleep.The Sleepmode offerslowerpower consumptionbuthas a longerwake-up timetore-entertherunmode; see theIdle Modes section. 0 = SelectStandbyMode 1 = SelectSleepMode (default) Bits DLY[2:0] 6–4 These bitssettheamount oftimetheconverterwilldelayafterindexingtoa new channelbutbefore startinga new conversion.Thisvalueshouldbe setlargeenough toallowforthefullsettlingof externalfilteringorbufferingcircuitsused between theMUXOUTP, MUXOUTN, and ADCINP, ADCINN pins;see theSwitchTime Delaysection.(default= 000) Bits SBCS[1:0] 3–2 These bitssetthesensorbiascurrentsource. 0 = SensorBiasCurrentSourceOff(default) 1 = 1.5µA Source 3 = 24µA Source Bits DRATE[1:0] 1–0 These bitssetthedatarateoftheconverter.Slowerreadingratesyieldincreasedresolution;see Table4.The actualdataratesshown inthetablecan be slower,dependingon theuse ofSwitchTime DelayortheChop feature.See theSwitchTime Delaysection.The readingratescaleswiththe masterclockfrequency. DATA RATE DATA RATE AUTO-SCAN MODE FIXED-CHANNEL MODE DRATE[1:0] (SPS) (SPS) 11 23739 125000 10 15123 31250 01 6168 7813 00 1831 1953 fCLK = 16MHz, Chop = 0,Delay= 0. Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39 ProductFolderLink(s):ADS1258-EP

SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com MUXSCH: MULTIPLEXER FIXED-CHANNEL REGISTER (Address = 02h) 7 6 5 4 3 2 1 0 AINP3 AINP2 AINP1 AINP0 AINN3 AINN2 AINN1 AINN0 Default= 00h. Thisregisterselectstheinputchannelsofthemultiplexertobe used fortheFixed-Channelmode. The MUXMOD bitinregisterCONFIG0 must be setto'1'.Inthismode, bitsAINN[3:0]selecttheanaloginputchannelforthe negativeADC input,and bitsAINP[3:0]selectthe analog inputchannelforthe positiveADC input.See the Fixed-ChannelMode section. MUXDIF: MULTIPLEXER DIFFERENTIAL INPUT SELECT REGISTER (Address = 03h) 7 6 5 4 3 2 1 0 DIFF7 DIFF6 DIFF5 DIFF4 DIFF3 DIFF2 DIFF1 DIFF0 Default= 00h. MUXSG0: MULTIPLEXER SINGLE-ENDED INPUT SELECT REGISTER 0 (Address = 04h) 7 6 5 4 3 2 1 0 AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 AIN1 AIN0 Default= FFh. MUXSG1: MULTIPLEXER SINGLE-ENDED INPUT SELECT REGISTER 1 (Address = 05h) 7 6 5 4 3 2 1 0 AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 AIN9 AIN8 Default= FFh. SYSRED: SYSTEM READING SELECT REGISTER (Address = 06h) 7 6 5 4 3 2 1 0 0 0 REF GAIN TEMP VCC 0 OFFSET Default= 00h. These fourregistersselecttheinputchannelsand theinternalreadingsformeasurement inAuto-Scanmode. For differentialchannelselections(DIFF0…DIFF7),adjacentinputpins(AIN0/AIN1,AIN2/AIN3,etc.)arepre-set as differentialinputs.Allsingle-endedinputsaremeasured withrespecttotheAINCOM input.AINCOM may be set to any levelwithin±100 mV of the analog supply range.Channels not selectedare skipped in the measurement sequence.Writingtoany ofthesefourregistersresetstheinternalchannelpointertothechannel withthehighestpriority(seeTable11).Note thatthebitsindicatedas '0'must be setto0. 0 = Channelnotselectedwithina readingsequence. 1 = Channelselectedwithina readingsequence.

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www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 GPIOC: GPIO CONFIGURATION REGISTER (Address = 07h) 7 6 5 4 3 2 1 0 CIO7 CIO6 CIO5 CIO4 CIO3 CIO2 CIO1 CIO0 Default= FFh. ThisregisterconfigurestheGPIO pinsas inputsoras outputs.Note thatthedefaultconfigurationsoftheport pinsareinputsand as such theyshouldnotbe leftfloating.See theGPIO DigitalPortsection. 0 = GPIO isan output;1 = GPIO isan input(default). CIO[7:0]GPIO Configuration bit7 CIO7,DigitalI/OConfigurationBitforPinGPIO7 bit6 CIO6,DigitalI/OConfigurationBitforPinGPIO6 bit5 CIO5,DigitalI/OConfigurationBitforPinGPIO5 bit4 CIO4,DigitalI/OConfigurationBitforPinGPIO4 bit3 CIO3,DigitalI/OConfigurationBitforPinGPIO3 bit2 CIO2,DigitalI/OConfigurationBitforPinGPIO2 bit1 CIO1,DigitalI/OConfigurationBitforPinGPIO1 bit0 CIO0,DigitalI/OConfigurationBitforPinGPIO0 GPIOD: GPIO DATA REGISTER (Address = 08h) 7 6 5 4 3 2 1 0 DIO7 DIO6 DIO5 DIO4 DIO3 DIO2 DIO1 DIO0 Default= 00h. Thisregisterisused toreadand writedatatotheGPIO portpins.When readingthisregister,thedatareturned correspondstothestateoftheGPIO externalpins,whethertheyareprogrammed as inputsoras outputs.As outputs,a writetotheGPIOD setstheoutputvalue.As inputs,a writetotheGPIOD has no effect.See the GPIO DigitalPortsection. 0 = GPIO islogiclow(default);1 = GPIO islogichigh. DIO[7:0]GPIO Data bit7 DIO7,DigitalI/OData bitforPinGPIO7 bit6 DIO6,DigitalI/OData bitforPinGPIO6 bit5 DIO5,DigitalI/OData bitforPinGPIO5 bit4 DIO4,DigitalI/OData bitforPinGPIO4 bit3 DIO3,DigitalI/OData bitforPinGPIO3 bit2 DIO2,DigitalI/OData bitforPinGPIO2 bit1 DIO1,DigitalI/OData bitforPinGPIO1 bit0 DIO0,DigitalI/OData bitforPinGPIO0 ID:DEVICE ID REGISTER (Address = 09h) 7 6 5 4 3 2 1 0 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 Default= 8Bh. ID[7:0]ID Bits Factory-programmedID bits.Read-only. ExceptfortheID4 bit,theID bytecan change atany timewithoutnotice. ID4:0= ADS1258, ADS1258-EP (24-BitADCs) ID4:1= ADS1158 (16-BitADC) Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 41 ProductFolderLink(s):ADS1258-EP

10kΩ typ. ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com

APPLICATIONS

The followingsummarizes the design and layout considerationswhen usingtheADS1258: a. Power Supplies:The converteracceptsa single +5V supply(AVDD = 5 V and AVSS = AGND) or dual,bipolarsupplies(typicallyAVDD = 2.5 V, AVSS = –2.5 V). Dual supply operation accommodates truebipolarinputsignals,withina ±2.5-Vrange.Note thatthe maximum negative inputvoltageto the multiplexeris limitedto Figure63. InputOverload ProtectionAVSS – 100 mV, and themaximum positiveinput voltageislimitedtoAVDD + 100 mV. The range d. ADC Inputs:The externalmultiplexerloopoftheforthe digitalpower supply(DVDD) is2.7 V to ADS1258 allows for the inclusionof signal5.25 V. For allsupplies,use a 10-μF tantalum conditioningbetween theoutputofthemultiplexercapacitor,bypassed with a 0.1-μF ceramic and theinputoftheADC. Typically,an amplifiercapacitor,placed close to the device pins. isused toprovidegain,buffering,and/orfilteringAlternatively,a single10-μF ceramic capacitor to the inputsignal.For best performance,thecan be used. The suppliesshouldbe relatively ADC inputsshould be drivendifferentially.Afreefrom noiseand shouldnot be shared with differential in/differentialout or adevices thatproduce voltagespikes (such as single-ended-to-differentialdriver is recom-relays,LED displaydrivers,etc.).Ifa switching mended. Ifthedriveruses highersupplyvoltagespower supplyisused, the voltagerippleshould than the device itself(for example, ±15V),be low (< 2 mV). The analogand digitalpower attentionshould be paid to power-supplysuppliesmay be sequenced inany order. e. Reference Inputs: Itisrecommended to use achannelsdo not have to be used consecutively. 10-μF tantalumwitha 0.1-μF ceramiccapacitorUnassignedchannelsare skippedby thedevice. directlyacross the referencepins,VREFP andIn the Fixed-Channelmode, any of the analog VREFN. The referenceinputsshouldbe driveninputs(AIN0 toAIN15) can be addressedforthe by a low-impedance source. For ratedpositiveinputand forthe negativeinput.The performance,thereferenceshouldhave lessthanfull-scalerangeofthedeviceis2.13 VREF ,butthe 3μVRMS broadband noise.For referenceswithabsoluteanaloginputvoltageislimitedto100 mV highernoise,externalfilteringmay be necessary.beyond the analog supply rails.Inputsignals Note that when exitingthe sleep mode, theexceedingthe analog supplyrails(forexample, devicebeginstodraw a smallcurrentthroughthe±10 V) must be dividedpriorto the multiplexer referencepins.Under thiscondition,thetransientinputs. response of the referencedrivershouldbe fastc. Input Overload Protection: Overdrivingthe enough to settlecompletelybefore the firstmultiplexerinputsmay affectthe conversionsof reading is taken, or simply discardthe firstotherchannels.In the case of inputoverload, severalreadings.externalSchottky diode clamps and series resistorare recommended, as shown in Figure 61.

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www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 f. Clock Source: The ADS1258 requiresa clock interfacecan be operated in a minimum signalforoperation.The clockcan originatefrom configurationwithoutthe use of CS (tieCS low; eitherthe crystaloscillatoror from an external see the SerialInterfaceand Communication clocksource.The internaloscillatoruses a PLL Protocolsections). must be limitedto1,1/2,1/4,1/8,etc. CONFIGURATION GUIDEg. DigitalInputs: It is recommended to source Configurationof the ADS1258 involvessettingtheterminatethe digitalinputsand outputsof the configurationregistersviatheSPI interface.Afterthedevicewitha 50-Ω (typical)seriesresistor.The deviceis configuredforoperation,channel data isresistorsshould be placed closeto the driving readfromthedevicethroughthesame SPI interface.end of the source (outputpins,oscillator,logic The followingis a suggested procedure forgates,DSP, etc).Thisplacementhelpstoreduce configuringthedevice:theringingand overshooton thedigitallines. 1. Reset the SPI Interface: Beforeusingthe SPIh. Hardware Pins: START, DRDY, RESET, and interface,itmay be necessarytorecovertheSPIPWDN. These pinsallowdirectpincontrolofthe interface.To resetthe interface,setCS highorADS1258. The equivalentof the START and disableSCLK for4096 (256)fCLK cycles.DRDY pins is providedvia commands through theSPI interface;thesepinsmay be leftunused. 2. Stop the Converter: Set the START pinlow to The devicealso has a RESET command. The stop the converter.Althoughnot necessaryfor PWDN pin placesthe ADC intovery low-power configuration,thiscommand stops the channel state where the device is inactive. scanningsequence which thenpointstothefirst channelafterconfiguration.i. SPI Interface: The ADS1258 has an SPI-compatibleinterface.This interfaceconsists 3. Reset the Converter: The reset pin can be of foursignallines:SCLK, DIN, DOUT, and CS. pulsed low or a Reset command can be sent. When CS ishigh,the DIN inputisignoredand Althoughnot necessaryforconfiguration,reset the DOUT output tri-states.See Chip Select re-initializesthedeviceintoa known state. (CS )formore details.The SPI Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 43 ProductFolderLink(s):ADS1258-EP

SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com 4. Configure the Registers: The registersare Convertcommand sentthroughtheinterface. 5. VerifyRegisterData: The registerdata may be alsoindicatesthe originof the channeldata.If read back for verificationof device the data fora givenchannelisnot read before communications. DRDY asserts low again, the data for that channel is lostand replacedwithnew channel6. Start the Converter: The convertercan be data.startedwith the START pin or with a Pulse

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CS (1) ADS1258 SPISIMO SPISOMI XINT1 SPICLK SPISTA TMS320R2811 (1) CS may be tied low. DIN DOUT DRDY SCLK CS (1) ADS1258 (1) CS may be tied low. P1.3 P1.2 P1.0 P1.6 P1.4 MSP430 GPIOx (Input) GPIOx (Output) ADS1258 4.7kΩ 10kΩ Key Pad 3.3V 3.3V 470 LED Indicator DIN DOUT DRDY SCLK CS (1) ADS1258 (1) CS may be tied low. MOSI MISO INT SCK IO MSC12xx or 68HC11 ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 DIGITAL INTERFACE CONNECTIONS The ADS1258 SPI-compatible interfaceeasily connectsto a wide varietyof microcontrollersand DSPs. Figure64 shows the basicconnectionto TI's MSP430 family of low-power microcontrollers. Figure65 shows the connectionto microcontrollers withan SPI interfacesuch as the68HC11 family,or TI's MSC12xx family. Note that the MSC12xx includesa high-resolutionADC; theADS1258 can be used toprovideadditionalchannelsofmeasurement or add higher-speedconnections.Finally,Figure66 shows how to connectthe ADS1258 to a TMS320x DSP. Figure66. Connection toa TMS320R2811 DSP GPIO Connections The ADS1258 has eightgeneralpurposeinput/output (GPIO) pins.Each pincan be configuredas an input or an output.Note thatpins configuredas inputs shouldnot float.The pinscan be used to read key pads,driveLED indicator,etc.,by readingand writing theGPIO dataregister(GPIOD).See Figure67. Figure64. Connection toMSP430 Microcontroller Figure67. GPIO Connections Figure65. Connection toMicrocontrollerswithan SPI Interface Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 45 ProductFolderLink(s):ADS1258-EP

100 W 10k W9.09kW 10k W OPA350 OPA365 O PA365 AD S1258 47W 10kW 2.2nF +2.5V +2.5V MU XOUTN MU XOUTP ADCINP ADCINN - 2.5V +2.5V - 2.5V +2.5V - 2.5V AIN15 AINCOM REFP R EFN AIN0 AVSS AVDD ± 10V 9.09kW ± 10V 50W AINx 20mA Input 1kW 1kW +2.5V - 2.5V 0.1m F 100 m F 0.1m F 0.47m F+ 10 mF REF3125 0.1m F 10m F - 2.5V 0.1m F +10m F NOTE: 0.1 m F capacitors not shown. 47W ADS1258-EP SBAS445D –MARCH 2009–REVISED MARCH 2011 www.ti.com ANALOG INPUT CONNECTIONS When using Auto-Scan mode to sequence through the channels, the switch time delay featureFigure 68 shows the ADS1258 interfacingto (programmableby registers)can be used to providehigh-level±10V inputs,commonly used in industrial additionalsettlingtimeoftheexternalcomponents.environments.Inthiscase,bipolarpower suppliesare used,avoidingtheneed forinputsignallevel-shifting Figure 69 illustratesthe ADS1258 interfacingto otherwiserequiredwhen a singlesupplyisused.The multiplepressuresensors having a resistorbridge inputresistorsserveboth to reduce the levelof the output.Each sensor is excitedby the 5-V single 10V inputsignalto withinthe ADC range and also supplythatalsopowers theADS1258 and likewiseis protecttheinputsfrominadvertentsignalover-voltage used as the ADS1258 referenceinput;the 6% input up to 30V. The externalamplifiersconvert the overrangecapabilityaccommodates inputlevelsator single-endedinputsto a fullydifferentialoutputto above VREF . The ratiometricconnectionprovides drivetheADC inputs.Drivingtheinputsdifferentiallycancellationofexcitationvoltagedriftand noise.For maintainsgood linearityperformance.The 2.2-nF bestperformance,the5-V supplyshouldbe freefrom capacitorattheADC inputsisrequiredtobypass the glitchesortransients.The 5-V supplyinputamplifiers ADC sampling currents.The 2.5-V reference, (two OPA365 s) form a differentialinput/differential REF3125 , is filteredand bufferedto provide a outputbufferwiththegainsetto10.The chop feature low-noisereferenceinputto the ADC. The chop of the ADS1258 isused to reduce offsetand offset featureoftheADC can be used toreduceoffsetand driftto very low levels.The 2.2-nFcapacitorat the offsetdriftoftheamplifiers. ADC inputsisrequiredtobypass theADC sampling currents.The 47-Ω resistorsisolatethe op-ampFor ±1V inputsignals,the inputresistordividercan outputsfromthefiltercapacitor.be removed and replacedwitha seriesprotection resistor.For 20-mA inputsignals,the inputresistor dividerisreplacedby a 50-Ω resistor,connectedfrom each inputtoAINCOM. Figure68. Multichannel,±10V Single-EndedInput,BipolarSupply Operation

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R 10k/c87 ADS1258 2.2nF+5V +5V 47/c87 AIN0 AINCOM MUXOUTNMUXOUTP ADCINPADCINN 2k/c87 AIN1 2k/c87 AIN14 2k/c87 AIN15 REFP REFN AVSS AVDD R 2.2k/c87

10 F/c109

0.1 F/c109

0.1 F□supply□bypass□capacitor□not□shown./c109 /c188/c188 /c188 R 10k/c87 ADS1258-EP www.ti.com SBAS445D –MARCH 2009–REVISED MARCH 2011 Figure69. BridgeInput,Single-SupplyOperation Copyright© 2009–2011,Texas InstrumentsIncorporated SubmitDocumentationFeedback 47 ProductFolderLink(s):ADS1258-EP

www.ti.com 16-Mar-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) ADS1258IPHPREP ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS1258IPHPREPG4 ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS1258MPHPTEP ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS1258MPHPTEPG4 ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR ADS1258MRTCTEP ACTIVE VQFN RTC 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR V62/09626-01XE ACTIVE VQFN RTC 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR V62/09626-01YE ACTIVE HTQFP PHP 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR V62/09626-02XE ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR V62/09626-02YE ACTIVE HTQFP PHP 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

www.ti.com 16-Mar-2011 Addendum-Page 2 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADS1258-EP :

Catalog: ADS1258 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS1258IPHPREP HTQFP PHP 48 1000 367.0 367.0 38.0 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 Pack Materials-Page 2

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Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments: ADS1258MRTCTEP V62/09626-01XE ADS1258IPHPREPG4 V62/09626-01YE V62/09626-02YE ADS1258IPHPREP ADS1258MPHPTEP ADS1258MPHPTEPG4 V62/09626-02XE

Product Information

V6209626-01XE specifications and overview.

Summary

16-CHANNEL, 24-BIT ANALOG-TO-DIGITAL CONVERTER

Description

16-CHANNEL, 24-BIT ANALOG-TO-DIGITAL CONVERTER

Source title V6209626-01XE Datasheet(PDF) - Texas Instruments

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V6209626-01XE

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ADS1258-EP_14 TI1 | Alldatasheet

Document overview

Technical content

DESCRIPTION

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ELECTRICAL CHARACTERISTICS

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1 AIN3 AnalogInput AnalogInput3:Single-EndedChannel3,DifferentialChannel1 (–)

2 AIN2 AnalogInput AnalogInput2:Single-EndedChannel2,DifferentialChannel1 (+)

3 AIN1 AnalogInput AnalogInput1:Single-EndedChannel1,DifferentialChannel0 (–)

4 AIN0 AnalogInput AnalogInput0:Single-EndedChannel0,DifferentialChannel0 (+)

14 GPIO0 DigitalI/O General-PurposeDigitalInput/Output0

15 GPIO1 DigitalI/O General-PurposeDigitalInput/Output1

16 GPIO2 DigitalI/O General-PurposeDigitalInput/Output2

17 GPIO3 DigitalI/O General-PurposeDigitalInput/Output3

18 GPIO4 DigitalI/O General-PurposeDigitalInput/Output4

19 GPIO5 DigitalI/O General-PurposeDigitalInput/Output5

20 GPIO6 DigitalI/O General-PurposeDigitalInput/Output6

21 GPIO7 DigitalI/O General-PurposeDigitalInput/Output7

29 DGND Digital DigitalGround

30 VREFN AnalogInput ReferenceInputNegative

31 VREFP AnalogInput ReferenceInputPositive

33 AIN15 AnalogInput AnalogInput15:Single-EndedChannel15,DifferentialChannel7 (–)

34 AIN14 AnalogInput AnalogInput14:Single-EndedChannel14,DifferentialChannel7 (+)

35 AIN13 AnalogInput AnalogInput13:Single-EndedChannel13,DifferentialChannel6 (–)

36 AIN12 AnalogInput AnalogInput12:Single-EndedChannel12,DifferentialChannel6 (+)

37 AIN11 AnalogInput AnalogInput11:Single-EndedChannel11,DifferentialChannel5 (–)

38 AIN10 AnalogInput AnalogInput10:Single-EndedChannel10,DifferentialChannel5 (+)

39 AIN9 AnalogInput AnalogInput9:Single-EndedChannel9,DifferentialChannel4 (–)

40 AIN8 AnalogInput AnalogInput8:Single-EndedChannel8,DifferentialChannel4 (+)

41 ADCINN AnalogInput ADC DifferentialInput(–)

42 ADCINP AnalogInput ADC DifferentialInput(+)

43 MUXOUTN AnalogOutput MultiplexerDifferentialOutput(–)

44 MUXOUTP AnalogOutput MultiplexerDifferentialOutput(+)

45 AIN7 AnalogInput AnalogInput7:Single-EndedChannel7,DifferentialChannel3 (–)

46 AIN6 AnalogInput AnalogInput6 :Single-EndedChannel6,DifferentialChannel3 (+)

47 AIN5 AnalogInput AnalogInput5:Single-EndedChannel5,DifferentialChannel2 (–)

48 AIN4 AnalogInput AnalogInput4:Single-EndedChannel4,DifferentialChannel2 (+)

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16384 Points

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1 STATUS NEW OVF SUPPLY CHID4 CHID3 CHID2 CHID1 CHID0

2 MSB Data23 Data22 Data21 Data20 Data19 Data18 Data17 Data16

3 MSB-1 Data15 Data14 Data13 Data12 Data11 Data10 Data9 Data8

4 LSB Data7 Data6 Data5 Data4 Data3 Data2 Data1 Data0

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000 ChannelData Read Direct(nocommand) ToggleCS orallowSPI timeoutbeforesendingcommand

001 ChannelData Read Command (registerformat) SetMUL = 1;statusbytealwaysincludedindata

010 RegisterRead Command

011 RegisterWriteCommand

100 PulseConvertCommand MUL, A[3:0]aredon'tcare

101 Reserved

110 ResetCommand MUL, A[3:0]don'tcare

111 ChannelData Read Direct(nocommand) ToggleCS orallowSPI timeoutbeforesendingcommand

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0 SPIRST MUXMOD BYPAS CLKENB CHOP STAT 0

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APPLICATIONS

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10 F/c109

0.1 F/c109

V6209626-01XE specifications and overview.

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