V6205609-01YE

THS3201-EP_14 TI1 | Alldatasheet

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/C0068/C0066/C0086/C0045/C0053/C0068/C0071/C0078/C0045/C0056/C0068/C0071/C0075/C0045/C0056/C0068/C0045/C0056

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APPLICATIONS

www.ti.com SGLS283B APRIL 2005 REVISED JANUARY 2009 1.8-GHz LOW-DISTORTION CURRENT-FEEDBACK AMPLIFIER Unity Gain Bandwidth: 1.8 GHz High Slew Rate: 6700 µ s V/V, The THS3201 is a wide-band, high-speed current-feedback amplifier, designed to operate over R L 100 Ω 5-V Step) a wide supply range of 3.3 V to 7.5 V for today s IMD dBc at MHz: V/V, high-performance applications. R L 100 Ω 2-V PP Envelope) The wide supply range, combined with low distortion Noise Figure: dB V/V, R G Ω and high slew rate, makes the THS3201 ideally R F 255 Ω suited for arbitrary waveform driver applications. The Input Referred Noise MHz) distortion performance also enables driving Voltage Noise: 1.65 nV/ Hz high-resolution and high-sampling rate ADCs. Noninverting Current Noise: 13.4 pA/ Hz High-voltage operation capabilties make the THS3201 especially suitable for many test, Inverting Current Noise: pA/ Hz measurement, and ATE Drive: 100 mA lower-voltage devices do not offer enough voltage Power-Supply Voltage Range: 3.3 V to 7.5 V swing capabilty. Output rise and fall times are nearly independent of step size (to first-order appoximation), making the THS3201 ideal for buffering small to large AND MEDICAL systems. Controlled Baseline One Assembly/Test Site The THS3201 is offered in 8-pin SOIC and 8-pin MSOP with PowerPAD packages. One Fabrication Site Available in Military C/125 RELATED DEVICES AND DESCRIPTIONS Temperature Range (1) THS3202 7.5-V 2-GHz Dual Low-Distortion CFB Amplifier Extended Product Life Cycle THS3001 15-V 420-MHz Low-Distortion CFB Amplifier Extended Product-Change Notification THS3061/2 15-V 300-MHz Low-Distortion CFB Amplifier Product Traceability THS3122 15-V Dual CFB Amplifier With 350-mA Drive THS4271 7.5-V 1.4-GHz Low-Distortion VFB Amplifier High-Resolution, High-Sampling-Rate Analog-to-Digital Converter Drivers High-Resolution, High-Sampling-Rate Digital-to-Analog Converter Output Buffers Test and Measurement ATE (1) Additional temperature ranges are available contact factory Please be aware that an important notice concerning availability, standard warranty, and use in critical sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2005 2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

+7.5 V

49.9 WVI

-7.5 V

50 W Source

Low-Noise, Low-Distortion, Wideband Application Circuit NOTE : Power supply decoupling capacitors not shown 768 W 50 W THS3201 49.9 W 50 W 100 k 1 M 10 M 100 M 1 G 10 G f - Frequency - Hz Noninverting Gain - dB NONINVERTING SMALL SIGNAL FREQUENCY RESPONSE R F = 768 W Gain = 2. R L = 100 W , VO = 0.2 VPP. VS = ±7.5 V ABSOLUTE MAXIMUM RATINGS (1) THS3201-EP SGLS283B APRIL 2005 REVISED JANUARY 2009 www.ti.com over operating free-air temperature range (unless otherwise noted) V S Supply voltage 16.5 V V I Input voltage V S I O Output current 175 mA V ID Differential input voltage V Continuous power dissipation See Dissipation Ratings Table T J Maximum junction temperature (2) 150 C T J Maximum junction temperature, continuous operation, long-term reliability (3) 125 C T stg Storage temperature range C to 150 C Lead temperature 1,6 mm (1/16 in) from case for s 300 C Human body model 3000 V ESD ratings Charged device model 1500 V Machines model 100 V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) The absolute maximum ratings under any condition are limited by the constraints of the silicon process. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (3) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See Figure for additional information on thermal derating. Submit Documentation Feedback Copyright 2005 2009, Texas Instruments Incorporated Product Folder Link(s): THS3201-EP

TJ − Junction Temperature − °C Time-to-Fail − Hrs 80°C, 74M Hrs 100°C, 5.9M Hrs 120°C, 490K Hrs 140°C, 58K Hrs 10K 100K 10M 100M 10080 90 110 120 130 140 150 DISSIPATION RATINGS RECOMMENDED OPERATING CONDITIONS THS3201-EP www.ti.com SGLS283B APRIL 2005 REVISED JANUARY 2009 Figure EME-G600 Estimated Wirebond Life JC JA (1) PACKAGE C/W) C/W) D (8) 38.3 97.5 DGN (8) (2) 4.7 58.4 (1) This data was taken using the JEDEC standard High-K test PCB. (2) The THS3201 may incorporate a thermal pad on the underside of the chip. This acts as a heat sink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature; which could permanently damage the device. See Texas Instruments technical briefs SLMA002 and SLMA004 for more information about utilizing the PowerPAD thermally enhanced package. MIN MAX UNIT Dual supply 3.3 7.5 Supply voltage V Single supply 6.6 T A Operating free air temperature 125 C PACKAGE/ORDERING INFORMATION PART NUMBER PACKAGE TYPE PACKAGE MARKING TRANSPORT MEDIA, QUANTITY THS3201MDEP (1) Rails, SOIC-8 THS3201MDREP (1) Tape and reel, 2500 THS3201MDGNEP (1) Rails, MSOP-8-PP BLM THS3201MDGNREP Tape and reel, 2500 (1) Product Preview Copyright 2005 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): THS3201-EP

VIN − VIN + VS− NC V VOUT− NC D OR DGN P ACKAGE (TOP VIEW) NC − No internal connection THS3201-EP SGLS283B APRIL 2005 REVISED JANUARY 2009 www.ti.com If a PowerPAD package is used, the thermal pad is electrically isolated from the active circuitry. Submit Documentation Feedback Copyright 2005 2009, Texas Instruments Incorporated Product Folder Link(s): THS3201-EP

www.ti.com SGLS283B APRIL 2005 REVISED JANUARY 2009 V S 7.5 R f k Ω R L 100 Ω G (unless otherwise noted) OVER TYP MIN/ TEMPERATURE PARAMETER TEST CONDITIONS UNIT TYP/ C to MAX C C 125 C AC Performance G +1, R F 1.2 k Ω 1.8 GHz G +2, R F 768 Ω 850 Small-signal bandwidth, dB Typ O 200 mV PP G +5, R F 619 Ω 565 MHz G +10, R F 487 Ω 520 Bandwidth for 0.1-dB flatness G +2, V O 200 mV pp R F 768 Ω 380 MHz Typ Large-signal bandwidth G +2, V O V pp R F 715 Ω 880 MHz Typ G +2, V O 5-V step, R F 768 Ω Rise/fall Slew rate (25% to 75% level) µ s Typ G +2, V O 10-V step, R F 768 Ω Rise/fall G +2, V O 4-V step, R F 768 Ω Rise and fall time 0.7/0.9 ns Typ Rise/fall Settling time to 0.1% G V O 2-V step ns Typ Settling time to 0.01% Harmonic distortion Second-order harmonic G +5, f MHz, V O V pp, R L 100 Ω dBc Typ Third-order harmonic Third-order intermodulation G +10, f c MHz, Δ f MHz, dBc Typ distortion (IMD V O(envelope) V pp G +10, f c 100 MHz, R F 255 Ω Noise figure dB Typ R G Input voltage noise f MHz 1.65 nV/ Hz Typ Input current noise (noninverting) 13.4 pA/ Hz Typ f MHz Input current noise (inverting) pA/ Hz Typ NTSC 0.008 G +2, R L 150 Ω Differential gain Typ R F 768 Ω PAL 0.004 NTSC 0.007 G +2, R L 150 Ω Differential phase Typ R F 768 Ω PAL 0.011 DC Performance Open-loop transimpedance gain V O R L k Ω 300 200 100 k Ω Min Input offset voltage V CM R L k Ω 0.7 mV Max Average offset voltage drift V CM R L k Ω µ C Typ Input bias current (inverting) V CM R L k Ω µ A Max Average bias current drift V CM R L k Ω 400 nA/ C Typ Input bias current (noninverting) V CM R L k Ω µ A Max Average bias current drift (+) V CM R L k Ω 400 nA/ C Typ Copyright 2005 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): THS3201-EP

www.ti.com ELECTRICAL CHARACTERISTICS (continued) V S 7.5 R f k Ω R L 100 Ω G (unless otherwise noted) OVER TYP MIN/ TEMPERATURE PARAMETER TEST CONDITIONS UNIT TYP/ C to MAX C C 125 C Input Common-mode input range R L k Ω 5.1 V Min Common-mode rejection ratio V CM 3.75 V dB Min Inverting input impedance, Z in Open loop Ω Typ Noninverting 780 k Ω Input resistance Typ Inverting Ω Input capacitance Noninverting pF Typ Output R L k Ω 5.9 5.7 Voltage output swing V Min R L 100 Ω 5.8 5.7 5.35 Current output, sourcing R L Ω 115 105 100 mA Min Current output, sinking R L Ω 100 mA Min Closed-loop output impedance G +1, f MHz 0.01 Ω Typ Power Supply Minimum operating voltage Absolute minimum 3.3 3.3 V Min Maximum operating voltage Absolute maximum 7.5 7.5 V Max Maximum quiescent current Output open mA Max Power-supply rejection (+PSRR) V V to R L k Ω dB Min Power-supply rejection PSRR) V S V to R L k Ω dB Min Submit Documentation Feedback Copyright 2005 2009, Texas Instruments Incorporated Product Folder Link(s): THS3201-EP

www.ti.com SGLS283B APRIL 2005 REVISED JANUARY 2009 V S R f k Ω R L 100 Ω G (unless otherwise noted) OVER TYP MIN/ TEMPERATURE PARAMETER TEST CONDITIONS UNIT TYP/ C to MAX C C 125 C AC Performance G +1, R F 1.2 k Ω 1.3 GHz G +2, R F 715 Ω 725 Small-signal bandwidth, dB Typ O 200 mV PP G +5, R F 576 Ω 540 MHz G +10, R F 464 Ω 480 Bandwidth for 0.1-dB flatness G +2, V O 200 mV pp, R F 715 Ω 170 MHz Typ Large-signal bandwidth G +2, V O V pp R F 715 Ω 900 MHz Typ G +2, V O 5-V step, R F 715 Ω Slew rate (25% to 75% level) µ s Typ Rise/Fall G +2, V O 4-V step, R F 715 Ω Rise and fall time 0.7/0.9 ns Typ Rise/Fall Settling time to 0.1% G V O 2-V step ns Typ Settling time to 0.01% Harmonic distortion G +5, f MHz, Second-order harmonic R L 100 Ω dBc Typ V O V pp G +5, f MHz, Third-order harmonic R L 100 Ω dBc Typ V O V pp Third-order intermodulation G +10, f c MHz, Δ f MHz, dBc Typ distortion (IMD V O(envelope) V pp G +10, f c 100 MHz, R F 255 Ω Noise figure dB Typ R G Input voltage noise f MHz 1.65 nV/ Hz Typ Input current noise (noninverting) 13.4 pA/ Hz Typ f MHz Input current noise (inverting) pA/ Hz Typ NTSC 0.006 G +2, R L 150 Ω Differential gain Typ R F 768 Ω PAL 0.004 NTSC 0.03 G +2, R L 150 Ω Differential phase Typ R F 768 Ω PAL 0.04 DC Performance Open-loop transimpedance gain V O R L k Ω 300 200 100 k Ω Min Input offset voltage V CM R L k Ω 0.7 5.5 mV Max Average offset voltage drift V CM R L k Ω µ C Typ Input bias current (inverting) V CM R L k Ω µ A Max Average bias current drift V CM R L k Ω 400 nA/ C Typ Input bias current (noninverting) V CM R L k Ω µ A Max Average bias current drift (+) V CM R L k Ω 400 nA/ C Typ Copyright 2005 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): THS3201-EP

www.ti.com ELECTRICAL CHARACTERISTICS (continued) V S R f k Ω R L 100 Ω G (unless otherwise noted) OVER TYP MIN/ TEMPERATURE PARAMETER TEST CONDITIONS UNIT TYP/ C to MAX C C 125 C Input Common-mode input range R L k Ω 2.6 2.5 2.5 V Min Common-mode rejection ratio V CM 2.5 V dB Min Inverting input impedance, Z in Open loop, R L k Ω 17.5 Ω Typ Noninverting 780 k Ω Input resistance Typ Inverting Ω Input capacitance Noninverting pF Typ Output R L k Ω 3.65 3.5 3.4 Voltage output swing V Min R L 100 Ω 3.45 3.33 3.2 Current output, sourcing R L Ω 115 105 mA Min Current output, sinking R L Ω 100 mA Min Closed-loop output impedance G +1, f MHz 0.01 Ω Typ Power Supply Minimum operating voltage Absolute minimum 3.3 3.3 V Min Maximum operating voltage Absolute maximum 7.5 7.5 V Max Maximum quiescent current 16.8 20.5 mA Max Power-supply rejection (+PSRR) V 4.5 V to 5.5 R L k Ω dB Min Power-supply rejection PSRR) V S 4.5 V to 5.5 R L k Ω dB Min Submit Documentation Feedback Copyright 2005 2009, Texas Instruments Incorporated Product Folder Link(s): THS3201-EP

S 7.5 THS3201-EP www.ti.com SGLS283B APRIL 2005 REVISED JANUARY 2009 FIGURE NO. Noninverting small-signal frequency response Inverting small-signal frequency response Inverting large-signal frequency response 0.1-dB gain flatness frequency response Capacitive load frequency response Recommended switching resistance vs Capacitive load 2nd harmonic distortion vs Frequency 3rd harmonic distortion vs Frequency 2nd-order harmonic distortion, G vs Output voltage 3rd-order harmonic distortion, G vs Output voltage 2nd-order harmonic distortion, G vs Output voltage 3rd-order harmonic distortion, G vs Output voltage 2nd-order harmonic distortion, G vs Output voltage 3rd-order harmonic distortion, G vs Output voltage 3rd-order intermodulation distortion (IMD vs Frequency S-Parameter vs Frequency 19, Input voltage and current noise vs Frequency Noise figure vs Frequency Transimpedance vs Frequency Input offset voltage vs Case temperature Input bias and offset current vs Case temperature Slew rate vs Output voltage Settling time 27, Quiescent current vs Supply voltage Output voltage vs Load resistance Rejection ratio vs Frequency Noninverting small-signal transient response Inverting large-signal transient response Overdrive recovery time Differential gain vs Number of loads Differential phase vs Number of loads Closed-loop output impedance vs Frequency Copyright 2005 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): THS3201-EP

S THS3201-EP SGLS283B APRIL 2005 REVISED JANUARY 2009 www.ti.com Figure No. Noninverting small-signal frequency response Inverting small-signal frequency response 0.1-dB gain flatness frequency response 2nd-order harmonic distortion vs Frequency 3rd-order harmonic distortion vs Frequency 2nd-order harmonic distortion, G vs Output voltage 3rd-order harmonic distortion, G vs Output voltage 2nd-order harmonic distortion, G vs Output voltage 3rd-order harmonic distortion, G vs Output voltage 2nd-order harmonic distortion, G vs Output voltage 3rd-order harmonic distortion, G vs Output voltage 3rd-order intermodulation distortion (IMD vs Frequency S-Parameter vs Frequency 50, Slew rate vs Output voltage Noninverting small-signal transient response Inverting large-signal transient response Overdrive recovery time Submit Documentation Feedback Copyright 2005 2009, Texas Instruments Incorporated Product Folder Link(s): THS3201-EP

V S 7.5 V Graphs 100 k 1 M 10 M 100 M 1 G 10 G f - Frequency - Hz Noninverting Gain - dB R F = 619 W R F = 768 W R F = 1 kW Gain = 2. R L = 100 W , VO = 0.2 VPP. VS = ±7.5 V 100 k 1 M 10 M 100 M 1 G 10 G f - Frequency - Hz R L = 100 W , VO = 0.2 VPP. VS = ±7.5 V G = 10, RF = 487 W G = 5, RF = 619 W G = 2, RF = 768 W G =1, RF = 1.2 kW Noninverting Gain - dB 100 k 1 M 10 M 100 M 1 G 10 G f - Frequency - Hz R L = 100 W , VO = 0.2 VPP. VS = ±7.5 V G = -10, RF = 499 W G = -5, RF = 549 W G = -2, RF = 576 W G = -1, RF = 619 W Noninverting Gain - dB 5.6 5.7 5.8 5.9 6.1 6.2 6.3 6.4 100 k 10 M 100 M 1 G 10 G f - Frequency - Hz Gain = 2, R F = 768 W , R L = 100 W , VO = 0.2 VPP, VS = ±7.5 V 1 M Noninverting Gain - dB 100 k 1 M 10 M 100 M 1 G f - Frequency - Hz G =-5, RF = 549 W G = -1, RF = 576 W R L = 100 W , VO = 2 VPP. VS = ±7.5 V Inverting Gain - dB 100 k 1 M 10 M 100 M 1 G f - Frequency - Hz Inverting Gain - dB G =-5, RF = 576 W G = 2, RF = 715 W R L = 100 W , VO = 2 VPP. VS = ±7.5 V 0 100 200 300 400 500 f - Frequency - MHz Gain - dB R (ISO) = 30 W , CL = 22 pF R (ISO) = 20 W , C L = 47 pF Gain = 5 R F = 619 W R L = 100 W VS =/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr±7.5 V R (ISO) = 20 W , C L = 50 pF R (ISO) = 15 W , C L = 100 pF 10 100 C L - Capacitive Load - pF Recommended R ISO W Gain = 5, R F = 619 W R L = 100 W , VS = ±7.5 V R ISO C L -100 -90 -80 -70 -60 -50 -40 1 100 f□-□Frequency□-□MHz 2nd□Order□Harmonic□Distortion□-□dBc Vs□= 5V V =□2V R =□100 out PP L /c87 ±7. G□=□10 R =□499 ,□R =□54.9 F G /c87 /c87 G□=□5 R =□619 , R =□154 F G /c87 /c87 G□=□2 R =□768 ,□R =□768 F G /c87 /c87 THS3201-EP www.ti.com SGLS283B APRIL 2005 REVISED JANUARY 2009 NONINVERTING SMALL-SIGNAL NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNAL FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE Figure Figure Figure INVERTING LARGE-SIGNAL INVERTING LARGE-SIGNAL 0.1-dB GAIN FLATNESS FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE Figure Figure Figure RECOMMENDED SWITCHING RESISTANCE 2nd HARMONIC DISTORTION CAPACITIVE LOAD vs vs FREQUENCY RESPONSE CAPACITIVE LOAD FREQUENCY Figure Figure Figure 10. Copyright 2005 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): THS3201-EP

-100 -95 -90 -85 -80 -75 -70 -65 -60 1 10 100 f□-□Frequency□-□MHz 3rd□Order□Harmonic□Distortion□-□dBc Vs□= 5V V =□2V R =□100 out PP L /c87 ±7. G□=□10 R =□499 ,□R =□54.9 F G /c87 /c87 G□=□2 R =□768 ,□R =□768 F G /c87 /c87 G□=□5 R =□619 ,□R =□154 F G /c87 /c87 -110 -100 -90 -80 -70 -60 -50 -40 -30 0 1 2 3 4 5 6 V Output□Voltage□-□Vout PP- 2nd□Order□Harmonic□Distortion□-□dBc Vs□= 5V F G L G□=□2 R =□768 ,□R =□768 R =□100 /c87 ±7. /c87 /c87 1MHz 2MHz 8MHz 4MHz 64MHz 32MHz 16MHz -110 -100 -90 -80 -70 -60 -50 -40 -30 0 1 2 3 4 5 6 V Output□Voltage□-□Vout PP- 3rd□Order□Harmonic□Distortion□-□dBc Vs□= 5V F G L G□=□2 R =□768 ,□R =□768 R =□100 /c87 ±7. /c87 /c87 1MHz 8MHz 4MHz 64MHz 32MHz 16MHz 2MHz -110 -100 -90 -80 -70 -60 -50 -40 -30 0 1 2 3 4 5 6 V Output□Voltage□-□Vout PP- 2nd□Order□Harmonic□Distortion□-□dBc Vs□= 5V F G L G□=□5 R =□619 ,□R =□154 R =□100 /c87 ±7. /c87 /c87 1MHz 2MHz 8MHz 4MHz 64MHz 32MHz 16MHz -110 -100 -90 -80 -70 -60 -50 -40 -30 0 1 2 3 4 5 6 V Output□Voltage□-□Vout PP- 3rd□Order□Harmonic□Distortion□-□dBc Vs□= 5V F G L G□=□5 R =□649 ,□R =□154 R =□100 /c87 ±7. /c87 /c87 1MHz 8MHz 4MHz 64MHz 32MHz 16MHz 2MHz -110 -100 -90 -80 -70 -60 -50 -40 -30 0 1 2 3 4 5 6 V Output□Voltage□-□Vout PP- 2nd□Order□Harmonic□Distortion□-□dBc Vs□= 5V, G□=□10 R =□499 ,□R =□54.9 R =□100 F G L /c87 ±7. /c87 /c87 1MHz 4MHz 64MHz 32MHz 16MHz 2MHz 8MHz -100 -80 -60 -40 -20

1 M 10 M 100 M 10 G

C 50 W 50 W

50 W50 W

VS =/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr±7.5 V Gain = +10 C = 0 pF -110 -100 -90 -80 -70 -60 -50 -40 -30 0 1 2 3 4 5 6 V Output□Voltage□-□Vout PP- 3rd□Order□Harmonic□Distortion□-□dBc Vs□= 5V F G L G□=□10 R =□499 ,□R =□54.9 R =□100 /c87 ±7. /c87 /c87 1MHz 8MHz 4MHz 64MHz 32MHz 16MHz 2MHz -100 -90 -70 -50 -40 10 30 40 60 70 90 100 f□-□Frequency□-□MHz 3rd□Order□Intermodulation□Distortion□-□dBc -80 -60 20 50 80 Vs□= 5V V =□2V R =□100 out PP L /c87 ±7. R =□768 ,□R =□768 F G /c87 /c87 G10 R =□499 ,□R =□54.9 F G /c87 /c87 R =□619 ,□R =□154 F G /c87 /c87 THS3201-EP SGLS283B APRIL 2005 REVISED JANUARY 2009 www.ti.com V S 7.5 V Graphs (continued) 2nd HARMONIC DISTORTION 3rd HARMONIC DISTORTION 3rd HARMONIC DISTORTION G G vs vs vs FREQUENCY OUTPUT VOLTAGE OUTPUT VOLTAGE Figure 11. Figure 12. Figure 13. 2nd HARMONIC DISTORTION 3rd HARMONIC DISTORTION 2nd ORDER HARMONIC DISTORTION G G G vs vs vs OUTPUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE Figure 14. Figure 15. Figure 16. 3rd ORDER HARMONIC DISTORTION 3rd ORDER INTERMODULATION G DISTORTION S-PARAMETER vs vs vs OUTPUT VOLTAGE FREQUENCY FREQUENCY Figure 17. Figure 18. Figure 19. Submit Documentation Feedback Copyright 2005 2009, Texas Instruments Incorporated Product Folder Link(s): THS3201-EP

-100 -80 -60 -40 -20 C 50 W 50 W VS =/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr±7.5 V Gain = +10 C = 3.3 pF S22 S11 S12 100 k 1 M 10 M 100 M Inverting Noise Current Noninverting Current Noise VS = ±7.5 V and ±5 V TA = 25°C f - Frequency - Hz 0.5 1.5 2.5 Voltage Noise Density - nV/ Hz Input Current Noise Density -pA HzIn - V n - Vn 3.5 0 50 100 150 200 250 300 350 400 Noise Figure - dB f - Frequency - MHz Gain = +10 R G = 28 W R F = 255 W VS = ±7.5 V & ±5 V 100 120 VS =/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr±5 and ±7.5V f - Frequency - Hz 100 k 10 M 1 G100 M1 M Transimpedance Gain -dBW Gain /C0087/C0043 V O IIB 10 W 0.5 1.5 2.5 -40-30-20 -10 0 10 20 30 40 50 60 70 80 90 TC - Case Temperature - °C - Input Offset Voltage - mVVOS VS = ±5 V VS = ±7.5 V -1.5 -0.5 0.5 1.5 0 2 4 6 8 10 Gain = -2 R L = 100 W R F = 576 W f= 1 MHz V S = ±7.5 V Rising Edge Falling Edge t - Time - ns - Output Voltage - VVO -40-30 -20-10 0 10 20 30 40 50 60 70 80 90 TC - Case Temperature - °C - Input Bias Currents -IIB IOS - Input Offset Currents - Am Am IOS IIB- IIB+ VS =/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr±7.5 V 2000 4000 6000 8000 9000 10000 1 2 4 10 V Output□Voltage□-□Vstepout - SR -□V/ s /c109 -□Slew□Rate SR+ SR- 1000 3000 5000 7000 5 73 6 8 THS3201-EP www.ti.com SGLS283B APRIL 2005 REVISED JANUARY 2009 V S 7.5 V Graphs (continued) INPUT VOLTAGE AND S-PARAMETER CURRENT NOISE vs vs FREQUENCY FREQUENCY Figure 20. Figure 21. NOISE FIGURE TRANSIMPEDANCE INPUT OFFSET VOLTAGE vs vs vs FREQUENCY FREQUENCY CASE TEMPERATURE Figure 22. Figure 23. Figure 24. INPUT BIAS AND OFFSET CURRENT SLEW RATE vs vs CASE TEMPERATURE OUTPUT VOLTAGE SETTLING TIME Figure 25. Figure 26. Figure 27. Copyright 2005 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): THS3201-EP

-2.5 -1.5 -0.5 0.5 1.5 2.5 0 2.5 7.5 12.5 t - Time - ns - Output Voltage - VVO Rising Edge Gain = -2 R L = 100 W R F = 576 W f= 1 MHz V S = ±7.5 V Falling Edge 5 10 10 100 1000 R L - Load Resistance - W - Output Voltage - VVO VS = ±7.5 V TA = -40 to 85°C VS - Supply Voltage - ±V Quiescent Current - mA TA = 85°C TA = 25°C TA = -40°C -0.3 -0.2 -0.1 0.1 0.2 0.3 t - Time - ms - Output Voltage - VVO Output Input Gain = 2 R L = 100 W R F = 715 W VS = ±7.5 V 100 k 1 M 10 M 100 M CMRR PSRR+ VS = ±7.5 V Rejection Ratios - dB f - Frequency - Hz t - Time - ms - Output Voltage - VVO Output Input Gain = -5 R L = 100 W R F = 549 W VS = ±7.5 V 0.005 0.010 0.015 0.020 0.025 0.030 0 1 2 3 4 5 6 7 8 Number of Loads - 150 W Differential Gain - % Gain = 2 R F = 768 W VS = ±7.5 V

40 IRE - NTSC and Pal

Worst Case ±100 IRE RampNTSC PAL -10 0 0.2 0.4 0.6 0.8 1 t - Time - ms - Output Voltage - V - Input Voltage - VVI VO G = 2, R F = 768 W , VS = ±7.5 V THS3201-EP SGLS283B APRIL 2005 REVISED JANUARY 2009 www.ti.com V S 7.5 V Graphs (continued) QUIESCENT CURRENT OUTPUT VOLTAGE vs vs SETTLING TIME SUPPLY VOLTAGE LOAD RESISTANCE Figure 28. Figure 29. Figure 30. REJECTION RATIO vs NONINVERTING SMALL-SIGNAL INVERTING LARGE-SIGNAL FREQUENCY TRANSIENT RESPONSE TRANSIENT RESPONSE Figure 31. Figure 32. Figure 33. DIFFERENTIAL GAIN vs OVERDRIVE RECOVERY TIME NUMBER OF LOADS Figure 34. Figure 35. Submit Documentation Feedback Copyright 2005 2009, Texas Instruments Incorporated Product Folder Link(s): THS3201-EP

0.005 0.010 0.015 0.020 0.025 0.030 0.035 0.040 0 1 2 3 4 5 6 7 8 Number of Loads - 150 W Differential Phase - Gain = 2 R F = 768 kW VS = ±7.5 V Worst Case ±100 IRE RampNTSC PAL 0.001 0.01 0.1 100 1000 100 k 1 M 10 M 1 M 1 G f - Frequency - Hz Closed-Loop Output Impedance -W Gain = 2 R F = 715 W R L = 100 W VS = ±7.5 V V S V Graphs 5.6 5.7 5.8 5.9 6.1 6.2 6.3 6.4 100 k 1 M 10 M 100 M 1 G 10 G f - Frequency - Hz Gain = 2, R F = 715 W , R L = 100 W , VO = 0.2 VPP, VS = ±5 V Noninverting Gain - dB 100 k 1 M 10 M 100 M 1 G 10 G f - Frequency - Hz R L = 100 W , VO = 0.2 VPP. VS = ±5 V G = 10, RF = 464 W G = 5, RF = 576 W G = 2, RF = 715 W G =1, RF = 1.2 kW Noninverting Gain - dB 100 k 1 M 10 M 100 M 1 G 10 G f - Frequency - Hz R L = 100 W , VO = 0.2 VPP. VS = ±5 V G = -10, RF = 499 W G = -5, RF = 549 W G = -2, RF = 576 W G =-1, RF = 576 W Inverting Gain - dB -100 -95 -90 -85 -80 -75 -70 -65 -60 1 10 100 f□-□Frequency□-□MHz 3rd□Order□Harmonic□Distortion□-□dBc Vs□= 5V V =□2V R =□100 out PP L /c87 G□=□10 R =□464 ,□R =□51.1 F G /c87 /c87 G□=□2 R =□715 ,□R =□715 F G /c87 /c87 G□=□5 R =□576 ,□R =□143 F G /c87 /c87 -110 -100 -90 -80 -70 -60 -50 -40 -30 0 1 2 3 4 5 6 V Output□Voltage□-□Vout PP- 2nd□Order□Harmonic□Distortion□-□dBc Vs□= 5V L G□=□2 R =□100 /c87 /c87 /c87 1MHz 2MHz 8MHz 4MHz 64MHz 32MHz 16MHz -100 -90 -80 -70 -60 -50 -40 1 100 f□-□Frequency□-□MHz 2nd□Order□Harmonic□Distortion□-□dBc Vs□= 5V V =□2V R =□100 out PP L /c87 G□=□10 R =□464 ,□R =□51.1 F G /c87 /c87 G□=□5 R =□576 , R =□143 F G /c87 /c87 G□=□2 R =□715 ,□R =□715 F G /c87 /c87 THS3201-EP www.ti.com SGLS283B APRIL 2005 REVISED JANUARY 2009 V S 7.5 V Graphs (continued) DIFFERENTIAL PHASE CLOSED-LOOP OUTPUT IMPEDANCE vs vs NUMBER OF LOADS FREQUENCY Figure 36. Figure 37. NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNAL 0.1-dB GAIN FLATNESS FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE Figure 38. Figure 39. Figure 40. 2nd ORDER HARMONIC DISTORTION 2nd HARMONIC DISTORTION 3rd ORDER HARMONIC DISTORTION G vs vs vs FREQUENCY FREQUENCY OUTPUT VOLTAGE Figure 41. Figure 42. Figure 43. Copyright 2005 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): THS3201-EP

-110 -100 -90 -80 -70 -60 -50 -40 -30 0 1 2 3 4 5 6 V Output□Voltage□-□Vout PP- 3rd□Order□Harmonic□Distortion□-□dBc Vs□= 5V F G L G□=□2 R =□715 ,□R =□715 R =□100 /c87 /c87 /c87 1MHz 2MHz 8MHz 4MHz 64MHz 32MHz 16MHz -110 -100 -90 -80 -70 -60 -50 -40 -30 0 1 2 3 4 5 6 V Output□Voltage□-□Vout PP- 2nd□Order□Harmonic□Distortion□-□dBc Vs□= 5V F G L G□=□5 R =□576 ,□R =□143 R =□100 /c87 /c87 /c87 1MHz 2MHz 8MHz 4MHz 64MHz 32MHz 16MHz -110 -100 -90 -80 -70 -60 -50 -40 -30 0 1 2 3 4 5 6 V Output□Voltage□-□Vout PP- 3rd□Order□Harmonic□Distortion□-□dBc Vs□= 5V F G L G□=□5 R =□576 ,□R =□143 R =□100 /c87 /c87 /c87 1MHz 2MHz 8MHz 4MHz 64MHz 32MHz 16MHz -110 -100 -90 -80 -70 -60 -50 -40 -30 0 1 2 3 4 5 6 V Output□Voltage□-□Vout PP- 2nd□Order□Harmonic□Distortion□-□dBc Vs□= 5V, G□=□10 R =□464 ,□R =□51.1 R =□100 F G L /c87 /c87 /c87 1MHz 2MHz 8MHz 4MHz 64MHz32MHz 16MHz -110 -100 -90 -80 -70 -60 -50 -40 -30 0 1 2 3 4 5 6 V Output□Voltage□-□Vout PP- 3rd□Order□Harmonic□Distortion□-□dBc Vs□= 5V F G L G□=□10 R =□464 ,□R =□51.1 R =□100 /c87 /c87 /c87 1MHz 2MHz 8MHz 4MHz 64MHz 32MHz 16MHz -100 -95 -90 -85 -75 -70 -60 -55 -50 10 30 40 60 70 90 100 f□-□Frequency□-□MHz 3rd□Order□Intermodulation□Distortion□-□dBc Vs□= 5V V =□2V R =□100 out PP L /c87 R =□715 ,□R =□715 F G /c87 /c87 G10 R =□464 , R =□51.1 F G /c87 /c87 R =□576 , R =□143 F G /c87 /c87 -80 -65 20 50 80 -100 -80 -60 -40 -20 VS =/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr±5 V Gain = +10 C = 0 pF Source C 50 W 50 W -100 -80 -60 -40 -20 VS =/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr±5 V Gain = +10 C = 3.3 pF S22 S11 Source C 50 W 50 W V Output□Voltage□-□Vstepout - SR -□V/ s /c109 -□Slew□Rate SR+ SR- THS3201-EP SGLS283B APRIL 2005 REVISED JANUARY 2009 www.ti.com V S V Graphs (continued) 3rd ORDER HARMONIC 2nd ORDER HARMONIC 3rd ORDER HARMONIC DISTORTION, G DISTORTION, G DISTORTION, G vs vs vs OUTPUT VOLTAGE OUTPUT VOLTAGE OUTPUT VOLTAGE Figure 44. Figure 45. Figure 46. 2nd ORDER HARMONIC 3rd ORDER HARMONIC 3rd ORDER INTERMODULATION DISTORTION, G DISTORTION, G DISTORTION vs vs vs OUTPUT VOLTAGE OUTPUT VOLTAGE FREQUENCY Figure 47. Figure 48. Figure 49. S-PARAMETER S-PARAMETER SLEW RATE vs vs vs FREQUENCY FREQUENCY OUTPUT VOLTAGE Figure 50. Figure 51. Figure 52. Submit Documentation Feedback Copyright 2005 2009, Texas Instruments Incorporated Product Folder Link(s): THS3201-EP

-0.3 -0.2 -0.1 0.1 0.2 0.3 t - Time - ms - Output Voltage - VVO Output Input Gain = 2 R L = 100 W R F = 715 W VS = ±5 V -2.5 -1.5 -0.5 0.5 1.5 2.5 t - Time -ms - Output Voltage - VVO Output Input Gain = -5 R L = 100 W R F = 549 W VS = ±5 V 0 0.2 0.4 0.6 0.8 1 t - Time - ms - Output Voltage - V - Input Voltage - VVI VO G = 2, R F = 715 W , VS = ±5 V THS3201-EP www.ti.com SGLS283B APRIL 2005 REVISED JANUARY 2009 V S V Graphs (continued) NONINVERTING SMALL-SIGNAL INVERTING LARGE-SIGNAL TRANSIENT RESPONSE TRANSIENT RESPONSE OVERDRIVE RECOVERY TIME Figure 53. Figure 54. Figure 55. Copyright 2005 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): THS3201-EP

768 Ω 49.9 Ω 100 pF 0.1 µF 6.8 µF -VS-7.5 V R G 50 Ω Source VI 100 pF 0.1 µF 6.8 µF +VS 7.5 V 50 Ω 768 Ω 49.9 Ω THS3201 R G 287 Ω 100 pF 0.1 µF 6.8 µF -VS-7.5 V 50 Ω Source VI 100 pF 0.1 µF 6.8 µF +VS7.5 V R F 576 Ω R M 60.4 Ω 50 Ω 49.9 Ω THS3201-EP SGLS283B APRIL 2005 REVISED JANUARY 2009 www.ti.com Table Recommended Resistor Values for Optimum Frequency Response The THS3201 is a unity gain stable 1.8-GHz THS3201 R F for AC When R load 100 Ω current-feedback operational amplifier, designed to Gain Supply Voltage R G R F operate from a 3.3-V to 7.5-V power supply. (V/V) (V) Ω Ω Figure shows the THS3201 in a noninverting gain 7.5 1.2 k of 2-V/V configuration typically used to generate the 1.2 k performance curves. Most of the curves are 7.5 768 768 characterized using signal sources with 50- Ω source 715 715 impedance, and with measurement equipment presenting a 50- Ω load impedance. The 49.9- Ω shunt 7.5 154.9 619 resistor at the V I terminal in Figure matches the 143 576 source impedance of the test generator. 7.5 54.9 487 51.1 464 7.5 619 619 576 576 7.5 and 287 576 7.5 and 110 549 7.5 and 49.9 499 Figure shows the THS3201 is a typical inverting gain configuration, where the input and output impedances and signal gain from Figure are retained in an inverting circuit configuration. Figure 56. Wideband Noninverting Gain Configuration Unlike voltage-feedback amplifiers, current-feedback amplifiers are highly dependent on the feedback resistor R F for maximum performance and stability. Table shows the optimal gain setting resistors R F and R G at different gains to give maximum bandwidth with minimal peaking in the frequency response. Higher bandwidths can be achieved, at the expense of added peaking in the frequency response, by using even lower values for R F Conversely, increasing R F decreases the bandwidth, but stability is improved. Figure 57. Wideband Inverting Gain Configuration Submit Documentation Feedback Copyright 2005 2009, Texas Instruments Incorporated Product Folder Link(s): THS3201-EP

VO(1) VO(n) THS3201 75-W Transmission Line VI

768 W 768 W

±7.5 V ±7.5 V ADC Driver Application THS320149.9 Ω 50 Ω Source VI +VS R F 768 ΩR G 768 Ω +VS +VS THS3201287 Ω 50 Ω Source VI VS R F 576 Ω +VS +VS 60.4 Ω R G 50 Ω R T 50 Ω R T 49.9 Ω 49.9 Ω Video HDTV Drivers THS3201 47pF CM ADC47pF 1:n 24.9 Ω VS+ R F VS- VIN R G 0.1 µF 0.1 µF 24.9 Ω R OUT 0.1 µF R T THS3201-EP www.ti.com SGLS283B APRIL 2005 REVISED JANUARY 2009 The THS3201 has the capability to operate from a single-supply voltage ranging from 6.6 V to When operating from a single power supply, care must be taken to ensure the input signal and amplifier is biased appropriately to allow for the maximum output voltage swing. The circuits shown in Figure demonstrate methods to configure an amplifier in a manner conducive for single-supply operation Figure 59. Video Distribution Amplifier Application The THS3201 can be used as a high-performance ADC driver in devices. All high-performance ADCs have differential inputs. The THS3201 can be used in conjunction with a transformer as a drive amplifier in these applications. Figure and Figure show two different approaches. In Figure a transformer is used after the amplifier to convert the signal to differential. The advantage of this approach is fewer components are required. R OUT and R T are required for impedance matching the transformer. Figure 58. DC-Coupled Single-Supply Operation The exceptional bandwidth and slew rate of the THS3201 matches the demands for professional video and HDTV. Most commercial HDTV standards require a video passband of MHz. To ensure high signal quality with minimal degradation of performance, a 0.1-dB gain flatness should be at least the passband frequency to minimize group delay variations requiring 210-MHz 0.1-dB frequency flatness from the amplifier. High slew rates ensure there is minimal distortion of the video signal. Figure 60. Differential ADC Driver Circuit Component video and RGB video signals require fast transition times and fast settling times to keep high signal quality. The THS8135, for example, is a In Figure a transformer is used before two 240-MSPS video DAC and has a transition time amplifiers to convert the signal to differential. The two approaching ns. The THS3201 is a perfect amplifiers then amplify the differential signal. The candidate for interfacing the output of such advantage to this approach is each amplifier is high-performance video components. required to drive one half the voltage as before. R T is used to impedance match the transformer. Copyright 2005 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): THS3201-EP

1:n 24.9 Ω 0.1 µF R FR G VS- VS+ 24.9 Ω 0.1 µF 0.1 µF VIN R T R G R F IOUT2 DAC IOUT1 THS3201 THS320147pF 47pF 24.9 Ω VS+ R FR G 0.1 µF R OUT VOUT1 VOUT2 R OUT VS- 0.1 µF R FR G 24.9 Ω AV DD AV DD R PU R PU 0.1 µF THS3201-EP SGLS283B APRIL 2005 REVISED JANUARY 2009 www.ti.com Placing this pole at about 10x the highest frequency of interest ensures it has no impact on the signal. Since the resistor is typically a small value, it is bad practice to place the pole at (or near) frequencies of interest. At the pole frequency, the amplifiers see a load with a magnitude of: If R is only Ω the amplifier is heavily loaded above the pole frequency, and generates excessive distortion. The THS3201 can be used as a high-performance DAC output driver in stages, and arbitrary waveform generators. All high-performance DACs have Figure 61. Differential ADC Driver Circuit differential current outputs. Two THS3201s can be used as a differential drive amplifier in these It is almost universally recommended to use a R PU on the DAC output is used to convert the output amplifier output and the ADC input as shown in current to voltage. The 24.9- Ω resistor and 47-pF Figure and Figure capacitor between each DAC output and the This resistor-capacitor (RC) combination has multiple operational amplifier input is used to reduce the functions: images generated at multiples of the sampling rate. The values shown form a pole a 136 MHz. R OUT sets The capacitor is a local charge reservoir for ADC. the output impedance of each amplifier. The resistor isolates the amplifier from the ADC. In conjunction, they form a low-pass noise filter. During the sampling phase, current is required to charge the ADC input sampling capacitors. By placing external capacitors directly at the input pins, most of the current is drawn from them. They are seen as a low-impedance source. They can be thought of as serving much the same purpose as a power-supply bypass capacitor to supply transient current with the amplifier then providing the bulk charge. Typically, a low-value capacitor in the range of pF to 100 pF provides the required transient charge reservoir. The capacitance and the switching action of the ADC is one of the worst loading scenarios that a high-speed amplifier encounters. The resistor provides a simple means of isolating the associated phase shift from the feedback network and maintaining the phase margin of the amplifier. Figure 62. Differential DAC Driver Circuit Typically, a low-value resistor in the range of Ω to 100 Ω provides the required isolation. Together, the R and C form a real pole in the s-plane located at the frequency: Submit Documentation Feedback Copyright 2005 2009, Texas Instruments Incorporated Product Folder Link(s): THS3201-EP

www.ti.com SGLS283B APRIL 2005 REVISED JANUARY 2009 resistors, excessively high resistor values can Optimal Performance create significant time constants that can degrade performance. Good axial metal-film or Achieving optimum performance with high-frequency surface-mount resistors have approximately amplifier-like devices in the THS3201 requires careful 0.2 pF in shunt with the resistor. For resistor attention to board layout parasitic and external values k Ω this parasitic capacitance can add a component types. pole and/or a zero that can effect circuit operation. Keep resistor values as low as possible, Recommendations that optimize performance include: consistent with load driving considerations. Minimize parasitic capacitance to any power or Connections to other wideband devices on the ground plane for the negative input and ouput pins board may be made with short direct traces or by voiding the area directly below these pins and through onboard transmission lines. For short connecting traces and the feedback path. connections, consider the trace and the input to Parasitic capacitance on the output and negative the next device as a lumped capacitive load. input pins can cause instability. To reduce Relatively wide traces (50 mils to 100 mils) should unwanted capacitance, a window around the be used, preferably with ground and power planes signal I/O pins should be opened in all of the opened up around them. Estimate the total ground and power planes around those pins and capacitive load and determine if isolation resistors the feedback path. Otherwise, ground and power on the outputs are necessary. Low parasitic planes should be unbroken elsewhere on the capacitive loads pF) may not need an R S board. since the THS3201 is nominally compensated to Minimize the distance 0.25 in) from the operate with a 2-pF parasitic load. Higher parasitic power-supply pins to high frequency 0.1- µ F and capacitive loads without an R S are allowed as the 100-pF decoupling capacitors. At the device pins, signal gain increases (increasing the unloaded the ground and power-plane layout should not be phase margin). If a long trace is required and the in close proximity to the signal I/O pins. Avoid 6-dB signal loss intrinsic to a doubly-terminated narrow power and ground traces to minimize transmission line is acceptable, implement a inductance between the pins and the decoupling matched impedance transmission line using capacitors. The power-supply connections should microstrip or stripline techniques (consult an ECL always be decoupled with these capacitors. design handbook for these techniques). Larger (6.8 µ F or more) tantalum decoupling A 50- Ω environment is not necessary onboard capacitors, effective at lower frequency, should and, in fact, a higher-impedance environment also be used on the main supply pins. These may improves distortion as shown in the distortion be placed somewhat farther from the device and versus load plots. With a characteristic board may be shared among several devices in the trace impedance based on board material and same area of the PC board. The primary goal is to trace dimensions, a matching series resistor into minimize the impedance seen in the the trace from the output of the THS3201 is used, differential-current return paths. For driving as well as a terminating shunt resistor at the input differential loads with the THS3201, adding a of the destination device. capacitor between the power-supply pins improves 2nd order harmonic distortion Remember also that the terminating impedance is performance. This also minimizes the current loop the parallel combination of the shunt resistor and formed by the differential drive. the input impedance of the destination device; this total effective impedance should be set to match Careful selection and placement of external the trace impedance. If the 6-dB attenuation of a components preserve the high frequency doubly-terminated transmission line is performance of the THS3201. Resistors should be unacceptable, a long trace can be a low-reactance type. Surface-mount resistors series-terminated at the source end only. Treat work best and allow a tighter overall layout. Again, the trace as a capacitive load in this case. This keep their leads and PC board trace length as does not preserve signal integrity as well as a short as possible. Never use wirebound-type doubly-terminated line. If the input impedance of resistors in a high-frequency application. Since the the destination device is low, there is some signal output pin and inverting input pins are the most attenuation due to the voltage divider formed by sensitive to parasitic capacitance, always position the series output into the terminating impedance. the feedback and series output resistors, if any, as close as possible to the inverting input pins and Socketing a high-speed part such as the THS3201 output pins. Other network components, such as is not recommended. The additional lead length input termination resistors, should be placed close and pin-to-pin capacitance introduced by the to the gain-setting resistors. Even with a socket can create an extremely troublesome low-parasitic capacitance shunting the external parasitic network, which can make it almost Copyright 2005 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): THS3201-EP

0.060 0.040 0.075 0.025 0.205 0.010 vias Pin 1 Top View 0.017 0.035 0.094 0.030 0.013 PowerPAD PCB Layout Considerations DIE Side View (a) DIE End View (b) Thermal Pad Bottom View (c) THS3201-EP SGLS283B APRIL 2005 REVISED JANUARY 2009 www.ti.com impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering THS3201 parts directly onto the board. The THS3201 is available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see Figure (a) and Figure (b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure (c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. Figure 64. DGN PowerPAD PCB Etch and Via The PowerPAD package allows for both assembly Pattern and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this Prepare the PCB with a top-side etch pattern as copper area, heat can be conducted away from the shown in Figure There should be etch for the package into either a ground plane or other leads as well as etch for the thermal pad. heat-dissipating device. Place five holes in the area of the thermal pad. The PowerPAD package represents a breakthrough These holes should be mils in diameter. Keep in combining the small area and ease of assembly of them small so that solder wicking through the surface mount with the, heretofore, awkward holes is not a problem during reflow. mechanical methods of heatsinking. Additional vias may be placed anywhere along the thermal plane outside of the thermal-pad area. This helps dissipate the heat generated by the THS3201 IC. These additional vias may be larger than the 10-mil diameter vias directly under the thermal-pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem. Connect all holes to the internal ground plane. Figure 63. Views of Thermally Enhanced Package When connecting these holes to the ground plane, do not use the typical web or spoke via Although there are many ways to properly heat sink connection methodology. Web connections have the PowerPAD package, the following steps define a high thermal resistance connection that is the recommended approach. useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS3201 PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole. The top-side solder mask should leave the terminals of the package and the thermal-pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal-pad area. This prevents solder from Submit Documentation Feedback Copyright 2005 2009, Texas Instruments Incorporated Product Folder Link(s): THS3201-EP

qJA = 58.4°C/W for 8-Pin MSOP w/PowerPad (DGN) qJA = 98°C/W for 8-Pin SOIC High Test PCB (D) qJA = 158°C/W for 8-Pin MSOP w/PowerPad w/o Solder Results are With No Air Flow and PCB Size = 3ºx3º 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 -40 -20 0 20 40 60 80 100 PD - Maximum Power Dissipation - W TA - Free-Air Temperature - °C qJA = 98°C/W qJA = 158°C/W TJ = 125°C qJA = 58.4°C/W Design Tools Evaluation Fixture, Spice Models, and P Dmax /C0043Tmax /C0042TA /C0113JA where: PDmax is the maximum power dissipation in the amplifier (W). Tmax is the absolute maximum junction temperature (°C). TA is the ambient temperature (°C). qJA = qJC + qCA qJC is the thermal coefficient from the silicon junctions to the case (°C/W). qCA is the thermal coefficient from the case to ambient air (°C/W). THS3201-EP www.ti.com SGLS283B APRIL 2005 REVISED JANUARY 2009 being pulled away from the thermal-pad area the effect of not soldering the PowerPAD to a PCB. during the reflow process. The thermal impedance increases substantially, which may cause serious heat and performance Apply solder paste to the exposed thermal-pad issues. Be sure to always solder the PowerPAD to area and all of the IC terminals. the PCB for optimum performance. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed. Considerations To maintain maximum output capabilities, the THS3201 does not incorporate automatic thermal shutoff protection. The designer must take care to ensure that the design does not violate the absolute maximum junction temperature of the device. Failure may result if the absolute maximum junction temperature of 150 C is exceeded. For the best performance, design for a maximum junction temperature of 125 Between 125 C and 150 damage does not occur, but the performance of the amplifier begins to degrade. Figure 65. Maximum Power Dissipation vs The thermal characteristics of the device are dictated Ambient Temperature by the package and the PC board. Maximum power dissipation for a given package can be calculated When determining whether or not the device satisfies using the following formula. the maximum power-dissipation requirement, it is important to not only consider quiescent power dissipation, but also dynamic power dissipation. Often times, this is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem. support. To support this For systems where heat dissipation is more critical, goal, an evaluation board has been developed for the the THS3201 is offered in an 8-pin MSOP with THS3201 operational amplifier. The board is easy to PowerPAD and the THS3201 is available in the use, allowing for straightforward evaluation of the SOIC-8 PowerPAD package offering even better device. The evaluation board can be ordered through thermal performance. The thermal coefficient for the the TI web site, www.ti.com or through your local TI PowerPAD packages are substantially improved over sales representative. The schematic diagram, board the traditional SOIC. Maximum power dissipation layers, and bill of materials of the evaluation boards levels are listed in the Dissipation Ratings table.. The are in Figure through Figure data for the PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines referenced above and detailed in the PowerPAD application report SLMA002. Figure also shows Copyright 2005 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): THS3201-EP

J8* Vs+ C8* C7* J9* Vout Vs - R3J1 Vin- TP1 VS- C6 C5 C2 VS+ FB2 C4 C3 FB1 VS- GND VS+ +*Does Not Apply to the THS3201 PD 768 Ω 768 Ω 49.9 Ω0 Ω PD Ref 49.9 Ω Not Populated 0.1 µF22 µF 100 pF 100 pF 0.1 µF 22 µF THS3201-EP SGLS283B APRIL 2005 REVISED JANUARY 2009 www.ti.com Figure 66. THS3201 EVM Circuit Configuration Submit Documentation Feedback Copyright 2005 2009, Texas Instruments Incorporated Product Folder Link(s): THS3201-EP

www.ti.com SGLS283B APRIL 2005 REVISED JANUARY 2009 Figure 67. THS3201 EVM Board Layout (Top Layer) Figure 69. THS3201 EVM Board Layout (Third Layer, Power) Figure 68. THS3201 EVM Board Layout Figure 70. THS3201 EVM Board Layout (Second Layer, Ground) (Bottom Layer) Copyright 2005 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): THS3201-EP

www.ti.com Table Bill of Materials (1) THS3201DGN EVM PCB ITEM Bead, ferrite, Ω 1206 FB1, FB2 (Steward) HI1206N800R-00 Cap, tanatalum, 10% D C1, (AVX) TAJD226K025R Cap, 100 pF, ceramic, 5%, 150 V AQ12 C4, (AVX) AQ12EM101JAJME Cap, 0.1 ceramic, X7R, V 0805 C3, (AVX) 08055C104KAT2A Open 0805 Resistor, 49.9 Ω 0805 (Phycomp) 9C08052A49R9FKHFT Resistor, 768 Ω 0805 R3, (Phycomp) 9C08052A7680FKHFT Open 1206 C7, Resistor, Ω 1206 (KOA) RK73Z2BLTD Resistor, 49.9 Ω 1206 (Phycomp) 9C12063A49R9FKRFT Test point, black TP1 (Keystone) 5001 Open J8, Jack, Banana Receptance, 0.25 dia. J5, J6, (HH Smith) 101 hole Connector, edge, SMA PCB jack J1, J2, (Johnson) 142-0701-801 Standoff, 4-40 hex, 0.625 length (Keystone) 1804 Screw, Phillips, 4-40, .250 SHR-0440-016-SN IC, THS3201 (Texas Instruments) THS3201DGN Board, printed circuit (Texas Instruments) Edge 6447972 Rev.A (1) The components shown in the BOM were used in test by TI. Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is PowerPAD Made Easy, application brief particularly true for video and R F -amplifier circuits, (SLMA004) where parasitic capacitance and inductance can have PowerPAD Thermally-Enhanced Package, a major effect on circuit performance. A SPICE model technical brief (SLMA002) for the THS4500 family of devices is available Voltage Feedback vs Current Feedback Amplifiers through the TI web site www.ti.com The Product (SLVA051) Information Center (PIC) is available for design assistance and detailed product information. These Current Feedback Analysis and Compensation models do a good job of predicting small-signal ac (SLOA021) and transient performance under a wide variety of Current Feedback Amplifiers: Review, Stability, operating conditions. They are not intended to model and Application (SBOA081) the distortion characteristics of the amplifier, nor do Effect of Parasitic Capacitance in Op Amp Circuits they attempt to distinguish between the package (SLOA013) types in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the model file itself. Submit Documentation Feedback Copyright 2005 2009, Texas Instruments Incorporated Product Folder Link(s): THS3201-EP

www.ti.com 31-May-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples THS3201MDGNREP ACTIVE MSOP- PowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -55 to 125 BLM V62/05609-01YE ACTIVE MSOP- PowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAUAG Level-1-260C-UNLIM -55 to 125 BLM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 31-May-2014 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF THS3201-EP :

• Catalog: THS3201 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant THS3201MDGNREP MSOP- Power PAD PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2014 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS3201MDGNREP MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 17-May-2014 Pack Materials-Page 2

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