V620560803YE

THS4503-EP NSC | Alldatasheet

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THS4503−EP SGLS291A − APRIL 2005 − JANUARY 2012 WIDEBAND, LOW-DISTORTION FULLY DIFFERENTIAL AMPLIFIERS DGN−8

FEATURES

/C0068Controlled Baseline /C0068One Assembly/Test Site, One Fabrication Site /C0068Enhanced Diminishing Manufacturing Sources (DMS) Support /C0068Enhanced Product-Change Notification /C0068Qualification Pedigree(1) /C0068Fully Differential Architecture /C0068Bandwidth: 370 MHz /C0068Slew Rate: 2800 V/μs /C0068IMD3: −95 dBc at 30 MHz /C0068OIP3: 51 dBm at 30 MHz /C0068Output Common-Mode Control /C0068Wide Power Supply Voltage Range: 5 V, ±5 V,

12 V, 15 V

/C0068Centered Input Common-Mode Range /C0068Evaluation Module Available (1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperaturerange. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life.

APPLICATIONS

/C0068High Linearity Analog-to-Digital Converter Preamplifier /C0068Wireless Communication Receiver Chains /C0068Single-Ended to Differential Conversion /C0068Differential Line Driver /C0068Active Filtering of Differential Signals VIN− VIN+ VOCM VS+ VOUT+ NC VS− VOUT− RELATED DEVICES DEVICE(1) DESCRIPTION THS4500/1 370 MHz, 2800 V/μs, VICR Includes VS− THS4502/3 370 MHz, 2800 V/μs, Centered VICR THS4120/1 3.3 V, 100 MHz, 43 V/μs, 3.7 nV√Hz THS4130/1 ±15 V, 150 MHz, 51 V/μs, 1.3 nV√Hz THS4140/1 ±15 V, 160 MHz, 450 V/μs, 6.5 nV√Hz THS4150/1 ±15 V, 150 MHz, 650 V/μs, 7.6 nV√Hz (1) Even numbered devices feature power-down capability

DESCRIPTION

The THS4503 is a high-performance fully differential amplifier from Texas Instruments. The THS4503, without power-down capability, set new performance standards for fully differential amplifiers with unsurpassed linearity, supporting 14-bit operation through 40 MHz. Package options include the 8-pin MSOP with PowerPAD™ for a smaller footprint, enhanced ac performance, and improved thermal dissipation capability. WARNING: The THS4503 may have low−level oscillation when the die temperature (also known as the junction temperature) exceeds 60/C0053C. These devices are not recommended for new designs where the die temperature is expected to exceed 60/C0053C. For more information, see Maximum Die Temperature to Oscillation. PowerPAD is a trademark of Texas Instruments. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. www.ti.com Copyright © 2005 − 2012, Texas Instruments Incorporated

THS4503−EP SGLS291A − APRIL 2005 − JANUARY 2012 www.ti.com APPLICATION CIRCUIT DIAGRAM f − Frequency − MHz −80 −92 02 0 4 06 0 − Third-Order Intermodulation Distortion − dBc −74 THIRD-ORDER INTERMODULATION DISTORTION −62 80 100 −68 −86 −98 IMD3 Bits VS 392 Ω + 800 Ω 5 V −5 V VOUT 392 Ω 402 Ω 56.2 Ω 50 Ω 374 Ω VOCM2.5 V + − VOCM 14 Bit/80 MSps IN IN 5 V Vref 5 V −5 V VS 0.1 μF 10 μF 0.1 μF 10 μF THS4503 392 Ω 10 pF 1 μF 56.2 Ω ADC 374 Ω50 Ω 402 Ω 392 Ω 10 pF 24.9 Ω 24.9 Ω ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNIT Supply voltage, VS 16.5 V Input voltage, VI ±VS Output current, I O (2) 150 mA Differential input voltage, V ID 4 V Continuous power dissipation See Dissipation Rating Table Maximum junction temperature, T J (3) 150°C Maximum junction temperature, continuous operation, long term reliability T J (4) 125°C Maximum junction temperature, to prevent oscillation TJ (5) 60°C Operating free-air temperature range, T A −55°C to 60°C Storage temperature range, T stg −65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C HBM 4000 V ESD ratings: CDM 2000 VESD ratings: MM 100 V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) The THS450x may incorporate a PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See Texas Instruments technical brief SLMA002 for more information about utilizing the PowerPAD thermally enhanced package. (3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process. (4) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of overall device life. See Figure 1 for additional information on thermal derating. (5) See Maximum Die Temperature to Prevent Oscillation section in the Application Information of this data sheet. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE DISSIPATION RATINGS PACKAGE θJC θJA(1) PACKAGE θJC (°C/W) θJA() (°C/W) DGN (8 pin) 4.7 58.4 (1) This data was taken using the JEDEC standard High-K test PCB. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Supply voltage Dual supply ±5 ±7.5 VSupply voltage Single supply 4.5 5 15 V Operating free-air temperature, TA −55 60 °C

Figure 1. EME−G600 Estimated Wirebond Life (1) All packages are available taped and reeled. The R suffix standard quantity is 2500.

THS4503−EP SGLS291A − APRIL 2005 − JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS VS = ±5 V Rf = Rg = 1 kΩ, RL = 399 Ω, G = +1, Single-ended input unless otherwise noted THS4503 PARAMETER TEST CONDITIONS TYP OVER TEMPERATURE(1) MIN/PARAMETER TEST CONDITIONS 25°C 25°C −55°C TO 60°C UNITS MIN/ TYP/ MAX AC PERFORMANCE G = +1, PIN= −20 dBm, Rf = 392 Ω 370 Small signal bandwidth G = +2, PIN= −30 dBm, Rf = 1 kΩ 175 MHz TypSmall-signal bandwidth G = +5, PIN= −30 dBm, Rf = 1.3 kΩ 70 MHz Typ G = +10, PIN = −30 dBm, Rf = 1.3 kΩ 30 Gain-bandwidth product G > +10 300 MHz Typ Bandwidth for 0.1dB flatness PIN = −20 dBm 150 MHz Typ Large-signal bandwidth VP = 2 V 220 MHz Typ Slew rate 4 VPP Step 2800 V/μs Typ Rise time 2 VPP Step 0.8 ns Typ Fall time 2 VPP Step 0.6 ns Typ Settling time to 0.01% VO = 4 VPP 8.3 ns Typ Settling time to 0.1% VO = 4 VPP 6.3 ns Typ Harmonic distortion G = +1, VO = 2 VPP Typ 2nd harmonic f = 8 MHz −83 dBc Typ 2nd harmonic f = 30 MHz −74 dBc Typ 3rd harmonic f = 8 MHz −97 dBc Typ 3rd harmonic f = 30 MHz −78 dBc Typ Third-order intermodulation distortion VO = 2VPP, fc = 30 MHz, Rf = 392 Ω, 200-kHz tone spacing −94 dBc Typ Third-order output intercept point fc = 30 MHz, Rf = 392 Ω, Referenced to 50 Ω 52 dBm Typ Input voltage noise f > 1 MHz 6.8 nV/√Hz Typ Input current noise f > 100 kHz 1.7 pA/√Hz Typ Overdrive recovery time Overdrive = 5.5 V 75 ns Typ DC PERFORMANCE Open-loop voltage gain 55 52 48 dB Min Input offset voltage VOD = ±4 V, VOCM = 0 V −1 ±6 ±7 mV Max Average offset voltage drift ±10 μV/°C Typ Input bias current 4 4.6 5.4 μA Max Average bias current drift ±10 nA/°C Typ Input offset current 0.5 1 2 μA Max Average offset current drift ±40 nA/°C Typ INPUT Common-mode input range ±4.0 ±3.7 ±3.4 V Min Common-mode rejection ratio 80 74 70 dB Min Input impedance VICM = ±0.5 V, VOCM = 0 V 107 || 1 Ω || pF Typ OUTPUT Differential output voltage swing RL = 399 Ω ±8 ±7.6 ±7.4 V Min Differential output current drive RL = 20 Ω 120 110 100 mA Min Output balance error PIN = −20 dBm, f = 100 kHz −58 dB Typ Closed-loop output impedance (single-ended) f = 1 MHz 0.1 Ω Typ

THS4503−EP SGLS291A − APRIL 2005 − JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS VS = ±5 V Rf = Rg = 1 kΩ, RL = 399 Ω, G = +1, Single-ended input unless otherwise noted PARAMETER THS4503 TEST CONDITIONSPARAMETER MIN/ TYP/ MAX OVER TEMPERATURE(1)TYPTEST CONDITIONSPARAMETER MIN/ TYP/ MAXUNITS−55°C TO 60°C25°C25°C TEST CONDITIONS OUTPUT COMMON-MODE VOLTAGE CONTROL Small-signal bandwidth RL = 400 Ω 180 MHz Typ Slew rate 2 VPP step 87 V/μs Typ Minimum gain 1 0.98 0.98 V/V Min Maximum gain 1 1.02 1.02 V/V Max Common-mode offset voltage +2 ±7.5 ±9.9 mV Max Input bias current VOCM = 2.5 V 100 150 170 μA Max Input voltage range ±4 ±3.7 ±3.4 V Min Input impedance 25 || 1 kΩ || pF Typ Maximum default voltage VOCM left floating 0 0.05 0.1 V Max Minimum default voltage VOCM left floating 0 −0.05 −0.1 V Min POWER SUPPLY Specified operating voltage ±5 ±7.5 ±7.5 V Max Maximum quiescent current 23 28 34 mA Max Minimum quiescent current 23 16 10 mA Min Power supply rejection (±PSRR) VS+ = 4 V to 5 V, VS− = −5 V to −4 V 80 76 70 dB Min (1) See Maximum Die Temperature to Prevent Oscillation section in the Application Information of this data sheet. ELECTRICAL CHARACTERISTICS VS = 5 V Rf = Rg = 1 kΩ, RL = 399 Ω, G = +1, Single-ended input unless otherwise noted THS4503 PARAMETER TEST CONDITIONS TYP OVER TEMPERATURE MIN /PARAMETER TEST CONDITIONS 25°C 25°C −55°C TO 60°C UNITS MIN / TYP / MAX AC PERFORMANCE G = +1, PIN = −20 dBm, Rf = 392 Ω 320 Small signal bandwidth G = +2, PIN = −30 dBm, Rf = 1 kΩ 160 MHz TypSmall-signal bandwidth G = +5, PIN = −30 dBm, Rf = 1.3 kΩ 60 MHz Typ G = +10, PIN = −30 dBm, Rf = 1.3 kΩ 30 Gain-bandwidth product G > +10 300 MHz Typ Bandwidth for 0.1-dB flatness PIN = −20 dBm 180 MHz Typ Large-signal bandwidth VP = 1 V 200 MHz Typ Slew rate 2 VPP Step 1300 V/μs Typ Rise time 2 VPP Step 0.6 ns Typ Fall time 2 VPP Step 0.8 ns Typ Settling time to 0.01% VO = 2 V Step 13.1 ns Typ Settling time to 0.1% VO = 2 V Step 8.3 ns Typ Harmonic distortion VO = 2 VPP Typ 2nd harmonic f = 8 MHz, −81 dBc Typ 2nd harmonic f = 30 MHz −60 dBc Typ 3rd harmonic f = 8 MHz −74 dBc Typ 3rd harmonic f = 30 MHz −62 dBc Typ Input voltage noise f > 1 MHz 6.8 nV/√Hz Typ Input current noise f > 100 kHz 1.6 pA/√Hz Typ Overdrive recovery time Overdrive = 5.5 V 75 ns Typ

THS4503−EP SGLS291A − APRIL 2005 − JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS VS = 5 V Rf = Rg = 1 kΩ, RL = 399 Ω, G = +1, Single-ended input unless otherwise noted PARAMETER THS4503 TEST CONDITIONSPARAMETER MIN / TYP / MAX OVER TEMPERATURETYPTEST CONDITIONSPARAMETER MIN / TYP / MAXUNITS−55°C TO 60°C25°C25°C TEST CONDITIONS DC PERFORMANCE Open-loop voltage gain 54 51 48 dB Min Input offset voltage VOD = ±1 V, VOCM = 2.5 V −0.6 ±5 ±6.5 mV Max Average offset voltage drift ±10 μV/°C Typ Input bias current 4 4.6 5.2 μA Max Average bias current drift ±10 nA/°C Typ Input offset current 0.5 0.7 1.2 μA Max Average offset current drift ±20 nA/°C Typ INPUT Common-mode input range 1 / 4 1.3 / 3.7 1.6 / 3.4 V Min Common-mode rejection ratio 80 74 60 dB Min Input impedance VICM = 2.25 V to 2.75 V, VOCM = 2.5 V 107 || 1 Ω || pF Typ OUTPUT Differential output voltage swing RL = 399 Ω, Referenced to 2.5 V ±3.3 ±2.8 ±2.6 V Min Output current drive RL = 20 Ω 100 90 80 mA Min Output balance error PIN = −20 dBm, f = 100 kHz −58 dB Typ Closed-loop output impedance (single ended) f = 1 MHz 0.1 Ω Typ OUTPUT COMMON-MODE VOLTAGE CONTROL Small-signal bandwidth RL = 400 Ω 180 MHz Typ Slew rate 2 VPP Step 80 V/μs Typ Minimum gain 1 0.98 0.98 V/V Min Maximum gain 1 1.02 1.02 V/V Max Common-mode offset voltage 2 ±6.7 ±9.2 mV Max Input bias current VOCM = 2.5 V 1 2 3 μA Max Input voltage range 1/4 1.2/3.8 1.3/3.7 V Min Input impedance 25 || 1 kΩ || pF Typ Maximum default voltage VOCM left floating 2.5 2.55 2.6 V Max Minimum default voltage VOCM left floating 2.5 2.45 2.4 V Min POWER SUPPLY Specified operating voltage 5 15 15 V Max Maximum quiescent current 20 25 31 mA Max Minimum quiescent current 20 15 8 mA Min Power supply rejection (+PSRR) VS+ = 4.5 V to 5.5 V 75 72 66 dB Min

THS4503−EP SGLS291A − APRIL 2005 − JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS Table of Graphs (±5 V) FIGURE Small signal unity gain frequency response 1 Small signal frequency response 2 0.1 dB gain flatness frequency response 3 Harmonic distortion (single-ended input to differential output) vs Frequency 4, 6, 12, 14 Harmonic distortion (differential input to differential output) vs Frequency 5, 7, 13, 15 Harmonic distortion (single-ended input to differential output) vs Output voltage swing 8, 10, 16, 18 Harmonic distortion (differential input to differential output) vs Output voltage swing 9, 11, 17, 19 Harmonic distortion (single-ended input to differential output) vs Load resistance 20 Harmonic distortion (differential input to differential output) vs Load resistance 21 Third order intermodulation distortion (single-ended input to differential output) vs Frequency 22 Third order output intercept point vs Frequency 23 Slew rate vs Differential output voltage step 24 Settling time 25, 26 Large-signal transient response 27 Small-signal transient response 28 Overdrive recovery 29, 30 Voltage and current noise vs Frequency 31 Rejection ratios vs Frequency 32 Rejection ratios vs Case temperature 33 Output balance error vs Frequency 34 Open-loop gain and phase vs Frequency 35 Open-loop gain vs Case temperature 36 Input bias and offset current vs Case temperature 37 Quiescent current vs Supply voltage 38 Input offset voltage vs Case temperature 39 Common-mode rejection ratio vs Input common-mode range 40 Differential output current drive vs Case temperature 41 Harmonic distortion (single-ended and differential input to differential output) vs Output common-mode voltage 42 Small signal frequency response at VOCM 43 Output offset voltage at VOCM vs Output common-mode voltage 44 Quiescent current vs Power-down voltage 45 Turnon and turnoff delay times 46 Single-ended output impedance in power down vs Frequency 47 Power-down quiescent current vs Case temperature 48 Power-down quiescent current vs Supply voltage 49

THS4503−EP SGLS291A − APRIL 2005 − JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS Table of Graphs (5 V) FIGURE Small signal unity gain frequency response 50 Small signal frequency response 51 0.1 dB gain flatness frequency response 52 Harmonic distortion (single-ended input to differential output) vs Frequency 53, 54, 61, 63 Harmonic distortion (differential input to differential output) vs Frequency 55, 56, 62, 64 Harmonic distortion (single-ended input to differential output) vs Output voltage swing 57, 58, 65, 67 Harmonic distortion (differential input to differential output) vs Output voltage swing 59, 60, 66, 68 Harmonic distortion (single-ended input to differential output) vs Load resistance 69 Harmonic distortion (differential input to differential output) vs Load resistance 70 Slew rate vs Differential output voltage step 71 Large-signal transient response 72 Small-signal transient response 73 Voltage and current noise vs Frequency 74 Rejection ratios vs Frequency 75 Rejection ratios vs Case temperature 76 Output balance error vs Frequency 77 Open-loop gain and phase vs Frequency 78 Open-loop gain vs Case temperature 79 Input bias and offset current vs Case temperature 80 Quiescent current vs Supply voltage 81 Input offset voltage vs Case temperature 82 Common-mode rejection ratio vs Input common-mode range 83 Output drive vs Case temperature 84 Harmonic distortion (single-ended and differential input) vs Output common-mode range 85 Small signal frequency response at VOCM 86 Output offset voltage vs Output common-mode voltage 87 Quiescent current vs Power-down voltage 88 Turnon and turnoff delay times 89 Single-ended output impedance in power down vs Frequency 90 Power-down quiescent current vs Case temperature 91 Power-down quiescent current vs Supply voltage 92

THS4503−EP SGLS291A − APRIL 2005 − JANUARY 2012 www.ti.com

APPLICATION INFORMATION

MAXIMUM DIE TEMPERATURE TO PREVENT OSCILLATION The THS4503 may have low level oscillation when the die temperature (also called junction temperature) exceeds +60°C and is not recommended for new designs where the die temperature is expected to exceed +60°C. The oscillation is due to internal design and external configuration is not expected to mitigate or reduce the problem. This problem is random due to normal process variations and normal testing cannot identify problem units. The THS4500 and THS4501 are recommended replacement devices. The die temperature depends on the power dissipation and the thermal resistance of the device and can be approximated with the following formula: Die Temperature = PDISS × θJA + TA Where: PDISS ≈ (VS(TOTAL) × IQ) + (VS+ − VOUT) × IOUT) × θJA + TA Table 1 shows the estimated maximum ambient temperature (TA max) in °C for package option of the THS4503 using the thermal dissipation rating given in the PACKAGE DISSIPATION RATINGS table for a JEDEC standard High −K test PCB. For each case shown, V S(TOTAL) = 10V, RL = 800 Ω differential, and the quiescent current = 32mA (the maximum over 0 °C to 70 °C temperature range). The last entry for each package option lists the worst case where the output voltage is 5V DC. Table 1. Estimated Maximum Ambient

6 Vpp

VP and the circuit inputs as VIN+ and VIN−. Table 2. Negative-Rail Referenced input signal on a single 5-V supply as shown in Figure 94. VNMIN = VPMIN and VNMAX = VPMAX. Table 3. Midrail Referenced signal on a single 5-V supply. VNMIN = VPMIN and VNMAX = VPMAX. considerations (see Table 4). directly impacting the input impedance of the entire circuit. these trends can provide qualitative design guidance. configurations and gives some design guidelines. are a few of the circuits that are covered.

Table 4. Resistor Values for Balanced Operation NOTE: Values in the table above assume a 50-Ω source impedance. referenced at the end of this data sheet. example ADC/fully differential amplifier interface circuits. /C0068Design a symmetric printed-circuit board layout. will minimize these distortion products. differential currents exist in the power supply pins. can create higher distortion products as well. path does not have this effect. regardless of the load impedance present. /C0068Comprehend the V OCM input drive requirements. desired value. A buffer may be needed.

THS4503−EP SGLS291A − APRIL 2005 − JANUARY 2012 www.ti.com FILTERING WITH FULLY DIFFERENTIAL AMPLIFIERS Similar to their single-ended counterparts, fully differential amplifiers have the ability to couple filtering functionality with voltage gain. Numerous filter topologies can be based on fully differential amplifiers. Several of these are outlined in A Differential Circuit Collection, (SLOA064) referenced at the end of this data sheet. The circuit below depicts a simple two-pole low-pass filter applicable to many different types of systems. The first pole is set by the resistors and capacitors in the feedback paths, and the second pole is set by the isolation resistors and the capacitor across the outputs of the isolation resistors. Figure 101 VS RS Rg1 Rf1 Rf2 RT VO Riso C CF2 CF1 Rg2 Riso A Two-Pole, Low-Pass Filter Design Using a Fully Differential Amplifier With Poles Located at: P1 = (2πRfCF)−1 in Hz and P2 = (4πRisoC)−1 in Hz Often times, filters like these are used to eliminate broadband noise and out-of-band distortion products in signal acquisition systems. It should be noted that the increased load placed on the output of the amplifier by the second low-pass filter has a detrimental effect on the distortion performance. The preferred method of filtering is using the feedback network, as the typically smaller capacitances required at these points in the circuit do not load the amplifier nearly as heavily in the pass-band. SETTING THE OUTPUT COMMON-MODE VOLTAGE WITH THE VOCM INPUT The output common-mode voltage pin provides a critical function to the fully differential amplifier; it accepts an input voltage and reproduces that input voltage as the output common-mode voltage. In other words, the V OCM input provides the ability to level-shift the outputs to any voltage inside the output voltage swing of the amplifier. A description of the input circuitry of the VOCM pin is shown below to facilitate an easier understanding of the V OCM interface requirements. The V OCM pin has two 50-k Ω resistors between the power supply rails to set the default output common-mode voltage to midrail. A voltage applied to the VOCM pin alters the output common-mode voltage as long as the source has the ability to provide enough current to overdrive the two 50-kΩ resistors. This phenomenon is depicted in the V OCM equivalent circuit diagram. The table contains some representative examples to aid in determining the current drive requirement for the VOCM voltage source. This parameter is especially important when using the reference voltage of an analog-to-digital converter to drive V OCM. Output current drive capabilities differ from part to part, so a voltage buffer may be necessary in some applications. Figure 102 R = 50 kΩ R = 50 kΩ VS+ VS− VOCM IIN IIN =

2 VOCM − VS+ − VS−

R Equivalent Input Circuit for VOCM By design, the input signal applied to the V OCM pin propagates to the outputs as a common-mode signal. As shown in the equivalent circuit diagram, the V OCM input has a high impedance associated with it, dictated by the two 50-kΩ resistors. While the high impedance allows for relaxed drive requirements, it also allows the pin and any associated printed-circuit board traces to act as an antenna. For this reason, a decoupling capacitor is recommended on this node for the sole purpose of filtering any high frequency noise that could couple into the signal path through the V OCM circuitry. A 0.1- μF or 1- μF capacitance is a reasonable value for eliminating a great deal of broadband interference, but additional, tuned decoupling capacitors should be considered if a specific source of electromagnetic or radio frequency interference is present elsewhere in the system. Information on the ac performance (bandwidth, slew rate) of the V OCM circuitry is included in the specification table and graph section. Since the VOCM pin provides the ability to set an output common-mode voltage, the ability for increased power dissipation exists. While this does not pose a performance problem for the amplifier, it can cause additional power dissipation of which the system designer should be aware. The circuit shown in Figure 103 demonstrates an example of this phenomenon. For a device operating on a single 5-V supply with an input signal referenced around ground and an output common-mode voltage of 2.5 V, a dc potential exists between the outputs and the inputs of the device. The amplifier sources current into the feedback network in order to provide the circuit with the proper operating point. While there are no serious effects on the circuit performance, the extra power dissipation may need to be included in the system’s power budget.

THS4503−EP SGLS291A − APRIL 2005 − JANUARY 2012 www.ti.com PRINTED-CIRCUIT BOARD LAYOUT TECHNIQUES FOR OPTIMAL PERFORMANCE Achieving optimum performance with high frequency amplifier-like devices in the THS4500 family requires careful attention to board layout parasitic and external component types. Recommendations that optimize performance include: /C0068Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. /C0068Minimize the distance (< 0.25”) from the power supply pins to high frequency 0.1-μF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (6.8 μF or more) tantalum decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. The primary goal is to minimize the impedance seen in the differential-current return paths. /C0068Careful selection and placement of external components preserve the high frequency performance of the THS4500 family. Resistors should be a low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film and carbon composition, axially-leaded resistors can also provide good high frequency performance. Again, keep their leads and PC board trace length as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and inverting input pins are the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close as possible to the inverting input pins and output pins. Other network components, such as input termination resistors, should be placed close to the gain-setting resistors. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values > 2 kΩ, this parasitic capacitance can add a pole and/or a zero below 400 MHz that can effect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations. /C0068Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and determine if isolation resistors on the outputs are necessary. Low parasitic capacitive loads (< 4 pF) may not need an R S since the THS4500 family is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an R S are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50- Ω environment is normally not necessary onboard, and in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS4500 family is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case. This does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance. /C0068Socketing a high speed part like the THS4500 family is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS4500 family parts directly onto the board.

THS4503−EP SGLS291A − APRIL 2005 − JANUARY 2012 www.ti.com EVALUATION FIXTURES, SPICE MODELS, AND APPLICATIONS SUPPORT Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal, an evaluation board has been developed for the THS4500 family of fully differential amplifiers. The evaluation board can be obtained by ordering through the Texas Instruments web site, www.ti.com, or through your local Texas Instruments sales representative. Schematic for the evaluation board is shown below with their default component values. Unpopulated footprints are shown to provide insight into design flexibility. Figure 116 2 6 VOCM −VS PwrPad VS PD R0805 C4 C0805 R5 R0805 C0805 R0805 R0805 C0805 C0805 C0805 R0805 R0805 C0805 C0805 R1206 R11 R1206 R0805 R0805 R0805 THS450X Simplified Schematic of the Evaluation Board. Power Supply Decoupling, VOCM, and Power Down Circuitry Not Shown Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS4500 family of devices is available through the Texas Instruments web site (www.ti.com). The PIC is also available for design assistance and detailed product information. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the model file itself. ADDITIONAL REFERENCE MATERIAL /C0068PowerPAD Made Easy, application brief, Texas Instruments (SLMA004) /C0068PowerPAD Thermally Enhanced Package, technical brief, Texas Instruments (SLMA002) /C0068Karki, James. Fully Differential Amplifiers. application report, Texas Instruments (SLOA054D) /C0068Karki, James. Fully Differential Amplifiers Applications: Line Termination, Driving High-Speed ADCs, and Differential Transmission Lines. Texas Instruments Analog Applications Journal, February 2001 /C0068Carter, Bruce. A Differential Op-Amp Circuit Collection. application report, Texas Instruments (SLOA064) /C0068Carter, Bruce. Differential Op-Amp Single-Supply Design Technique , application report, Texas Instruments (SLOA072) /C0068Karki, James. Designing for Low Distortion with High-Speed Op Amps . Texas Instruments Analog Applications Journal, July 2001

www.ti.com 11-Apr-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Top-Side Markings (4) Samples THS4503MDGNREP ACTIVE MSOP- PowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 60 BLB V62/05608-03YE ACTIVE MSOP- PowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 60 BLB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF THS4503-EP :

www.ti.com 11-Apr-2013 Addendum-Page 2

• Catalog: THS4503 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant THS4503MDGNREP MSOP- Power PAD PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS4503MDGNREP MSOP-PowerPAD DGN 8 2500 358.0 335.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 Pack Materials-Page 2

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